1179055Sjfv/****************************************************************************** 2171384Sjfv 3247822Sjfv Copyright (c) 2001-2013, Intel Corporation 4171384Sjfv All rights reserved. 5171384Sjfv 6171384Sjfv Redistribution and use in source and binary forms, with or without 7171384Sjfv modification, are permitted provided that the following conditions are met: 8171384Sjfv 9171384Sjfv 1. Redistributions of source code must retain the above copyright notice, 10171384Sjfv this list of conditions and the following disclaimer. 11171384Sjfv 12171384Sjfv 2. Redistributions in binary form must reproduce the above copyright 13171384Sjfv notice, this list of conditions and the following disclaimer in the 14171384Sjfv documentation and/or other materials provided with the distribution. 15171384Sjfv 16171384Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17171384Sjfv contributors may be used to endorse or promote products derived from 18171384Sjfv this software without specific prior written permission. 19171384Sjfv 20171384Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21171384Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22171384Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23171384Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24171384Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25171384Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26171384Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27171384Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28171384Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29171384Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30171384Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD$*/ 34171384Sjfv 35171384Sjfv#ifndef _IXGBE_TYPE_H_ 36171384Sjfv#define _IXGBE_TYPE_H_ 37171384Sjfv 38251964Sjfv/* 39251964Sjfv * The following is a brief description of the error categories used by the 40251964Sjfv * ERROR_REPORT* macros. 41251964Sjfv * 42251964Sjfv * - IXGBE_ERROR_INVALID_STATE 43251964Sjfv * This category is for errors which represent a serious failure state that is 44251964Sjfv * unexpected, and could be potentially harmful to device operation. It should 45251964Sjfv * not be used for errors relating to issues that can be worked around or 46251964Sjfv * ignored. 47251964Sjfv * 48251964Sjfv * - IXGBE_ERROR_POLLING 49251964Sjfv * This category is for errors related to polling/timeout issues and should be 50251964Sjfv * used in any case where the timeout occured, or a failure to obtain a lock, or 51251964Sjfv * failure to receive data within the time limit. 52251964Sjfv * 53251964Sjfv * - IXGBE_ERROR_CAUTION 54251964Sjfv * This category should be used for reporting issues that may be the cause of 55251964Sjfv * other errors, such as temperature warnings. It should indicate an event which 56251964Sjfv * could be serious, but hasn't necessarily caused problems yet. 57251964Sjfv * 58251964Sjfv * - IXGBE_ERROR_SOFTWARE 59251964Sjfv * This category is intended for errors due to software state preventing 60251964Sjfv * something. The category is not intended for errors due to bad arguments, or 61251964Sjfv * due to unsupported features. It should be used when a state occurs which 62251964Sjfv * prevents action but is not a serious issue. 63251964Sjfv * 64251964Sjfv * - IXGBE_ERROR_ARGUMENT 65251964Sjfv * This category is for when a bad or invalid argument is passed. It should be 66251964Sjfv * used whenever a function is called and error checking has detected the 67251964Sjfv * argument is wrong or incorrect. 68251964Sjfv * 69251964Sjfv * - IXGBE_ERROR_UNSUPPORTED 70251964Sjfv * This category is for errors which are due to unsupported circumstances or 71251964Sjfv * configuration issues. It should not be used when the issue is due to an 72251964Sjfv * invalid argument, but for when something has occurred that is unsupported 73251964Sjfv * (Ex: Flow control autonegotiation or an unsupported SFP+ module.) 74251964Sjfv */ 75251964Sjfv 76171384Sjfv#include "ixgbe_osdep.h" 77171384Sjfv 78194875Sjfv 79251964Sjfv/* Vendor ID */ 80251964Sjfv#define IXGBE_INTEL_VENDOR_ID 0x8086 81251964Sjfv 82171384Sjfv/* Device IDs */ 83230775Sjfv#define IXGBE_DEV_ID_82598 0x10B6 84230775Sjfv#define IXGBE_DEV_ID_82598_BX 0x1508 85230775Sjfv#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 86230775Sjfv#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 87230775Sjfv#define IXGBE_DEV_ID_82598AT 0x10C8 88230775Sjfv#define IXGBE_DEV_ID_82598AT2 0x150B 89230775Sjfv#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB 90230775Sjfv#define IXGBE_DEV_ID_82598EB_CX4 0x10DD 91230775Sjfv#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC 92230775Sjfv#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 93230775Sjfv#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 94230775Sjfv#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 95230775Sjfv#define IXGBE_DEV_ID_82599_KX4 0x10F7 96230775Sjfv#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514 97230775Sjfv#define IXGBE_DEV_ID_82599_KR 0x1517 98230775Sjfv#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8 99230775Sjfv#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C 100230775Sjfv#define IXGBE_DEV_ID_82599_CX4 0x10F9 101230775Sjfv#define IXGBE_DEV_ID_82599_SFP 0x10FB 102230775Sjfv#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9 103247822Sjfv#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72 104230775Sjfv#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0 105247822Sjfv#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470 106251964Sjfv#define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B 107251964Sjfv#define IXGBE_SUBDEV_ID_82599_LOM_SFP 0x8976 108230775Sjfv#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A 109230775Sjfv#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529 110230775Sjfv#define IXGBE_DEV_ID_82599_SFP_EM 0x1507 111238149Sjfv#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D 112247822Sjfv#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A 113230775Sjfv#define IXGBE_DEV_ID_82599EN_SFP 0x1557 114251964Sjfv#define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001 115230775Sjfv#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC 116230775Sjfv#define IXGBE_DEV_ID_82599_T3_LOM 0x151C 117230775Sjfv#define IXGBE_DEV_ID_82599_VF 0x10ED 118247822Sjfv#define IXGBE_DEV_ID_82599_VF_HV 0x152E 119247822Sjfv#define IXGBE_DEV_ID_82599_BYPASS 0x155D 120247822Sjfv#define IXGBE_DEV_ID_X540T 0x1528 121230775Sjfv#define IXGBE_DEV_ID_X540_VF 0x1515 122247822Sjfv#define IXGBE_DEV_ID_X540_VF_HV 0x1530 123247822Sjfv#define IXGBE_DEV_ID_X540_BYPASS 0x155C 124171384Sjfv 125171384Sjfv/* General Registers */ 126230775Sjfv#define IXGBE_CTRL 0x00000 127230775Sjfv#define IXGBE_STATUS 0x00008 128230775Sjfv#define IXGBE_CTRL_EXT 0x00018 129230775Sjfv#define IXGBE_ESDP 0x00020 130230775Sjfv#define IXGBE_EODSDP 0x00028 131230775Sjfv#define IXGBE_I2CCTL 0x00028 132230775Sjfv#define IXGBE_PHY_GPIO 0x00028 133230775Sjfv#define IXGBE_MAC_GPIO 0x00030 134230775Sjfv#define IXGBE_PHYINT_STATUS0 0x00100 135230775Sjfv#define IXGBE_PHYINT_STATUS1 0x00104 136230775Sjfv#define IXGBE_PHYINT_STATUS2 0x00108 137230775Sjfv#define IXGBE_LEDCTL 0x00200 138230775Sjfv#define IXGBE_FRTIMER 0x00048 139230775Sjfv#define IXGBE_TCPTIMER 0x0004C 140230775Sjfv#define IXGBE_CORESPARE 0x00600 141230775Sjfv#define IXGBE_EXVET 0x05078 142171384Sjfv 143171384Sjfv/* NVM Registers */ 144230775Sjfv#define IXGBE_EEC 0x10010 145230775Sjfv#define IXGBE_EERD 0x10014 146230775Sjfv#define IXGBE_EEWR 0x10018 147230775Sjfv#define IXGBE_FLA 0x1001C 148230775Sjfv#define IXGBE_EEMNGCTL 0x10110 149230775Sjfv#define IXGBE_EEMNGDATA 0x10114 150230775Sjfv#define IXGBE_FLMNGCTL 0x10118 151230775Sjfv#define IXGBE_FLMNGDATA 0x1011C 152230775Sjfv#define IXGBE_FLMNGCNT 0x10120 153230775Sjfv#define IXGBE_FLOP 0x1013C 154230775Sjfv#define IXGBE_GRC 0x10200 155230775Sjfv#define IXGBE_SRAMREL 0x10210 156230775Sjfv#define IXGBE_PHYDBG 0x10218 157171384Sjfv 158190873Sjfv/* General Receive Control */ 159230775Sjfv#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ 160230775Sjfv#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */ 161190873Sjfv 162230775Sjfv#define IXGBE_VPDDIAG0 0x10204 163230775Sjfv#define IXGBE_VPDDIAG1 0x10208 164190873Sjfv 165190873Sjfv/* I2CCTL Bit Masks */ 166230775Sjfv#define IXGBE_I2C_CLK_IN 0x00000001 167230775Sjfv#define IXGBE_I2C_CLK_OUT 0x00000002 168230775Sjfv#define IXGBE_I2C_DATA_IN 0x00000004 169230775Sjfv#define IXGBE_I2C_DATA_OUT 0x00000008 170238149Sjfv#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500 171190873Sjfv 172238149Sjfv 173171384Sjfv/* Interrupt Registers */ 174230775Sjfv#define IXGBE_EICR 0x00800 175230775Sjfv#define IXGBE_EICS 0x00808 176230775Sjfv#define IXGBE_EIMS 0x00880 177230775Sjfv#define IXGBE_EIMC 0x00888 178230775Sjfv#define IXGBE_EIAC 0x00810 179230775Sjfv#define IXGBE_EIAM 0x00890 180230775Sjfv#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) 181230775Sjfv#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) 182230775Sjfv#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) 183230775Sjfv#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) 184190873Sjfv/* 82599 EITR is only 12 bits, with the lower 3 always zero */ 185190873Sjfv/* 186190873Sjfv * 82598 EITR is 16 bits but set the limits based on the max 187190873Sjfv * supported by all ixgbe hardware 188190873Sjfv */ 189230775Sjfv#define IXGBE_MAX_INT_RATE 488281 190230775Sjfv#define IXGBE_MIN_INT_RATE 956 191230775Sjfv#define IXGBE_MAX_EITR 0x00000FF8 192230775Sjfv#define IXGBE_MIN_EITR 8 193230775Sjfv#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ 194230775Sjfv (0x012300 + (((_i) - 24) * 4))) 195230775Sjfv#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 196230775Sjfv#define IXGBE_EITR_LLI_MOD 0x00008000 197230775Sjfv#define IXGBE_EITR_CNT_WDIS 0x80000000 198230775Sjfv#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 199230775Sjfv#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ 200230775Sjfv#define IXGBE_EITRSEL 0x00894 201230775Sjfv#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 202230775Sjfv#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 203230775Sjfv#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) 204230775Sjfv#define IXGBE_GPIE 0x00898 205171384Sjfv 206171384Sjfv/* Flow Control Registers */ 207230775Sjfv#define IXGBE_FCADBUL 0x03210 208230775Sjfv#define IXGBE_FCADBUH 0x03214 209230775Sjfv#define IXGBE_FCAMACL 0x04328 210230775Sjfv#define IXGBE_FCAMACH 0x0432C 211230775Sjfv#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ 212230775Sjfv#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ 213230775Sjfv#define IXGBE_PFCTOP 0x03008 214230775Sjfv#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 215230775Sjfv#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 216230775Sjfv#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 217230775Sjfv#define IXGBE_FCRTV 0x032A0 218230775Sjfv#define IXGBE_FCCFG 0x03D00 219230775Sjfv#define IXGBE_TFCS 0x0CE00 220171384Sjfv 221171384Sjfv/* Receive DMA Registers */ 222230775Sjfv#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ 223230775Sjfv (0x0D000 + (((_i) - 64) * 0x40))) 224230775Sjfv#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ 225230775Sjfv (0x0D004 + (((_i) - 64) * 0x40))) 226230775Sjfv#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ 227230775Sjfv (0x0D008 + (((_i) - 64) * 0x40))) 228230775Sjfv#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ 229230775Sjfv (0x0D010 + (((_i) - 64) * 0x40))) 230230775Sjfv#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ 231230775Sjfv (0x0D018 + (((_i) - 64) * 0x40))) 232230775Sjfv#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ 233230775Sjfv (0x0D028 + (((_i) - 64) * 0x40))) 234230775Sjfv#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ 235230775Sjfv (0x0D02C + (((_i) - 64) * 0x40))) 236230775Sjfv#define IXGBE_RSCDBU 0x03028 237230775Sjfv#define IXGBE_RDDCC 0x02F20 238230775Sjfv#define IXGBE_RXMEMWRAP 0x03190 239230775Sjfv#define IXGBE_STARCTRL 0x03024 240179055Sjfv/* 241179055Sjfv * Split and Replication Receive Control Registers 242179055Sjfv * 00-15 : 0x02100 + n*4 243179055Sjfv * 16-64 : 0x01014 + n*0x40 244179055Sjfv * 64-127: 0x0D014 + (n-64)*0x40 245179055Sjfv */ 246230775Sjfv#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ 247230775Sjfv (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ 248230775Sjfv (0x0D014 + (((_i) - 64) * 0x40)))) 249179055Sjfv/* 250179055Sjfv * Rx DCA Control Register: 251179055Sjfv * 00-15 : 0x02200 + n*4 252179055Sjfv * 16-64 : 0x0100C + n*0x40 253179055Sjfv * 64-127: 0x0D00C + (n-64)*0x40 254179055Sjfv */ 255230775Sjfv#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ 256230775Sjfv (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ 257230775Sjfv (0x0D00C + (((_i) - 64) * 0x40)))) 258230775Sjfv#define IXGBE_RDRXCTL 0x02F00 259230775Sjfv/* 8 of these 0x03C00 - 0x03C1C */ 260230775Sjfv#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 261230775Sjfv#define IXGBE_RXCTRL 0x03000 262230775Sjfv#define IXGBE_DROPEN 0x03D04 263230775Sjfv#define IXGBE_RXPBSIZE_SHIFT 10 264251964Sjfv#define IXGBE_RXPBSIZE_MASK 0x000FFC00 265171384Sjfv 266171384Sjfv/* Receive Registers */ 267230775Sjfv#define IXGBE_RXCSUM 0x05000 268230775Sjfv#define IXGBE_RFCTL 0x05008 269230775Sjfv#define IXGBE_DRECCCTL 0x02F08 270230775Sjfv#define IXGBE_DRECCCTL_DISABLE 0 271230775Sjfv#define IXGBE_DRECCCTL2 0x02F8C 272205720Sjfv 273179055Sjfv/* Multicast Table Array - 128 entries */ 274230775Sjfv#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 275230775Sjfv#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 276230775Sjfv (0x0A200 + ((_i) * 8))) 277230775Sjfv#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 278230775Sjfv (0x0A204 + ((_i) * 8))) 279230775Sjfv#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) 280230775Sjfv#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) 281179055Sjfv/* Packet split receive type */ 282230775Sjfv#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ 283230775Sjfv (0x0EA00 + ((_i) * 4))) 284179055Sjfv/* array of 4096 1-bit vlan filters */ 285230775Sjfv#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 286179055Sjfv/*array of 4096 4-bit vlan vmdq indices */ 287230775Sjfv#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 288230775Sjfv#define IXGBE_FCTRL 0x05080 289230775Sjfv#define IXGBE_VLNCTRL 0x05088 290230775Sjfv#define IXGBE_MCSTCTRL 0x05090 291230775Sjfv#define IXGBE_MRQC 0x05818 292230775Sjfv#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ 293230775Sjfv#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ 294230775Sjfv#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ 295230775Sjfv#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ 296230775Sjfv#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ 297230775Sjfv#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ 298230775Sjfv#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */ 299230775Sjfv#define IXGBE_RQTC 0x0EC70 300230775Sjfv#define IXGBE_MTQC 0x08120 301230775Sjfv#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */ 302230775Sjfv#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */ 303230775Sjfv#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */ 304230775Sjfv#define IXGBE_VT_CTL 0x051B0 305230775Sjfv#define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */ 306230775Sjfv/* 64 Mailboxes, 16 DW each */ 307230775Sjfv#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) 308230775Sjfv#define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ 309230775Sjfv#define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */ 310230775Sjfv#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) 311230775Sjfv#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) 312230775Sjfv#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4)) 313230775Sjfv#define IXGBE_QDE 0x2F04 314230775Sjfv#define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */ 315230775Sjfv#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */ 316230775Sjfv#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) 317230775Sjfv#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4)) 318230775Sjfv#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) 319230775Sjfv#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) 320230775Sjfv#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ 321230775Sjfv#define IXGBE_RXFECCERR0 0x051B8 322230775Sjfv#define IXGBE_LLITHRESH 0x0EC90 323230775Sjfv#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 324230775Sjfv#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 325230775Sjfv#define IXGBE_IMIRVP 0x05AC0 326230775Sjfv#define IXGBE_VMD_CTL 0x0581C 327230775Sjfv#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 328230775Sjfv#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 329171384Sjfv 330247822Sjfv 331190873Sjfv/* Flow Director registers */ 332230775Sjfv#define IXGBE_FDIRCTRL 0x0EE00 333230775Sjfv#define IXGBE_FDIRHKEY 0x0EE68 334230775Sjfv#define IXGBE_FDIRSKEY 0x0EE6C 335230775Sjfv#define IXGBE_FDIRDIP4M 0x0EE3C 336230775Sjfv#define IXGBE_FDIRSIP4M 0x0EE40 337230775Sjfv#define IXGBE_FDIRTCPM 0x0EE44 338230775Sjfv#define IXGBE_FDIRUDPM 0x0EE48 339230775Sjfv#define IXGBE_FDIRIP6M 0x0EE74 340230775Sjfv#define IXGBE_FDIRM 0x0EE70 341179055Sjfv 342190873Sjfv/* Flow Director Stats registers */ 343230775Sjfv#define IXGBE_FDIRFREE 0x0EE38 344230775Sjfv#define IXGBE_FDIRLEN 0x0EE4C 345230775Sjfv#define IXGBE_FDIRUSTAT 0x0EE50 346230775Sjfv#define IXGBE_FDIRFSTAT 0x0EE54 347230775Sjfv#define IXGBE_FDIRMATCH 0x0EE58 348230775Sjfv#define IXGBE_FDIRMISS 0x0EE5C 349190873Sjfv 350190873Sjfv/* Flow Director Programming registers */ 351190873Sjfv#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */ 352230775Sjfv#define IXGBE_FDIRIPSA 0x0EE18 353230775Sjfv#define IXGBE_FDIRIPDA 0x0EE1C 354230775Sjfv#define IXGBE_FDIRPORT 0x0EE20 355230775Sjfv#define IXGBE_FDIRVLAN 0x0EE24 356230775Sjfv#define IXGBE_FDIRHASH 0x0EE28 357230775Sjfv#define IXGBE_FDIRCMD 0x0EE2C 358190873Sjfv 359171384Sjfv/* Transmit DMA registers */ 360230775Sjfv#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/ 361230775Sjfv#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 362230775Sjfv#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 363230775Sjfv#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 364230775Sjfv#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 365230775Sjfv#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 366230775Sjfv#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 367230775Sjfv#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 368230775Sjfv#define IXGBE_DTXCTL 0x07E00 369179055Sjfv 370230775Sjfv#define IXGBE_DMATXCTL 0x04A80 371230775Sjfv#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */ 372230775Sjfv#define IXGBE_PFDTXGSWC 0x08220 373230775Sjfv#define IXGBE_DTXMXSZRQ 0x08100 374230775Sjfv#define IXGBE_DTXTCPFLGL 0x04A88 375230775Sjfv#define IXGBE_DTXTCPFLGH 0x04A8C 376230775Sjfv#define IXGBE_LBDRPEN 0x0CA00 377230775Sjfv#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */ 378190873Sjfv 379230775Sjfv#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ 380230775Sjfv#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ 381230775Sjfv#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ 382230775Sjfv#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ 383194875Sjfv 384230775Sjfv#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ 385215911Sjfv 386215911Sjfv/* Anti-spoofing defines */ 387230775Sjfv#define IXGBE_SPOOF_MACAS_MASK 0xFF 388230775Sjfv#define IXGBE_SPOOF_VLANAS_MASK 0xFF00 389230775Sjfv#define IXGBE_SPOOF_VLANAS_SHIFT 8 390230775Sjfv#define IXGBE_PFVFSPOOF_REG_COUNT 8 391230775Sjfv/* 16 of these (0-15) */ 392230775Sjfv#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) 393190873Sjfv/* Tx DCA Control register : 128 of these (0-127) */ 394230775Sjfv#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) 395230775Sjfv#define IXGBE_TIPG 0x0CB00 396230775Sjfv#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ 397230775Sjfv#define IXGBE_MNGTXMAP 0x0CD10 398230775Sjfv#define IXGBE_TIPG_FIBER_DEFAULT 3 399230775Sjfv#define IXGBE_TXPBSIZE_SHIFT 10 400171384Sjfv 401171384Sjfv/* Wake up registers */ 402230775Sjfv#define IXGBE_WUC 0x05800 403230775Sjfv#define IXGBE_WUFC 0x05808 404230775Sjfv#define IXGBE_WUS 0x05810 405230775Sjfv#define IXGBE_IPAV 0x05838 406230775Sjfv#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 407230775Sjfv#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 408185352Sjfv 409230775Sjfv#define IXGBE_WUPL 0x05900 410230775Sjfv#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 411247822Sjfv 412230775Sjfv#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */ 413230775Sjfv/* Ext Flexible Host Filter Table */ 414230775Sjfv#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) 415171384Sjfv 416247822Sjfv/* Four Flexible Filters are supported */ 417230775Sjfv#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 418247822Sjfv 419247822Sjfv/* Six Flexible Filters are supported */ 420247822Sjfv#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6 421230775Sjfv#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 422185352Sjfv 423185352Sjfv/* Each Flexible Filter is at most 128 (0x80) bytes in length */ 424230775Sjfv#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 425230775Sjfv#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ 426230775Sjfv#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ 427185352Sjfv 428185352Sjfv/* Definitions for power management and wakeup registers */ 429185352Sjfv/* Wake Up Control */ 430230775Sjfv#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ 431230775Sjfv#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ 432230775Sjfv#define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */ 433185352Sjfv 434185352Sjfv/* Wake Up Filter Control */ 435230775Sjfv#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 436230775Sjfv#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 437230775Sjfv#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 438230775Sjfv#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 439230775Sjfv#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 440230775Sjfv#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 441230775Sjfv#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 442230775Sjfv#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 443230775Sjfv#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */ 444185352Sjfv 445230775Sjfv#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 446230775Sjfv#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 447230775Sjfv#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 448230775Sjfv#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 449230775Sjfv#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 450230775Sjfv#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ 451230775Sjfv#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ 452247822Sjfv#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ 453230775Sjfv/* Mask for Ext. flex filters */ 454230775Sjfv#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 455247822Sjfv#define IXGBE_WUFC_ALL_FILTERS 0x000F00FF /* Mask all 4 flex filters */ 456247822Sjfv#define IXGBE_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 flex filters */ 457230775Sjfv#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 458185352Sjfv 459185352Sjfv/* Wake Up Status */ 460230775Sjfv#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC 461230775Sjfv#define IXGBE_WUS_MAG IXGBE_WUFC_MAG 462230775Sjfv#define IXGBE_WUS_EX IXGBE_WUFC_EX 463230775Sjfv#define IXGBE_WUS_MC IXGBE_WUFC_MC 464230775Sjfv#define IXGBE_WUS_BC IXGBE_WUFC_BC 465230775Sjfv#define IXGBE_WUS_ARP IXGBE_WUFC_ARP 466230775Sjfv#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4 467230775Sjfv#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6 468230775Sjfv#define IXGBE_WUS_MNG IXGBE_WUFC_MNG 469230775Sjfv#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0 470230775Sjfv#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1 471230775Sjfv#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2 472230775Sjfv#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3 473230775Sjfv#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4 474230775Sjfv#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5 475230775Sjfv#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS 476185352Sjfv 477230775Sjfv#define IXGBE_WUPL_LENGTH_MASK 0xFFFF 478185352Sjfv 479185352Sjfv/* DCB registers */ 480230775Sjfv#define IXGBE_DCB_MAX_TRAFFIC_CLASS 8 481230775Sjfv#define IXGBE_RMCS 0x03D00 482230775Sjfv#define IXGBE_DPMCS 0x07F40 483230775Sjfv#define IXGBE_PDPMCS 0x0CD00 484230775Sjfv#define IXGBE_RUPPBMR 0x050A0 485230775Sjfv#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 486230775Sjfv#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 487230775Sjfv#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 488230775Sjfv#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 489230775Sjfv#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 490230775Sjfv#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 491171384Sjfv 492179055Sjfv 493251964Sjfv 494190873Sjfv/* Security Control Registers */ 495230775Sjfv#define IXGBE_SECTXCTRL 0x08800 496230775Sjfv#define IXGBE_SECTXSTAT 0x08804 497230775Sjfv#define IXGBE_SECTXBUFFAF 0x08808 498230775Sjfv#define IXGBE_SECTXMINIFG 0x08810 499230775Sjfv#define IXGBE_SECRXCTRL 0x08D00 500230775Sjfv#define IXGBE_SECRXSTAT 0x08D04 501179055Sjfv 502190873Sjfv/* Security Bit Fields and Masks */ 503230775Sjfv#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001 504230775Sjfv#define IXGBE_SECTXCTRL_TX_DIS 0x00000002 505230775Sjfv#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004 506190873Sjfv 507230775Sjfv#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001 508230775Sjfv#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002 509190873Sjfv 510230775Sjfv#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001 511230775Sjfv#define IXGBE_SECRXCTRL_RX_DIS 0x00000002 512190873Sjfv 513230775Sjfv#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001 514230775Sjfv#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002 515190873Sjfv 516190873Sjfv/* LinkSec (MacSec) Registers */ 517230775Sjfv#define IXGBE_LSECTXCAP 0x08A00 518230775Sjfv#define IXGBE_LSECRXCAP 0x08F00 519230775Sjfv#define IXGBE_LSECTXCTRL 0x08A04 520230775Sjfv#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ 521230775Sjfv#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ 522230775Sjfv#define IXGBE_LSECTXSA 0x08A10 523230775Sjfv#define IXGBE_LSECTXPN0 0x08A14 524230775Sjfv#define IXGBE_LSECTXPN1 0x08A18 525230775Sjfv#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ 526230775Sjfv#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ 527230775Sjfv#define IXGBE_LSECRXCTRL 0x08F04 528230775Sjfv#define IXGBE_LSECRXSCL 0x08F08 529230775Sjfv#define IXGBE_LSECRXSCH 0x08F0C 530230775Sjfv#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ 531230775Sjfv#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ 532230775Sjfv#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) 533230775Sjfv#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */ 534230775Sjfv#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */ 535230775Sjfv#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */ 536230775Sjfv#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */ 537230775Sjfv#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */ 538230775Sjfv#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */ 539230775Sjfv#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */ 540230775Sjfv#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */ 541230775Sjfv#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */ 542230775Sjfv#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */ 543230775Sjfv#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */ 544230775Sjfv#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */ 545230775Sjfv#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */ 546230775Sjfv#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */ 547230775Sjfv#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ 548230775Sjfv#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ 549230775Sjfv#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ 550230775Sjfv#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */ 551230775Sjfv#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */ 552190873Sjfv 553190873Sjfv/* LinkSec (MacSec) Bit Fields and Masks */ 554230775Sjfv#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000 555230775Sjfv#define IXGBE_LSECTXCAP_SUM_SHIFT 16 556230775Sjfv#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000 557230775Sjfv#define IXGBE_LSECRXCAP_SUM_SHIFT 16 558190873Sjfv 559230775Sjfv#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003 560230775Sjfv#define IXGBE_LSECTXCTRL_DISABLE 0x0 561230775Sjfv#define IXGBE_LSECTXCTRL_AUTH 0x1 562230775Sjfv#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2 563230775Sjfv#define IXGBE_LSECTXCTRL_AISCI 0x00000020 564230775Sjfv#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 565230775Sjfv#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8 566190873Sjfv 567230775Sjfv#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C 568230775Sjfv#define IXGBE_LSECRXCTRL_EN_SHIFT 2 569230775Sjfv#define IXGBE_LSECRXCTRL_DISABLE 0x0 570230775Sjfv#define IXGBE_LSECRXCTRL_CHECK 0x1 571230775Sjfv#define IXGBE_LSECRXCTRL_STRICT 0x2 572230775Sjfv#define IXGBE_LSECRXCTRL_DROP 0x3 573230775Sjfv#define IXGBE_LSECRXCTRL_PLSH 0x00000040 574230775Sjfv#define IXGBE_LSECRXCTRL_RP 0x00000080 575230775Sjfv#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 576190873Sjfv 577190873Sjfv/* IpSec Registers */ 578230775Sjfv#define IXGBE_IPSTXIDX 0x08900 579230775Sjfv#define IXGBE_IPSTXSALT 0x08904 580230775Sjfv#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ 581230775Sjfv#define IXGBE_IPSRXIDX 0x08E00 582230775Sjfv#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ 583230775Sjfv#define IXGBE_IPSRXSPI 0x08E14 584230775Sjfv#define IXGBE_IPSRXIPIDX 0x08E18 585230775Sjfv#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ 586230775Sjfv#define IXGBE_IPSRXSALT 0x08E2C 587230775Sjfv#define IXGBE_IPSRXMOD 0x08E30 588190873Sjfv 589230775Sjfv#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 590190873Sjfv 591190873Sjfv/* DCB registers */ 592230775Sjfv#define IXGBE_RTRPCS 0x02430 593230775Sjfv#define IXGBE_RTTDCS 0x04900 594230775Sjfv#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 595230775Sjfv#define IXGBE_RTTPCS 0x0CD00 596230775Sjfv#define IXGBE_RTRUP2TC 0x03020 597230775Sjfv#define IXGBE_RTTUP2TC 0x0C800 598230775Sjfv#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */ 599230775Sjfv#define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */ 600230775Sjfv#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */ 601230775Sjfv#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */ 602230775Sjfv#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */ 603230775Sjfv#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 604230775Sjfv#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 605230775Sjfv#define IXGBE_RTTDQSEL 0x04904 606230775Sjfv#define IXGBE_RTTDT1C 0x04908 607230775Sjfv#define IXGBE_RTTDT1S 0x0490C 608230775Sjfv#define IXGBE_RTTDTECC 0x04990 609230775Sjfv#define IXGBE_RTTDTECC_NO_BCN 0x00000100 610190873Sjfv 611230775Sjfv#define IXGBE_RTTBCNRC 0x04984 612230775Sjfv#define IXGBE_RTTBCNRC_RS_ENA 0x80000000 613230775Sjfv#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF 614230775Sjfv#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 615217593Sjfv#define IXGBE_RTTBCNRC_RF_INT_MASK \ 616217593Sjfv (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT) 617230775Sjfv#define IXGBE_RTTBCNRM 0x04980 618190873Sjfv 619190873Sjfv/* BCN (for DCB) Registers */ 620230775Sjfv#define IXGBE_RTTBCNRS 0x04988 621230775Sjfv#define IXGBE_RTTBCNCR 0x08B00 622230775Sjfv#define IXGBE_RTTBCNACH 0x08B04 623230775Sjfv#define IXGBE_RTTBCNACL 0x08B08 624230775Sjfv#define IXGBE_RTTBCNTG 0x04A90 625230775Sjfv#define IXGBE_RTTBCNIDX 0x08B0C 626230775Sjfv#define IXGBE_RTTBCNCP 0x08B10 627230775Sjfv#define IXGBE_RTFRTIMER 0x08B14 628230775Sjfv#define IXGBE_RTTBCNRTT 0x05150 629230775Sjfv#define IXGBE_RTTBCNRD 0x0498C 630190873Sjfv 631247822Sjfv 632190873Sjfv/* FCoE DMA Context Registers */ 633230775Sjfv#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ 634230775Sjfv#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ 635230775Sjfv#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ 636230775Sjfv#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ 637230775Sjfv#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ 638230775Sjfv#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */ 639230775Sjfv#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */ 640230775Sjfv#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ 641230775Sjfv#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ 642230775Sjfv#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 643230775Sjfv#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 644230775Sjfv#define IXGBE_FCBUFF_OFFSET_SHIFT 16 645230775Sjfv#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */ 646230775Sjfv#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */ 647230775Sjfv#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ 648230775Sjfv#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ 649230775Sjfv#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 650190873Sjfv/* FCoE SOF/EOF */ 651230775Sjfv#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */ 652230775Sjfv#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */ 653230775Sjfv#define IXGBE_REOFF 0x05158 /* Rx FC EOF */ 654230775Sjfv#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */ 655190873Sjfv/* FCoE Filter Context Registers */ 656230775Sjfv#define IXGBE_FCFLT 0x05108 /* FC FLT Context */ 657230775Sjfv#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ 658230775Sjfv#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ 659230775Sjfv#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */ 660230775Sjfv#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */ 661230775Sjfv#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ 662230775Sjfv#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ 663230775Sjfv#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */ 664230775Sjfv#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */ 665230775Sjfv#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */ 666190873Sjfv/* FCoE Receive Control */ 667230775Sjfv#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ 668230775Sjfv#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */ 669230775Sjfv#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */ 670230775Sjfv#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */ 671230775Sjfv#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */ 672230775Sjfv#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */ 673230775Sjfv#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */ 674230775Sjfv#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */ 675230775Sjfv#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */ 676230775Sjfv#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ 677230775Sjfv#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 678190873Sjfv/* FCoE Redirection */ 679230775Sjfv#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */ 680230775Sjfv#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */ 681230775Sjfv#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ 682230775Sjfv#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */ 683230775Sjfv#define IXGBE_FCRETASEL_ENA 0x2 /* FCoE FCRETASEL bit */ 684230775Sjfv#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */ 685230775Sjfv#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */ 686190873Sjfv 687171384Sjfv/* Stats registers */ 688230775Sjfv#define IXGBE_CRCERRS 0x04000 689230775Sjfv#define IXGBE_ILLERRC 0x04004 690230775Sjfv#define IXGBE_ERRBC 0x04008 691230775Sjfv#define IXGBE_MSPDC 0x04010 692230775Sjfv#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 693230775Sjfv#define IXGBE_MLFC 0x04034 694230775Sjfv#define IXGBE_MRFC 0x04038 695230775Sjfv#define IXGBE_RLEC 0x04040 696230775Sjfv#define IXGBE_LXONTXC 0x03F60 697230775Sjfv#define IXGBE_LXONRXC 0x0CF60 698230775Sjfv#define IXGBE_LXOFFTXC 0x03F68 699230775Sjfv#define IXGBE_LXOFFRXC 0x0CF68 700230775Sjfv#define IXGBE_LXONRXCNT 0x041A4 701230775Sjfv#define IXGBE_LXOFFRXCNT 0x041A8 702230775Sjfv#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */ 703230775Sjfv#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */ 704230775Sjfv#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */ 705230775Sjfv#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 706230775Sjfv#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 707230775Sjfv#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 708230775Sjfv#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 709230775Sjfv#define IXGBE_PRC64 0x0405C 710230775Sjfv#define IXGBE_PRC127 0x04060 711230775Sjfv#define IXGBE_PRC255 0x04064 712230775Sjfv#define IXGBE_PRC511 0x04068 713230775Sjfv#define IXGBE_PRC1023 0x0406C 714230775Sjfv#define IXGBE_PRC1522 0x04070 715230775Sjfv#define IXGBE_GPRC 0x04074 716230775Sjfv#define IXGBE_BPRC 0x04078 717230775Sjfv#define IXGBE_MPRC 0x0407C 718230775Sjfv#define IXGBE_GPTC 0x04080 719230775Sjfv#define IXGBE_GORCL 0x04088 720230775Sjfv#define IXGBE_GORCH 0x0408C 721230775Sjfv#define IXGBE_GOTCL 0x04090 722230775Sjfv#define IXGBE_GOTCH 0x04094 723230775Sjfv#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 724230775Sjfv#define IXGBE_RUC 0x040A4 725230775Sjfv#define IXGBE_RFC 0x040A8 726230775Sjfv#define IXGBE_ROC 0x040AC 727230775Sjfv#define IXGBE_RJC 0x040B0 728230775Sjfv#define IXGBE_MNGPRC 0x040B4 729230775Sjfv#define IXGBE_MNGPDC 0x040B8 730230775Sjfv#define IXGBE_MNGPTC 0x0CF90 731230775Sjfv#define IXGBE_TORL 0x040C0 732230775Sjfv#define IXGBE_TORH 0x040C4 733230775Sjfv#define IXGBE_TPR 0x040D0 734230775Sjfv#define IXGBE_TPT 0x040D4 735230775Sjfv#define IXGBE_PTC64 0x040D8 736230775Sjfv#define IXGBE_PTC127 0x040DC 737230775Sjfv#define IXGBE_PTC255 0x040E0 738230775Sjfv#define IXGBE_PTC511 0x040E4 739230775Sjfv#define IXGBE_PTC1023 0x040E8 740230775Sjfv#define IXGBE_PTC1522 0x040EC 741230775Sjfv#define IXGBE_MPTC 0x040F0 742230775Sjfv#define IXGBE_BPTC 0x040F4 743230775Sjfv#define IXGBE_XEC 0x04120 744230775Sjfv#define IXGBE_SSVPC 0x08780 745171384Sjfv 746230775Sjfv#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) 747230775Sjfv#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ 748230775Sjfv (0x08600 + ((_i) * 4))) 749230775Sjfv#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) 750171384Sjfv 751230775Sjfv#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 752230775Sjfv#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 753230775Sjfv#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 754230775Sjfv#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 755230775Sjfv#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 756230775Sjfv#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */ 757230775Sjfv#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ 758230775Sjfv#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ 759230775Sjfv#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ 760230775Sjfv#define IXGBE_FCCRC 0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */ 761230775Sjfv#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ 762230775Sjfv#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ 763230775Sjfv#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ 764230775Sjfv#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ 765230775Sjfv#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ 766230775Sjfv#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ 767230775Sjfv#define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */ 768230775Sjfv#define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */ 769230775Sjfv#define IXGBE_O2BGPTC 0x041C4 770230775Sjfv#define IXGBE_O2BSPC 0x087B0 771230775Sjfv#define IXGBE_B2OSPC 0x041C0 772230775Sjfv#define IXGBE_B2OGPRC 0x02F90 773230775Sjfv#define IXGBE_BUPRC 0x04180 774230775Sjfv#define IXGBE_BMPRC 0x04184 775230775Sjfv#define IXGBE_BBPRC 0x04188 776230775Sjfv#define IXGBE_BUPTC 0x0418C 777230775Sjfv#define IXGBE_BMPTC 0x04190 778230775Sjfv#define IXGBE_BBPTC 0x04194 779230775Sjfv#define IXGBE_BCRCERRS 0x04198 780230775Sjfv#define IXGBE_BXONRXC 0x0419C 781230775Sjfv#define IXGBE_BXOFFRXC 0x041E0 782230775Sjfv#define IXGBE_BXONTXC 0x041E4 783230775Sjfv#define IXGBE_BXOFFTXC 0x041E8 784230775Sjfv#define IXGBE_PCRC8ECL 0x0E810 785230775Sjfv#define IXGBE_PCRC8ECH 0x0E811 786230775Sjfv#define IXGBE_PCRC8ECH_MASK 0x1F 787230775Sjfv#define IXGBE_LDPCECL 0x0E820 788230775Sjfv#define IXGBE_LDPCECH 0x0E821 789171384Sjfv 790171384Sjfv/* Management */ 791230775Sjfv#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 792230775Sjfv#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 793230775Sjfv#define IXGBE_MANC 0x05820 794230775Sjfv#define IXGBE_MFVAL 0x05824 795230775Sjfv#define IXGBE_MANC2H 0x05860 796230775Sjfv#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 797230775Sjfv#define IXGBE_MIPAF 0x058B0 798230775Sjfv#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 799230775Sjfv#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 800230775Sjfv#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 801230775Sjfv#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ 802230775Sjfv#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ 803230775Sjfv#define IXGBE_LSWFW 0x15014 804230775Sjfv#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */ 805230775Sjfv#define IXGBE_BMCIPVAL 0x05060 806230775Sjfv#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001 807230775Sjfv#define IXGBE_BMCIP_IPADDR_VALID 0x00000002 808171384Sjfv 809230775Sjfv/* Management Bit Fields and Masks */ 810247822Sjfv#define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */ 811230775Sjfv#define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Ena BMC2OS and OS2BMC traffic */ 812230775Sjfv#define IXGBE_MANC_EN_BMC2OS_SHIFT 28 813230775Sjfv 814230775Sjfv/* Firmware Semaphore Register */ 815230775Sjfv#define IXGBE_FWSM_MODE_MASK 0xE 816247822Sjfv#define IXGBE_FWSM_TS_ENABLED 0x1 817247822Sjfv#define IXGBE_FWSM_FW_MODE_PT 0x4 818230775Sjfv 819171384Sjfv/* ARC Subsystem registers */ 820230775Sjfv#define IXGBE_HICR 0x15F00 821230775Sjfv#define IXGBE_FWSTS 0x15F0C 822230775Sjfv#define IXGBE_HSMC0R 0x15F04 823230775Sjfv#define IXGBE_HSMC1R 0x15F08 824230775Sjfv#define IXGBE_SWSR 0x15F10 825230775Sjfv#define IXGBE_HFDR 0x15FE8 826230775Sjfv#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 827171384Sjfv 828230775Sjfv#define IXGBE_HICR_EN 0x01 /* Enable bit - RO */ 829230775Sjfv/* Driver sets this bit when done to put command in RAM */ 830230775Sjfv#define IXGBE_HICR_C 0x02 831230775Sjfv#define IXGBE_HICR_SV 0x04 /* Status Validity */ 832230775Sjfv#define IXGBE_HICR_FW_RESET_ENABLE 0x40 833230775Sjfv#define IXGBE_HICR_FW_RESET 0x80 834230775Sjfv 835171384Sjfv/* PCI-E registers */ 836230775Sjfv#define IXGBE_GCR 0x11000 837230775Sjfv#define IXGBE_GTV 0x11004 838230775Sjfv#define IXGBE_FUNCTAG 0x11008 839230775Sjfv#define IXGBE_GLT 0x1100C 840230775Sjfv#define IXGBE_PCIEPIPEADR 0x11004 841230775Sjfv#define IXGBE_PCIEPIPEDAT 0x11008 842230775Sjfv#define IXGBE_GSCL_1 0x11010 843230775Sjfv#define IXGBE_GSCL_2 0x11014 844230775Sjfv#define IXGBE_GSCL_3 0x11018 845230775Sjfv#define IXGBE_GSCL_4 0x1101C 846230775Sjfv#define IXGBE_GSCN_0 0x11020 847230775Sjfv#define IXGBE_GSCN_1 0x11024 848230775Sjfv#define IXGBE_GSCN_2 0x11028 849230775Sjfv#define IXGBE_GSCN_3 0x1102C 850230775Sjfv#define IXGBE_FACTPS 0x10150 851230775Sjfv#define IXGBE_PCIEANACTL 0x11040 852230775Sjfv#define IXGBE_SWSM 0x10140 853230775Sjfv#define IXGBE_FWSM 0x10148 854230775Sjfv#define IXGBE_GSSR 0x10160 855230775Sjfv#define IXGBE_MREVID 0x11064 856230775Sjfv#define IXGBE_DCA_ID 0x11070 857230775Sjfv#define IXGBE_DCA_CTRL 0x11074 858230775Sjfv#define IXGBE_SWFW_SYNC IXGBE_GSSR 859171384Sjfv 860190873Sjfv/* PCI-E registers 82599-Specific */ 861230775Sjfv#define IXGBE_GCR_EXT 0x11050 862230775Sjfv#define IXGBE_GSCL_5_82599 0x11030 863230775Sjfv#define IXGBE_GSCL_6_82599 0x11034 864230775Sjfv#define IXGBE_GSCL_7_82599 0x11038 865230775Sjfv#define IXGBE_GSCL_8_82599 0x1103C 866230775Sjfv#define IXGBE_PHYADR_82599 0x11040 867230775Sjfv#define IXGBE_PHYDAT_82599 0x11044 868230775Sjfv#define IXGBE_PHYCTL_82599 0x11048 869230775Sjfv#define IXGBE_PBACLR_82599 0x11068 870230775Sjfv#define IXGBE_CIAA_82599 0x11088 871230775Sjfv#define IXGBE_CIAD_82599 0x1108C 872230775Sjfv#define IXGBE_PICAUSE 0x110B0 873230775Sjfv#define IXGBE_PIENA 0x110B8 874230775Sjfv#define IXGBE_CDQ_MBR_82599 0x110B4 875230775Sjfv#define IXGBE_PCIESPARE 0x110BC 876230775Sjfv#define IXGBE_MISC_REG_82599 0x110F0 877230775Sjfv#define IXGBE_ECC_CTRL_0_82599 0x11100 878230775Sjfv#define IXGBE_ECC_CTRL_1_82599 0x11104 879230775Sjfv#define IXGBE_ECC_STATUS_82599 0x110E0 880230775Sjfv#define IXGBE_BAR_CTRL_82599 0x110F4 881190873Sjfv 882200239Sjfv/* PCI Express Control */ 883230775Sjfv#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 884230775Sjfv#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 885230775Sjfv#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 886230775Sjfv#define IXGBE_GCR_CAP_VER2 0x00040000 887200239Sjfv 888230775Sjfv#define IXGBE_GCR_EXT_MSIX_EN 0x80000000 889230775Sjfv#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000 890230775Sjfv#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001 891230775Sjfv#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002 892230775Sjfv#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003 893230775Sjfv#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \ 894230775Sjfv IXGBE_GCR_EXT_VT_MODE_64) 895238149Sjfv#define IXGBE_GCR_EXT_VT_MODE_MASK 0x00000003 896190873Sjfv/* Time Sync Registers */ 897230775Sjfv#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ 898230775Sjfv#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ 899230775Sjfv#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */ 900230775Sjfv#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */ 901230775Sjfv#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */ 902230775Sjfv#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */ 903230775Sjfv#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */ 904230775Sjfv#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */ 905230775Sjfv#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */ 906230775Sjfv#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */ 907230775Sjfv#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */ 908230775Sjfv#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */ 909230775Sjfv#define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */ 910230775Sjfv#define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */ 911230775Sjfv#define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */ 912230775Sjfv#define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */ 913230775Sjfv#define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */ 914230775Sjfv#define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */ 915230775Sjfv#define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */ 916238149Sjfv#define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */ 917238149Sjfv#define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */ 918230775Sjfv#define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */ 919230775Sjfv#define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */ 920230775Sjfv#define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */ 921230775Sjfv#define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */ 922230775Sjfv#define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */ 923230775Sjfv#define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */ 924190873Sjfv 925171384Sjfv/* Diagnostic Registers */ 926230775Sjfv#define IXGBE_RDSTATCTL 0x02C20 927230775Sjfv#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 928230775Sjfv#define IXGBE_RDHMPN 0x02F08 929230775Sjfv#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) 930230775Sjfv#define IXGBE_RDPROBE 0x02F20 931230775Sjfv#define IXGBE_RDMAM 0x02F30 932230775Sjfv#define IXGBE_RDMAD 0x02F34 933230775Sjfv#define IXGBE_TDHMPN 0x07F08 934230775Sjfv#define IXGBE_TDHMPN2 0x082FC 935230775Sjfv#define IXGBE_TXDESCIC 0x082CC 936230775Sjfv#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) 937230775Sjfv#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4)) 938230775Sjfv#define IXGBE_TDPROBE 0x07F20 939230775Sjfv#define IXGBE_TXBUFCTRL 0x0C600 940230775Sjfv#define IXGBE_TXBUFDATA0 0x0C610 941230775Sjfv#define IXGBE_TXBUFDATA1 0x0C614 942230775Sjfv#define IXGBE_TXBUFDATA2 0x0C618 943230775Sjfv#define IXGBE_TXBUFDATA3 0x0C61C 944230775Sjfv#define IXGBE_RXBUFCTRL 0x03600 945230775Sjfv#define IXGBE_RXBUFDATA0 0x03610 946230775Sjfv#define IXGBE_RXBUFDATA1 0x03614 947230775Sjfv#define IXGBE_RXBUFDATA2 0x03618 948230775Sjfv#define IXGBE_RXBUFDATA3 0x0361C 949230775Sjfv#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 950230775Sjfv#define IXGBE_RFVAL 0x050A4 951230775Sjfv#define IXGBE_MDFTC1 0x042B8 952230775Sjfv#define IXGBE_MDFTC2 0x042C0 953230775Sjfv#define IXGBE_MDFTFIFO1 0x042C4 954230775Sjfv#define IXGBE_MDFTFIFO2 0x042C8 955230775Sjfv#define IXGBE_MDFTS 0x042CC 956230775Sjfv#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 957230775Sjfv#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 958230775Sjfv#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 959230775Sjfv#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 960230775Sjfv#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 961230775Sjfv#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 962230775Sjfv#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 963230775Sjfv#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 964230775Sjfv#define IXGBE_PCIEECCCTL 0x1106C 965230775Sjfv#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ 966230775Sjfv#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ 967230775Sjfv#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ 968230775Sjfv#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ 969230775Sjfv#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ 970230775Sjfv#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ 971230775Sjfv#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ 972230775Sjfv#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ 973230775Sjfv#define IXGBE_PCIEECCCTL0 0x11100 974230775Sjfv#define IXGBE_PCIEECCCTL1 0x11104 975230775Sjfv#define IXGBE_RXDBUECC 0x03F70 976230775Sjfv#define IXGBE_TXDBUECC 0x0CF70 977230775Sjfv#define IXGBE_RXDBUEST 0x03F74 978230775Sjfv#define IXGBE_TXDBUEST 0x0CF74 979230775Sjfv#define IXGBE_PBTXECC 0x0C300 980230775Sjfv#define IXGBE_PBRXECC 0x03300 981230775Sjfv#define IXGBE_GHECCR 0x110B0 982171384Sjfv 983171384Sjfv/* MAC Registers */ 984230775Sjfv#define IXGBE_PCS1GCFIG 0x04200 985230775Sjfv#define IXGBE_PCS1GLCTL 0x04208 986230775Sjfv#define IXGBE_PCS1GLSTA 0x0420C 987230775Sjfv#define IXGBE_PCS1GDBG0 0x04210 988230775Sjfv#define IXGBE_PCS1GDBG1 0x04214 989230775Sjfv#define IXGBE_PCS1GANA 0x04218 990230775Sjfv#define IXGBE_PCS1GANLP 0x0421C 991230775Sjfv#define IXGBE_PCS1GANNP 0x04220 992230775Sjfv#define IXGBE_PCS1GANLPNP 0x04224 993230775Sjfv#define IXGBE_HLREG0 0x04240 994230775Sjfv#define IXGBE_HLREG1 0x04244 995230775Sjfv#define IXGBE_PAP 0x04248 996230775Sjfv#define IXGBE_MACA 0x0424C 997230775Sjfv#define IXGBE_APAE 0x04250 998230775Sjfv#define IXGBE_ARD 0x04254 999230775Sjfv#define IXGBE_AIS 0x04258 1000230775Sjfv#define IXGBE_MSCA 0x0425C 1001230775Sjfv#define IXGBE_MSRWD 0x04260 1002230775Sjfv#define IXGBE_MLADD 0x04264 1003230775Sjfv#define IXGBE_MHADD 0x04268 1004230775Sjfv#define IXGBE_MAXFRS 0x04268 1005230775Sjfv#define IXGBE_TREG 0x0426C 1006230775Sjfv#define IXGBE_PCSS1 0x04288 1007230775Sjfv#define IXGBE_PCSS2 0x0428C 1008230775Sjfv#define IXGBE_XPCSS 0x04290 1009230775Sjfv#define IXGBE_MFLCN 0x04294 1010230775Sjfv#define IXGBE_SERDESC 0x04298 1011230775Sjfv#define IXGBE_MACS 0x0429C 1012230775Sjfv#define IXGBE_AUTOC 0x042A0 1013230775Sjfv#define IXGBE_LINKS 0x042A4 1014230775Sjfv#define IXGBE_LINKS2 0x04324 1015230775Sjfv#define IXGBE_AUTOC2 0x042A8 1016230775Sjfv#define IXGBE_AUTOC3 0x042AC 1017230775Sjfv#define IXGBE_ANLP1 0x042B0 1018230775Sjfv#define IXGBE_ANLP2 0x042B4 1019230775Sjfv#define IXGBE_MACC 0x04330 1020230775Sjfv#define IXGBE_ATLASCTL 0x04800 1021230775Sjfv#define IXGBE_MMNGC 0x042D0 1022230775Sjfv#define IXGBE_ANLPNP1 0x042D4 1023230775Sjfv#define IXGBE_ANLPNP2 0x042D8 1024230775Sjfv#define IXGBE_KRPCSFC 0x042E0 1025230775Sjfv#define IXGBE_KRPCSS 0x042E4 1026230775Sjfv#define IXGBE_FECS1 0x042E8 1027230775Sjfv#define IXGBE_FECS2 0x042EC 1028230775Sjfv#define IXGBE_SMADARCTL 0x14F10 1029230775Sjfv#define IXGBE_MPVC 0x04318 1030230775Sjfv#define IXGBE_SGMIIC 0x04314 1031171384Sjfv 1032230775Sjfv/* Statistics Registers */ 1033230775Sjfv#define IXGBE_RXNFGPC 0x041B0 1034230775Sjfv#define IXGBE_RXNFGBCL 0x041B4 1035230775Sjfv#define IXGBE_RXNFGBCH 0x041B8 1036230775Sjfv#define IXGBE_RXDGPC 0x02F50 1037230775Sjfv#define IXGBE_RXDGBCL 0x02F54 1038230775Sjfv#define IXGBE_RXDGBCH 0x02F58 1039230775Sjfv#define IXGBE_RXDDGPC 0x02F5C 1040230775Sjfv#define IXGBE_RXDDGBCL 0x02F60 1041230775Sjfv#define IXGBE_RXDDGBCH 0x02F64 1042230775Sjfv#define IXGBE_RXLPBKGPC 0x02F68 1043230775Sjfv#define IXGBE_RXLPBKGBCL 0x02F6C 1044230775Sjfv#define IXGBE_RXLPBKGBCH 0x02F70 1045230775Sjfv#define IXGBE_RXDLPBKGPC 0x02F74 1046230775Sjfv#define IXGBE_RXDLPBKGBCL 0x02F78 1047230775Sjfv#define IXGBE_RXDLPBKGBCH 0x02F7C 1048230775Sjfv#define IXGBE_TXDGPC 0x087A0 1049230775Sjfv#define IXGBE_TXDGBCL 0x087A4 1050230775Sjfv#define IXGBE_TXDGBCH 0x087A8 1051230775Sjfv 1052230775Sjfv#define IXGBE_RXDSTATCTRL 0x02F40 1053230775Sjfv 1054200239Sjfv/* Copper Pond 2 link timeout */ 1055200239Sjfv#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50 1056200239Sjfv 1057190873Sjfv/* Omer CORECTL */ 1058230775Sjfv#define IXGBE_CORECTL 0x014F00 1059190873Sjfv/* BARCTRL */ 1060230775Sjfv#define IXGBE_BARCTRL 0x110F4 1061230775Sjfv#define IXGBE_BARCTRL_FLSIZE 0x0700 1062230775Sjfv#define IXGBE_BARCTRL_FLSIZE_SHIFT 8 1063230775Sjfv#define IXGBE_BARCTRL_CSRSIZE 0x2000 1064190873Sjfv 1065190873Sjfv/* RSCCTL Bit Masks */ 1066230775Sjfv#define IXGBE_RSCCTL_RSCEN 0x01 1067230775Sjfv#define IXGBE_RSCCTL_MAXDESC_1 0x00 1068230775Sjfv#define IXGBE_RSCCTL_MAXDESC_4 0x04 1069230775Sjfv#define IXGBE_RSCCTL_MAXDESC_8 0x08 1070230775Sjfv#define IXGBE_RSCCTL_MAXDESC_16 0x0C 1071247822Sjfv#define IXGBE_RSCCTL_TS_DIS 0x02 1072190873Sjfv 1073190873Sjfv/* RSCDBU Bit Masks */ 1074230775Sjfv#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F 1075230775Sjfv#define IXGBE_RSCDBU_RSCACKDIS 0x00000080 1076190873Sjfv 1077181003Sjfv/* RDRXCTL Bit Masks */ 1078230775Sjfv#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min THLD Size */ 1079230775Sjfv#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ 1080230775Sjfv#define IXGBE_RDRXCTL_MVMEN 0x00000020 1081251964Sjfv#define IXGBE_RDRXCTL_RSC_PUSH_DIS 0x00000020 1082230775Sjfv#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ 1083251964Sjfv#define IXGBE_RDRXCTL_RSC_PUSH 0x00000080 1084230775Sjfv#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ 1085230775Sjfv#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ 1086247822Sjfv#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI*/ 1087230775Sjfv#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC ena */ 1088230775Sjfv#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC ena */ 1089171384Sjfv 1090190873Sjfv/* RQTC Bit Masks and Shifts */ 1091230775Sjfv#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) 1092230775Sjfv#define IXGBE_RQTC_TC0_MASK (0x7 << 0) 1093230775Sjfv#define IXGBE_RQTC_TC1_MASK (0x7 << 4) 1094230775Sjfv#define IXGBE_RQTC_TC2_MASK (0x7 << 8) 1095230775Sjfv#define IXGBE_RQTC_TC3_MASK (0x7 << 12) 1096230775Sjfv#define IXGBE_RQTC_TC4_MASK (0x7 << 16) 1097230775Sjfv#define IXGBE_RQTC_TC5_MASK (0x7 << 20) 1098230775Sjfv#define IXGBE_RQTC_TC6_MASK (0x7 << 24) 1099230775Sjfv#define IXGBE_RQTC_TC7_MASK (0x7 << 28) 1100190873Sjfv 1101190873Sjfv/* PSRTYPE.RQPL Bit masks and shift */ 1102230775Sjfv#define IXGBE_PSRTYPE_RQPL_MASK 0x7 1103230775Sjfv#define IXGBE_PSRTYPE_RQPL_SHIFT 29 1104190873Sjfv 1105171384Sjfv/* CTRL Bit Masks */ 1106230775Sjfv#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ 1107230775Sjfv#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 1108230775Sjfv#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 1109230775Sjfv#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST) 1110171384Sjfv 1111171384Sjfv/* FACTPS */ 1112247822Sjfv#define IXGBE_FACTPS_MNGCG 0x20000000 /* Manageblility Clock Gated */ 1113230775Sjfv#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 1114171384Sjfv 1115171384Sjfv/* MHADD Bit Masks */ 1116230775Sjfv#define IXGBE_MHADD_MFS_MASK 0xFFFF0000 1117230775Sjfv#define IXGBE_MHADD_MFS_SHIFT 16 1118171384Sjfv 1119171384Sjfv/* Extended Device Control */ 1120230775Sjfv#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */ 1121230775Sjfv#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 1122230775Sjfv#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1123230775Sjfv#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1124171384Sjfv 1125171384Sjfv/* Direct Cache Access (DCA) definitions */ 1126230775Sjfv#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 1127230775Sjfv#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 1128171384Sjfv 1129230775Sjfv#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 1130230775Sjfv#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 1131171384Sjfv 1132230775Sjfv#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 1133230775Sjfv#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ 1134230775Sjfv#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ 1135230775Sjfv#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */ 1136230775Sjfv#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */ 1137230775Sjfv#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */ 1138230775Sjfv#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */ 1139238149Sjfv#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */ 1140238149Sjfv#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */ 1141171384Sjfv 1142230775Sjfv#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 1143230775Sjfv#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ 1144230775Sjfv#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ 1145230775Sjfv#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 1146238149Sjfv#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 1147238149Sjfv#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */ 1148238149Sjfv#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 1149230775Sjfv#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 1150171384Sjfv 1151171384Sjfv/* MSCA Bit Masks */ 1152230775Sjfv#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Addr (new prot) */ 1153230775Sjfv#define IXGBE_MSCA_NP_ADDR_SHIFT 0 1154230775Sjfv#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Dev Type (new prot) */ 1155230775Sjfv#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old prot */ 1156230775Sjfv#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 1157230775Sjfv#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 1158230775Sjfv#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 1159230775Sjfv#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 1160230775Sjfv#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 1161230775Sjfv#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (wr) */ 1162230775Sjfv#define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (rd) */ 1163230775Sjfv#define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (rd auto inc)*/ 1164230775Sjfv#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 1165230775Sjfv#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 1166230775Sjfv#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new prot) */ 1167230775Sjfv#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old prot) */ 1168230775Sjfv#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 1169230775Sjfv#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress ena */ 1170171384Sjfv 1171171384Sjfv/* MSRWD bit masks */ 1172230775Sjfv#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 1173230775Sjfv#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 1174230775Sjfv#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 1175230775Sjfv#define IXGBE_MSRWD_READ_DATA_SHIFT 16 1176171384Sjfv 1177172043Sjfv/* Atlas registers */ 1178230775Sjfv#define IXGBE_ATLAS_PDN_LPBK 0x24 1179230775Sjfv#define IXGBE_ATLAS_PDN_10G 0xB 1180230775Sjfv#define IXGBE_ATLAS_PDN_1G 0xC 1181230775Sjfv#define IXGBE_ATLAS_PDN_AN 0xD 1182172043Sjfv 1183172043Sjfv/* Atlas bit masks */ 1184230775Sjfv#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 1185230775Sjfv#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 1186230775Sjfv#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 1187230775Sjfv#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 1188230775Sjfv#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 1189172043Sjfv 1190190873Sjfv/* Omer bit masks */ 1191230775Sjfv#define IXGBE_CORECTL_WRITE_CMD 0x00010000 1192185352Sjfv 1193171384Sjfv/* Device Type definitions for new protocol MDIO commands */ 1194230775Sjfv#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 1195230775Sjfv#define IXGBE_MDIO_PCS_DEV_TYPE 0x3 1196230775Sjfv#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 1197230775Sjfv#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 1198230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ 1199230775Sjfv#define IXGBE_TWINAX_DEV 1 1200171384Sjfv 1201230775Sjfv#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 1202172043Sjfv 1203230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Ctrl Reg */ 1204230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 1205230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 1206230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0-10G, 1-1G */ 1207230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 1208230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 1209171384Sjfv 1210230775Sjfv#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ 1211230775Sjfv#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ 1212230775Sjfv#define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */ 1213230775Sjfv#define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */ 1214230775Sjfv#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */ 1215230775Sjfv#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ 1216230775Sjfv#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ 1217230775Sjfv#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ 1218230775Sjfv#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ 1219230775Sjfv#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ 1220230775Sjfv#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ 1221230775Sjfv#define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */ 1222230775Sjfv#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */ 1223230775Sjfv#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */ 1224230775Sjfv#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */ 1225230775Sjfv#define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */ 1226230775Sjfv#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */ 1227171384Sjfv 1228230775Sjfv#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */ 1229230775Sjfv#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ 1230230775Sjfv#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 1231230775Sjfv#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ 1232185352Sjfv 1233179055Sjfv/* MII clause 22/28 definitions */ 1234230775Sjfv#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 1235179055Sjfv 1236230775Sjfv#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */ 1237200239Sjfv#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ 1238230775Sjfv#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ 1239230775Sjfv#define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */ 1240230775Sjfv#define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/ 1241230775Sjfv#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ 1242230775Sjfv#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ 1243230775Sjfv#define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */ 1244230775Sjfv#define IXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */ 1245230775Sjfv#define IXGBE_MII_RESTART 0x200 1246230775Sjfv#define IXGBE_MII_AUTONEG_COMPLETE 0x20 1247230775Sjfv#define IXGBE_MII_AUTONEG_LINK_UP 0x04 1248230775Sjfv#define IXGBE_MII_AUTONEG_REG 0x0 1249179055Sjfv 1250230775Sjfv#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 1251230775Sjfv#define IXGBE_MAX_PHY_ADDR 32 1252171384Sjfv 1253171384Sjfv/* PHY IDs*/ 1254230775Sjfv#define TN1010_PHY_ID 0x00A19410 1255230775Sjfv#define TNX_FW_REV 0xB 1256230775Sjfv#define X540_PHY_ID 0x01540200 1257230775Sjfv#define AQ_FW_REV 0x20 1258230775Sjfv#define QT2022_PHY_ID 0x0043A400 1259230775Sjfv#define ATH_PHY_ID 0x03429050 1260171384Sjfv 1261179055Sjfv/* PHY Types */ 1262230775Sjfv#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 1263179055Sjfv 1264185352Sjfv/* Special PHY Init Routine */ 1265230775Sjfv#define IXGBE_PHY_INIT_OFFSET_NL 0x002B 1266230775Sjfv#define IXGBE_PHY_INIT_END_NL 0xFFFF 1267230775Sjfv#define IXGBE_CONTROL_MASK_NL 0xF000 1268230775Sjfv#define IXGBE_DATA_MASK_NL 0x0FFF 1269230775Sjfv#define IXGBE_CONTROL_SHIFT_NL 12 1270230775Sjfv#define IXGBE_DELAY_NL 0 1271230775Sjfv#define IXGBE_DATA_NL 1 1272230775Sjfv#define IXGBE_CONTROL_NL 0x000F 1273230775Sjfv#define IXGBE_CONTROL_EOL_NL 0x0FFF 1274230775Sjfv#define IXGBE_CONTROL_SOL_NL 0x0000 1275185352Sjfv 1276171384Sjfv/* General purpose Interrupt Enable */ 1277230775Sjfv#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 1278230775Sjfv#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ 1279230775Sjfv#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */ 1280230775Sjfv#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 1281230775Sjfv#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 1282230775Sjfv#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 1283230775Sjfv#define IXGBE_GPIE_EIAME 0x40000000 1284230775Sjfv#define IXGBE_GPIE_PBA_SUPPORT 0x80000000 1285230775Sjfv#define IXGBE_GPIE_RSC_DELAY_SHIFT 11 1286230775Sjfv#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */ 1287230775Sjfv#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */ 1288230775Sjfv#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */ 1289230775Sjfv#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */ 1290171384Sjfv 1291230775Sjfv/* Packet Buffer Initialization */ 1292230775Sjfv#define IXGBE_MAX_PACKET_BUFFERS 8 1293230775Sjfv 1294230775Sjfv#define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */ 1295230775Sjfv#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 1296230775Sjfv#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 1297230775Sjfv#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 1298230775Sjfv#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 1299230775Sjfv#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */ 1300230775Sjfv#define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer */ 1301230775Sjfv#define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer */ 1302230775Sjfv 1303230775Sjfv#define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 1304230775Sjfv#define IXGBE_MAX_PB 8 1305230775Sjfv 1306230775Sjfv/* Packet buffer allocation strategies */ 1307230775Sjfvenum { 1308230775Sjfv PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ 1309230775Sjfv#define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL 1310230775Sjfv PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ 1311230775Sjfv#define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED 1312230775Sjfv}; 1313230775Sjfv 1314171384Sjfv/* Transmit Flow Control status */ 1315230775Sjfv#define IXGBE_TFCS_TXOFF 0x00000001 1316230775Sjfv#define IXGBE_TFCS_TXOFF0 0x00000100 1317230775Sjfv#define IXGBE_TFCS_TXOFF1 0x00000200 1318230775Sjfv#define IXGBE_TFCS_TXOFF2 0x00000400 1319230775Sjfv#define IXGBE_TFCS_TXOFF3 0x00000800 1320230775Sjfv#define IXGBE_TFCS_TXOFF4 0x00001000 1321230775Sjfv#define IXGBE_TFCS_TXOFF5 0x00002000 1322230775Sjfv#define IXGBE_TFCS_TXOFF6 0x00004000 1323230775Sjfv#define IXGBE_TFCS_TXOFF7 0x00008000 1324171384Sjfv 1325171384Sjfv/* TCP Timer */ 1326230775Sjfv#define IXGBE_TCPTIMER_KS 0x00000100 1327230775Sjfv#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 1328230775Sjfv#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 1329230775Sjfv#define IXGBE_TCPTIMER_LOOP 0x00000800 1330230775Sjfv#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 1331171384Sjfv 1332171384Sjfv/* HLREG0 Bit Masks */ 1333230775Sjfv#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 1334230775Sjfv#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 1335230775Sjfv#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 1336230775Sjfv#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 1337230775Sjfv#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 1338230775Sjfv#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 1339230775Sjfv#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 1340230775Sjfv#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 1341230775Sjfv#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 1342230775Sjfv#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 1343230775Sjfv#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 1344230775Sjfv#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 1345230775Sjfv#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 1346230775Sjfv#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 1347230775Sjfv#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 1348171384Sjfv 1349171384Sjfv/* VMD_CTL bitmasks */ 1350230775Sjfv#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 1351230775Sjfv#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 1352171384Sjfv 1353190873Sjfv/* VT_CTL bitmasks */ 1354230775Sjfv#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ 1355230775Sjfv#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ 1356230775Sjfv#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ 1357230775Sjfv#define IXGBE_VT_CTL_POOL_SHIFT 7 1358230775Sjfv#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) 1359190873Sjfv 1360190873Sjfv/* VMOLR bitmasks */ 1361230775Sjfv#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ 1362230775Sjfv#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ 1363230775Sjfv#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ 1364230775Sjfv#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ 1365230775Sjfv#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ 1366190873Sjfv 1367190873Sjfv/* VFRE bitmask */ 1368230775Sjfv#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF 1369190873Sjfv 1370230775Sjfv#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 1371194875Sjfv 1372171384Sjfv/* RDHMPN and TDHMPN bitmasks */ 1373230775Sjfv#define IXGBE_RDHMPN_RDICADDR 0x007FF800 1374230775Sjfv#define IXGBE_RDHMPN_RDICRDREQ 0x00800000 1375230775Sjfv#define IXGBE_RDHMPN_RDICADDR_SHIFT 11 1376230775Sjfv#define IXGBE_TDHMPN_TDICADDR 0x003FF800 1377230775Sjfv#define IXGBE_TDHMPN_TDICRDREQ 0x00800000 1378230775Sjfv#define IXGBE_TDHMPN_TDICADDR_SHIFT 11 1379171384Sjfv 1380230775Sjfv#define IXGBE_RDMAM_MEM_SEL_SHIFT 13 1381230775Sjfv#define IXGBE_RDMAM_DWORD_SHIFT 9 1382230775Sjfv#define IXGBE_RDMAM_DESC_COMP_FIFO 1 1383230775Sjfv#define IXGBE_RDMAM_DFC_CMD_FIFO 2 1384230775Sjfv#define IXGBE_RDMAM_RSC_HEADER_ADDR 3 1385230775Sjfv#define IXGBE_RDMAM_TCN_STATUS_RAM 4 1386230775Sjfv#define IXGBE_RDMAM_WB_COLL_FIFO 5 1387230775Sjfv#define IXGBE_RDMAM_QSC_CNT_RAM 6 1388230775Sjfv#define IXGBE_RDMAM_QSC_FCOE_RAM 7 1389230775Sjfv#define IXGBE_RDMAM_QSC_QUEUE_CNT 8 1390230775Sjfv#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA 1391230775Sjfv#define IXGBE_RDMAM_QSC_RSC_RAM 0xB 1392230775Sjfv#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135 1393230775Sjfv#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4 1394230775Sjfv#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48 1395230775Sjfv#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7 1396230775Sjfv#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32 1397230775Sjfv#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4 1398230775Sjfv#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256 1399230775Sjfv#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9 1400230775Sjfv#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8 1401230775Sjfv#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4 1402230775Sjfv#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64 1403230775Sjfv#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4 1404230775Sjfv#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512 1405230775Sjfv#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5 1406230775Sjfv#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32 1407230775Sjfv#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4 1408230775Sjfv#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128 1409230775Sjfv#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8 1410230775Sjfv#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32 1411230775Sjfv#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8 1412190873Sjfv 1413230775Sjfv#define IXGBE_TXDESCIC_READY 0x80000000 1414190873Sjfv 1415171384Sjfv/* Receive Checksum Control */ 1416230775Sjfv#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 1417230775Sjfv#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 1418171384Sjfv 1419171384Sjfv/* FCRTL Bit Masks */ 1420230775Sjfv#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */ 1421230775Sjfv#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */ 1422171384Sjfv 1423171384Sjfv/* PAP bit masks*/ 1424230775Sjfv#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 1425171384Sjfv 1426171384Sjfv/* RMCS Bit Masks */ 1427230775Sjfv#define IXGBE_RMCS_RRM 0x00000002 /* Rx Recycle Mode enable */ 1428171384Sjfv/* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 1429230775Sjfv#define IXGBE_RMCS_RAC 0x00000004 1430230775Sjfv/* Deficit Fixed Prio ena */ 1431230775Sjfv#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC 1432230775Sjfv#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ 1433230775Sjfv#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ 1434230775Sjfv#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 1435171384Sjfv 1436190873Sjfv/* FCCFG Bit Masks */ 1437230775Sjfv#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */ 1438230775Sjfv#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */ 1439179055Sjfv 1440171384Sjfv/* Interrupt register bitmasks */ 1441171384Sjfv 1442171384Sjfv/* Extended Interrupt Cause Read */ 1443230775Sjfv#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 1444230775Sjfv#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */ 1445230775Sjfv#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */ 1446230775Sjfv#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */ 1447230775Sjfv#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */ 1448230775Sjfv#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 1449230775Sjfv#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */ 1450230775Sjfv#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ 1451230775Sjfv#define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */ 1452238149Sjfv#define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */ 1453230775Sjfv#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 1454230775Sjfv#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ 1455230775Sjfv#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */ 1456230775Sjfv#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */ 1457230775Sjfv#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 1458230775Sjfv#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 1459230775Sjfv#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 1460230775Sjfv#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 1461171384Sjfv 1462171384Sjfv/* Extended Interrupt Cause Set */ 1463230775Sjfv#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1464230775Sjfv#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1465230775Sjfv#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */ 1466230775Sjfv#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1467230775Sjfv#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1468230775Sjfv#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1469230775Sjfv#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1470238149Sjfv#define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1471230775Sjfv#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1472230775Sjfv#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1473230775Sjfv#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1474230775Sjfv#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */ 1475230775Sjfv#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1476230775Sjfv#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 1477230775Sjfv#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1478230775Sjfv#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1479171384Sjfv 1480171384Sjfv/* Extended Interrupt Mask Set */ 1481230775Sjfv#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1482230775Sjfv#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1483230775Sjfv#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1484230775Sjfv#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1485230775Sjfv#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1486230775Sjfv#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1487230775Sjfv#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1488230775Sjfv#define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermal Sensor Event */ 1489238149Sjfv#define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1490230775Sjfv#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1491230775Sjfv#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1492230775Sjfv#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1493230775Sjfv#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */ 1494230775Sjfv#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1495230775Sjfv#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 1496230775Sjfv#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1497230775Sjfv#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1498171384Sjfv 1499171384Sjfv/* Extended Interrupt Mask Clear */ 1500230775Sjfv#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1501230775Sjfv#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1502230775Sjfv#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1503230775Sjfv#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */ 1504230775Sjfv#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1505230775Sjfv#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 1506230775Sjfv#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1507238149Sjfv#define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1508230775Sjfv#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1509230775Sjfv#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1510230775Sjfv#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1511230775Sjfv#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */ 1512230775Sjfv#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1513230775Sjfv#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ 1514230775Sjfv#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1515230775Sjfv#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1516171384Sjfv 1517171384Sjfv#define IXGBE_EIMS_ENABLE_MASK ( \ 1518230775Sjfv IXGBE_EIMS_RTX_QUEUE | \ 1519230775Sjfv IXGBE_EIMS_LSC | \ 1520230775Sjfv IXGBE_EIMS_TCP_TIMER | \ 1521230775Sjfv IXGBE_EIMS_OTHER) 1522171384Sjfv 1523179055Sjfv/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 1524230775Sjfv#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 1525230775Sjfv#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 1526230775Sjfv#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 1527230775Sjfv#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 1528230775Sjfv#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 1529230775Sjfv#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 1530230775Sjfv#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 1531230775Sjfv#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 1532230775Sjfv#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 1533230775Sjfv#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 1534230775Sjfv#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */ 1535230775Sjfv#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */ 1536230775Sjfv#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */ 1537230775Sjfv#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */ 1538230775Sjfv#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ 1539230775Sjfv#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ 1540230775Sjfv#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ 1541230775Sjfv#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass chk of ctrl bits */ 1542230775Sjfv#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ 1543230775Sjfv#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ 1544230775Sjfv#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ 1545230775Sjfv#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */ 1546230775Sjfv#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */ 1547171384Sjfv 1548230775Sjfv#define IXGBE_MAX_FTQF_FILTERS 128 1549230775Sjfv#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003 1550230775Sjfv#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000 1551230775Sjfv#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001 1552230775Sjfv#define IXGBE_FTQF_PROTOCOL_SCTP 2 1553230775Sjfv#define IXGBE_FTQF_PRIORITY_MASK 0x00000007 1554230775Sjfv#define IXGBE_FTQF_PRIORITY_SHIFT 2 1555230775Sjfv#define IXGBE_FTQF_POOL_MASK 0x0000003F 1556230775Sjfv#define IXGBE_FTQF_POOL_SHIFT 8 1557230775Sjfv#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F 1558230775Sjfv#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25 1559230775Sjfv#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E 1560230775Sjfv#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D 1561230775Sjfv#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B 1562230775Sjfv#define IXGBE_FTQF_DEST_PORT_MASK 0x17 1563230775Sjfv#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F 1564230775Sjfv#define IXGBE_FTQF_POOL_MASK_EN 0x40000000 1565230775Sjfv#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 1566190873Sjfv 1567171384Sjfv/* Interrupt clear mask */ 1568230775Sjfv#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 1569171384Sjfv 1570171384Sjfv/* Interrupt Vector Allocation Registers */ 1571230775Sjfv#define IXGBE_IVAR_REG_NUM 25 1572230775Sjfv#define IXGBE_IVAR_REG_NUM_82599 64 1573230775Sjfv#define IXGBE_IVAR_TXRX_ENTRY 96 1574230775Sjfv#define IXGBE_IVAR_RX_ENTRY 64 1575230775Sjfv#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 1576230775Sjfv#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 1577230775Sjfv#define IXGBE_IVAR_TX_ENTRY 32 1578171384Sjfv 1579230775Sjfv#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 1580230775Sjfv#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 1581171384Sjfv 1582230775Sjfv#define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 1583171384Sjfv 1584230775Sjfv#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 1585171384Sjfv 1586190873Sjfv/* ETYPE Queue Filter/Select Bit Masks */ 1587230775Sjfv#define IXGBE_MAX_ETQF_FILTERS 8 1588230775Sjfv#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */ 1589230775Sjfv#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */ 1590230775Sjfv#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ 1591230775Sjfv#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ 1592230775Sjfv#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */ 1593238149Sjfv#define IXGBE_ETQF_POOL_SHIFT 20 1594190873Sjfv 1595230775Sjfv#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ 1596230775Sjfv#define IXGBE_ETQS_RX_QUEUE_SHIFT 16 1597230775Sjfv#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */ 1598230775Sjfv#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */ 1599190873Sjfv 1600190873Sjfv/* 1601190873Sjfv * ETQF filter list: one static filter per filter consumer. This is 1602230775Sjfv * to avoid filter collisions later. Add new filters 1603230775Sjfv * here!! 1604190873Sjfv * 1605190873Sjfv * Current filters: 1606230775Sjfv * EAPOL 802.1x (0x888e): Filter 0 1607230775Sjfv * FCoE (0x8906): Filter 2 1608230775Sjfv * 1588 (0x88f7): Filter 3 1609230775Sjfv * FIP (0x8914): Filter 4 1610190873Sjfv */ 1611230775Sjfv#define IXGBE_ETQF_FILTER_EAPOL 0 1612230775Sjfv#define IXGBE_ETQF_FILTER_FCOE 2 1613230775Sjfv#define IXGBE_ETQF_FILTER_1588 3 1614230775Sjfv#define IXGBE_ETQF_FILTER_FIP 4 1615171384Sjfv/* VLAN Control Bit Masks */ 1616230775Sjfv#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 1617230775Sjfv#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 1618230775Sjfv#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 1619230775Sjfv#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 1620230775Sjfv#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 1621171384Sjfv 1622190873Sjfv/* VLAN pool filtering masks */ 1623230775Sjfv#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */ 1624230775Sjfv#define IXGBE_VLVF_ENTRIES 64 1625230775Sjfv#define IXGBE_VLVF_VLANID_MASK 0x00000FFF 1626215911Sjfv/* Per VF Port VLAN insertion rules */ 1627230775Sjfv#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 1628230775Sjfv#define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 1629179055Sjfv 1630230775Sjfv#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 1631171384Sjfv 1632171384Sjfv/* STATUS Bit Masks */ 1633230775Sjfv#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 1634230775Sjfv#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ 1635230775Sjfv#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Ena Status */ 1636171384Sjfv 1637230775Sjfv#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 1638230775Sjfv#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 1639171384Sjfv 1640171384Sjfv/* ESDP Bit Masks */ 1641230775Sjfv#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */ 1642230775Sjfv#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */ 1643230775Sjfv#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */ 1644230775Sjfv#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */ 1645230775Sjfv#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */ 1646230775Sjfv#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */ 1647230775Sjfv#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */ 1648238149Sjfv#define IXGBE_ESDP_SDP7 0x00000080 /* SDP7 Data Value */ 1649238149Sjfv#define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */ 1650238149Sjfv#define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */ 1651247822Sjfv#define IXGBE_ESDP_SDP2_DIR 0x00000400 /* SDP1 IO direction */ 1652238149Sjfv#define IXGBE_ESDP_SDP3_DIR 0x00000800 /* SDP3 IO direction */ 1653238149Sjfv#define IXGBE_ESDP_SDP4_DIR 0x00001000 /* SDP4 IO direction */ 1654230775Sjfv#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */ 1655238149Sjfv#define IXGBE_ESDP_SDP6_DIR 0x00004000 /* SDP6 IO direction */ 1656238149Sjfv#define IXGBE_ESDP_SDP7_DIR 0x00008000 /* SDP7 IO direction */ 1657238149Sjfv#define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 IO mode */ 1658238149Sjfv#define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */ 1659171384Sjfv 1660238149Sjfv 1661171384Sjfv/* LEDCTL Bit Masks */ 1662230775Sjfv#define IXGBE_LED_IVRT_BASE 0x00000040 1663230775Sjfv#define IXGBE_LED_BLINK_BASE 0x00000080 1664230775Sjfv#define IXGBE_LED_MODE_MASK_BASE 0x0000000F 1665230775Sjfv#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 1666230775Sjfv#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i)) 1667230775Sjfv#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 1668230775Sjfv#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 1669230775Sjfv#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 1670171384Sjfv 1671171384Sjfv/* LED modes */ 1672230775Sjfv#define IXGBE_LED_LINK_UP 0x0 1673230775Sjfv#define IXGBE_LED_LINK_10G 0x1 1674230775Sjfv#define IXGBE_LED_MAC 0x2 1675230775Sjfv#define IXGBE_LED_FILTER 0x3 1676230775Sjfv#define IXGBE_LED_LINK_ACTIVE 0x4 1677230775Sjfv#define IXGBE_LED_LINK_1G 0x5 1678230775Sjfv#define IXGBE_LED_ON 0xE 1679230775Sjfv#define IXGBE_LED_OFF 0xF 1680171384Sjfv 1681171384Sjfv/* AUTOC Bit Masks */ 1682190873Sjfv#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000 1683230775Sjfv#define IXGBE_AUTOC_KX4_SUPP 0x80000000 1684230775Sjfv#define IXGBE_AUTOC_KX_SUPP 0x40000000 1685230775Sjfv#define IXGBE_AUTOC_PAUSE 0x30000000 1686230775Sjfv#define IXGBE_AUTOC_ASM_PAUSE 0x20000000 1687230775Sjfv#define IXGBE_AUTOC_SYM_PAUSE 0x10000000 1688230775Sjfv#define IXGBE_AUTOC_RF 0x08000000 1689230775Sjfv#define IXGBE_AUTOC_PD_TMR 0x06000000 1690230775Sjfv#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 1691230775Sjfv#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 1692230775Sjfv#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 1693230775Sjfv#define IXGBE_AUTOC_FECA 0x00040000 1694230775Sjfv#define IXGBE_AUTOC_FECR 0x00020000 1695230775Sjfv#define IXGBE_AUTOC_KR_SUPP 0x00010000 1696230775Sjfv#define IXGBE_AUTOC_AN_RESTART 0x00001000 1697230775Sjfv#define IXGBE_AUTOC_FLU 0x00000001 1698230775Sjfv#define IXGBE_AUTOC_LMS_SHIFT 13 1699230775Sjfv#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT) 1700230775Sjfv#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1701230775Sjfv#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT) 1702230775Sjfv#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1703230775Sjfv#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1704230775Sjfv#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1705230775Sjfv#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 1706230775Sjfv#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 1707230775Sjfv#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 1708230775Sjfv#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1709230775Sjfv#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1710230775Sjfv#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1711171384Sjfv 1712230775Sjfv#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200 1713230775Sjfv#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 1714230775Sjfv#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 1715230775Sjfv#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 1716230775Sjfv#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1717230775Sjfv#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1718230775Sjfv#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1719230775Sjfv#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1720230775Sjfv#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1721230775Sjfv#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1722230775Sjfv#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1723171384Sjfv 1724230775Sjfv#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 1725230775Sjfv#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 1726230775Sjfv#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 1727230775Sjfv#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1728230775Sjfv#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1729230775Sjfv#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1730251964Sjfv#define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000 1731251964Sjfv#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000 1732190873Sjfv 1733230775Sjfv#define IXGBE_MACC_FLU 0x00000001 1734230775Sjfv#define IXGBE_MACC_FSV_10G 0x00030000 1735230775Sjfv#define IXGBE_MACC_FS 0x00040000 1736230775Sjfv#define IXGBE_MAC_RX2TX_LPBK 0x00000002 1737205720Sjfv 1738171384Sjfv/* LINKS Bit Masks */ 1739230775Sjfv#define IXGBE_LINKS_KX_AN_COMP 0x80000000 1740230775Sjfv#define IXGBE_LINKS_UP 0x40000000 1741230775Sjfv#define IXGBE_LINKS_SPEED 0x20000000 1742230775Sjfv#define IXGBE_LINKS_MODE 0x18000000 1743230775Sjfv#define IXGBE_LINKS_RX_MODE 0x06000000 1744230775Sjfv#define IXGBE_LINKS_TX_MODE 0x01800000 1745230775Sjfv#define IXGBE_LINKS_XGXS_EN 0x00400000 1746230775Sjfv#define IXGBE_LINKS_SGMII_EN 0x02000000 1747230775Sjfv#define IXGBE_LINKS_PCS_1G_EN 0x00200000 1748230775Sjfv#define IXGBE_LINKS_1G_AN_EN 0x00100000 1749230775Sjfv#define IXGBE_LINKS_KX_AN_IDLE 0x00080000 1750230775Sjfv#define IXGBE_LINKS_1G_SYNC 0x00040000 1751230775Sjfv#define IXGBE_LINKS_10G_ALIGN 0x00020000 1752230775Sjfv#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 1753230775Sjfv#define IXGBE_LINKS_TL_FAULT 0x00001000 1754230775Sjfv#define IXGBE_LINKS_SIGNAL 0x00000F00 1755171384Sjfv 1756230775Sjfv#define IXGBE_LINKS_SPEED_82599 0x30000000 1757230775Sjfv#define IXGBE_LINKS_SPEED_10G_82599 0x30000000 1758230775Sjfv#define IXGBE_LINKS_SPEED_1G_82599 0x20000000 1759230775Sjfv#define IXGBE_LINKS_SPEED_100_82599 0x10000000 1760230775Sjfv#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 1761230775Sjfv#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 1762171384Sjfv 1763230775Sjfv#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 1764200239Sjfv 1765172043Sjfv/* PCS1GLSTA Bit Masks */ 1766230775Sjfv#define IXGBE_PCS1GLSTA_LINK_OK 1 1767230775Sjfv#define IXGBE_PCS1GLSTA_SYNK_OK 0x10 1768230775Sjfv#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 1769230775Sjfv#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 1770230775Sjfv#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 1771230775Sjfv#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 1772230775Sjfv#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 1773172043Sjfv 1774230775Sjfv#define IXGBE_PCS1GANA_SYM_PAUSE 0x80 1775230775Sjfv#define IXGBE_PCS1GANA_ASM_PAUSE 0x100 1776172043Sjfv 1777172043Sjfv/* PCS1GLCTL Bit Masks */ 1778230775Sjfv#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ 1779230775Sjfv#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 1780230775Sjfv#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 1781230775Sjfv#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 1782230775Sjfv#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 1783230775Sjfv#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 1784172043Sjfv 1785200239Sjfv/* ANLP1 Bit Masks */ 1786230775Sjfv#define IXGBE_ANLP1_PAUSE 0x0C00 1787230775Sjfv#define IXGBE_ANLP1_SYM_PAUSE 0x0400 1788230775Sjfv#define IXGBE_ANLP1_ASM_PAUSE 0x0800 1789230775Sjfv#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000 1790200239Sjfv 1791171384Sjfv/* SW Semaphore Register bitmasks */ 1792230775Sjfv#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 1793230775Sjfv#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 1794230775Sjfv#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 1795230775Sjfv#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */ 1796171384Sjfv 1797200239Sjfv/* SW_FW_SYNC/GSSR definitions */ 1798230775Sjfv#define IXGBE_GSSR_EEP_SM 0x0001 1799230775Sjfv#define IXGBE_GSSR_PHY0_SM 0x0002 1800230775Sjfv#define IXGBE_GSSR_PHY1_SM 0x0004 1801230775Sjfv#define IXGBE_GSSR_MAC_CSR_SM 0x0008 1802230775Sjfv#define IXGBE_GSSR_FLASH_SM 0x0010 1803230775Sjfv#define IXGBE_GSSR_SW_MNG_SM 0x0400 1804171384Sjfv 1805230775Sjfv/* FW Status register bitmask */ 1806230775Sjfv#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */ 1807230775Sjfv 1808171384Sjfv/* EEC Register */ 1809230775Sjfv#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 1810230775Sjfv#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 1811230775Sjfv#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 1812230775Sjfv#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 1813230775Sjfv#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 1814230775Sjfv#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1815230775Sjfv#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 1816230775Sjfv#define IXGBE_EEC_FWE_SHIFT 4 1817230775Sjfv#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 1818230775Sjfv#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 1819230775Sjfv#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 1820230775Sjfv#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 1821230775Sjfv#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */ 1822230775Sjfv#define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */ 1823230775Sjfv#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */ 1824171384Sjfv/* EEPROM Addressing bits based on type (0-small, 1-large) */ 1825230775Sjfv#define IXGBE_EEC_ADDR_SIZE 0x00000400 1826230775Sjfv#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 1827230775Sjfv#define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */ 1828171384Sjfv 1829230775Sjfv#define IXGBE_EEC_SIZE_SHIFT 11 1830230775Sjfv#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 1831230775Sjfv#define IXGBE_EEPROM_OPCODE_BITS 8 1832171384Sjfv 1833215911Sjfv/* Part Number String Length */ 1834230775Sjfv#define IXGBE_PBANUM_LENGTH 11 1835215911Sjfv 1836171384Sjfv/* Checksum and EEPROM pointers */ 1837230775Sjfv#define IXGBE_PBANUM_PTR_GUARD 0xFAFA 1838230775Sjfv#define IXGBE_EEPROM_CHECKSUM 0x3F 1839230775Sjfv#define IXGBE_EEPROM_SUM 0xBABA 1840230775Sjfv#define IXGBE_PCIE_ANALOG_PTR 0x03 1841230775Sjfv#define IXGBE_ATLAS0_CONFIG_PTR 0x04 1842230775Sjfv#define IXGBE_PHY_PTR 0x04 1843230775Sjfv#define IXGBE_ATLAS1_CONFIG_PTR 0x05 1844230775Sjfv#define IXGBE_OPTION_ROM_PTR 0x05 1845230775Sjfv#define IXGBE_PCIE_GENERAL_PTR 0x06 1846230775Sjfv#define IXGBE_PCIE_CONFIG0_PTR 0x07 1847230775Sjfv#define IXGBE_PCIE_CONFIG1_PTR 0x08 1848230775Sjfv#define IXGBE_CORE0_PTR 0x09 1849230775Sjfv#define IXGBE_CORE1_PTR 0x0A 1850230775Sjfv#define IXGBE_MAC0_PTR 0x0B 1851230775Sjfv#define IXGBE_MAC1_PTR 0x0C 1852230775Sjfv#define IXGBE_CSR0_CONFIG_PTR 0x0D 1853230775Sjfv#define IXGBE_CSR1_CONFIG_PTR 0x0E 1854230775Sjfv#define IXGBE_FW_PTR 0x0F 1855230775Sjfv#define IXGBE_PBANUM0_PTR 0x15 1856230775Sjfv#define IXGBE_PBANUM1_PTR 0x16 1857230775Sjfv#define IXGBE_ALT_MAC_ADDR_PTR 0x37 1858230775Sjfv#define IXGBE_FREE_SPACE_PTR 0X3E 1859171384Sjfv 1860230775Sjfv#define IXGBE_SAN_MAC_ADDR_PTR 0x28 1861230775Sjfv#define IXGBE_DEVICE_CAPS 0x2C 1862230775Sjfv#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 1863230775Sjfv#define IXGBE_PCIE_MSIX_82599_CAPS 0x72 1864238149Sjfv#define IXGBE_MAX_MSIX_VECTORS_82599 0x40 1865230775Sjfv#define IXGBE_PCIE_MSIX_82598_CAPS 0x62 1866238149Sjfv#define IXGBE_MAX_MSIX_VECTORS_82598 0x13 1867230775Sjfv 1868190873Sjfv/* MSI-X capability fields masks */ 1869230775Sjfv#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF 1870190873Sjfv 1871172043Sjfv/* Legacy EEPROM word offsets */ 1872230775Sjfv#define IXGBE_ISCSI_BOOT_CAPS 0x0033 1873230775Sjfv#define IXGBE_ISCSI_SETUP_PORT_0 0x0030 1874230775Sjfv#define IXGBE_ISCSI_SETUP_PORT_1 0x0034 1875172043Sjfv 1876171384Sjfv/* EEPROM Commands - SPI */ 1877230775Sjfv#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 1878230775Sjfv#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 1879230775Sjfv#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 1880230775Sjfv#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 1881230775Sjfv#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 1882230775Sjfv#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 1883179055Sjfv/* EEPROM reset Write Enable latch */ 1884230775Sjfv#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 1885230775Sjfv#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 1886230775Sjfv#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 1887230775Sjfv#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 1888230775Sjfv#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 1889230775Sjfv#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 1890171384Sjfv 1891171384Sjfv/* EEPROM Read Register */ 1892230775Sjfv#define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */ 1893230775Sjfv#define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */ 1894230775Sjfv#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */ 1895230775Sjfv#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1896230775Sjfv#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for wr complete */ 1897230775Sjfv#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for rd complete */ 1898171384Sjfv 1899230775Sjfv#define IXGBE_ETH_LENGTH_OF_ADDRESS 6 1900171384Sjfv 1901230775Sjfv#define IXGBE_EEPROM_PAGE_SIZE_MAX 128 1902247822Sjfv#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 256 /* words rd in burst */ 1903230775Sjfv#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* words wr in burst */ 1904251964Sjfv#define IXGBE_EEPROM_CTRL_2 1 /* EEPROM CTRL word 2 */ 1905251964Sjfv#define IXGBE_EEPROM_CCD_BIT 2 1906230775Sjfv 1907171384Sjfv#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 1908230775Sjfv#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM attempts to gain grant */ 1909171384Sjfv#endif 1910171384Sjfv 1911200239Sjfv/* Number of 5 microseconds we wait for EERD read and 1912200239Sjfv * EERW write to complete */ 1913230775Sjfv#define IXGBE_EERD_EEWR_ATTEMPTS 100000 1914171384Sjfv 1915200239Sjfv/* # attempts we wait for flush update to complete */ 1916230775Sjfv#define IXGBE_FLUDONE_ATTEMPTS 20000 1917200239Sjfv 1918230775Sjfv#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */ 1919230775Sjfv#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ 1920230775Sjfv#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ 1921230775Sjfv#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ 1922194875Sjfv 1923230775Sjfv#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 1924230775Sjfv#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 1925230775Sjfv#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 1926230775Sjfv#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 1927230775Sjfv#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2 1928230775Sjfv#define IXGBE_FW_LESM_STATE_1 0x1 1929230775Sjfv#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */ 1930230775Sjfv#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 1931230775Sjfv#define IXGBE_FW_PATCH_VERSION_4 0x7 1932230775Sjfv#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */ 1933230775Sjfv#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */ 1934230775Sjfv#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */ 1935230775Sjfv#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */ 1936230775Sjfv#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */ 1937230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */ 1938230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt SAN MAC capability */ 1939230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt SAN MAC 0 offset */ 1940230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt SAN MAC 1 offset */ 1941230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt WWNN prefix offset */ 1942230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt WWPN prefix offset */ 1943230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt SAN MAC exists */ 1944230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt WWN base exists */ 1945190873Sjfv 1946251964Sjfv/* FW header offset */ 1947251964Sjfv#define IXGBE_X540_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 1948251964Sjfv#define IXGBE_X540_FW_MODULE_MASK 0x7FFF 1949251964Sjfv/* 4KB multiplier */ 1950251964Sjfv#define IXGBE_X540_FW_MODULE_LENGTH 0x1000 1951251964Sjfv/* version word 2 (month & day) */ 1952251964Sjfv#define IXGBE_X540_FW_PATCH_VERSION_2 0x5 1953251964Sjfv/* version word 3 (silicon compatibility & year) */ 1954251964Sjfv#define IXGBE_X540_FW_PATCH_VERSION_3 0x6 1955251964Sjfv/* version word 4 (major & minor numbers) */ 1956251964Sjfv#define IXGBE_X540_FW_PATCH_VERSION_4 0x7 1957251964Sjfv 1958230775Sjfv#define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */ 1959230775Sjfv#define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */ 1960230775Sjfv#define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */ 1961230775Sjfv 1962171384Sjfv/* PCI Bus Info */ 1963230775Sjfv#define IXGBE_PCI_DEVICE_STATUS 0xAA 1964230775Sjfv#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020 1965230775Sjfv#define IXGBE_PCI_LINK_STATUS 0xB2 1966230775Sjfv#define IXGBE_PCI_DEVICE_CONTROL2 0xC8 1967230775Sjfv#define IXGBE_PCI_LINK_WIDTH 0x3F0 1968230775Sjfv#define IXGBE_PCI_LINK_WIDTH_1 0x10 1969230775Sjfv#define IXGBE_PCI_LINK_WIDTH_2 0x20 1970230775Sjfv#define IXGBE_PCI_LINK_WIDTH_4 0x40 1971230775Sjfv#define IXGBE_PCI_LINK_WIDTH_8 0x80 1972230775Sjfv#define IXGBE_PCI_LINK_SPEED 0xF 1973230775Sjfv#define IXGBE_PCI_LINK_SPEED_2500 0x1 1974230775Sjfv#define IXGBE_PCI_LINK_SPEED_5000 0x2 1975238149Sjfv#define IXGBE_PCI_LINK_SPEED_8000 0x3 1976230775Sjfv#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E 1977230775Sjfv#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 1978230775Sjfv#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 1979171384Sjfv 1980251964Sjfv#define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf 1981251964Sjfv#define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0 1982251964Sjfv#define IXGBE_PCIDEVCTRL2_50_100us 0x1 1983251964Sjfv#define IXGBE_PCIDEVCTRL2_1_2ms 0x2 1984251964Sjfv#define IXGBE_PCIDEVCTRL2_16_32ms 0x5 1985251964Sjfv#define IXGBE_PCIDEVCTRL2_65_130ms 0x6 1986251964Sjfv#define IXGBE_PCIDEVCTRL2_260_520ms 0x9 1987251964Sjfv#define IXGBE_PCIDEVCTRL2_1_2s 0xa 1988251964Sjfv#define IXGBE_PCIDEVCTRL2_4_8s 0xd 1989251964Sjfv#define IXGBE_PCIDEVCTRL2_17_34s 0xe 1990251964Sjfv 1991171384Sjfv/* Number of 100 microseconds we wait for PCI Express master disable */ 1992230775Sjfv#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 1993171384Sjfv 1994230775Sjfv/* Check whether address is multicast. This is little-endian specific check.*/ 1995171384Sjfv#define IXGBE_IS_MULTICAST(Address) \ 1996230775Sjfv (bool)(((u8 *)(Address))[0] & ((u8)0x01)) 1997171384Sjfv 1998171384Sjfv/* Check whether an address is broadcast. */ 1999230775Sjfv#define IXGBE_IS_BROADCAST(Address) \ 2000230775Sjfv ((((u8 *)(Address))[0] == ((u8)0xff)) && \ 2001230775Sjfv (((u8 *)(Address))[1] == ((u8)0xff))) 2002171384Sjfv 2003171384Sjfv/* RAH */ 2004230775Sjfv#define IXGBE_RAH_VIND_MASK 0x003C0000 2005230775Sjfv#define IXGBE_RAH_VIND_SHIFT 18 2006230775Sjfv#define IXGBE_RAH_AV 0x80000000 2007230775Sjfv#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF 2008171384Sjfv 2009171384Sjfv/* Header split receive */ 2010230775Sjfv#define IXGBE_RFCTL_ISCSI_DIS 0x00000001 2011230775Sjfv#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 2012230775Sjfv#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 2013230775Sjfv#define IXGBE_RFCTL_RSC_DIS 0x00000010 2014230775Sjfv#define IXGBE_RFCTL_NFSW_DIS 0x00000040 2015230775Sjfv#define IXGBE_RFCTL_NFSR_DIS 0x00000080 2016230775Sjfv#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 2017230775Sjfv#define IXGBE_RFCTL_NFS_VER_SHIFT 8 2018230775Sjfv#define IXGBE_RFCTL_NFS_VER_2 0 2019230775Sjfv#define IXGBE_RFCTL_NFS_VER_3 1 2020230775Sjfv#define IXGBE_RFCTL_NFS_VER_4 2 2021230775Sjfv#define IXGBE_RFCTL_IPV6_DIS 0x00000400 2022230775Sjfv#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 2023230775Sjfv#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 2024230775Sjfv#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 2025230775Sjfv#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 2026171384Sjfv 2027171384Sjfv/* Transmit Config masks */ 2028230775Sjfv#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */ 2029230775Sjfv#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */ 2030230775Sjfv#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 2031171384Sjfv/* Enable short packet padding to 64 bytes */ 2032230775Sjfv#define IXGBE_TX_PAD_ENABLE 0x00000400 2033230775Sjfv#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 2034171384Sjfv/* This allows for 16K packets + 4k for vlan */ 2035230775Sjfv#define IXGBE_MAX_FRAME_SZ 0x40040000 2036171384Sjfv 2037230775Sjfv#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 2038230775Sjfv#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ 2039171384Sjfv 2040171384Sjfv/* Receive Config masks */ 2041230775Sjfv#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 2042230775Sjfv#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Desc Monitor Bypass */ 2043230775Sjfv#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Ena specific Rx Queue */ 2044230775Sjfv#define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc wr-bk flushing */ 2045230775Sjfv#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* X540 supported only */ 2046230775Sjfv#define IXGBE_RXDCTL_RLPML_EN 0x00008000 2047230775Sjfv#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 2048171384Sjfv 2049238149Sjfv#define IXGBE_TSAUXC_EN_CLK 0x00000004 2050238149Sjfv#define IXGBE_TSAUXC_SYNCLK 0x00000008 2051238149Sjfv#define IXGBE_TSAUXC_SDP0_INT 0x00000040 2052238149Sjfv 2053230775Sjfv#define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 2054230775Sjfv#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */ 2055230775Sjfv 2056230775Sjfv#define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 2057230775Sjfv#define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 2058230775Sjfv#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00 2059230775Sjfv#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02 2060230775Sjfv#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 2061230775Sjfv#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 2062230775Sjfv#define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */ 2063230775Sjfv 2064230775Sjfv#define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF 2065230775Sjfv#define IXGBE_RXMTRL_V1_SYNC_MSG 0x00 2066230775Sjfv#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01 2067230775Sjfv#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02 2068230775Sjfv#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03 2069230775Sjfv#define IXGBE_RXMTRL_V1_MGMT_MSG 0x04 2070230775Sjfv 2071230775Sjfv#define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00 2072230775Sjfv#define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000 2073230775Sjfv#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100 2074230775Sjfv#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200 2075230775Sjfv#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300 2076230775Sjfv#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800 2077230775Sjfv#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900 2078230775Sjfv#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00 2079230775Sjfv#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00 2080230775Sjfv#define IXGBE_RXMTRL_V2_SIGNALLING_MSG 0x0C00 2081230775Sjfv#define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00 2082230775Sjfv 2083230775Sjfv#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 2084230775Sjfv#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 2085230775Sjfv#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 2086230775Sjfv#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 2087230775Sjfv#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 2088230775Sjfv#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 2089179055Sjfv/* Receive Priority Flow Control Enable */ 2090230775Sjfv#define IXGBE_FCTRL_RPFCE 0x00004000 2091230775Sjfv#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 2092230775Sjfv#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */ 2093230775Sjfv#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ 2094230775Sjfv#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ 2095230775Sjfv#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ 2096238149Sjfv#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Rx Priority FC bitmap mask */ 2097230775Sjfv#define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */ 2098171384Sjfv 2099171384Sjfv/* Multiple Receive Queue Control */ 2100230775Sjfv#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 2101230775Sjfv#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ 2102230775Sjfv#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */ 2103230775Sjfv#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ 2104230775Sjfv#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ 2105230775Sjfv#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ 2106230775Sjfv#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ 2107230775Sjfv#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ 2108230775Sjfv#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ 2109230775Sjfv#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ 2110230775Sjfv#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ 2111230775Sjfv#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 2112230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 2113230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 2114171384Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 2115230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 2116230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 2117230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 2118230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 2119230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 2120171384Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 2121230775Sjfv#define IXGBE_MRQC_L3L4TXSWEN 0x00008000 2122171384Sjfv 2123190873Sjfv/* Queue Drop Enable */ 2124230775Sjfv#define IXGBE_QDE_ENABLE 0x00000001 2125230775Sjfv#define IXGBE_QDE_IDX_MASK 0x00007F00 2126230775Sjfv#define IXGBE_QDE_IDX_SHIFT 8 2127230775Sjfv#define IXGBE_QDE_WRITE 0x00010000 2128230775Sjfv#define IXGBE_QDE_READ 0x00020000 2129190873Sjfv 2130230775Sjfv#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 2131230775Sjfv#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 2132230775Sjfv#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 2133230775Sjfv#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 2134230775Sjfv#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 2135230775Sjfv#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 2136230775Sjfv#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 2137230775Sjfv#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 2138230775Sjfv#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 2139171384Sjfv 2140230775Sjfv#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000 2141230775Sjfv#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 2142230775Sjfv#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 2143230775Sjfv#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000 2144230775Sjfv#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 2145190873Sjfv/* Multiple Transmit Queue Command Register */ 2146230775Sjfv#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */ 2147230775Sjfv#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */ 2148230775Sjfv#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */ 2149230775Sjfv#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */ 2150230775Sjfv#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */ 2151230775Sjfv#define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA and VT_ENA */ 2152230775Sjfv#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */ 2153190873Sjfv 2154171384Sjfv/* Receive Descriptor bit definitions */ 2155230775Sjfv#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 2156230775Sjfv#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 2157230775Sjfv#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 2158230775Sjfv#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 2159230775Sjfv#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 2160230775Sjfv#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 2161230775Sjfv#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 2162230775Sjfv#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 2163230775Sjfv#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 2164230775Sjfv#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 2165230775Sjfv#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 2166230775Sjfv#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 2167230775Sjfv#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 2168230775Sjfv#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 2169230775Sjfv#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */ 2170230775Sjfv#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 2171230775Sjfv#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 2172230775Sjfv#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 2173230775Sjfv#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 2174230775Sjfv#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 2175230775Sjfv#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 2176230775Sjfv#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 2177230775Sjfv#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 2178230775Sjfv#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 2179230775Sjfv#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 2180230775Sjfv#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 2181230775Sjfv#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */ 2182230775Sjfv#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 2183230775Sjfv#define IXGBE_RXDADV_ERR_RXE 0x20000000 /* Any MAC Error */ 2184230775Sjfv#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */ 2185230775Sjfv#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */ 2186230775Sjfv#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */ 2187230775Sjfv#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */ 2188230775Sjfv#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */ 2189230775Sjfv#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 2190230775Sjfv#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 2191230775Sjfv#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 2192230775Sjfv#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 2193230775Sjfv#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 2194230775Sjfv#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 2195230775Sjfv#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 2196230775Sjfv#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 2197230775Sjfv#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 2198230775Sjfv#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 2199230775Sjfv#define IXGBE_RXD_PRI_SHIFT 13 2200230775Sjfv#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 2201230775Sjfv#define IXGBE_RXD_CFI_SHIFT 12 2202171384Sjfv 2203230775Sjfv#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 2204230775Sjfv#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 2205230775Sjfv#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 2206230775Sjfv#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 2207230775Sjfv#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */ 2208230775Sjfv#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 2209230775Sjfv#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 2210230775Sjfv#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 2211230775Sjfv#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 2212230775Sjfv#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 2213230775Sjfv#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 2214230775Sjfv#define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE1588 Time Stamp */ 2215185352Sjfv 2216190873Sjfv/* PSRTYPE bit definitions */ 2217230775Sjfv#define IXGBE_PSRTYPE_TCPHDR 0x00000010 2218230775Sjfv#define IXGBE_PSRTYPE_UDPHDR 0x00000020 2219230775Sjfv#define IXGBE_PSRTYPE_IPV4HDR 0x00000100 2220230775Sjfv#define IXGBE_PSRTYPE_IPV6HDR 0x00000200 2221230775Sjfv#define IXGBE_PSRTYPE_L2HDR 0x00001000 2222190873Sjfv 2223171384Sjfv/* SRRCTL bit definitions */ 2224230775Sjfv#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 2225230775Sjfv#define IXGBE_SRRCTL_RDMTS_SHIFT 22 2226230775Sjfv#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 2227230775Sjfv#define IXGBE_SRRCTL_DROP_EN 0x10000000 2228230775Sjfv#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 2229230775Sjfv#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 2230230775Sjfv#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 2231171384Sjfv#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 2232230775Sjfv#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 2233171384Sjfv#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 2234171384Sjfv#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 2235230775Sjfv#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 2236171384Sjfv 2237230775Sjfv#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 2238230775Sjfv#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 2239171384Sjfv 2240230775Sjfv#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 2241230775Sjfv#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 2242230775Sjfv#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 2243230775Sjfv#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 2244230775Sjfv#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 2245230775Sjfv#define IXGBE_RXDADV_RSCCNT_SHIFT 17 2246230775Sjfv#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 2247230775Sjfv#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 2248230775Sjfv#define IXGBE_RXDADV_SPH 0x8000 2249171384Sjfv 2250171384Sjfv/* RSS Hash results */ 2251230775Sjfv#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 2252230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 2253230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 2254230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 2255230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 2256230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 2257171384Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 2258230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 2259230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 2260171384Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 2261171384Sjfv 2262171384Sjfv/* RSS Packet Types as indicated in the receive descriptor. */ 2263230775Sjfv#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 2264230775Sjfv#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 2265230775Sjfv#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 2266230775Sjfv#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 2267230775Sjfv#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 2268230775Sjfv#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 2269230775Sjfv#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 2270230775Sjfv#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 2271230775Sjfv#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 2272230775Sjfv#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 2273230775Sjfv#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 2274230775Sjfv#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 2275230775Sjfv#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 2276230775Sjfv#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 2277230775Sjfv#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 2278190873Sjfv 2279190873Sjfv/* Security Processing bit Indication */ 2280230775Sjfv#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000 2281230775Sjfv#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 2282230775Sjfv#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 2283230775Sjfv#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 2284230775Sjfv#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 2285190873Sjfv 2286171384Sjfv/* Masks to determine if packets should be dropped due to frame errors */ 2287171384Sjfv#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 2288230775Sjfv IXGBE_RXD_ERR_CE | \ 2289230775Sjfv IXGBE_RXD_ERR_LE | \ 2290230775Sjfv IXGBE_RXD_ERR_PE | \ 2291230775Sjfv IXGBE_RXD_ERR_OSE | \ 2292230775Sjfv IXGBE_RXD_ERR_USE) 2293171384Sjfv 2294171384Sjfv#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 2295230775Sjfv IXGBE_RXDADV_ERR_CE | \ 2296230775Sjfv IXGBE_RXDADV_ERR_LE | \ 2297230775Sjfv IXGBE_RXDADV_ERR_PE | \ 2298230775Sjfv IXGBE_RXDADV_ERR_OSE | \ 2299230775Sjfv IXGBE_RXDADV_ERR_USE) 2300171384Sjfv 2301230775Sjfv#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599 IXGBE_RXDADV_ERR_RXE 2302230775Sjfv 2303171384Sjfv/* Multicast bit mask */ 2304230775Sjfv#define IXGBE_MCSTCTRL_MFE 0x4 2305171384Sjfv 2306171384Sjfv/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 2307230775Sjfv#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 2308230775Sjfv#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 2309230775Sjfv#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 2310171384Sjfv 2311171384Sjfv/* Vlan-specific macros */ 2312230775Sjfv#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 2313230775Sjfv#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 2314230775Sjfv#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 2315230775Sjfv#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 2316171384Sjfv 2317194875Sjfv/* SR-IOV specific macros */ 2318230775Sjfv#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4) 2319230775Sjfv#define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4)) 2320230775Sjfv#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600)) 2321230775Sjfv#define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4)) 2322194875Sjfv 2323190873Sjfv/* Little Endian defines */ 2324179055Sjfv#ifndef __le16 2325179055Sjfv#define __le16 u16 2326190873Sjfv#endif 2327190873Sjfv#ifndef __le32 2328179055Sjfv#define __le32 u32 2329190873Sjfv#endif 2330190873Sjfv#ifndef __le64 2331179055Sjfv#define __le64 u64 2332179055Sjfv 2333179055Sjfv#endif 2334185352Sjfv#ifndef __be16 2335185352Sjfv/* Big Endian defines */ 2336185352Sjfv#define __be16 u16 2337185352Sjfv#define __be32 u32 2338185352Sjfv#define __be64 u64 2339179055Sjfv 2340185352Sjfv#endif 2341190873Sjfvenum ixgbe_fdir_pballoc_type { 2342230775Sjfv IXGBE_FDIR_PBALLOC_NONE = 0, 2343230775Sjfv IXGBE_FDIR_PBALLOC_64K = 1, 2344230775Sjfv IXGBE_FDIR_PBALLOC_128K = 2, 2345230775Sjfv IXGBE_FDIR_PBALLOC_256K = 3, 2346190873Sjfv}; 2347179055Sjfv 2348190873Sjfv/* Flow Director register values */ 2349230775Sjfv#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 2350230775Sjfv#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 2351230775Sjfv#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 2352230775Sjfv#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 2353230775Sjfv#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 2354230775Sjfv#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 2355230775Sjfv#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 2356230775Sjfv#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 2357230775Sjfv#define IXGBE_FDIRCTRL_FLEX_SHIFT 16 2358230775Sjfv#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 2359230775Sjfv#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 2360230775Sjfv#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 2361230775Sjfv#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 2362190873Sjfv 2363230775Sjfv#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16 2364230775Sjfv#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16 2365230775Sjfv#define IXGBE_FDIRIP6M_DIPM_SHIFT 16 2366230775Sjfv#define IXGBE_FDIRM_VLANID 0x00000001 2367230775Sjfv#define IXGBE_FDIRM_VLANP 0x00000002 2368230775Sjfv#define IXGBE_FDIRM_POOL 0x00000004 2369230775Sjfv#define IXGBE_FDIRM_L4P 0x00000008 2370230775Sjfv#define IXGBE_FDIRM_FLEX 0x00000010 2371230775Sjfv#define IXGBE_FDIRM_DIPv6 0x00000020 2372190873Sjfv 2373230775Sjfv#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF 2374230775Sjfv#define IXGBE_FDIRFREE_FREE_SHIFT 0 2375230775Sjfv#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000 2376230775Sjfv#define IXGBE_FDIRFREE_COLL_SHIFT 16 2377230775Sjfv#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F 2378230775Sjfv#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0 2379230775Sjfv#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000 2380230775Sjfv#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16 2381230775Sjfv#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF 2382230775Sjfv#define IXGBE_FDIRUSTAT_ADD_SHIFT 0 2383230775Sjfv#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000 2384230775Sjfv#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16 2385230775Sjfv#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF 2386230775Sjfv#define IXGBE_FDIRFSTAT_FADD_SHIFT 0 2387230775Sjfv#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00 2388230775Sjfv#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8 2389230775Sjfv#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16 2390230775Sjfv#define IXGBE_FDIRVLAN_FLEX_SHIFT 16 2391230775Sjfv#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15 2392230775Sjfv#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16 2393190873Sjfv 2394230775Sjfv#define IXGBE_FDIRCMD_CMD_MASK 0x00000003 2395230775Sjfv#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 2396230775Sjfv#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 2397230775Sjfv#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 2398230775Sjfv#define IXGBE_FDIRCMD_FILTER_VALID 0x00000004 2399230775Sjfv#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 2400230775Sjfv#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 2401230775Sjfv#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 2402230775Sjfv#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040 2403230775Sjfv#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060 2404230775Sjfv#define IXGBE_FDIRCMD_IPV6 0x00000080 2405230775Sjfv#define IXGBE_FDIRCMD_CLEARHT 0x00000100 2406230775Sjfv#define IXGBE_FDIRCMD_DROP 0x00000200 2407230775Sjfv#define IXGBE_FDIRCMD_INT 0x00000400 2408230775Sjfv#define IXGBE_FDIRCMD_LAST 0x00000800 2409230775Sjfv#define IXGBE_FDIRCMD_COLLISION 0x00001000 2410230775Sjfv#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000 2411230775Sjfv#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5 2412230775Sjfv#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16 2413230775Sjfv#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24 2414230775Sjfv#define IXGBE_FDIR_INIT_DONE_POLL 10 2415230775Sjfv#define IXGBE_FDIRCMD_CMD_POLL 10 2416190873Sjfv 2417230775Sjfv#define IXGBE_FDIR_DROP_QUEUE 127 2418230775Sjfv 2419230775Sjfv#define IXGBE_STATUS_OVERHEATING_BIT 20 /* STATUS overtemp bit num */ 2420251964Sjfv/* iTS sensor related defines*/ 2421251964Sjfv#define IXGBE_TEMP_STATUS_ADDR_X540 0xC830 2422251964Sjfv#define IXGBE_TEMP_VALUE_ADDR_X540 0xC820 2423251964Sjfv#define IXGBE_TEMP_PROV_2_ADDR_X540 0xC421 2424251964Sjfv#define IXGBE_TEMP_PROV_4_ADDR_X540 0xC423 2425251964Sjfv#define IXGBE_TEMP_STATUS_PAGE_X540 0x1E 2426251964Sjfv#define IXGBE_TEMP_HIGH_FAILURE_BIT_X540 0xE 2427251964Sjfv#define IXGBE_TEMP_HIGH_WARNING_BIT_X540 0xC 2428230775Sjfv 2429230775Sjfv/* Manageablility Host Interface defines */ 2430230775Sjfv#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ 2431230775Sjfv#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ 2432230775Sjfv#define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ 2433230775Sjfv 2434230775Sjfv/* CEM Support */ 2435230775Sjfv#define FW_CEM_HDR_LEN 0x4 2436230775Sjfv#define FW_CEM_CMD_DRIVER_INFO 0xDD 2437230775Sjfv#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 2438230775Sjfv#define FW_CEM_CMD_RESERVED 0X0 2439230775Sjfv#define FW_CEM_UNUSED_VER 0x0 2440230775Sjfv#define FW_CEM_MAX_RETRIES 3 2441230775Sjfv#define FW_CEM_RESP_STATUS_SUCCESS 0x1 2442230775Sjfv 2443230775Sjfv/* Host Interface Command Structures */ 2444230775Sjfv 2445230775Sjfvstruct ixgbe_hic_hdr { 2446230775Sjfv u8 cmd; 2447230775Sjfv u8 buf_len; 2448230775Sjfv union { 2449230775Sjfv u8 cmd_resv; 2450230775Sjfv u8 ret_status; 2451230775Sjfv } cmd_or_resp; 2452230775Sjfv u8 checksum; 2453230775Sjfv}; 2454230775Sjfv 2455230775Sjfvstruct ixgbe_hic_drv_info { 2456230775Sjfv struct ixgbe_hic_hdr hdr; 2457230775Sjfv u8 port_num; 2458230775Sjfv u8 ver_sub; 2459230775Sjfv u8 ver_build; 2460230775Sjfv u8 ver_min; 2461230775Sjfv u8 ver_maj; 2462230775Sjfv u8 pad; /* end spacing to ensure length is mult. of dword */ 2463230775Sjfv u16 pad2; /* end spacing to ensure length is mult. of dword2 */ 2464230775Sjfv}; 2465230775Sjfv 2466171384Sjfv/* Transmit Descriptor - Legacy */ 2467171384Sjfvstruct ixgbe_legacy_tx_desc { 2468230775Sjfv u64 buffer_addr; /* Address of the descriptor's data buffer */ 2469171384Sjfv union { 2470179055Sjfv __le32 data; 2471171384Sjfv struct { 2472230775Sjfv __le16 length; /* Data buffer length */ 2473230775Sjfv u8 cso; /* Checksum offset */ 2474230775Sjfv u8 cmd; /* Descriptor control */ 2475171384Sjfv } flags; 2476171384Sjfv } lower; 2477171384Sjfv union { 2478179055Sjfv __le32 data; 2479171384Sjfv struct { 2480230775Sjfv u8 status; /* Descriptor status */ 2481230775Sjfv u8 css; /* Checksum start */ 2482179055Sjfv __le16 vlan; 2483171384Sjfv } fields; 2484171384Sjfv } upper; 2485171384Sjfv}; 2486171384Sjfv 2487171384Sjfv/* Transmit Descriptor - Advanced */ 2488171384Sjfvunion ixgbe_adv_tx_desc { 2489171384Sjfv struct { 2490230775Sjfv __le64 buffer_addr; /* Address of descriptor's data buf */ 2491179055Sjfv __le32 cmd_type_len; 2492179055Sjfv __le32 olinfo_status; 2493171384Sjfv } read; 2494171384Sjfv struct { 2495230775Sjfv __le64 rsvd; /* Reserved */ 2496179055Sjfv __le32 nxtseq_seed; 2497179055Sjfv __le32 status; 2498171384Sjfv } wb; 2499171384Sjfv}; 2500171384Sjfv 2501171384Sjfv/* Receive Descriptor - Legacy */ 2502171384Sjfvstruct ixgbe_legacy_rx_desc { 2503179055Sjfv __le64 buffer_addr; /* Address of the descriptor's data buffer */ 2504230775Sjfv __le16 length; /* Length of data DMAed into data buffer */ 2505230775Sjfv __le16 csum; /* Packet checksum */ 2506230775Sjfv u8 status; /* Descriptor status */ 2507230775Sjfv u8 errors; /* Descriptor Errors */ 2508179055Sjfv __le16 vlan; 2509171384Sjfv}; 2510171384Sjfv 2511171384Sjfv/* Receive Descriptor - Advanced */ 2512171384Sjfvunion ixgbe_adv_rx_desc { 2513171384Sjfv struct { 2514179055Sjfv __le64 pkt_addr; /* Packet buffer address */ 2515179055Sjfv __le64 hdr_addr; /* Header buffer address */ 2516171384Sjfv } read; 2517171384Sjfv struct { 2518171384Sjfv struct { 2519179055Sjfv union { 2520179055Sjfv __le32 data; 2521179055Sjfv struct { 2522181003Sjfv __le16 pkt_info; /* RSS, Pkt type */ 2523181003Sjfv __le16 hdr_info; /* Splithdr, hdrlen */ 2524179055Sjfv } hs_rss; 2525171384Sjfv } lo_dword; 2526171384Sjfv union { 2527179055Sjfv __le32 rss; /* RSS Hash */ 2528171384Sjfv struct { 2529179055Sjfv __le16 ip_id; /* IP id */ 2530179055Sjfv __le16 csum; /* Packet Checksum */ 2531171384Sjfv } csum_ip; 2532171384Sjfv } hi_dword; 2533171384Sjfv } lower; 2534171384Sjfv struct { 2535179055Sjfv __le32 status_error; /* ext status/error */ 2536179055Sjfv __le16 length; /* Packet length */ 2537179055Sjfv __le16 vlan; /* VLAN tag */ 2538171384Sjfv } upper; 2539171384Sjfv } wb; /* writeback */ 2540171384Sjfv}; 2541171384Sjfv 2542171384Sjfv/* Context descriptors */ 2543171384Sjfvstruct ixgbe_adv_tx_context_desc { 2544179055Sjfv __le32 vlan_macip_lens; 2545179055Sjfv __le32 seqnum_seed; 2546179055Sjfv __le32 type_tucmd_mlhl; 2547179055Sjfv __le32 mss_l4len_idx; 2548171384Sjfv}; 2549171384Sjfv 2550171384Sjfv/* Adv Transmit Descriptor Config Masks */ 2551230775Sjfv#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ 2552230775Sjfv#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */ 2553230775Sjfv#define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 time stamp */ 2554230775Sjfv#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ 2555230775Sjfv#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ 2556230775Sjfv#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 2557230775Sjfv#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Adv Context Desc */ 2558230775Sjfv#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Adv Data Descriptor */ 2559230775Sjfv#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 2560230775Sjfv#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 2561230775Sjfv#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 2562230775Sjfv#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 2563230775Sjfv#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */ 2564230775Sjfv#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 2565230775Sjfv#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 2566230775Sjfv#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 2567230775Sjfv#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ 2568230775Sjfv#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 2569230775Sjfv#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 2570230775Sjfv#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 2571230775Sjfv#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 2572230775Sjfv#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 2573230775Sjfv IXGBE_ADVTXD_POPTS_SHIFT) 2574230775Sjfv#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 2575230775Sjfv IXGBE_ADVTXD_POPTS_SHIFT) 2576230775Sjfv#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 2577230775Sjfv#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 2578230775Sjfv#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 2579230775Sjfv/* 1st&Last TSO-full iSCSI PDU */ 2580230775Sjfv#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 2581230775Sjfv#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 2582230775Sjfv#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 2583230775Sjfv#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 2584230775Sjfv#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 2585230775Sjfv#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 2586230775Sjfv#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 2587230775Sjfv#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 2588230775Sjfv#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 2589230775Sjfv#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 2590230775Sjfv#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* req Markers and CRC */ 2591230775Sjfv#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 2592190873Sjfv#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 2593190873Sjfv#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ 2594230775Sjfv#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ 2595230775Sjfv#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ 2596230775Sjfv#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ 2597230775Sjfv#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ 2598230775Sjfv#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation End */ 2599230775Sjfv#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation Start */ 2600230775Sjfv#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ 2601230775Sjfv#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ 2602230775Sjfv#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ 2603230775Sjfv#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */ 2604230775Sjfv#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 2605230775Sjfv#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 2606171384Sjfv 2607171384Sjfv/* Autonegotiation advertised speeds */ 2608171384Sjfvtypedef u32 ixgbe_autoneg_advertised; 2609171384Sjfv/* Link speed */ 2610171384Sjfvtypedef u32 ixgbe_link_speed; 2611230775Sjfv#define IXGBE_LINK_SPEED_UNKNOWN 0 2612230775Sjfv#define IXGBE_LINK_SPEED_100_FULL 0x0008 2613230775Sjfv#define IXGBE_LINK_SPEED_1GB_FULL 0x0020 2614230775Sjfv#define IXGBE_LINK_SPEED_10GB_FULL 0x0080 2615230775Sjfv#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ 2616230775Sjfv IXGBE_LINK_SPEED_10GB_FULL) 2617230775Sjfv#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ 2618230775Sjfv IXGBE_LINK_SPEED_1GB_FULL | \ 2619230775Sjfv IXGBE_LINK_SPEED_10GB_FULL) 2620171384Sjfv 2621185352Sjfv/* Physical layer type */ 2622185352Sjfvtypedef u32 ixgbe_physical_layer; 2623230775Sjfv#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 2624230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001 2625230775Sjfv#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002 2626230775Sjfv#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004 2627230775Sjfv#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008 2628230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010 2629230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020 2630230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040 2631230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080 2632230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100 2633230775Sjfv#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200 2634230775Sjfv#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400 2635230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800 2636230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000 2637230775Sjfv#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000 2638238149Sjfv#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x4000 2639185352Sjfv 2640230775Sjfv/* Flow Control Data Sheet defined values 2641230775Sjfv * Calculation and defines taken from 802.1bb Annex O 2642230775Sjfv */ 2643205720Sjfv 2644230775Sjfv/* BitTimes (BT) conversion */ 2645238149Sjfv#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024)) 2646230775Sjfv#define IXGBE_B2BT(BT) (BT * 8) 2647215911Sjfv 2648230775Sjfv/* Calculate Delay to respond to PFC */ 2649230775Sjfv#define IXGBE_PFC_D 672 2650230775Sjfv 2651230775Sjfv/* Calculate Cable Delay */ 2652230775Sjfv#define IXGBE_CABLE_DC 5556 /* Delay Copper */ 2653230775Sjfv#define IXGBE_CABLE_DO 5000 /* Delay Optical */ 2654230775Sjfv 2655230775Sjfv/* Calculate Interface Delay X540 */ 2656230775Sjfv#define IXGBE_PHY_DC 25600 /* Delay 10G BASET */ 2657230775Sjfv#define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */ 2658230775Sjfv#define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */ 2659230775Sjfv 2660230775Sjfv#define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC) 2661230775Sjfv 2662230775Sjfv/* Calculate Interface Delay 82598, 82599 */ 2663230775Sjfv#define IXGBE_PHY_D 12800 2664230775Sjfv#define IXGBE_MAC_D 4096 2665230775Sjfv#define IXGBE_XAUI_D (2 * 1024) 2666230775Sjfv 2667230775Sjfv#define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D) 2668230775Sjfv 2669230775Sjfv/* Calculate Delay incurred from higher layer */ 2670230775Sjfv#define IXGBE_HD 6144 2671230775Sjfv 2672230775Sjfv/* Calculate PCI Bus delay for low thresholds */ 2673230775Sjfv#define IXGBE_PCI_DELAY 10000 2674230775Sjfv 2675230775Sjfv/* Calculate X540 delay value in bit times */ 2676238149Sjfv#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \ 2677238149Sjfv ((36 * \ 2678238149Sjfv (IXGBE_B2BT(_max_frame_link) + \ 2679238149Sjfv IXGBE_PFC_D + \ 2680238149Sjfv (2 * IXGBE_CABLE_DC) + \ 2681238149Sjfv (2 * IXGBE_ID_X540) + \ 2682238149Sjfv IXGBE_HD) / 25 + 1) + \ 2683238149Sjfv 2 * IXGBE_B2BT(_max_frame_tc)) 2684230775Sjfv 2685230775Sjfv/* Calculate 82599, 82598 delay value in bit times */ 2686238149Sjfv#define IXGBE_DV(_max_frame_link, _max_frame_tc) \ 2687238149Sjfv ((36 * \ 2688238149Sjfv (IXGBE_B2BT(_max_frame_link) + \ 2689238149Sjfv IXGBE_PFC_D + \ 2690238149Sjfv (2 * IXGBE_CABLE_DC) + \ 2691238149Sjfv (2 * IXGBE_ID) + \ 2692238149Sjfv IXGBE_HD) / 25 + 1) + \ 2693238149Sjfv 2 * IXGBE_B2BT(_max_frame_tc)) 2694230775Sjfv 2695230775Sjfv/* Calculate low threshold delay values */ 2696238149Sjfv#define IXGBE_LOW_DV_X540(_max_frame_tc) \ 2697238149Sjfv (2 * IXGBE_B2BT(_max_frame_tc) + \ 2698238149Sjfv (36 * IXGBE_PCI_DELAY / 25) + 1) 2699238149Sjfv#define IXGBE_LOW_DV(_max_frame_tc) \ 2700238149Sjfv (2 * IXGBE_LOW_DV_X540(_max_frame_tc)) 2701230775Sjfv 2702190873Sjfv/* Software ATR hash keys */ 2703230775Sjfv#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 2704230775Sjfv#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 2705185352Sjfv 2706215911Sjfv/* Software ATR input stream values and masks */ 2707230775Sjfv#define IXGBE_ATR_HASH_MASK 0x7fff 2708230775Sjfv#define IXGBE_ATR_L4TYPE_MASK 0x3 2709230775Sjfv#define IXGBE_ATR_L4TYPE_UDP 0x1 2710230775Sjfv#define IXGBE_ATR_L4TYPE_TCP 0x2 2711230775Sjfv#define IXGBE_ATR_L4TYPE_SCTP 0x3 2712230775Sjfv#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4 2713215911Sjfvenum ixgbe_atr_flow_type { 2714230775Sjfv IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, 2715230775Sjfv IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, 2716230775Sjfv IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, 2717230775Sjfv IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, 2718230775Sjfv IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, 2719230775Sjfv IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, 2720230775Sjfv IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, 2721230775Sjfv IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, 2722215911Sjfv}; 2723190873Sjfv 2724190873Sjfv/* Flow Director ATR input struct. */ 2725215911Sjfvunion ixgbe_atr_input { 2726217593Sjfv /* 2727217593Sjfv * Byte layout in order, all values with MSB first: 2728190873Sjfv * 2729230775Sjfv * vm_pool - 1 byte 2730230775Sjfv * flow_type - 1 byte 2731230775Sjfv * vlan_id - 2 bytes 2732230775Sjfv * src_ip - 16 bytes 2733230775Sjfv * dst_ip - 16 bytes 2734230775Sjfv * src_port - 2 bytes 2735230775Sjfv * dst_port - 2 bytes 2736230775Sjfv * flex_bytes - 2 bytes 2737230775Sjfv * bkt_hash - 2 bytes 2738190873Sjfv */ 2739215911Sjfv struct { 2740230775Sjfv u8 vm_pool; 2741230775Sjfv u8 flow_type; 2742215911Sjfv __be16 vlan_id; 2743215911Sjfv __be32 dst_ip[4]; 2744215911Sjfv __be32 src_ip[4]; 2745215911Sjfv __be16 src_port; 2746215911Sjfv __be16 dst_port; 2747215911Sjfv __be16 flex_bytes; 2748230775Sjfv __be16 bkt_hash; 2749215911Sjfv } formatted; 2750215911Sjfv __be32 dword_stream[11]; 2751190873Sjfv}; 2752190873Sjfv 2753217593Sjfv/* Flow Director compressed ATR hash input struct */ 2754217593Sjfvunion ixgbe_atr_hash_dword { 2755217593Sjfv struct { 2756217593Sjfv u8 vm_pool; 2757217593Sjfv u8 flow_type; 2758217593Sjfv __be16 vlan_id; 2759217593Sjfv } formatted; 2760217593Sjfv __be32 ip; 2761217593Sjfv struct { 2762217593Sjfv __be16 src; 2763217593Sjfv __be16 dst; 2764217593Sjfv } port; 2765217593Sjfv __be16 flex_bytes; 2766217593Sjfv __be32 dword; 2767217593Sjfv}; 2768217593Sjfv 2769217593Sjfv 2770215911Sjfv/* 2771215911Sjfv * Unavailable: The FCoE Boot Option ROM is not present in the flash. 2772215911Sjfv * Disabled: Present; boot order is not set for any targets on the port. 2773215911Sjfv * Enabled: Present; boot order is set for at least one target on the port. 2774215911Sjfv */ 2775215911Sjfvenum ixgbe_fcoe_boot_status { 2776230775Sjfv ixgbe_fcoe_bootstatus_disabled = 0, 2777230775Sjfv ixgbe_fcoe_bootstatus_enabled = 1, 2778230775Sjfv ixgbe_fcoe_bootstatus_unavailable = 0xFFFF 2779215911Sjfv}; 2780215911Sjfv 2781171384Sjfvenum ixgbe_eeprom_type { 2782171384Sjfv ixgbe_eeprom_uninitialized = 0, 2783171384Sjfv ixgbe_eeprom_spi, 2784200239Sjfv ixgbe_flash, 2785171384Sjfv ixgbe_eeprom_none /* No NVM support */ 2786171384Sjfv}; 2787171384Sjfv 2788171384Sjfvenum ixgbe_mac_type { 2789171384Sjfv ixgbe_mac_unknown = 0, 2790171384Sjfv ixgbe_mac_82598EB, 2791190873Sjfv ixgbe_mac_82599EB, 2792215911Sjfv ixgbe_mac_82599_vf, 2793230775Sjfv ixgbe_mac_X540, 2794230775Sjfv ixgbe_mac_X540_vf, 2795171384Sjfv ixgbe_num_macs 2796171384Sjfv}; 2797171384Sjfv 2798171384Sjfvenum ixgbe_phy_type { 2799171384Sjfv ixgbe_phy_unknown = 0, 2800190873Sjfv ixgbe_phy_none, 2801179055Sjfv ixgbe_phy_tn, 2802190873Sjfv ixgbe_phy_aq, 2803190873Sjfv ixgbe_phy_cu_unknown, 2804171384Sjfv ixgbe_phy_qt, 2805179055Sjfv ixgbe_phy_xaui, 2806185352Sjfv ixgbe_phy_nl, 2807205720Sjfv ixgbe_phy_sfp_passive_tyco, 2808205720Sjfv ixgbe_phy_sfp_passive_unknown, 2809205720Sjfv ixgbe_phy_sfp_active_unknown, 2810185352Sjfv ixgbe_phy_sfp_avago, 2811185352Sjfv ixgbe_phy_sfp_ftl, 2812205720Sjfv ixgbe_phy_sfp_ftl_active, 2813185352Sjfv ixgbe_phy_sfp_unknown, 2814190873Sjfv ixgbe_phy_sfp_intel, 2815190873Sjfv ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/ 2816179055Sjfv ixgbe_phy_generic 2817171384Sjfv}; 2818171384Sjfv 2819185352Sjfv/* 2820185352Sjfv * SFP+ module type IDs: 2821185352Sjfv * 2822185352Sjfv * ID Module Type 2823185352Sjfv * ============= 2824185352Sjfv * 0 SFP_DA_CU 2825185352Sjfv * 1 SFP_SR 2826185352Sjfv * 2 SFP_LR 2827230775Sjfv * 3 SFP_DA_CU_CORE0 - 82599-specific 2828230775Sjfv * 4 SFP_DA_CU_CORE1 - 82599-specific 2829230775Sjfv * 5 SFP_SR/LR_CORE0 - 82599-specific 2830230775Sjfv * 6 SFP_SR/LR_CORE1 - 82599-specific 2831185352Sjfv */ 2832185352Sjfvenum ixgbe_sfp_type { 2833185352Sjfv ixgbe_sfp_type_da_cu = 0, 2834185352Sjfv ixgbe_sfp_type_sr = 1, 2835185352Sjfv ixgbe_sfp_type_lr = 2, 2836190873Sjfv ixgbe_sfp_type_da_cu_core0 = 3, 2837190873Sjfv ixgbe_sfp_type_da_cu_core1 = 4, 2838190873Sjfv ixgbe_sfp_type_srlr_core0 = 5, 2839190873Sjfv ixgbe_sfp_type_srlr_core1 = 6, 2840205720Sjfv ixgbe_sfp_type_da_act_lmt_core0 = 7, 2841205720Sjfv ixgbe_sfp_type_da_act_lmt_core1 = 8, 2842215911Sjfv ixgbe_sfp_type_1g_cu_core0 = 9, 2843215911Sjfv ixgbe_sfp_type_1g_cu_core1 = 10, 2844238149Sjfv ixgbe_sfp_type_1g_sx_core0 = 11, 2845238149Sjfv ixgbe_sfp_type_1g_sx_core1 = 12, 2846185352Sjfv ixgbe_sfp_type_not_present = 0xFFFE, 2847185352Sjfv ixgbe_sfp_type_unknown = 0xFFFF 2848185352Sjfv}; 2849185352Sjfv 2850171384Sjfvenum ixgbe_media_type { 2851171384Sjfv ixgbe_media_type_unknown = 0, 2852171384Sjfv ixgbe_media_type_fiber, 2853247822Sjfv ixgbe_media_type_fiber_fixed, 2854171384Sjfv ixgbe_media_type_copper, 2855179055Sjfv ixgbe_media_type_backplane, 2856200239Sjfv ixgbe_media_type_cx4, 2857179055Sjfv ixgbe_media_type_virtual 2858171384Sjfv}; 2859171384Sjfv 2860171384Sjfv/* Flow Control Settings */ 2861185352Sjfvenum ixgbe_fc_mode { 2862171384Sjfv ixgbe_fc_none = 0, 2863171384Sjfv ixgbe_fc_rx_pause, 2864171384Sjfv ixgbe_fc_tx_pause, 2865171384Sjfv ixgbe_fc_full, 2866171384Sjfv ixgbe_fc_default 2867171384Sjfv}; 2868171384Sjfv 2869200239Sjfv/* Smart Speed Settings */ 2870200239Sjfv#define IXGBE_SMARTSPEED_MAX_RETRIES 3 2871200239Sjfvenum ixgbe_smart_speed { 2872200239Sjfv ixgbe_smart_speed_auto = 0, 2873200239Sjfv ixgbe_smart_speed_on, 2874200239Sjfv ixgbe_smart_speed_off 2875200239Sjfv}; 2876200239Sjfv 2877171384Sjfv/* PCI bus types */ 2878171384Sjfvenum ixgbe_bus_type { 2879171384Sjfv ixgbe_bus_type_unknown = 0, 2880171384Sjfv ixgbe_bus_type_pci, 2881171384Sjfv ixgbe_bus_type_pcix, 2882171384Sjfv ixgbe_bus_type_pci_express, 2883171384Sjfv ixgbe_bus_type_reserved 2884171384Sjfv}; 2885171384Sjfv 2886171384Sjfv/* PCI bus speeds */ 2887171384Sjfvenum ixgbe_bus_speed { 2888230775Sjfv ixgbe_bus_speed_unknown = 0, 2889230775Sjfv ixgbe_bus_speed_33 = 33, 2890230775Sjfv ixgbe_bus_speed_66 = 66, 2891230775Sjfv ixgbe_bus_speed_100 = 100, 2892230775Sjfv ixgbe_bus_speed_120 = 120, 2893230775Sjfv ixgbe_bus_speed_133 = 133, 2894230775Sjfv ixgbe_bus_speed_2500 = 2500, 2895230775Sjfv ixgbe_bus_speed_5000 = 5000, 2896238149Sjfv ixgbe_bus_speed_8000 = 8000, 2897171384Sjfv ixgbe_bus_speed_reserved 2898171384Sjfv}; 2899171384Sjfv 2900171384Sjfv/* PCI bus widths */ 2901171384Sjfvenum ixgbe_bus_width { 2902230775Sjfv ixgbe_bus_width_unknown = 0, 2903230775Sjfv ixgbe_bus_width_pcie_x1 = 1, 2904230775Sjfv ixgbe_bus_width_pcie_x2 = 2, 2905230775Sjfv ixgbe_bus_width_pcie_x4 = 4, 2906230775Sjfv ixgbe_bus_width_pcie_x8 = 8, 2907230775Sjfv ixgbe_bus_width_32 = 32, 2908230775Sjfv ixgbe_bus_width_64 = 64, 2909171384Sjfv ixgbe_bus_width_reserved 2910171384Sjfv}; 2911171384Sjfv 2912171384Sjfvstruct ixgbe_addr_filter_info { 2913171384Sjfv u32 num_mc_addrs; 2914171384Sjfv u32 rar_used_count; 2915171384Sjfv u32 mta_in_use; 2916179055Sjfv u32 overflow_promisc; 2917179055Sjfv bool user_set_promisc; 2918171384Sjfv}; 2919171384Sjfv 2920171384Sjfv/* Bus parameters */ 2921171384Sjfvstruct ixgbe_bus_info { 2922171384Sjfv enum ixgbe_bus_speed speed; 2923171384Sjfv enum ixgbe_bus_width width; 2924171384Sjfv enum ixgbe_bus_type type; 2925185352Sjfv 2926185352Sjfv u16 func; 2927190873Sjfv u16 lan_id; 2928171384Sjfv}; 2929171384Sjfv 2930171384Sjfv/* Flow control parameters */ 2931171384Sjfvstruct ixgbe_fc_info { 2932230775Sjfv u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */ 2933238149Sjfv u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */ 2934171384Sjfv u16 pause_time; /* Flow Control Pause timer */ 2935171384Sjfv bool send_xon; /* Flow control send XON */ 2936171384Sjfv bool strict_ieee; /* Strict IEEE mode */ 2937190873Sjfv bool disable_fc_autoneg; /* Do not autonegotiate FC */ 2938190873Sjfv bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ 2939185352Sjfv enum ixgbe_fc_mode current_mode; /* FC mode in effect */ 2940185352Sjfv enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */ 2941171384Sjfv}; 2942171384Sjfv 2943171384Sjfv/* Statistics counters collected by the MAC */ 2944171384Sjfvstruct ixgbe_hw_stats { 2945171384Sjfv u64 crcerrs; 2946171384Sjfv u64 illerrc; 2947171384Sjfv u64 errbc; 2948171384Sjfv u64 mspdc; 2949171384Sjfv u64 mpctotal; 2950171384Sjfv u64 mpc[8]; 2951171384Sjfv u64 mlfc; 2952171384Sjfv u64 mrfc; 2953171384Sjfv u64 rlec; 2954171384Sjfv u64 lxontxc; 2955171384Sjfv u64 lxonrxc; 2956171384Sjfv u64 lxofftxc; 2957171384Sjfv u64 lxoffrxc; 2958171384Sjfv u64 pxontxc[8]; 2959171384Sjfv u64 pxonrxc[8]; 2960171384Sjfv u64 pxofftxc[8]; 2961171384Sjfv u64 pxoffrxc[8]; 2962171384Sjfv u64 prc64; 2963171384Sjfv u64 prc127; 2964171384Sjfv u64 prc255; 2965171384Sjfv u64 prc511; 2966171384Sjfv u64 prc1023; 2967171384Sjfv u64 prc1522; 2968171384Sjfv u64 gprc; 2969171384Sjfv u64 bprc; 2970171384Sjfv u64 mprc; 2971171384Sjfv u64 gptc; 2972171384Sjfv u64 gorc; 2973171384Sjfv u64 gotc; 2974171384Sjfv u64 rnbc[8]; 2975171384Sjfv u64 ruc; 2976171384Sjfv u64 rfc; 2977171384Sjfv u64 roc; 2978171384Sjfv u64 rjc; 2979171384Sjfv u64 mngprc; 2980171384Sjfv u64 mngpdc; 2981171384Sjfv u64 mngptc; 2982171384Sjfv u64 tor; 2983171384Sjfv u64 tpr; 2984171384Sjfv u64 tpt; 2985171384Sjfv u64 ptc64; 2986171384Sjfv u64 ptc127; 2987171384Sjfv u64 ptc255; 2988171384Sjfv u64 ptc511; 2989171384Sjfv u64 ptc1023; 2990171384Sjfv u64 ptc1522; 2991171384Sjfv u64 mptc; 2992171384Sjfv u64 bptc; 2993171384Sjfv u64 xec; 2994171384Sjfv u64 qprc[16]; 2995171384Sjfv u64 qptc[16]; 2996171384Sjfv u64 qbrc[16]; 2997171384Sjfv u64 qbtc[16]; 2998190873Sjfv u64 qprdc[16]; 2999190873Sjfv u64 pxon2offc[8]; 3000190873Sjfv u64 fdirustat_add; 3001190873Sjfv u64 fdirustat_remove; 3002190873Sjfv u64 fdirfstat_fadd; 3003190873Sjfv u64 fdirfstat_fremove; 3004190873Sjfv u64 fdirmatch; 3005190873Sjfv u64 fdirmiss; 3006190873Sjfv u64 fccrc; 3007190873Sjfv u64 fclast; 3008190873Sjfv u64 fcoerpdc; 3009190873Sjfv u64 fcoeprc; 3010190873Sjfv u64 fcoeptc; 3011190873Sjfv u64 fcoedwrc; 3012190873Sjfv u64 fcoedwtc; 3013230775Sjfv u64 fcoe_noddp; 3014230775Sjfv u64 fcoe_noddp_ext_buff; 3015230775Sjfv u64 ldpcec; 3016230775Sjfv u64 pcrc8ec; 3017230775Sjfv u64 b2ospc; 3018230775Sjfv u64 b2ogprc; 3019230775Sjfv u64 o2bgptc; 3020230775Sjfv u64 o2bspc; 3021171384Sjfv}; 3022171384Sjfv 3023171384Sjfv/* forward declaration */ 3024171384Sjfvstruct ixgbe_hw; 3025171384Sjfv 3026179055Sjfv/* iterator type for walking multicast address lists */ 3027179055Sjfvtypedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, 3028230775Sjfv u32 *vmdq); 3029179055Sjfv 3030171384Sjfv/* Function pointer table */ 3031179055Sjfvstruct ixgbe_eeprom_operations { 3032179055Sjfv s32 (*init_params)(struct ixgbe_hw *); 3033179055Sjfv s32 (*read)(struct ixgbe_hw *, u16, u16 *); 3034230775Sjfv s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 3035179055Sjfv s32 (*write)(struct ixgbe_hw *, u16, u16); 3036230775Sjfv s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 3037179055Sjfv s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); 3038179055Sjfv s32 (*update_checksum)(struct ixgbe_hw *); 3039200239Sjfv u16 (*calc_checksum)(struct ixgbe_hw *); 3040179055Sjfv}; 3041171384Sjfv 3042179055Sjfvstruct ixgbe_mac_operations { 3043179055Sjfv s32 (*init_hw)(struct ixgbe_hw *); 3044179055Sjfv s32 (*reset_hw)(struct ixgbe_hw *); 3045179055Sjfv s32 (*start_hw)(struct ixgbe_hw *); 3046179055Sjfv s32 (*clear_hw_cntrs)(struct ixgbe_hw *); 3047205720Sjfv void (*enable_relaxed_ordering)(struct ixgbe_hw *); 3048179055Sjfv enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 3049185352Sjfv u32 (*get_supported_physical_layer)(struct ixgbe_hw *); 3050179055Sjfv s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 3051190873Sjfv s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); 3052190873Sjfv s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *); 3053190873Sjfv s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); 3054200239Sjfv s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *); 3055215911Sjfv s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *); 3056179055Sjfv s32 (*stop_adapter)(struct ixgbe_hw *); 3057179055Sjfv s32 (*get_bus_info)(struct ixgbe_hw *); 3058185352Sjfv void (*set_lan_id)(struct ixgbe_hw *); 3059179055Sjfv s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); 3060179055Sjfv s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 3061190873Sjfv s32 (*setup_sfp)(struct ixgbe_hw *); 3062190873Sjfv s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); 3063230775Sjfv s32 (*disable_sec_rx_path)(struct ixgbe_hw *); 3064230775Sjfv s32 (*enable_sec_rx_path)(struct ixgbe_hw *); 3065194875Sjfv s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16); 3066194875Sjfv void (*release_swfw_sync)(struct ixgbe_hw *, u16); 3067179055Sjfv 3068171384Sjfv /* Link */ 3069215911Sjfv void (*disable_tx_laser)(struct ixgbe_hw *); 3070215911Sjfv void (*enable_tx_laser)(struct ixgbe_hw *); 3071215911Sjfv void (*flap_tx_laser)(struct ixgbe_hw *); 3072247822Sjfv s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3073179055Sjfv s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); 3074179055Sjfv s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, 3075230775Sjfv bool *); 3076171384Sjfv 3077230775Sjfv /* Packet Buffer manipulation */ 3078230775Sjfv void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int); 3079230775Sjfv 3080171384Sjfv /* LED */ 3081179055Sjfv s32 (*led_on)(struct ixgbe_hw *, u32); 3082179055Sjfv s32 (*led_off)(struct ixgbe_hw *, u32); 3083179055Sjfv s32 (*blink_led_start)(struct ixgbe_hw *, u32); 3084179055Sjfv s32 (*blink_led_stop)(struct ixgbe_hw *, u32); 3085171384Sjfv 3086171384Sjfv /* RAR, Multicast, VLAN */ 3087179055Sjfv s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); 3088230775Sjfv s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *); 3089181003Sjfv s32 (*clear_rar)(struct ixgbe_hw *, u32); 3090190873Sjfv s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32); 3091179055Sjfv s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); 3092238149Sjfv s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32); 3093181003Sjfv s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); 3094179055Sjfv s32 (*init_rx_addrs)(struct ixgbe_hw *); 3095179055Sjfv s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32, 3096230775Sjfv ixgbe_mc_addr_itr); 3097179055Sjfv s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, 3098230775Sjfv ixgbe_mc_addr_itr, bool clear); 3099179055Sjfv s32 (*enable_mc)(struct ixgbe_hw *); 3100179055Sjfv s32 (*disable_mc)(struct ixgbe_hw *); 3101179055Sjfv s32 (*clear_vfta)(struct ixgbe_hw *); 3102179055Sjfv s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool); 3103230775Sjfv s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *); 3104181003Sjfv s32 (*init_uta_tables)(struct ixgbe_hw *); 3105215911Sjfv void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int); 3106215911Sjfv void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int); 3107171384Sjfv 3108171384Sjfv /* Flow Control */ 3109238149Sjfv s32 (*fc_enable)(struct ixgbe_hw *); 3110230775Sjfv 3111230775Sjfv /* Manageability interface */ 3112230775Sjfv s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8); 3113251964Sjfv s32 (*dmac_config)(struct ixgbe_hw *hw); 3114251964Sjfv s32 (*dmac_update_tcs)(struct ixgbe_hw *hw); 3115251964Sjfv s32 (*dmac_config_tcs)(struct ixgbe_hw *hw); 3116251964Sjfv void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map); 3117171384Sjfv}; 3118171384Sjfv 3119179055Sjfvstruct ixgbe_phy_operations { 3120179055Sjfv s32 (*identify)(struct ixgbe_hw *); 3121185352Sjfv s32 (*identify_sfp)(struct ixgbe_hw *); 3122190873Sjfv s32 (*init)(struct ixgbe_hw *); 3123179055Sjfv s32 (*reset)(struct ixgbe_hw *); 3124179055Sjfv s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); 3125179055Sjfv s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); 3126251964Sjfv s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *); 3127251964Sjfv s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16); 3128179055Sjfv s32 (*setup_link)(struct ixgbe_hw *); 3129247822Sjfv s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3130179055Sjfv s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); 3131179055Sjfv s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); 3132185352Sjfv s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); 3133185352Sjfv s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); 3134247822Sjfv s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *); 3135185352Sjfv s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); 3136185352Sjfv s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); 3137190873Sjfv void (*i2c_bus_clear)(struct ixgbe_hw *); 3138205720Sjfv s32 (*check_overtemp)(struct ixgbe_hw *); 3139179055Sjfv}; 3140179055Sjfv 3141179055Sjfvstruct ixgbe_eeprom_info { 3142230775Sjfv struct ixgbe_eeprom_operations ops; 3143230775Sjfv enum ixgbe_eeprom_type type; 3144230775Sjfv u32 semaphore_delay; 3145230775Sjfv u16 word_size; 3146230775Sjfv u16 address_bits; 3147230775Sjfv u16 word_page_size; 3148179055Sjfv}; 3149179055Sjfv 3150205720Sjfv#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 3151171384Sjfvstruct ixgbe_mac_info { 3152230775Sjfv struct ixgbe_mac_operations ops; 3153230775Sjfv enum ixgbe_mac_type type; 3154230775Sjfv u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 3155230775Sjfv u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 3156230775Sjfv u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 3157200239Sjfv /* prefix for World Wide Node Name (WWNN) */ 3158230775Sjfv u16 wwnn_prefix; 3159200239Sjfv /* prefix for World Wide Port Name (WWPN) */ 3160230775Sjfv u16 wwpn_prefix; 3161215911Sjfv#define IXGBE_MAX_MTA 128 3162230775Sjfv u32 mta_shadow[IXGBE_MAX_MTA]; 3163230775Sjfv s32 mc_filter_type; 3164230775Sjfv u32 mcft_size; 3165230775Sjfv u32 vft_size; 3166230775Sjfv u32 num_rar_entries; 3167230775Sjfv u32 rar_highwater; 3168230775Sjfv u32 rx_pb_size; 3169230775Sjfv u32 max_tx_queues; 3170230775Sjfv u32 max_rx_queues; 3171230775Sjfv u32 orig_autoc; 3172247822Sjfv u32 cached_autoc; 3173238149Sjfv u8 san_mac_rar_index; 3174247822Sjfv bool get_link_status; 3175238149Sjfv u32 orig_autoc2; 3176238149Sjfv u16 max_msix_vectors; 3177230775Sjfv bool arc_subsystem_valid; 3178230775Sjfv bool orig_link_settings_stored; 3179230775Sjfv bool autotry_restart; 3180230775Sjfv u8 flags; 3181171384Sjfv}; 3182171384Sjfv 3183171384Sjfvstruct ixgbe_phy_info { 3184230775Sjfv struct ixgbe_phy_operations ops; 3185230775Sjfv enum ixgbe_phy_type type; 3186230775Sjfv u32 addr; 3187230775Sjfv u32 id; 3188230775Sjfv enum ixgbe_sfp_type sfp_type; 3189230775Sjfv bool sfp_setup_needed; 3190230775Sjfv u32 revision; 3191230775Sjfv enum ixgbe_media_type media_type; 3192230775Sjfv bool reset_disable; 3193230775Sjfv ixgbe_autoneg_advertised autoneg_advertised; 3194230775Sjfv enum ixgbe_smart_speed smart_speed; 3195230775Sjfv bool smart_speed_active; 3196230775Sjfv bool multispeed_fiber; 3197230775Sjfv bool reset_if_overtemp; 3198171384Sjfv}; 3199171384Sjfv 3200215911Sjfv#include "ixgbe_mbx.h" 3201215911Sjfv 3202215911Sjfvstruct ixgbe_mbx_operations { 3203215911Sjfv void (*init_params)(struct ixgbe_hw *hw); 3204215911Sjfv s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16); 3205215911Sjfv s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16); 3206215911Sjfv s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16); 3207215911Sjfv s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16); 3208215911Sjfv s32 (*check_for_msg)(struct ixgbe_hw *, u16); 3209215911Sjfv s32 (*check_for_ack)(struct ixgbe_hw *, u16); 3210215911Sjfv s32 (*check_for_rst)(struct ixgbe_hw *, u16); 3211215911Sjfv}; 3212215911Sjfv 3213215911Sjfvstruct ixgbe_mbx_stats { 3214215911Sjfv u32 msgs_tx; 3215215911Sjfv u32 msgs_rx; 3216215911Sjfv 3217215911Sjfv u32 acks; 3218215911Sjfv u32 reqs; 3219215911Sjfv u32 rsts; 3220215911Sjfv}; 3221215911Sjfv 3222215911Sjfvstruct ixgbe_mbx_info { 3223215911Sjfv struct ixgbe_mbx_operations ops; 3224215911Sjfv struct ixgbe_mbx_stats stats; 3225215911Sjfv u32 timeout; 3226215911Sjfv u32 usec_delay; 3227215911Sjfv u32 v2p_mailbox; 3228215911Sjfv u16 size; 3229215911Sjfv}; 3230215911Sjfv 3231171384Sjfvstruct ixgbe_hw { 3232230775Sjfv u8 *hw_addr; 3233230775Sjfv void *back; 3234230775Sjfv struct ixgbe_mac_info mac; 3235230775Sjfv struct ixgbe_addr_filter_info addr_ctrl; 3236230775Sjfv struct ixgbe_fc_info fc; 3237230775Sjfv struct ixgbe_phy_info phy; 3238230775Sjfv struct ixgbe_eeprom_info eeprom; 3239230775Sjfv struct ixgbe_bus_info bus; 3240230775Sjfv struct ixgbe_mbx_info mbx; 3241230775Sjfv u16 device_id; 3242230775Sjfv u16 vendor_id; 3243230775Sjfv u16 subsystem_device_id; 3244230775Sjfv u16 subsystem_vendor_id; 3245230775Sjfv u8 revision_id; 3246230775Sjfv bool adapter_stopped; 3247247822Sjfv int api_version; 3248230775Sjfv bool force_full_reset; 3249238149Sjfv bool allow_unsupported_sfp; 3250251964Sjfv bool mng_fw_enabled; 3251251964Sjfv bool wol_enabled; 3252171384Sjfv}; 3253171384Sjfv 3254171384Sjfv#define ixgbe_call_func(hw, func, params, error) \ 3255230775Sjfv (func != NULL) ? func params : error 3256171384Sjfv 3257194875Sjfv 3258171384Sjfv/* Error Codes */ 3259230775Sjfv#define IXGBE_SUCCESS 0 3260230775Sjfv#define IXGBE_ERR_EEPROM -1 3261230775Sjfv#define IXGBE_ERR_EEPROM_CHECKSUM -2 3262230775Sjfv#define IXGBE_ERR_PHY -3 3263230775Sjfv#define IXGBE_ERR_CONFIG -4 3264230775Sjfv#define IXGBE_ERR_PARAM -5 3265230775Sjfv#define IXGBE_ERR_MAC_TYPE -6 3266230775Sjfv#define IXGBE_ERR_UNKNOWN_PHY -7 3267230775Sjfv#define IXGBE_ERR_LINK_SETUP -8 3268230775Sjfv#define IXGBE_ERR_ADAPTER_STOPPED -9 3269230775Sjfv#define IXGBE_ERR_INVALID_MAC_ADDR -10 3270230775Sjfv#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 3271230775Sjfv#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 3272230775Sjfv#define IXGBE_ERR_INVALID_LINK_SETTINGS -13 3273230775Sjfv#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 3274230775Sjfv#define IXGBE_ERR_RESET_FAILED -15 3275230775Sjfv#define IXGBE_ERR_SWFW_SYNC -16 3276230775Sjfv#define IXGBE_ERR_PHY_ADDR_INVALID -17 3277230775Sjfv#define IXGBE_ERR_I2C -18 3278230775Sjfv#define IXGBE_ERR_SFP_NOT_SUPPORTED -19 3279230775Sjfv#define IXGBE_ERR_SFP_NOT_PRESENT -20 3280230775Sjfv#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 3281230775Sjfv#define IXGBE_ERR_NO_SAN_ADDR_PTR -22 3282230775Sjfv#define IXGBE_ERR_FDIR_REINIT_FAILED -23 3283230775Sjfv#define IXGBE_ERR_EEPROM_VERSION -24 3284230775Sjfv#define IXGBE_ERR_NO_SPACE -25 3285230775Sjfv#define IXGBE_ERR_OVERTEMP -26 3286230775Sjfv#define IXGBE_ERR_FC_NOT_NEGOTIATED -27 3287230775Sjfv#define IXGBE_ERR_FC_NOT_SUPPORTED -28 3288230775Sjfv#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30 3289230775Sjfv#define IXGBE_ERR_PBA_SECTION -31 3290230775Sjfv#define IXGBE_ERR_INVALID_ARGUMENT -32 3291230775Sjfv#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33 3292230775Sjfv#define IXGBE_ERR_OUT_OF_MEM -34 3293247822Sjfv#define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36 3294251964Sjfv#define IXGBE_ERR_EEPROM_PROTECTED_REGION -37 3295171384Sjfv 3296230775Sjfv#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 3297171384Sjfv 3298171384Sjfv#endif /* _IXGBE_TYPE_H_ */ 3299