1251964Sjfv/****************************************************************************** 2251964Sjfv 3251964Sjfv Copyright (c) 2001-2013, Intel Corporation 4251964Sjfv All rights reserved. 5251964Sjfv 6251964Sjfv Redistribution and use in source and binary forms, with or without 7251964Sjfv modification, are permitted provided that the following conditions are met: 8251964Sjfv 9251964Sjfv 1. Redistributions of source code must retain the above copyright notice, 10251964Sjfv this list of conditions and the following disclaimer. 11251964Sjfv 12251964Sjfv 2. Redistributions in binary form must reproduce the above copyright 13251964Sjfv notice, this list of conditions and the following disclaimer in the 14251964Sjfv documentation and/or other materials provided with the distribution. 15251964Sjfv 16251964Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17251964Sjfv contributors may be used to endorse or promote products derived from 18251964Sjfv this software without specific prior written permission. 19251964Sjfv 20251964Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21251964Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22251964Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23251964Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24251964Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25251964Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26251964Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27251964Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28251964Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29251964Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30251964Sjfv POSSIBILITY OF SUCH DAMAGE. 31251964Sjfv 32251964Sjfv******************************************************************************/ 33251964Sjfv/*$FreeBSD$*/ 34251964Sjfv 35251964Sjfv#ifndef _IXGBE_DCB_82598_H_ 36251964Sjfv#define _IXGBE_DCB_82598_H_ 37251964Sjfv 38251964Sjfv/* DCB register definitions */ 39251964Sjfv 40251964Sjfv#define IXGBE_DPMCS_MTSOS_SHIFT 16 41251964Sjfv#define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 42251964Sjfv * 1 DFP - Deficit Fixed Priority */ 43251964Sjfv#define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */ 44251964Sjfv#define IXGBE_DPMCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 45251964Sjfv#define IXGBE_DPMCS_TSOEF 0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */ 46251964Sjfv 47251964Sjfv#define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */ 48251964Sjfv 49251964Sjfv#define IXGBE_RT2CR_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ 50251964Sjfv#define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */ 51251964Sjfv 52251964Sjfv#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet 53251964Sjfv * buffers enable */ 54251964Sjfv#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores 55251964Sjfv * (RSS) enable */ 56251964Sjfv 57251964Sjfv#define IXGBE_TDTQ2TCCR_MCL_SHIFT 12 58251964Sjfv#define IXGBE_TDTQ2TCCR_BWG_SHIFT 9 59251964Sjfv#define IXGBE_TDTQ2TCCR_GSP 0x40000000 60251964Sjfv#define IXGBE_TDTQ2TCCR_LSP 0x80000000 61251964Sjfv 62251964Sjfv#define IXGBE_TDPT2TCCR_MCL_SHIFT 12 63251964Sjfv#define IXGBE_TDPT2TCCR_BWG_SHIFT 9 64251964Sjfv#define IXGBE_TDPT2TCCR_GSP 0x40000000 65251964Sjfv#define IXGBE_TDPT2TCCR_LSP 0x80000000 66251964Sjfv 67251964Sjfv#define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 68251964Sjfv * 1 DFP - Deficit Fixed Priority */ 69251964Sjfv#define IXGBE_PDPMCS_ARBDIS 0x00000040 /* Arbiter disable */ 70251964Sjfv#define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */ 71251964Sjfv 72251964Sjfv#define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */ 73251964Sjfv 74251964Sjfv#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 75251964Sjfv#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 76251964Sjfv#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 77251964Sjfv#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 78251964Sjfv 79251964Sjfv/* DCB driver APIs */ 80251964Sjfv 81251964Sjfv/* DCB PFC */ 82251964Sjfvs32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8); 83251964Sjfv 84251964Sjfv/* DCB stats */ 85251964Sjfvs32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *); 86251964Sjfvs32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *, 87251964Sjfv struct ixgbe_hw_stats *, u8); 88251964Sjfvs32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *, 89251964Sjfv struct ixgbe_hw_stats *, u8); 90251964Sjfv 91251964Sjfv/* DCB config arbiters */ 92251964Sjfvs32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, 93251964Sjfv u8 *, u8 *); 94251964Sjfvs32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, 95251964Sjfv u8 *, u8 *); 96251964Sjfvs32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, u8 *); 97251964Sjfv 98251964Sjfv/* DCB initialization */ 99251964Sjfvs32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, u8 *); 100251964Sjfv#endif /* _IXGBE_DCB_82958_H_ */ 101