1179055Sjfv/****************************************************************************** 2171384Sjfv 3251964Sjfv Copyright (c) 2001-2013, Intel Corporation 4179055Sjfv All rights reserved. 5179055Sjfv 6179055Sjfv Redistribution and use in source and binary forms, with or without 7179055Sjfv modification, are permitted provided that the following conditions are met: 8179055Sjfv 9179055Sjfv 1. Redistributions of source code must retain the above copyright notice, 10179055Sjfv this list of conditions and the following disclaimer. 11179055Sjfv 12179055Sjfv 2. Redistributions in binary form must reproduce the above copyright 13179055Sjfv notice, this list of conditions and the following disclaimer in the 14179055Sjfv documentation and/or other materials provided with the distribution. 15179055Sjfv 16179055Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17179055Sjfv contributors may be used to endorse or promote products derived from 18179055Sjfv this software without specific prior written permission. 19179055Sjfv 20179055Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21179055Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22179055Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23179055Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24179055Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25179055Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26179055Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27179055Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28179055Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29179055Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30179055Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD$*/ 34171384Sjfv 35185352Sjfv 36171384Sjfv#ifndef _IXGBE_H_ 37171384Sjfv#define _IXGBE_H_ 38171384Sjfv 39171384Sjfv 40171384Sjfv#include <sys/param.h> 41171384Sjfv#include <sys/systm.h> 42243725Sjfv#ifndef IXGBE_LEGACY_TX 43194875Sjfv#include <sys/buf_ring.h> 44194875Sjfv#endif 45171384Sjfv#include <sys/mbuf.h> 46171384Sjfv#include <sys/protosw.h> 47171384Sjfv#include <sys/socket.h> 48171384Sjfv#include <sys/malloc.h> 49171384Sjfv#include <sys/kernel.h> 50171384Sjfv#include <sys/module.h> 51171384Sjfv#include <sys/sockio.h> 52171384Sjfv 53171384Sjfv#include <net/if.h> 54171384Sjfv#include <net/if_arp.h> 55171384Sjfv#include <net/bpf.h> 56171384Sjfv#include <net/ethernet.h> 57171384Sjfv#include <net/if_dl.h> 58171384Sjfv#include <net/if_media.h> 59171384Sjfv 60171384Sjfv#include <net/bpf.h> 61171384Sjfv#include <net/if_types.h> 62171384Sjfv#include <net/if_vlan_var.h> 63171384Sjfv 64171384Sjfv#include <netinet/in_systm.h> 65171384Sjfv#include <netinet/in.h> 66171384Sjfv#include <netinet/if_ether.h> 67171384Sjfv#include <netinet/ip.h> 68171384Sjfv#include <netinet/ip6.h> 69171384Sjfv#include <netinet/tcp.h> 70190873Sjfv#include <netinet/tcp_lro.h> 71171384Sjfv#include <netinet/udp.h> 72171384Sjfv 73171384Sjfv#include <machine/in_cksum.h> 74171384Sjfv 75171384Sjfv#include <sys/bus.h> 76171384Sjfv#include <machine/bus.h> 77171384Sjfv#include <sys/rman.h> 78171384Sjfv#include <machine/resource.h> 79171384Sjfv#include <vm/vm.h> 80171384Sjfv#include <vm/pmap.h> 81171384Sjfv#include <machine/clock.h> 82171384Sjfv#include <dev/pci/pcivar.h> 83171384Sjfv#include <dev/pci/pcireg.h> 84171384Sjfv#include <sys/proc.h> 85171384Sjfv#include <sys/sysctl.h> 86171384Sjfv#include <sys/endian.h> 87171384Sjfv#include <sys/taskqueue.h> 88179055Sjfv#include <sys/pcpu.h> 89194875Sjfv#include <sys/smp.h> 90194875Sjfv#include <machine/smp.h> 91171384Sjfv 92171384Sjfv#include "ixgbe_api.h" 93171384Sjfv 94171384Sjfv/* Tunables */ 95171384Sjfv 96171384Sjfv/* 97172043Sjfv * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 98171384Sjfv * number of transmit descriptors allocated by the driver. Increasing this 99171384Sjfv * value allows the driver to queue more transmits. Each descriptor is 16 100172043Sjfv * bytes. Performance tests have show the 2K value to be optimal for top 101172043Sjfv * performance. 102171384Sjfv */ 103190873Sjfv#define DEFAULT_TXD 1024 104172043Sjfv#define PERFORM_TXD 2048 105171384Sjfv#define MAX_TXD 4096 106171384Sjfv#define MIN_TXD 64 107171384Sjfv 108171384Sjfv/* 109172043Sjfv * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 110172043Sjfv * number of receive descriptors allocated for each RX queue. Increasing this 111171384Sjfv * value allows the driver to buffer more incoming packets. Each descriptor 112172043Sjfv * is 16 bytes. A receive buffer is also allocated for each descriptor. 113171384Sjfv * 114172043Sjfv * Note: with 8 rings and a dual port card, it is possible to bump up 115172043Sjfv * against the system mbuf pool limit, you can tune nmbclusters 116172043Sjfv * to adjust for this. 117171384Sjfv */ 118190873Sjfv#define DEFAULT_RXD 1024 119172043Sjfv#define PERFORM_RXD 2048 120171384Sjfv#define MAX_RXD 4096 121171384Sjfv#define MIN_RXD 64 122171384Sjfv 123172043Sjfv/* Alignment for rings */ 124172043Sjfv#define DBA_ALIGN 128 125172043Sjfv 126171384Sjfv/* 127171384Sjfv * This parameter controls the maximum no of times the driver will loop in 128171384Sjfv * the isr. Minimum Value = 1 129171384Sjfv */ 130185352Sjfv#define MAX_LOOP 10 131171384Sjfv 132171384Sjfv/* 133200239Sjfv * This is the max watchdog interval, ie. the time that can 134200239Sjfv * pass between any two TX clean operations, such only happening 135200239Sjfv * when the TX hardware is functioning. 136171384Sjfv */ 137200239Sjfv#define IXGBE_WATCHDOG (10 * hz) 138171384Sjfv 139171384Sjfv/* 140171384Sjfv * This parameters control when the driver calls the routine to reclaim 141171384Sjfv * transmit descriptors. 142171384Sjfv */ 143171384Sjfv#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 144171384Sjfv#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 145171384Sjfv 146171384Sjfv#define IXGBE_MAX_FRAME_SIZE 0x3F00 147171384Sjfv 148172043Sjfv/* Flow control constants */ 149200239Sjfv#define IXGBE_FC_PAUSE 0xFFFF 150172043Sjfv#define IXGBE_FC_HI 0x20000 151172043Sjfv#define IXGBE_FC_LO 0x10000 152171384Sjfv 153239940Sscottl/* 154239940Sscottl * Used for optimizing small rx mbufs. Effort is made to keep the copy 155239940Sscottl * small and aligned for the CPU L1 cache. 156239940Sscottl * 157239940Sscottl * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 158239940Sscottl * 32 byte alignment needed for the fast bcopy results in 8 bytes being 159239940Sscottl * wasted. Getting 64 byte alignment, which _should_ be ideal for 160239940Sscottl * modern Intel CPUs, results in 40 bytes wasted and a significant drop 161239940Sscottl * in observed efficiency of the optimization, 97.9% -> 81.8%. 162239940Sscottl */ 163239940Sscottl#define IXGBE_RX_COPY_LEN 160 164239940Sscottl#define IXGBE_RX_COPY_ALIGN (MHLEN - IXGBE_RX_COPY_LEN) 165239940Sscottl 166221189Sjfv/* Keep older OS drivers building... */ 167221189Sjfv#if !defined(SYSCTL_ADD_UQUAD) 168221189Sjfv#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 169221189Sjfv#endif 170221189Sjfv 171171384Sjfv/* Defines for printing debug information */ 172171384Sjfv#define DEBUG_INIT 0 173171384Sjfv#define DEBUG_IOCTL 0 174171384Sjfv#define DEBUG_HW 0 175171384Sjfv 176171384Sjfv#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 177171384Sjfv#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 178171384Sjfv#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 179171384Sjfv#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 180171384Sjfv#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 181171384Sjfv#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 182171384Sjfv#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 183171384Sjfv#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 184171384Sjfv#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 185171384Sjfv 186171384Sjfv#define MAX_NUM_MULTICAST_ADDRESSES 128 187190873Sjfv#define IXGBE_82598_SCATTER 100 188190873Sjfv#define IXGBE_82599_SCATTER 32 189185352Sjfv#define MSIX_82598_BAR 3 190185352Sjfv#define MSIX_82599_BAR 4 191234620Sbz#define IXGBE_TSO_SIZE 262140 192171384Sjfv#define IXGBE_TX_BUFFER_SIZE ((u32) 1514) 193205720Sjfv#define IXGBE_RX_HDR 128 194194875Sjfv#define IXGBE_VFTA_SIZE 128 195194875Sjfv#define IXGBE_BR_SIZE 4096 196230775Sjfv#define IXGBE_QUEUE_MIN_FREE 32 197171384Sjfv 198243718Sjfv/* IOCTL define to gather SFP+ Diagnostic data */ 199243718Sjfv#define SIOCGI2C SIOCGIFGENERIC 200243718Sjfv 201205904Sjfv/* Offload bits in mbuf flag */ 202205904Sjfv#if __FreeBSD_version >= 800000 203205904Sjfv#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 204205904Sjfv#else 205205904Sjfv#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 206205904Sjfv#endif 207205904Sjfv 208171384Sjfv/* 209171384Sjfv * Interrupt Moderation parameters 210171384Sjfv */ 211185352Sjfv#define IXGBE_LOW_LATENCY 128 212185352Sjfv#define IXGBE_AVE_LATENCY 400 213185352Sjfv#define IXGBE_BULK_LATENCY 1200 214185352Sjfv#define IXGBE_LINK_ITR 2000 215171384Sjfv 216251964Sjfv 217171384Sjfv/* 218185352Sjfv ***************************************************************************** 219171384Sjfv * vendor_info_array 220171384Sjfv * 221171384Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 222171384Sjfv * should load. 223171384Sjfv * 224185352Sjfv ***************************************************************************** 225171384Sjfv */ 226171384Sjfvtypedef struct _ixgbe_vendor_info_t { 227171384Sjfv unsigned int vendor_id; 228171384Sjfv unsigned int device_id; 229171384Sjfv unsigned int subvendor_id; 230171384Sjfv unsigned int subdevice_id; 231171384Sjfv unsigned int index; 232185352Sjfv} ixgbe_vendor_info_t; 233171384Sjfv 234251964Sjfv 235243718Sjfv/* This is used to get SFP+ module data */ 236243718Sjfvstruct ixgbe_i2c_req { 237243718Sjfv u8 dev_addr; 238243718Sjfv u8 offset; 239243718Sjfv u8 len; 240243718Sjfv u8 data[8]; 241243718Sjfv}; 242171384Sjfv 243171384Sjfvstruct ixgbe_tx_buf { 244243736Sjfv union ixgbe_adv_tx_desc *eop; 245171384Sjfv struct mbuf *m_head; 246171384Sjfv bus_dmamap_t map; 247171384Sjfv}; 248171384Sjfv 249171384Sjfvstruct ixgbe_rx_buf { 250243714Sjfv struct mbuf *buf; 251205720Sjfv struct mbuf *fmp; 252244514Sluigi bus_dmamap_t pmap; 253239940Sscottl u_int flags; 254239940Sscottl#define IXGBE_RX_COPY 0x01 255243714Sjfv uint64_t addr; 256171384Sjfv}; 257171384Sjfv 258171384Sjfv/* 259171384Sjfv * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 260171384Sjfv */ 261171384Sjfvstruct ixgbe_dma_alloc { 262171384Sjfv bus_addr_t dma_paddr; 263171384Sjfv caddr_t dma_vaddr; 264171384Sjfv bus_dma_tag_t dma_tag; 265171384Sjfv bus_dmamap_t dma_map; 266171384Sjfv bus_dma_segment_t dma_seg; 267171384Sjfv bus_size_t dma_size; 268171384Sjfv int dma_nseg; 269171384Sjfv}; 270171384Sjfv 271171384Sjfv/* 272205720Sjfv** Driver queue struct: this is the interrupt container 273205720Sjfv** for the associated tx and rx ring. 274205720Sjfv*/ 275205720Sjfvstruct ix_queue { 276205720Sjfv struct adapter *adapter; 277205720Sjfv u32 msix; /* This queue's MSIX vector */ 278205720Sjfv u32 eims; /* This queue's EIMS bit */ 279205720Sjfv u32 eitr_setting; 280205720Sjfv struct resource *res; 281205720Sjfv void *tag; 282205720Sjfv struct tx_ring *txr; 283205720Sjfv struct rx_ring *rxr; 284205720Sjfv struct task que_task; 285205720Sjfv struct taskqueue *tq; 286205720Sjfv u64 irqs; 287205720Sjfv}; 288205720Sjfv 289205720Sjfv/* 290205720Sjfv * The transmit ring, one per queue 291171384Sjfv */ 292171384Sjfvstruct tx_ring { 293171384Sjfv struct adapter *adapter; 294179055Sjfv struct mtx tx_mtx; 295171384Sjfv u32 me; 296243729Sjfv int watchdog_time; 297243729Sjfv union ixgbe_adv_tx_desc *tx_base; 298243729Sjfv struct ixgbe_tx_buf *tx_buffers; 299243729Sjfv struct ixgbe_dma_alloc txdma; 300243729Sjfv volatile u16 tx_avail; 301243729Sjfv u16 next_avail_desc; 302243729Sjfv u16 next_to_clean; 303243729Sjfv u16 process_limit; 304243729Sjfv u16 num_desc; 305243716Sjfv enum { 306243716Sjfv IXGBE_QUEUE_IDLE, 307243716Sjfv IXGBE_QUEUE_WORKING, 308243716Sjfv IXGBE_QUEUE_HUNG, 309243716Sjfv } queue_status; 310179055Sjfv u32 txd_cmd; 311171384Sjfv bus_dma_tag_t txtag; 312185352Sjfv char mtx_name[16]; 313243725Sjfv#ifndef IXGBE_LEGACY_TX 314194875Sjfv struct buf_ring *br; 315240968Sjhb struct task txq_task; 316194875Sjfv#endif 317200239Sjfv#ifdef IXGBE_FDIR 318200239Sjfv u16 atr_sample; 319200239Sjfv u16 atr_count; 320200239Sjfv#endif 321205720Sjfv u32 bytes; /* used for AIM */ 322205720Sjfv u32 packets; 323179055Sjfv /* Soft Stats */ 324243729Sjfv unsigned long tso_tx; 325243729Sjfv unsigned long no_tx_map_avail; 326243729Sjfv unsigned long no_tx_dma_setup; 327205720Sjfv u64 no_desc_avail; 328185352Sjfv u64 total_packets; 329171384Sjfv}; 330171384Sjfv 331171384Sjfv 332171384Sjfv/* 333171384Sjfv * The Receive ring, one per rx queue 334171384Sjfv */ 335171384Sjfvstruct rx_ring { 336179055Sjfv struct adapter *adapter; 337179055Sjfv struct mtx rx_mtx; 338179055Sjfv u32 me; 339179055Sjfv union ixgbe_adv_rx_desc *rx_base; 340179055Sjfv struct ixgbe_dma_alloc rxdma; 341179055Sjfv struct lro_ctrl lro; 342194875Sjfv bool lro_enabled; 343200239Sjfv bool hw_rsc; 344205720Sjfv bool discard; 345230775Sjfv bool vtag_strip; 346243729Sjfv u16 next_to_refresh; 347243729Sjfv u16 next_to_check; 348243729Sjfv u16 num_desc; 349243729Sjfv u16 mbuf_sz; 350243729Sjfv u16 process_limit; 351205720Sjfv char mtx_name[16]; 352179055Sjfv struct ixgbe_rx_buf *rx_buffers; 353244514Sluigi bus_dma_tag_t ptag; 354185352Sjfv 355185352Sjfv u32 bytes; /* Used for AIM calc */ 356205720Sjfv u32 packets; 357185352Sjfv 358171384Sjfv /* Soft stats */ 359179055Sjfv u64 rx_irq; 360239940Sscottl u64 rx_copies; 361185352Sjfv u64 rx_packets; 362185352Sjfv u64 rx_bytes; 363205720Sjfv u64 rx_discarded; 364200239Sjfv u64 rsc_num; 365200239Sjfv#ifdef IXGBE_FDIR 366200239Sjfv u64 flm; 367200239Sjfv#endif 368171384Sjfv}; 369171384Sjfv 370171384Sjfv/* Our adapter structure */ 371171384Sjfvstruct adapter { 372205720Sjfv struct ifnet *ifp; 373205720Sjfv struct ixgbe_hw hw; 374171384Sjfv 375171384Sjfv struct ixgbe_osdep osdep; 376205720Sjfv struct device *dev; 377171384Sjfv 378205720Sjfv struct resource *pci_mem; 379205720Sjfv struct resource *msix_mem; 380179055Sjfv 381171384Sjfv /* 382194875Sjfv * Interrupt resources: this set is 383194875Sjfv * either used for legacy, or for Link 384194875Sjfv * when doing MSIX 385171384Sjfv */ 386205720Sjfv void *tag; 387205720Sjfv struct resource *res; 388171384Sjfv 389205720Sjfv struct ifmedia media; 390205720Sjfv struct callout timer; 391205720Sjfv int msix; 392205720Sjfv int if_flags; 393179055Sjfv 394205720Sjfv struct mtx core_mtx; 395179055Sjfv 396205720Sjfv eventhandler_tag vlan_attach; 397205720Sjfv eventhandler_tag vlan_detach; 398194875Sjfv 399205720Sjfv u16 num_vlans; 400205720Sjfv u16 num_queues; 401194875Sjfv 402215911Sjfv /* 403215911Sjfv ** Shadow VFTA table, this is needed because 404215911Sjfv ** the real vlan filter table gets cleared during 405215911Sjfv ** a soft reset and the driver needs to be able 406215911Sjfv ** to repopulate it. 407215911Sjfv */ 408215911Sjfv u32 shadow_vfta[IXGBE_VFTA_SIZE]; 409215911Sjfv 410215911Sjfv /* Info about the interface */ 411205720Sjfv u32 optics; 412230775Sjfv u32 fc; /* local flow ctrl setting */ 413209609Sjfv int advertise; /* link speeds */ 414205720Sjfv bool link_active; 415205720Sjfv u16 max_frame_size; 416217593Sjfv u16 num_segs; 417205720Sjfv u32 link_speed; 418205720Sjfv bool link_up; 419205720Sjfv u32 linkvec; 420171384Sjfv 421185352Sjfv /* Mbuf cluster size */ 422205720Sjfv u32 rx_mbuf_sz; 423171384Sjfv 424190873Sjfv /* Support for pluggable optics */ 425205720Sjfv bool sfp_probe; 426205720Sjfv struct task link_task; /* Link tasklet */ 427205720Sjfv struct task mod_task; /* SFP tasklet */ 428205720Sjfv struct task msf_task; /* Multispeed Fiber */ 429200239Sjfv#ifdef IXGBE_FDIR 430200239Sjfv int fdir_reinit; 431200239Sjfv struct task fdir_task; 432200239Sjfv#endif 433190873Sjfv struct taskqueue *tq; 434185352Sjfv 435171384Sjfv /* 436205720Sjfv ** Queues: 437205720Sjfv ** This is the irq holder, it has 438205720Sjfv ** and RX/TX pair or rings associated 439205720Sjfv ** with it. 440205720Sjfv */ 441205720Sjfv struct ix_queue *queues; 442205720Sjfv 443205720Sjfv /* 444171384Sjfv * Transmit rings: 445171384Sjfv * Allocated at run time, an array of rings. 446171384Sjfv */ 447205720Sjfv struct tx_ring *tx_rings; 448243729Sjfv u32 num_tx_desc; 449171384Sjfv 450171384Sjfv /* 451171384Sjfv * Receive rings: 452171384Sjfv * Allocated at run time, an array of rings. 453171384Sjfv */ 454205720Sjfv struct rx_ring *rx_rings; 455205720Sjfv u64 que_mask; 456243729Sjfv u32 num_rx_desc; 457171384Sjfv 458215914Sjfv /* Multicast array memory */ 459215914Sjfv u8 *mta; 460215914Sjfv 461251964Sjfv 462171384Sjfv /* Misc stats maintained by the driver */ 463205720Sjfv unsigned long dropped_pkts; 464205720Sjfv unsigned long mbuf_defrag_failed; 465205720Sjfv unsigned long mbuf_header_failed; 466205720Sjfv unsigned long mbuf_packet_failed; 467205720Sjfv unsigned long watchdog_events; 468205720Sjfv unsigned long link_irq; 469171384Sjfv 470205720Sjfv struct ixgbe_hw_stats stats; 471171384Sjfv}; 472171384Sjfv 473251964Sjfv 474190873Sjfv/* Precision Time Sync (IEEE 1588) defines */ 475190873Sjfv#define ETHERTYPE_IEEE1588 0x88F7 476190873Sjfv#define PICOSECS_PER_TICK 20833 477190873Sjfv#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 478190873Sjfv#define IXGBE_ADVTXD_TSTAMP 0x00080000 479190873Sjfv 480190873Sjfv 481179055Sjfv#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 482179055Sjfv mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 483179055Sjfv#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 484200239Sjfv#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 485200239Sjfv#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 486179055Sjfv#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 487200239Sjfv#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 488200239Sjfv#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 489200239Sjfv#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 490179055Sjfv#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 491179055Sjfv#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 492179055Sjfv#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 493179055Sjfv#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 494179055Sjfv#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 495179055Sjfv 496251964Sjfv/* For backward compatibility */ 497251964Sjfv#if !defined(PCIER_LINK_STA) 498251964Sjfv#define PCIER_LINK_STA PCIR_EXPRESS_LINK_STA 499251964Sjfv#endif 500179055Sjfv 501190873Sjfvstatic inline bool 502190873Sjfvixgbe_is_sfp(struct ixgbe_hw *hw) 503190873Sjfv{ 504190873Sjfv switch (hw->phy.type) { 505190873Sjfv case ixgbe_phy_sfp_avago: 506190873Sjfv case ixgbe_phy_sfp_ftl: 507190873Sjfv case ixgbe_phy_sfp_intel: 508190873Sjfv case ixgbe_phy_sfp_unknown: 509205720Sjfv case ixgbe_phy_sfp_passive_tyco: 510205720Sjfv case ixgbe_phy_sfp_passive_unknown: 511190873Sjfv return TRUE; 512190873Sjfv default: 513190873Sjfv return FALSE; 514190873Sjfv } 515190873Sjfv} 516190873Sjfv 517208762Sjfv/* Workaround to make 8.0 buildable */ 518217129Sjfv#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 519208762Sjfvstatic __inline int 520208762Sjfvdrbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 521208762Sjfv{ 522208762Sjfv#ifdef ALTQ 523208762Sjfv if (ALTQ_IS_ENABLED(&ifp->if_snd)) 524208762Sjfv return (1); 525208762Sjfv#endif 526208762Sjfv return (!buf_ring_empty(br)); 527208762Sjfv} 528208762Sjfv#endif 529208762Sjfv 530221041Sjfv/* 531221041Sjfv** Find the number of unrefreshed RX descriptors 532221041Sjfv*/ 533221041Sjfvstatic inline u16 534221041Sjfvixgbe_rx_unrefreshed(struct rx_ring *rxr) 535221041Sjfv{ 536221041Sjfv if (rxr->next_to_check > rxr->next_to_refresh) 537221041Sjfv return (rxr->next_to_check - rxr->next_to_refresh - 1); 538221041Sjfv else 539243729Sjfv return ((rxr->num_desc + rxr->next_to_check) - 540221041Sjfv rxr->next_to_refresh - 1); 541221041Sjfv} 542221041Sjfv 543171384Sjfv#endif /* _IXGBE_H_ */ 544