1230557Sjimharris/*- 2230557Sjimharris * This file is provided under a dual BSD/GPLv2 license. When using or 3230557Sjimharris * redistributing this file, you may do so under either license. 4230557Sjimharris * 5230557Sjimharris * GPL LICENSE SUMMARY 6230557Sjimharris * 7230557Sjimharris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8230557Sjimharris * 9230557Sjimharris * This program is free software; you can redistribute it and/or modify 10230557Sjimharris * it under the terms of version 2 of the GNU General Public License as 11230557Sjimharris * published by the Free Software Foundation. 12230557Sjimharris * 13230557Sjimharris * This program is distributed in the hope that it will be useful, but 14230557Sjimharris * WITHOUT ANY WARRANTY; without even the implied warranty of 15230557Sjimharris * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16230557Sjimharris * General Public License for more details. 17230557Sjimharris * 18230557Sjimharris * You should have received a copy of the GNU General Public License 19230557Sjimharris * along with this program; if not, write to the Free Software 20230557Sjimharris * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21230557Sjimharris * The full GNU General Public License is included in this distribution 22230557Sjimharris * in the file called LICENSE.GPL. 23230557Sjimharris * 24230557Sjimharris * BSD LICENSE 25230557Sjimharris * 26230557Sjimharris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27230557Sjimharris * All rights reserved. 28230557Sjimharris * 29230557Sjimharris * Redistribution and use in source and binary forms, with or without 30230557Sjimharris * modification, are permitted provided that the following conditions 31230557Sjimharris * are met: 32230557Sjimharris * 33230557Sjimharris * * Redistributions of source code must retain the above copyright 34230557Sjimharris * notice, this list of conditions and the following disclaimer. 35230557Sjimharris * * Redistributions in binary form must reproduce the above copyright 36230557Sjimharris * notice, this list of conditions and the following disclaimer in 37230557Sjimharris * the documentation and/or other materials provided with the 38230557Sjimharris * distribution. 39230557Sjimharris * 40230557Sjimharris * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41230557Sjimharris * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42230557Sjimharris * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43230557Sjimharris * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44230557Sjimharris * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45230557Sjimharris * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46230557Sjimharris * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47230557Sjimharris * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48230557Sjimharris * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49230557Sjimharris * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50230557Sjimharris * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51230557Sjimharris * 52230557Sjimharris * $FreeBSD$ 53230557Sjimharris */ 54230557Sjimharris#ifndef _SCU_REGISTERS_H_ 55230557Sjimharris#define _SCU_REGISTERS_H_ 56230557Sjimharris 57230557Sjimharris/** 58230557Sjimharris * @file 59230557Sjimharris * 60230557Sjimharris * @brief This file contains the constants and structures for the SCU memory 61230557Sjimharris * mapped registers. 62230557Sjimharris */ 63230557Sjimharris#ifdef __cplusplus 64230557Sjimharrisextern "C" { 65230557Sjimharris#endif 66230557Sjimharris 67230557Sjimharris#include <dev/isci/scil/sci_types.h> 68230557Sjimharris#include <dev/isci/scil/scu_viit_data.h> 69230557Sjimharris 70230557Sjimharris 71230557Sjimharris 72230557Sjimharris// Generate a value for an SCU register 73230557Sjimharris#define SCU_GEN_VALUE(name, value) \ 74230557Sjimharris (((U32)(value) << name ## _SHIFT) & (name ## _MASK)) 75230557Sjimharris 76230557Sjimharris// Generate a bit value for an SCU register 77230557Sjimharris// Make sure that the register MASK is just a single bit 78230557Sjimharris#define SCU_GEN_BIT(name) \ 79230557Sjimharris SCU_GEN_VALUE(name, ((U32)1)) 80230557Sjimharris 81230557Sjimharris#define SCU_SET_BIT(name, reg_value) \ 82230557Sjimharris ((reg_value) | SCU_GEN_BIT(name)) 83230557Sjimharris 84230557Sjimharris#define SCU_CLEAR_BIT(name, reg_value) \ 85230557Sjimharris ((reg_value) $ ~(SCU_GEN_BIT(name))) 86230557Sjimharris 87230557Sjimharris//***************************************************************************** 88230557Sjimharris// Unions for bitfield definitions of SCU Registers 89230557Sjimharris// SMU Post Context Port 90230557Sjimharris//***************************************************************************** 91230557Sjimharris#define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT (0UL) 92230557Sjimharris#define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_MASK (0x00000FFFUL) 93230557Sjimharris#define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_SHIFT (12UL) 94230557Sjimharris#define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_MASK (0x0000F000UL) 95230557Sjimharris#define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_SHIFT (16UL) 96230557Sjimharris#define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_MASK (0x00030000UL) 97230557Sjimharris#define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_SHIFT (18UL) 98230557Sjimharris#define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_MASK (0x00FC0000UL) 99230557Sjimharris#define SMU_POST_CONTEXT_PORT_RESERVED_MASK (0xFF000000UL) 100230557Sjimharris 101230557Sjimharris#define SMU_PCP_GEN_VAL(name, value) \ 102230557Sjimharris SCU_GEN_VALUE(SMU_POST_CONTEXT_PORT_##name, value) 103230557Sjimharris 104230557Sjimharris//***************************************************************************** 105230557Sjimharris#define SMU_INTERRUPT_STATUS_COMPLETION_SHIFT (31UL) 106230557Sjimharris#define SMU_INTERRUPT_STATUS_COMPLETION_MASK (0x80000000UL) 107230557Sjimharris#define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_SHIFT (1UL) 108230557Sjimharris#define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_MASK (0x00000002UL) 109230557Sjimharris#define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT (0UL) 110230557Sjimharris#define SMU_INTERRUPT_STATUS_QUEUE_ERROR_MASK (0x00000001UL) 111230557Sjimharris#define SMU_INTERRUPT_STATUS_RESERVED_MASK (0x7FFFFFFCUL) 112230557Sjimharris 113230557Sjimharris#define SMU_ISR_GEN_BIT(name) \ 114230557Sjimharris SCU_GEN_BIT(SMU_INTERRUPT_STATUS_##name) 115230557Sjimharris 116230557Sjimharris#define SMU_ISR_QUEUE_ERROR SMU_ISR_GEN_BIT(QUEUE_ERROR) 117230557Sjimharris#define SMU_ISR_QUEUE_SUSPEND SMU_ISR_GEN_BIT(QUEUE_SUSPEND) 118230557Sjimharris#define SMU_ISR_COMPLETION SMU_ISR_GEN_BIT(COMPLETION) 119230557Sjimharris 120230557Sjimharris//***************************************************************************** 121230557Sjimharris#define SMU_INTERRUPT_MASK_COMPLETION_SHIFT (31UL) 122230557Sjimharris#define SMU_INTERRUPT_MASK_COMPLETION_MASK (0x80000000UL) 123230557Sjimharris#define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_SHIFT (1UL) 124230557Sjimharris#define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_MASK (0x00000002UL) 125230557Sjimharris#define SMU_INTERRUPT_MASK_QUEUE_ERROR_SHIFT (0UL) 126230557Sjimharris#define SMU_INTERRUPT_MASK_QUEUE_ERROR_MASK (0x00000001UL) 127230557Sjimharris#define SMU_INTERRUPT_MASK_RESERVED_MASK (0x7FFFFFFCUL) 128230557Sjimharris 129230557Sjimharris#define SMU_IMR_GEN_BIT(name) \ 130230557Sjimharris SCU_GEN_BIT(SMU_INTERRUPT_MASK_##name) 131230557Sjimharris 132230557Sjimharris#define SMU_IMR_QUEUE_ERROR SMU_IMR_GEN_BIT(QUEUE_ERROR) 133230557Sjimharris#define SMU_IMR_QUEUE_SUSPEND SMU_IMR_GEN_BIT(QUEUE_SUSPEND) 134230557Sjimharris#define SMU_IMR_COMPLETION SMU_IMR_GEN_BIT(COMPLETION) 135230557Sjimharris 136230557Sjimharris//***************************************************************************** 137230557Sjimharris#define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_SHIFT (0UL) 138230557Sjimharris#define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_MASK (0x0000001FUL) 139230557Sjimharris#define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_SHIFT (8UL) 140230557Sjimharris#define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_MASK (0x0000FF00UL) 141230557Sjimharris#define SMU_INTERRUPT_COALESCING_CONTROL_RESERVED_MASK (0xFFFF00E0UL) 142230557Sjimharris 143230557Sjimharris#define SMU_ICC_GEN_VAL(name, value) \ 144230557Sjimharris SCU_GEN_VALUE(SMU_INTERRUPT_COALESCING_CONTROL_##name, value) 145230557Sjimharris 146230557Sjimharris//***************************************************************************** 147230557Sjimharris#define SMU_TASK_CONTEXT_RANGE_START_SHIFT (0UL) 148230557Sjimharris#define SMU_TASK_CONTEXT_RANGE_START_MASK (0x00000FFFUL) 149230557Sjimharris#define SMU_TASK_CONTEXT_RANGE_ENDING_SHIFT (16UL) 150230557Sjimharris#define SMU_TASK_CONTEXT_RANGE_ENDING_MASK (0x0FFF0000UL) 151230557Sjimharris#define SMU_TASK_CONTEXT_RANGE_ENABLE_SHIFT (31UL) 152230557Sjimharris#define SMU_TASK_CONTEXT_RANGE_ENABLE_MASK (0x80000000UL) 153230557Sjimharris#define SMU_TASK_CONTEXT_RANGE_RESERVED_MASK (0x7000F000UL) 154230557Sjimharris 155230557Sjimharris#define SMU_TCR_GEN_VAL(name, value) \ 156230557Sjimharris SCU_GEN_VALUE(SMU_TASK_CONTEXT_RANGE_##name, value) 157230557Sjimharris 158230557Sjimharris#define SMU_TCR_GEN_BIT(name, value) \ 159230557Sjimharris SCU_GEN_BIT(SMU_TASK_CONTEXT_RANGE_##name) 160230557Sjimharris 161230557Sjimharris//***************************************************************************** 162230557Sjimharris 163230557Sjimharris#define SMU_COMPLETION_QUEUE_PUT_POINTER_SHIFT (0UL) 164230557Sjimharris#define SMU_COMPLETION_QUEUE_PUT_POINTER_MASK (0x00003FFFUL) 165230557Sjimharris#define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_SHIFT (15UL) 166230557Sjimharris#define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_MASK (0x00008000UL) 167230557Sjimharris#define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_SHIFT (16UL) 168230557Sjimharris#define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_MASK (0x03FF0000UL) 169230557Sjimharris#define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_SHIFT (26UL) 170230557Sjimharris#define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_MASK (0x04000000UL) 171230557Sjimharris#define SMU_COMPLETION_QUEUE_PUT_RESERVED_MASK (0xF8004000UL) 172230557Sjimharris 173230557Sjimharris#define SMU_CQPR_GEN_VAL(name, value) \ 174230557Sjimharris SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_PUT_##name, value) 175230557Sjimharris 176230557Sjimharris#define SMU_CQPR_GEN_BIT(name) \ 177230557Sjimharris SCU_GEN_BIT(SMU_COMPLETION_QUEUE_PUT_##name) 178230557Sjimharris 179230557Sjimharris//***************************************************************************** 180230557Sjimharris 181230557Sjimharris#define SMU_COMPLETION_QUEUE_GET_POINTER_SHIFT (0UL) 182230557Sjimharris#define SMU_COMPLETION_QUEUE_GET_POINTER_MASK (0x00003FFFUL) 183230557Sjimharris#define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT (15UL) 184230557Sjimharris#define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_MASK (0x00008000UL) 185230557Sjimharris#define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT (16UL) 186230557Sjimharris#define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK (0x03FF0000UL) 187230557Sjimharris#define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT (26UL) 188230557Sjimharris#define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_MASK (0x04000000UL) 189230557Sjimharris#define SMU_COMPLETION_QUEUE_GET_ENABLE_SHIFT (30UL) 190230557Sjimharris#define SMU_COMPLETION_QUEUE_GET_ENABLE_MASK (0x40000000UL) 191230557Sjimharris#define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_SHIFT (31UL) 192230557Sjimharris#define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_MASK (0x80000000UL) 193230557Sjimharris#define SMU_COMPLETION_QUEUE_GET_RESERVED_MASK (0x38004000UL) 194230557Sjimharris 195230557Sjimharris#define SMU_CQGR_GEN_VAL(name, value) \ 196230557Sjimharris SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_GET_##name, value) 197230557Sjimharris 198230557Sjimharris#define SMU_CQGR_GEN_BIT(name) \ 199230557Sjimharris SCU_GEN_BIT(SMU_COMPLETION_QUEUE_GET_##name) 200230557Sjimharris 201230557Sjimharris#define SMU_CQGR_CYCLE_BIT \ 202230557Sjimharris SMU_CQGR_GEN_BIT(CYCLE_BIT) 203230557Sjimharris 204230557Sjimharris#define SMU_CQGR_EVENT_CYCLE_BIT \ 205230557Sjimharris SMU_CQGR_GEN_BIT(EVENT_CYCLE_BIT) 206230557Sjimharris 207230557Sjimharris#define SMU_CQGR_GET_POINTER_SET(value) \ 208230557Sjimharris SMU_CQGR_GEN_VAL(POINTER, value) 209230557Sjimharris 210230557Sjimharris 211230557Sjimharris//***************************************************************************** 212230557Sjimharris#define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_SHIFT (0UL) 213230557Sjimharris#define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_MASK (0x00003FFFUL) 214230557Sjimharris#define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_SHIFT (16UL) 215230557Sjimharris#define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_MASK (0x03FF0000UL) 216230557Sjimharris#define SMU_COMPLETION_QUEUE_CONTROL_RESERVED_MASK (0xFC00C000UL) 217230557Sjimharris 218230557Sjimharris#define SMU_CQC_GEN_VAL(name, value) \ 219230557Sjimharris SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_CONTROL_##name, value) 220230557Sjimharris 221230557Sjimharris#define SMU_CQC_QUEUE_LIMIT_SET(value) \ 222230557Sjimharris SMU_CQC_GEN_VAL(QUEUE_LIMIT, value) 223230557Sjimharris 224230557Sjimharris#define SMU_CQC_EVENT_LIMIT_SET(value) \ 225230557Sjimharris SMU_CQC_GEN_VAL(EVENT_LIMIT, value) 226230557Sjimharris 227230557Sjimharris 228230557Sjimharris//***************************************************************************** 229230557Sjimharris#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT (0UL) 230230557Sjimharris#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK (0x00000FFFUL) 231230557Sjimharris#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT (12UL) 232230557Sjimharris#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK (0x00007000UL) 233230557Sjimharris#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT (15UL) 234230557Sjimharris#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK (0x07FF8000UL) 235230557Sjimharris#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_SHIFT (27UL) 236230557Sjimharris#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK (0x08000000UL) 237230557Sjimharris#define SMU_DEVICE_CONTEXT_CAPACITY_RESERVED_MASK (0xF0000000UL) 238230557Sjimharris 239230557Sjimharris#define SMU_DCC_GEN_VAL(name, value) \ 240230557Sjimharris SCU_GEN_VALUE(SMU_DEVICE_CONTEXT_CAPACITY_##name, value) 241230557Sjimharris 242230557Sjimharris#define SMU_DCC_GET_MAX_PEG(value) \ 243230557Sjimharris ( \ 244230557Sjimharris ((U32)((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK)) \ 245230557Sjimharris >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \ 246230557Sjimharris ) 247230557Sjimharris 248230557Sjimharris#define SMU_DCC_GET_MAX_LP(value) \ 249230557Sjimharris ( \ 250230557Sjimharris ((U32)((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK)) \ 251230557Sjimharris >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \ 252230557Sjimharris ) 253230557Sjimharris 254230557Sjimharris#define SMU_DCC_GET_MAX_TC(value) \ 255230557Sjimharris ( \ 256230557Sjimharris ((U32)((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK)) \ 257230557Sjimharris >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT \ 258230557Sjimharris ) 259230557Sjimharris 260230557Sjimharris#define SMU_DCC_GET_MAX_RNC(value) \ 261230557Sjimharris ( \ 262230557Sjimharris ((U32)((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK)) \ 263230557Sjimharris >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT \ 264230557Sjimharris ) 265230557Sjimharris 266230557Sjimharris//***************************************************************************** 267230557Sjimharris#define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_SHIFT (0UL) 268230557Sjimharris#define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_MASK (0x00000001UL) 269230557Sjimharris#define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_SHIFT (1UL) 270230557Sjimharris#define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_MASK (0x00000002UL) 271230557Sjimharris#define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_SHIFT (2UL) 272230557Sjimharris#define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_MASK (0x00000004UL) 273230557Sjimharris#define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_SHIFT (3UL) 274230557Sjimharris#define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_MASK (0x00000008UL) 275230557Sjimharris#define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_SHIFT (16UL) 276230557Sjimharris#define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_MASK (0x000F0000UL) 277230557Sjimharris#define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_SHIFT (31UL) 278230557Sjimharris#define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_MASK (0x80000000UL) 279230557Sjimharris#define SMU_CLOCK_GATING_CONTROL_RESERVED_MASK (0x7FF0FFF0UL) 280230557Sjimharris 281230557Sjimharris#define SMU_CGUCR_GEN_VAL(name, value) \ 282230557Sjimharris SCU_GEN_VALUE(SMU_CLOCK_GATING_CONTROL_##name, value) 283230557Sjimharris 284230557Sjimharris#define SMU_CGUCR_GEN_BIT(name) \ 285230557Sjimharris SCU_GEN_BIT(SMU_CLOCK_GATING_CONTROL_##name) 286230557Sjimharris 287230557Sjimharris// -------------------------------------------------------------------------- 288230557Sjimharris 289230557Sjimharris#define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_SHIFT (0UL) 290230557Sjimharris#define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_MASK (0x00000001UL) 291230557Sjimharris#define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_SHIFT (1UL) 292230557Sjimharris#define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_MASK (0x00000002UL) 293230557Sjimharris#define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_SHIFT (16UL) 294230557Sjimharris#define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_MASK (0x00010000UL) 295230557Sjimharris#define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_SHIFT (17UL) 296230557Sjimharris#define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_MASK (0x00020000UL) 297230557Sjimharris#define SMU_CONTROL_STATUS_RESERVED_MASK (0xFFFCFFFCUL) 298230557Sjimharris 299230557Sjimharris#define SMU_SMUCSR_GEN_BIT(name) \ 300230557Sjimharris SCU_GEN_BIT(SMU_CONTROL_STATUS_##name) 301230557Sjimharris 302230557Sjimharris#define SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \ 303230557Sjimharris (SMU_SMUCSR_GEN_BIT(SCHEDULER_RAM_INIT_COMPLETED)) 304230557Sjimharris 305230557Sjimharris#define SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED \ 306230557Sjimharris (SMU_SMUCSR_GEN_BIT(CONTEXT_RAM_INIT_COMPLETED)) 307230557Sjimharris 308230557Sjimharris#define SCU_RAM_INIT_COMPLETED \ 309230557Sjimharris ( \ 310230557Sjimharris SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED \ 311230557Sjimharris | SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \ 312230557Sjimharris ) 313230557Sjimharris 314230557Sjimharris// -------------------------------------------------------------------------- 315230557Sjimharris 316230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_SHIFT (0UL) 317230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_MASK (0x00000001UL) 318230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_SHIFT (1UL) 319230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_MASK (0x00000002UL) 320230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_SHIFT (2UL) 321230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_MASK (0x00000004UL) 322230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_SHIFT (3UL) 323230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_MASK (0x00000008UL) 324230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_SHIFT (8UL) 325230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_MASK (0x00000100UL) 326230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_SHIFT (9UL) 327230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_MASK (0x00000200UL) 328230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_SHIFT (10UL) 329230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_MASK (0x00000400UL) 330230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_SHIFT (11UL) 331230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_MASK (0x00000800UL) 332230557Sjimharris 333230557Sjimharris#define SMU_RESET_PROTOCOL_ENGINE(peg, pe) \ 334230557Sjimharris ((1UL << (pe)) << ((peg) * 8UL)) 335230557Sjimharris 336230557Sjimharris#define SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \ 337230557Sjimharris ( \ 338230557Sjimharris SMU_RESET_PROTOCOL_ENGINE(peg, 0) \ 339230557Sjimharris | SMU_RESET_PROTOCOL_ENGINE(peg, 1) \ 340230557Sjimharris | SMU_RESET_PROTOCOL_ENGINE(peg, 2) \ 341230557Sjimharris | SMU_RESET_PROTOCOL_ENGINE(peg, 3) \ 342230557Sjimharris ) 343230557Sjimharris 344230557Sjimharris#define SMU_RESET_ALL_PROTOCOL_ENGINES() \ 345230557Sjimharris ( \ 346230557Sjimharris SMU_RESET_PEG_PROTOCOL_ENGINES(0) \ 347230557Sjimharris | SMU_RESET_PEG_PROTOCOL_ENGINES(1) \ 348230557Sjimharris ) 349230557Sjimharris 350230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_SHIFT (16UL) 351230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_MASK (0x00010000UL) 352230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_SHIFT (17UL) 353230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_MASK (0x00020000UL) 354230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_SHIFT (18UL) 355230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_MASK (0x00040000UL) 356230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_SHIFT (19UL) 357230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_MASK (0x00080000UL) 358230557Sjimharris 359230557Sjimharris#define SMU_RESET_WIDE_PORT_QUEUE(peg, wide_port) \ 360230557Sjimharris ((1UL << ((wide_port) / 2)) << ((peg) * 2UL) << 16UL) 361230557Sjimharris 362230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG0_SHIFT (20UL) 363230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG0_MASK (0x00100000UL) 364230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG1_SHIFT (21UL) 365230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_PEG1_MASK (0x00200000UL) 366230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_SCU_SHIFT (22UL) 367230557Sjimharris#define SMU_SOFTRESET_CONTROL_RESET_SCU_MASK (0x00400000UL) 368230557Sjimharris 369230557Sjimharris// It seems to make sense that if you are going to reset the protocol 370230557Sjimharris// engine group that you would also reset all of the protocol engines 371230557Sjimharris#define SMU_RESET_PROTOCOL_ENGINE_GROUP(peg) \ 372230557Sjimharris ( \ 373230557Sjimharris (1UL << ((peg) + 20)) \ 374230557Sjimharris | SMU_RESET_WIDE_PORT_QUEUE(peg, 0) \ 375230557Sjimharris | SMU_RESET_WIDE_PORT_QUEUE(peg, 1) \ 376230557Sjimharris | SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \ 377230557Sjimharris ) 378230557Sjimharris 379230557Sjimharris#define SMU_RESET_ALL_PROTOCOL_ENGINE_GROUPS() \ 380230557Sjimharris ( \ 381230557Sjimharris SMU_RESET_PROTOCOL_ENGINE_GROUP(0) \ 382230557Sjimharris | SMU_RESET_PROTOCOL_ENGINE_GROUP(1) \ 383230557Sjimharris ) 384230557Sjimharris 385230557Sjimharris#define SMU_RESET_SCU() (0xFFFFFFFF) 386230557Sjimharris 387230557Sjimharris 388230557Sjimharris 389230557Sjimharris//***************************************************************************** 390230557Sjimharris#define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_SHIFT (0UL) 391230557Sjimharris#define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_MASK (0x00000FFFUL) 392230557Sjimharris#define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_SHIFT (16UL) 393230557Sjimharris#define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_MASK (0x0FFF0000UL) 394230557Sjimharris#define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_SHIFT (31UL) 395230557Sjimharris#define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_MASK (0x80000000UL) 396230557Sjimharris#define SMU_TASK_CONTEXT_ASSIGNMENT_RESERVED_MASK (0x7000F000UL) 397230557Sjimharris 398230557Sjimharris#define SMU_TCA_GEN_VAL(name, value) \ 399230557Sjimharris SCU_GEN_VALUE(SMU_TASK_CONTEXT_ASSIGNMENT_##name, value) 400230557Sjimharris 401230557Sjimharris#define SMU_TCA_GEN_BIT(name) \ 402230557Sjimharris SCU_GEN_BIT(SMU_TASK_CONTEXT_ASSIGNMENT_##name) 403230557Sjimharris 404230557Sjimharris//***************************************************************************** 405230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_SHIFT (0UL) 406230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_MASK (0x00000FFFUL) 407230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_RESERVED_MASK (0xFFFFF000UL) 408230557Sjimharris 409230557Sjimharris#define SCU_UFQC_GEN_VAL(name, value) \ 410230557Sjimharris SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_##name, value) 411230557Sjimharris 412230557Sjimharris#define SCU_UFQC_QUEUE_SIZE_SET(value) \ 413230557Sjimharris SCU_UFQC_GEN_VAL(QUEUE_SIZE, value) 414230557Sjimharris 415230557Sjimharris//***************************************************************************** 416230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_SHIFT (0UL) 417230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_MASK (0x00000FFFUL) 418230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_SHIFT (12UL) 419230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_MASK (0x00001000UL) 420230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_RESERVED_MASK (0xFFFFE000UL) 421230557Sjimharris 422230557Sjimharris#define SCU_UFQPP_GEN_VAL(name, value) \ 423230557Sjimharris SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_##name, value) 424230557Sjimharris 425230557Sjimharris#define SCU_UFQPP_GEN_BIT(name) \ 426230557Sjimharris SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_##name) 427230557Sjimharris 428230557Sjimharris//***************************************************************************** 429230557Sjimharris//* SDMA Registers 430230557Sjimharris//***************************************************************************** 431230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_SHIFT (0UL) 432230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_MASK (0x00000FFFUL) 433230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_SHIFT (12UL) 434230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_MASK (12UL) 435230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_SHIFT (31UL) 436230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_MASK (0x80000000UL) 437230557Sjimharris#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_RESERVED_MASK (0x7FFFE000UL) 438230557Sjimharris 439230557Sjimharris#define SCU_UFQGP_GEN_VAL(name, value) \ 440230557Sjimharris SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_##name, value) 441230557Sjimharris 442230557Sjimharris#define SCU_UFQGP_GEN_BIT(name) \ 443230557Sjimharris SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_##name) 444230557Sjimharris 445230557Sjimharris#define SCU_UFQGP_CYCLE_BIT(value) \ 446230557Sjimharris SCU_UFQGP_GEN_BIT(CYCLE_BIT, value) 447230557Sjimharris 448230557Sjimharris#define SCU_UFQGP_GET_POINTER(value) \ 449230557Sjimharris SCU_UFQGP_GEN_VALUE(POINTER, value) 450230557Sjimharris 451230557Sjimharris#define SCU_UFQGP_ENABLE(value) \ 452230557Sjimharris (SCU_UFQGP_GEN_BIT(ENABLE) | value) 453230557Sjimharris 454230557Sjimharris#define SCU_UFQGP_DISABLE(value) \ 455230557Sjimharris (~SCU_UFQGP_GEN_BIT(ENABLE) & value) 456230557Sjimharris 457230557Sjimharris#define SCU_UFQGP_VALUE(bit, value) \ 458230557Sjimharris (SCU_UFQGP_CYCLE_BIT(bit) | SCU_UFQGP_GET_POINTER(value)) 459230557Sjimharris 460230557Sjimharris//***************************************************************************** 461230557Sjimharris#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SHIFT (0UL) 462230557Sjimharris#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_MASK (0x0000FFFFUL) 463230557Sjimharris#define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT (16UL) 464230557Sjimharris#define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK (0x00010000UL) 465230557Sjimharris#define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_SHIFT (17UL) 466230557Sjimharris#define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_MASK (0x00020000UL) 467230557Sjimharris#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_SHIFT (18UL) 468230557Sjimharris#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_MASK (0x00040000UL) 469230557Sjimharris#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_SHIFT (19UL) 470230557Sjimharris#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_MASK (0x00080000UL) 471230557Sjimharris#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_SHIFT (20UL) 472230557Sjimharris#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_MASK (0x00100000UL) 473230557Sjimharris#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_SHIFT (21UL) 474230557Sjimharris#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_MASK (0x00200000UL) 475230557Sjimharris#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_SHIFT (22UL) 476230557Sjimharris#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_MASK (0x00400000UL) 477230557Sjimharris#define SCU_PDMA_CONFIGURATION_RESERVED_MASK (0xFF800000UL) 478230557Sjimharris 479230557Sjimharris#define SCU_PDMACR_GEN_VALUE(name, value) \ 480230557Sjimharris SCU_GEN_VALUE(SCU_PDMA_CONFIGURATION_##name, value) 481230557Sjimharris 482230557Sjimharris#define SCU_PDMACR_GEN_BIT(name) \ 483230557Sjimharris SCU_GEN_BIT(SCU_PDMA_CONFIGURATION_##name) 484230557Sjimharris 485230557Sjimharris#define SCU_PDMACR_BE_GEN_BIT(name) \ 486230557Sjimharris SCU_PCMACR_GEN_BIT(BIG_ENDIAN_CONTROL_##name) 487230557Sjimharris 488230557Sjimharris//***************************************************************************** 489230557Sjimharris#define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT (8UL) 490230557Sjimharris#define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK (0x00000100UL) 491230557Sjimharris 492230557Sjimharris#define SCU_CDMACR_GEN_BIT(name) \ 493230557Sjimharris SCU_GEN_BIT(SCU_CDMA_CONFIGURATION_##name) 494230557Sjimharris 495230557Sjimharris//***************************************************************************** 496230557Sjimharris//* SCU Link Layer Registers 497230557Sjimharris//***************************************************************************** 498230557Sjimharris#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_SHIFT (0UL) 499230557Sjimharris#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_MASK (0x000000FFUL) 500230557Sjimharris#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_SHIFT (8UL) 501230557Sjimharris#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_MASK (0x0000FF00UL) 502230557Sjimharris#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_SHIFT (16UL) 503230557Sjimharris#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_MASK (0x00FF0000UL) 504230557Sjimharris#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_SHIFT (24UL) 505230557Sjimharris#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_MASK (0xFF000000UL) 506230557Sjimharris#define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_REQUIRED_MASK (0x00000000UL) 507230557Sjimharris#define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_DEFAULT_MASK (0x7D00676FUL) 508230557Sjimharris#define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_RESERVED_MASK (0x00FF0000UL) 509230557Sjimharris 510230557Sjimharris#define SCU_SAS_SPDTOV_GEN_VALUE(name, value) \ 511230557Sjimharris SCU_GEN_VALUE(SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_##name, value) 512230557Sjimharris 513230557Sjimharris 514230557Sjimharris#define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_SHIFT (2UL) 515230557Sjimharris#define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_MASK (0x00000004UL) 516230557Sjimharris#define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_SHIFT (4UL) 517230557Sjimharris#define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_MASK (0x00000010UL) 518230557Sjimharris#define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_SHIFT (5UL) 519230557Sjimharris#define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_MASK (0x00000020UL) 520230557Sjimharris#define SCU_LINK_STATUS_RESERVED_MASK (0xFFFFFFCDUL) 521230557Sjimharris 522230557Sjimharris#define SCU_SAS_LLSTA_GEN_BIT(name) \ 523230557Sjimharris SCU_GEN_BIT(SCU_LINK_STATUS_##name) 524230557Sjimharris 525230557Sjimharris 526230557Sjimharris// TODO: Where is the SATA_PSELTOV register? 527230557Sjimharris 528230557Sjimharris//***************************************************************************** 529230557Sjimharris//* SCU SAS Maximum Arbitration Wait Time Timeout Register 530230557Sjimharris//***************************************************************************** 531230557Sjimharris#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_SHIFT (0UL) 532230557Sjimharris#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_MASK (0x00007FFFUL) 533230557Sjimharris#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_SHIFT (15UL) 534230557Sjimharris#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_MASK (0x00008000UL) 535230557Sjimharris 536230557Sjimharris#define SCU_SAS_MAWTTOV_GEN_VALUE(name, value) \ 537230557Sjimharris SCU_GEN_VALUE(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_##name, value) 538230557Sjimharris 539230557Sjimharris#define SCU_SAS_MAWTTOV_GEN_BIT(name) \ 540230557Sjimharris SCU_GEN_BIT(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_##name) 541230557Sjimharris 542230557Sjimharris 543230557Sjimharris// TODO: Where is the SAS_LNKTOV regsiter? 544230557Sjimharris// TODO: Where is the SAS_PHYTOV register? 545230557Sjimharris 546230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_SHIFT (1UL) 547230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_MASK (0x00000002UL) 548230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_SHIFT (2UL) 549230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_MASK (0x00000004UL) 550230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_SHIFT (3UL) 551230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_MASK (0x00000008UL) 552230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_SHIFT (8UL) 553230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_MASK (0x00000100UL) 554230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_SHIFT (9UL) 555230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_MASK (0x00000200UL) 556230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_SHIFT (10UL) 557230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_MASK (0x00000400UL) 558230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_SHIFT (11UL) 559230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_MASK (0x00000800UL) 560230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_SHIFT (16UL) 561230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_MASK (0x000F0000UL) 562230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_SHIFT (24UL) 563230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_MASK (0x0F000000UL) 564230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_SHIFT (28UL) 565230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_MASK (0x70000000UL) 566230557Sjimharris#define SCU_SAS_TRANSMIT_IDENTIFICATION_RESERVED_MASK (0x80F0F1F1UL) 567230557Sjimharris 568230557Sjimharris#define SCU_SAS_TIID_GEN_VAL(name, value) \ 569230557Sjimharris SCU_GEN_VALUE(SCU_SAS_TRANSMIT_IDENTIFICATION_##name, value) 570230557Sjimharris 571230557Sjimharris#define SCU_SAS_TIID_GEN_BIT(name) \ 572230557Sjimharris SCU_GEN_BIT(SCU_SAS_TRANSMIT_IDENTIFICATION_##name) 573230557Sjimharris 574230557Sjimharris// SAS Identify Frame PHY Identifier Register 575230557Sjimharris#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_SHIFT (16UL) 576230557Sjimharris#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_MASK (0x00010000UL) 577230557Sjimharris#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_SHIFT (17UL) 578230557Sjimharris#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_MASK (0x00020000UL) 579230557Sjimharris#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_SHIFT (18UL) 580230557Sjimharris#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_MASK (0x00040000UL) 581230557Sjimharris#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_SHIFT (24UL) 582230557Sjimharris#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_MASK (0xFF000000UL) 583230557Sjimharris#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_RESERVED_MASK (0x00F800FFUL) 584230557Sjimharris 585230557Sjimharris#define SCU_SAS_TIPID_GEN_VALUE(name, value) \ 586230557Sjimharris SCU_GEN_VALUE(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_##name, value) 587230557Sjimharris 588230557Sjimharris#define SCU_SAS_TIPID_GEN_BIT(name) \ 589230557Sjimharris SCU_GEN_BIT(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_##name) 590230557Sjimharris 591230557Sjimharris 592230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_SHIFT (4UL) 593230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_MASK (0x00000010UL) 594230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_SHIFT (6UL) 595230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_MASK (0x00000040UL) 596230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_SHIFT (7UL) 597230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_MASK (0x00000080UL) 598230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_SHIFT (8UL) 599230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_MASK (0x00000100UL) 600230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_SHIFT (9UL) 601230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_MASK (0x00000200UL) 602230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_SHIFT (11UL) 603230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_MASK (0x00000800UL) 604230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_SHIFT (12UL) 605230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_MASK (0x00001000UL) 606230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_SHIFT (13UL) 607230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_MASK (0x00002000UL) 608230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_SHIFT (14UL) 609230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_MASK (0x00004000UL) 610230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_SHIFT (15UL) 611230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_MASK (0x00008000UL) 612230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_SHIFT (23UL) 613230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_MASK (0x00800000UL) 614230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_SHIFT (27UL) 615230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_MASK (0x08000000UL) 616230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_SHIFT (28UL) 617230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_MASK (0x10000000UL) 618230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_SHIFT (29UL) 619230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_MASK (0x20000000UL) 620230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_SHIFT (30UL) 621230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_MASK (0x40000000UL) 622230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_SHIFT (31UL) 623230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_MASK (0x80000000UL) 624230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_REQUIRED_MASK (0x0100000FUL) 625230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_DEFAULT_MASK (0x4180100FUL) 626230557Sjimharris#define SCU_SAS_PHY_CONFIGURATION_RESERVED_MASK (0x00000000UL) 627230557Sjimharris 628230557Sjimharris#define SCU_SAS_PCFG_GEN_BIT(name) \ 629230557Sjimharris SCU_GEN_BIT(SCU_SAS_PHY_CONFIGURATION_##name) 630230557Sjimharris 631230557Sjimharris#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_SHIFT (0UL) 632230557Sjimharris#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_MASK (0x000007FFUL) 633230557Sjimharris#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_SHIFT (16UL) 634230557Sjimharris#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_MASK (0x00ff0000UL) 635230557Sjimharris 636230557Sjimharris#define SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(name, value) \ 637230557Sjimharris SCU_GEN_VALUE(SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_##name, value) 638230557Sjimharris 639230557Sjimharris#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_SHIFT (0UL) 640230557Sjimharris#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_MASK (0x0003FFFFUL) 641230557Sjimharris#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_SHIFT (31UL) 642230557Sjimharris#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_MASK (0x80000000UL) 643230557Sjimharris#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_RESERVED_MASK (0x7FFC0000UL) 644230557Sjimharris 645230557Sjimharris#define SCU_ENSPINUP_GEN_VAL(name, value) \ 646230557Sjimharris SCU_GEN_VALUE(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_##name, value) 647230557Sjimharris 648230557Sjimharris#define SCU_ENSPINUP_GEN_BIT(name) \ 649230557Sjimharris SCU_GEN_BIT(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_##name) 650230557Sjimharris 651230557Sjimharris 652230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_SHIFT (1UL) 653230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_MASK (0x00000002UL) 654230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_SHIFT (4UL) 655230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_MASK (0x000000F0UL) 656230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_SHIFT (8UL) 657230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_MASK (0x00000100UL) 658230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_SHIFT (9UL) 659230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_MASK (0x00000201UL) 660230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_SHIFT (10UL) 661230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_MASK (0x00000401UL) 662230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_SHIFT (11UL) 663230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_MASK (0x00000801UL) 664230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_SHIFT (12UL) 665230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_MASK (0x00001001UL) 666230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_SHIFT (13UL) 667230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_MASK (0x00002001UL) 668230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_SHIFT (31UL) 669230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_MASK (0x80000000UL) 670230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_DEFAULT_MASK (0x00003F01UL) 671230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_REQUIRED_MASK (0x00000001UL) 672230557Sjimharris#define SCU_LINK_LAYER_PHY_CAPABILITIES_RESERVED_MASK (0x7FFFC00DUL) 673230557Sjimharris 674230557Sjimharris#define SCU_SAS_PHYCAP_GEN_VAL(name, value) \ 675230557Sjimharris SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_CAPABILITIES_##name, value) 676230557Sjimharris 677230557Sjimharris#define SCU_SAS_PHYCAP_GEN_BIT(name) \ 678230557Sjimharris SCU_GEN_BIT(SCU_LINK_LAYER_PHY_CAPABILITIES_##name) 679230557Sjimharris 680230557Sjimharris 681230557Sjimharris#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_SHIFT (0UL) 682230557Sjimharris#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_MASK (0x000000FFUL) 683230557Sjimharris#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_SHIFT (31UL) 684230557Sjimharris#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_MASK (0x80000000UL) 685230557Sjimharris#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_RESERVED_MASK (0x7FFFFF00UL) 686230557Sjimharris 687230557Sjimharris#define SCU_PSZGCR_GEN_VAL(name, value) \ 688230557Sjimharris SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_##name, value) 689230557Sjimharris 690230557Sjimharris#define SCU_PSZGCR_GEN_BIT(name) \ 691230557Sjimharris SCU_GEN_BIT(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_##name) 692230557Sjimharris 693230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_SHIFT (1UL) 694230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_MASK (0x00000002UL) 695230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_SHIFT (2UL) 696230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_MASK (0x00000004UL) 697230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_SHIFT (4UL) 698230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_MASK (0x00000010UL) 699230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_SHIFT (5UL) 700230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_MASK (0x00000020UL) 701230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_SHIFT (16UL) 702230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_MASK (0x00030000UL) 703230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_SHIFT (19UL) 704230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_MASK (0x00080000UL) 705230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_SHIFT (20UL) 706230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_MASK (0x00300000UL) 707230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_SHIFT (23UL) 708230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_MASK (0x00800000UL) 709230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_SHIFT (24UL) 710230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_MASK (0x03000000UL) 711230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_SHIFT (27UL) 712230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_MASK (0x08000000UL) 713230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_SHIFT (28UL) 714230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_MASK (0x30000000UL) 715230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_SHIFT (31UL) 716230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_MASK (0x80000000UL) 717230557Sjimharris#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_RESERVED_MASK (0x4444FFC9UL) 718230557Sjimharris 719230557Sjimharris#define SCU_PEG_SCUVZECR_GEN_VAL(name, val) \ 720230557Sjimharris SCU_GEN_VALUE(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_##name, val) 721230557Sjimharris 722230557Sjimharris#define SCU_PEG_SCUVZECR_GEN_BIT(name) \ 723230557Sjimharris SCU_GEN_BIT(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_##name) 724230557Sjimharris 725230557Sjimharris 726230557Sjimharris//***************************************************************************** 727230557Sjimharris//* Port Task Scheduler registers shift and mask values 728230557Sjimharris//***************************************************************************** 729230557Sjimharris#define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_SHIFT (0UL) 730230557Sjimharris#define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_MASK (0x0000FFFFUL) 731230557Sjimharris#define SCU_PTSG_CONTROL_TASK_TIMEOUT_SHIFT (16UL) 732230557Sjimharris#define SCU_PTSG_CONTROL_TASK_TIMEOUT_MASK (0x00FF0000UL) 733230557Sjimharris#define SCU_PTSG_CONTROL_PTSG_ENABLE_SHIFT (24UL) 734230557Sjimharris#define SCU_PTSG_CONTROL_PTSG_ENABLE_MASK (0x01000000UL) 735230557Sjimharris#define SCU_PTSG_CONTROL_ETM_ENABLE_SHIFT (25UL) 736230557Sjimharris#define SCU_PTSG_CONTROL_ETM_ENABLE_MASK (0x02000000UL) 737230557Sjimharris#define SCU_PTSG_CONTROL_DEFAULT_MASK (0x00020002UL) 738230557Sjimharris#define SCU_PTSG_CONTROL_REQUIRED_MASK (0x00000000UL) 739230557Sjimharris#define SCU_PTSG_CONTROL_RESERVED_MASK (0xFC000000UL) 740230557Sjimharris 741230557Sjimharris#define SCU_PTSGCR_GEN_VAL(name, val) \ 742230557Sjimharris SCU_GEN_VALUE(SCU_PTSG_CONTROL_##name, val) 743230557Sjimharris 744230557Sjimharris#define SCU_PTSGCR_GEN_BIT(name) \ 745230557Sjimharris SCU_GEN_BIT(SCU_PTSG_CONTROL_##name) 746230557Sjimharris 747230557Sjimharris 748230557Sjimharris//***************************************************************************** 749230557Sjimharris#define SCU_PTSG_REAL_TIME_CLOCK_SHIFT (0UL) 750230557Sjimharris#define SCU_PTSG_REAL_TIME_CLOCK_MASK (0x0000FFFFUL) 751230557Sjimharris#define SCU_PTSG_REAL_TIME_CLOCK_RESERVED_MASK (0xFFFF0000UL) 752230557Sjimharris 753230557Sjimharris#define SCU_RTCR_GEN_VAL(name, val) \ 754230557Sjimharris SCU_GEN_VALUE(SCU_PTSG_##name, val) 755230557Sjimharris 756230557Sjimharris 757230557Sjimharris#define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_SHIFT (0UL) 758230557Sjimharris#define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_MASK (0x00FFFFFFUL) 759230557Sjimharris#define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_RESERVED_MASK (0xFF000000UL) 760230557Sjimharris 761230557Sjimharris#define SCU_RTCCR_GEN_VAL(name, val) \ 762230557Sjimharris SCU_GEN_VALUE(SCU_PTSG_REAL_TIME_CLOCK_CONTROL_##name, val) 763230557Sjimharris 764230557Sjimharris 765230557Sjimharris#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_SHIFT (0UL) 766230557Sjimharris#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_MASK (0x00000001UL) 767230557Sjimharris#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_SHIFT (1UL) 768230557Sjimharris#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_MASK (0x00000002UL) 769230557Sjimharris#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_RESERVED_MASK (0xFFFFFFFCUL) 770230557Sjimharris 771230557Sjimharris#define SCU_PTSxCR_GEN_BIT(name) \ 772230557Sjimharris SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_##name) 773230557Sjimharris 774230557Sjimharris 775230557Sjimharris#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_SHIFT (0UL) 776230557Sjimharris#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_MASK (0x00000001UL) 777230557Sjimharris#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_SHIFT (1UL) 778230557Sjimharris#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_MASK (0x00000002UL) 779230557Sjimharris#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_SHIFT (2UL) 780230557Sjimharris#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_MASK (0x00000004UL) 781230557Sjimharris#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_RESERVED_MASK (0xFFFFFFF8UL) 782230557Sjimharris 783230557Sjimharris#define SCU_PTSxSR_GEN_BIT(name) \ 784230557Sjimharris SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_##name) 785230557Sjimharris 786230557Sjimharris 787230557Sjimharris//***************************************************************************** 788230557Sjimharris//* SGPIO Register shift and mask values 789230557Sjimharris//***************************************************************************** 790230557Sjimharris#define SCU_SGPIO_CONTROL_SGPIO_ENABLE_SHIFT (0UL) 791230557Sjimharris#define SCU_SGPIO_CONTROL_SGPIO_ENABLE_MASK (0x00000001UL) 792230557Sjimharris#define SCU_SGPIO_CONTROL_SGPIO_SERIAL_CLOCK_SELECT_SHIFT (1UL) 793230557Sjimharris#define SCU_SGPIO_CONTROL_SGPIO_SERIAL_CLOCK_SELECT_MASK (0x00000002UL) 794230557Sjimharris#define SCU_SGPIO_CONTROL_SGPIO_SERIAL_SHIFT_WIDTH_SELECT_SHIFT (2UL) 795230557Sjimharris#define SCU_SGPIO_CONTROL_SGPIO_SERIAL_SHIFT_WIDTH_SELECT_MASK (0x00000004UL) 796230557Sjimharris#define SCU_SGPIO_CONTROL_SGPIO_TEST_BIT_SHIFT (15UL) 797230557Sjimharris#define SCU_SGPIO_CONTROL_SGPIO_TEST_BIT_MASK (0x00008000UL) 798230557Sjimharris#define SCU_SGPIO_CONTROL_SGPIO_RESERVED_MASK (0xFFFF7FF8UL) 799230557Sjimharris 800230557Sjimharris#define SCU_SGICRx_GEN_BIT(name) \ 801230557Sjimharris SCU_GEN_BIT(SCU_SGPIO_CONTROL_SGPIO_##name) 802230557Sjimharris 803230557Sjimharris#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_SHIFT (0UL) 804230557Sjimharris#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_MASK (0x0000000FUL) 805230557Sjimharris#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R1_SHIFT (4UL) 806230557Sjimharris#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R1_MASK (0x000000F0UL) 807230557Sjimharris#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R2_SHIFT (8UL) 808230557Sjimharris#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R2_MASK (0x00000F00UL) 809230557Sjimharris#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R3_SHIFT (12UL) 810230557Sjimharris#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R3_MASK (0x0000F000UL) 811230557Sjimharris#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_RESERVED_MASK (0xFFFF0000UL) 812230557Sjimharris 813230557Sjimharris#define SCU_SGPBRx_GEN_VAL(name, valueUL) \ 814230557Sjimharris SCU_GEN_VALUE(SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_##name, value) 815230557Sjimharris 816230557Sjimharris#define SCU_SGPIO_START_DRIVE_LOWER_R0_SHIFT (0UL) 817230557Sjimharris#define SCU_SGPIO_START_DRIVE_LOWER_R0_MASK (0x00000003UL) 818230557Sjimharris#define SCU_SGPIO_START_DRIVE_LOWER_R1_SHIFT (4UL) 819230557Sjimharris#define SCU_SGPIO_START_DRIVE_LOWER_R1_MASK (0x00000030UL) 820230557Sjimharris#define SCU_SGPIO_START_DRIVE_LOWER_R2_SHIFT (8UL) 821230557Sjimharris#define SCU_SGPIO_START_DRIVE_LOWER_R2_MASK (0x00000300UL) 822230557Sjimharris#define SCU_SGPIO_START_DRIVE_LOWER_R3_SHIFT (12UL) 823230557Sjimharris#define SCU_SGPIO_START_DRIVE_LOWER_R3_MASK (0x00003000UL) 824230557Sjimharris#define SCU_SGPIO_START_DRIVE_LOWER_RESERVED_MASK (0xFFFF8888UL) 825230557Sjimharris 826230557Sjimharris#define SCU_SGSDLRx_GEN_VAL(name, value) \ 827230557Sjimharris SCU_GEN_VALUE(SCU_SGPIO_START_DRIVE_LOWER_##name, value) 828230557Sjimharris 829230557Sjimharris#define SCU_SGPIO_START_DRIVE_UPPER_R0_SHIFT (0UL) 830230557Sjimharris#define SCU_SGPIO_START_DRIVE_UPPER_R0_MASK (0x00000003UL) 831230557Sjimharris#define SCU_SGPIO_START_DRIVE_UPPER_R1_SHIFT (4UL) 832230557Sjimharris#define SCU_SGPIO_START_DRIVE_UPPER_R1_MASK (0x00000030UL) 833230557Sjimharris#define SCU_SGPIO_START_DRIVE_UPPER_R2_SHIFT (8UL) 834230557Sjimharris#define SCU_SGPIO_START_DRIVE_UPPER_R2_MASK (0x00000300UL) 835230557Sjimharris#define SCU_SGPIO_START_DRIVE_UPPER_R3_SHIFT (12UL) 836230557Sjimharris#define SCU_SGPIO_START_DRIVE_UPPER_R3_MASK (0x00003000UL) 837230557Sjimharris#define SCU_SGPIO_START_DRIVE_UPPER_RESERVED_MASK (0xFFFF8888UL) 838230557Sjimharris 839230557Sjimharris#define SCU_SGSDURx_GEN_VAL(name, value) \ 840230557Sjimharris SCU_GEN_VALUE(SCU_SGPIO_START_DRIVE_LOWER_##name, value) 841230557Sjimharris 842230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_SHIFT (0UL) 843230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_MASK (0x00000003UL) 844230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D1_SHIFT (4UL) 845230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D1_MASK (0x00000030UL) 846230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D2_SHIFT (8UL) 847230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D2_MASK (0x00000300UL) 848230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D3_SHIFT (12UL) 849230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D3_MASK (0x00003000UL) 850230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_RESERVED_MASK (0xFFFF8888UL) 851230557Sjimharris 852230557Sjimharris#define SCU_SGSIDLRx_GEN_VAL(name, valueUL) \ 853230557Sjimharris SCU_GEN_VALUE(SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_##name, value) 854230557Sjimharris 855230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_SHIFT (0UL) 856230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_MASK (0x00000003UL) 857230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D1_SHIFT (4UL) 858230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D1_MASK (0x00000030UL) 859230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D2_SHIFT (8UL) 860230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D2_MASK (0x00000300UL) 861230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D3_SHIFT (12UL) 862230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D3_MASK (0x00003000UL) 863230557Sjimharris#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_RESERVED_MASK (0xFFFF8888UL) 864230557Sjimharris 865230557Sjimharris#define SCU_SGSIDURx_GEN_VAL(name, value) \ 866230557Sjimharris SCU_GEN_VALUE(SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_##name, value) 867230557Sjimharris 868230557Sjimharris#define SCU_SGPIO_VENDOR_SPECIFIC_CODE_SHIFT (0UL) 869230557Sjimharris#define SCU_SGPIO_VENDOR_SPECIFIC_CODE_MASK (0x0000000FUL) 870230557Sjimharris#define SCU_SGPIO_VENDOR_SPECIFIC_CODE_RESERVED_MASK (0xFFFFFFF0UL) 871230557Sjimharris 872230557Sjimharris#define SCU_SGVSCR_GEN_VAL(value) \ 873230557Sjimharris SCU_GEN_VALUE(SCU_SGPIO_VENDOR_SPECIFIC_CODE##name, value) 874230557Sjimharris 875230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_SHIFT (0UL) 876230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_MASK (0x00000003UL) 877230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA0_SHIFT (2UL) 878230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA0_MASK (0x00000004UL) 879230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA0_SHIFT (3UL) 880230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA0_MASK (0x00000008UL) 881230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA1_SHIFT (4UL) 882230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA1_MASK (0x00000030UL) 883230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA1_SHIFT (6UL) 884230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA1_MASK (0x00000040UL) 885230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA1_SHIFT (7UL) 886230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA1_MASK (0x00000080UL) 887230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA2_SHIFT (8UL) 888230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA2_MASK (0x00000300UL) 889230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA2_SHIFT (10UL) 890230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA2_MASK (0x00000400UL) 891230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA2_SHIFT (11UL) 892230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA2_MASK (0x00000800UL) 893230557Sjimharris#define SCU_SGPIO_OUPUT_DATA_SELECT_RESERVED_MASK (0xFFFFF000UL) 894230557Sjimharris 895230557Sjimharris#define SCU_SGODSR_GEN_VAL(name, value) \ 896230557Sjimharris SCU_GEN_VALUE(SCU_SGPIO_OUPUT_DATA_SELECT_##name, value) 897230557Sjimharris 898230557Sjimharris#define SCU_SGODSR_GEN_BIT(name) \ 899230557Sjimharris SCU_GEN_BIT(SCU_SGPIO_OUPUT_DATA_SELECT_##name) 900230557Sjimharris 901230557Sjimharris#ifdef ARLINGTON_BUILD 902230557Sjimharristypedef char LEX_REGISTERS_T; 903230557Sjimharris#endif 904230557Sjimharris 905230557Sjimharris//***************************************************************************** 906230557Sjimharris//* SMU Registers 907230557Sjimharris//***************************************************************************** 908230557Sjimharris 909230557Sjimharris// ---------------------------------------------------------------------------- 910230557Sjimharris// SMU Registers 911230557Sjimharris// These registers are based off of BAR0 912230557Sjimharris// 913230557Sjimharris// To calculate the offset for other functions use 914230557Sjimharris// BAR0 + FN# * SystemPageSize * 2 915230557Sjimharris// 916230557Sjimharris// The TCA is only accessable from FN#0 (Physical Function) and each 917230557Sjimharris// is programmed by (BAR0 + SCU_SMU_TCA_OFFSET + (FN# * 0x04)) or 918230557Sjimharris// TCA0 for FN#0 is at BAR0 + 0x0400 919230557Sjimharris// TCA1 for FN#1 is at BAR0 + 0x0404 920230557Sjimharris// etc. 921230557Sjimharris// ---------------------------------------------------------------------------- 922230557Sjimharris// Accessable to all FN#s 923230557Sjimharris#define SCU_SMU_PCP_OFFSET 0x0000 924230557Sjimharris#define SCU_SMU_AMR_OFFSET 0x0004 925230557Sjimharris#define SCU_SMU_ISR_OFFSET 0x0010 926230557Sjimharris#define SCU_SMU_IMR_OFFSET 0x0014 927230557Sjimharris#define SCU_SMU_ICC_OFFSET 0x0018 928230557Sjimharris#define SCU_SMU_HTTLBAR_OFFSET 0x0020 929230557Sjimharris#define SCU_SMU_HTTUBAR_OFFSET 0x0024 930230557Sjimharris#define SCU_SMU_TCR_OFFSET 0x0028 931230557Sjimharris#define SCU_SMU_CQLBAR_OFFSET 0x0030 932230557Sjimharris#define SCU_SMU_CQUBAR_OFFSET 0x0034 933230557Sjimharris#define SCU_SMU_CQPR_OFFSET 0x0040 934230557Sjimharris#define SCU_SMU_CQGR_OFFSET 0x0044 935230557Sjimharris#define SCU_SMU_CQC_OFFSET 0x0048 936230557Sjimharris// Accessable to FN#0 only 937230557Sjimharris#define SCU_SMU_RNCLBAR_OFFSET 0x0080 938230557Sjimharris#define SCU_SMU_RNCUBAR_OFFSET 0x0084 939230557Sjimharris#define SCU_SMU_DCC_OFFSET 0x0090 940230557Sjimharris#define SCU_SMU_DFC_OFFSET 0x0094 941230557Sjimharris#define SCU_SMU_SMUCSR_OFFSET 0x0098 942230557Sjimharris#define SCU_SMU_SCUSRCR_OFFSET 0x009C 943230557Sjimharris#define SCU_SMU_SMAW_OFFSET 0x00A0 944230557Sjimharris#define SCU_SMU_SMDW_OFFSET 0x00A4 945230557Sjimharris// Accessable to FN#0 only 946230557Sjimharris#define SCU_SMU_TCA_OFFSET 0x0400 947230557Sjimharris// Accessable to all FN#s 948230557Sjimharris#define SCU_SMU_MT_MLAR0_OFFSET 0x2000 949230557Sjimharris#define SCU_SMU_MT_MUAR0_OFFSET 0x2004 950230557Sjimharris#define SCU_SMU_MT_MDR0_OFFSET 0x2008 951230557Sjimharris#define SCU_SMU_MT_VCR0_OFFSET 0x200C 952230557Sjimharris#define SCU_SMU_MT_MLAR1_OFFSET 0x2010 953230557Sjimharris#define SCU_SMU_MT_MUAR1_OFFSET 0x2014 954230557Sjimharris#define SCU_SMU_MT_MDR1_OFFSET 0x2018 955230557Sjimharris#define SCU_SMU_MT_VCR1_OFFSET 0x201C 956230557Sjimharris#define SCU_SMU_MPBA_OFFSET 0x3000 957230557Sjimharris 958230557Sjimharris/** 959230557Sjimharris * @struct SMU_REGISTERS 960230557Sjimharris * 961230557Sjimharris * @brief These are the SMU registers 962230557Sjimharris * See SCU SMU Specification on how this register space is used. 963230557Sjimharris */ 964230557Sjimharristypedef struct SMU_REGISTERS 965230557Sjimharris{ 966230557Sjimharris// 0x0000 PCP 967230557Sjimharris U32 post_context_port; 968230557Sjimharris// 0x0004 AMR 969230557Sjimharris U32 address_modifier; 970230557Sjimharris U32 reserved_08; 971230557Sjimharris U32 reserved_0C; 972230557Sjimharris// 0x0010 ISR 973230557Sjimharris U32 interrupt_status; 974230557Sjimharris// 0x0014 IMR 975230557Sjimharris U32 interrupt_mask; 976230557Sjimharris// 0x0018 ICC 977230557Sjimharris U32 interrupt_coalesce_control; 978230557Sjimharris U32 reserved_1C; 979230557Sjimharris// 0x0020 HTTLBAR 980230557Sjimharris U32 host_task_table_lower; 981230557Sjimharris// 0x0024 HTTUBAR 982230557Sjimharris U32 host_task_table_upper; 983230557Sjimharris// 0x0028 TCR 984230557Sjimharris U32 task_context_range; 985230557Sjimharris U32 reserved_2C; 986230557Sjimharris// 0x0030 CQLBAR 987230557Sjimharris U32 completion_queue_lower; 988230557Sjimharris// 0x0034 CQUBAR 989230557Sjimharris U32 completion_queue_upper; 990230557Sjimharris U32 reserved_38; 991230557Sjimharris U32 reserved_3C; 992230557Sjimharris// 0x0040 CQPR 993230557Sjimharris U32 completion_queue_put; 994230557Sjimharris// 0x0044 CQGR 995230557Sjimharris U32 completion_queue_get; 996230557Sjimharris// 0x0048 CQC 997230557Sjimharris U32 completion_queue_control; 998230557Sjimharris U32 reserved_4C; 999230557Sjimharris U32 reserved_5x[4]; 1000230557Sjimharris U32 reserved_6x[4]; 1001230557Sjimharris U32 reserved_7x[4]; 1002230557Sjimharris// Accessable to FN#0 only 1003230557Sjimharris// 0x0080 RNCLBAR 1004230557Sjimharris U32 remote_node_context_lower; 1005230557Sjimharris// 0x0084 RNCUBAR 1006230557Sjimharris U32 remote_node_context_upper; 1007230557Sjimharris U32 reserved_88; 1008230557Sjimharris U32 reserved_8C; 1009230557Sjimharris// 0x0090 DCC 1010230557Sjimharris U32 device_context_capacity; 1011230557Sjimharris// 0x0094 DFC 1012230557Sjimharris U32 device_function_capacity; 1013230557Sjimharris// 0x0098 SMUCSR 1014230557Sjimharris U32 control_status; 1015230557Sjimharris// 0x009C SCUSRCR 1016230557Sjimharris U32 soft_reset_control; 1017230557Sjimharris// 0x00A0 SMAW 1018230557Sjimharris U32 mmr_address_window; 1019230557Sjimharris// 0x00A4 SMDW 1020230557Sjimharris U32 mmr_data_window; 1021230557Sjimharris// 0x00A8 CGUCR 1022230557Sjimharris U32 clock_gating_control; 1023230557Sjimharris// 0x00AC CGUPC 1024230557Sjimharris U32 clock_gating_performance; 1025230557Sjimharris// A whole bunch of reserved space 1026230557Sjimharris U32 reserved_Bx[4]; 1027230557Sjimharris U32 reserved_Cx[4]; 1028230557Sjimharris U32 reserved_Dx[4]; 1029230557Sjimharris U32 reserved_Ex[4]; 1030230557Sjimharris U32 reserved_Fx[4]; 1031230557Sjimharris U32 reserved_1xx[64]; 1032230557Sjimharris U32 reserved_2xx[64]; 1033230557Sjimharris U32 reserved_3xx[64]; 1034230557Sjimharris// Accessable to FN#0 only 1035230557Sjimharris// 0x0400 TCA 1036230557Sjimharris U32 task_context_assignment[256]; 1037230557Sjimharris// MSI-X registers not included 1038230557Sjimharris} SMU_REGISTERS_T; 1039230557Sjimharris 1040230557Sjimharris//***************************************************************************** 1041230557Sjimharris// SDMA Registers 1042230557Sjimharris//***************************************************************************** 1043230557Sjimharris#define SCU_SDMA_BASE 0x6000 1044230557Sjimharris#define SCU_SDMA_PUFATLHAR_OFFSET 0x0000 1045230557Sjimharris#define SCU_SDMA_PUFATUHAR_OFFSET 0x0004 1046230557Sjimharris#define SCU_SDMA_UFLHBAR_OFFSET 0x0008 1047230557Sjimharris#define SCU_SDMA_UFUHBAR_OFFSET 0x000C 1048230557Sjimharris#define SCU_SDMA_UFQC_OFFSET 0x0010 1049230557Sjimharris#define SCU_SDMA_UFQPP_OFFSET 0x0014 1050230557Sjimharris#define SCU_SDMA_UFQGP_OFFSET 0x0018 1051230557Sjimharris#define SCU_SDMA_PDMACR_OFFSET 0x001C 1052230557Sjimharris#define SCU_SDMA_CDMACR_OFFSET 0x0080 1053230557Sjimharris 1054230557Sjimharris/** 1055230557Sjimharris * @struct SCU_SDMA_REGISTERS 1056230557Sjimharris * 1057230557Sjimharris * @brief These are the SCU SDMA Registers 1058230557Sjimharris * See SCU SDMA specification on how these registers are used. 1059230557Sjimharris */ 1060230557Sjimharristypedef struct SCU_SDMA_REGISTERS 1061230557Sjimharris{ 1062230557Sjimharris// 0x0000 PUFATLHAR 1063230557Sjimharris U32 uf_address_table_lower; 1064230557Sjimharris// 0x0004 PUFATUHAR 1065230557Sjimharris U32 uf_address_table_upper; 1066230557Sjimharris// 0x0008 UFLHBAR 1067230557Sjimharris U32 uf_header_base_address_lower; 1068230557Sjimharris// 0x000C UFUHBAR 1069230557Sjimharris U32 uf_header_base_address_upper; 1070230557Sjimharris// 0x0010 UFQC 1071230557Sjimharris U32 unsolicited_frame_queue_control; 1072230557Sjimharris// 0x0014 UFQPP 1073230557Sjimharris U32 unsolicited_frame_put_pointer; 1074230557Sjimharris// 0x0018 UFQGP 1075230557Sjimharris U32 unsolicited_frame_get_pointer; 1076230557Sjimharris// 0x001C PDMACR 1077230557Sjimharris U32 pdma_configuration; 1078230557Sjimharris// Reserved until offset 0x80 1079230557Sjimharris U32 reserved_0020_007C[0x18]; 1080230557Sjimharris// 0x0080 CDMACR 1081230557Sjimharris U32 cdma_configuration; 1082230557Sjimharris// Remainder SDMA register space 1083230557Sjimharris U32 reserved_0084_0400[0xDF]; 1084230557Sjimharris 1085230557Sjimharris} SCU_SDMA_REGISTERS_T; 1086230557Sjimharris 1087230557Sjimharris//***************************************************************************** 1088230557Sjimharris//* SCU Link Registers 1089230557Sjimharris//***************************************************************************** 1090230557Sjimharris#define SCU_PEG0_OFFSET 0x0000 1091230557Sjimharris#define SCU_PEG1_OFFSET 0x8000 1092230557Sjimharris 1093230557Sjimharris#define SCU_TL0_OFFSET 0x0000 1094230557Sjimharris#define SCU_TL1_OFFSET 0x0400 1095230557Sjimharris#define SCU_TL2_OFFSET 0x0800 1096230557Sjimharris#define SCU_TL3_OFFSET 0x0C00 1097230557Sjimharris 1098230557Sjimharris#define SCU_LL_OFFSET 0x0080 1099230557Sjimharris#define SCU_LL0_OFFSET (SCU_TL0_OFFSET + SCU_LL_OFFSET) 1100230557Sjimharris#define SCU_LL1_OFFSET (SCU_TL1_OFFSET + SCU_LL_OFFSET) 1101230557Sjimharris#define SCU_LL2_OFFSET (SCU_TL2_OFFSET + SCU_LL_OFFSET) 1102230557Sjimharris#define SCU_LL3_OFFSET (SCU_TL3_OFFSET + SCU_LL_OFFSET) 1103230557Sjimharris 1104230557Sjimharris// Transport Layer Offsets (PEG + TL) 1105230557Sjimharris#define SCU_TLCR_OFFSET 0x0000 1106230557Sjimharris#define SCU_TLADTR_OFFSET 0x0004 1107230557Sjimharris#define SCU_TLTTMR_OFFSET 0x0008 1108230557Sjimharris#define SCU_TLEECR0_OFFSET 0x000C 1109230557Sjimharris#define SCU_STPTLDARNI_OFFSET 0x0010 1110230557Sjimharris 1111230557Sjimharris 1112230557Sjimharris#define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_SHIFT (0UL) 1113230557Sjimharris#define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_MASK (0x00000001UL) 1114230557Sjimharris#define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_SHIFT (1UL) 1115230557Sjimharris#define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_MASK (0x00000002UL) 1116230557Sjimharris#define SCU_TLCR_STP_WRITE_DATA_PREFETCH_SHIFT (3UL) 1117230557Sjimharris#define SCU_TLCR_STP_WRITE_DATA_PREFETCH_MASK (0x00000008UL) 1118230557Sjimharris#define SCU_TLCR_CMD_NAK_STATUS_CODE_SHIFT (4UL) 1119230557Sjimharris#define SCU_TLCR_CMD_NAK_STATUS_CODE_MASK (0x00000010UL) 1120230557Sjimharris#define SCU_TLCR_RESERVED_MASK (0xFFFFFFEBUL) 1121230557Sjimharris 1122230557Sjimharris#define SCU_TLCR_GEN_BIT(name) \ 1123230557Sjimharris SCU_GEN_BIT(SCU_TLCR_##name) 1124230557Sjimharris 1125230557Sjimharris/** 1126230557Sjimharris * @struct SCU_TRANSPORT_LAYER_REGISTERS 1127230557Sjimharris * 1128230557Sjimharris * @brief These are the SCU Transport Layer registers see SSPTL spec for how 1129230557Sjimharris * they are used. 1130230557Sjimharris */ 1131230557Sjimharristypedef struct SCU_TRANSPORT_LAYER_REGISTERS 1132230557Sjimharris{ 1133230557Sjimharris // 0x0000 TLCR 1134230557Sjimharris U32 control; 1135230557Sjimharris // 0x0004 TLADTR 1136230557Sjimharris U32 arbitration_delay_timer; 1137230557Sjimharris // 0x0008 TLTTMR 1138230557Sjimharris U32 timer_test_mode; 1139230557Sjimharris // 0x000C reserved 1140230557Sjimharris U32 reserved_0C; 1141230557Sjimharris // 0x0010 STPTLDARNI 1142230557Sjimharris U32 stp_rni; 1143230557Sjimharris // 0x0014 TLFEWPORCTRL 1144230557Sjimharris U32 tlfe_wpo_read_control; 1145230557Sjimharris // 0x0018 TLFEWPORDATA 1146230557Sjimharris U32 tlfe_wpo_read_data; 1147230557Sjimharris // 0x001C RXTLSSCSR1 1148230557Sjimharris U32 rxtl_single_step_control_status_1; 1149230557Sjimharris // 0x0020 RXTLSSCSR2 1150230557Sjimharris U32 rxtl_single_step_control_status_2; 1151230557Sjimharris // 0x0024 AWTRDDCR 1152230557Sjimharris U32 tlfe_awt_retry_delay_debug_control; 1153230557Sjimharris // Remainder of TL memory space 1154230557Sjimharris U32 reserved_0028_007F[0x16]; 1155230557Sjimharris 1156230557Sjimharris} SCU_TRANSPORT_LAYER_REGISTERS_T; 1157230557Sjimharris 1158230557Sjimharris// Protocol Engine Group Registers 1159230557Sjimharris#define SCU_SCUVZECRx_OFFSET 0x1080 1160230557Sjimharris 1161230557Sjimharris// Link Layer Offsets (PEG + TL + LL) 1162230557Sjimharris#define SCU_SAS_SPDTOV_OFFSET 0x0000 1163230557Sjimharris#define SCU_SAS_LLSTA_OFFSET 0x0004 1164230557Sjimharris#define SCU_SATA_PSELTOV_OFFSET 0x0008 1165230557Sjimharris#define SCU_SAS_TIMETOV_OFFSET 0x0010 1166230557Sjimharris#define SCU_SAS_LOSTOT_OFFSET 0x0014 1167230557Sjimharris#define SCU_SAS_LNKTOV_OFFSET 0x0018 1168230557Sjimharris#define SCU_SAS_PHYTOV_OFFSET 0x001C 1169230557Sjimharris#define SCU_SAS_AFERCNT_OFFSET 0x0020 1170230557Sjimharris#define SCU_SAS_WERCNT_OFFSET 0x0024 1171230557Sjimharris#define SCU_SAS_TIID_OFFSET 0x0028 1172230557Sjimharris#define SCU_SAS_TIDNH_OFFSET 0x002C 1173230557Sjimharris#define SCU_SAS_TIDNL_OFFSET 0x0030 1174230557Sjimharris#define SCU_SAS_TISSAH_OFFSET 0x0034 1175230557Sjimharris#define SCU_SAS_TISSAL_OFFSET 0x0038 1176230557Sjimharris#define SCU_SAS_TIPID_OFFSET 0x003C 1177230557Sjimharris#define SCU_SAS_TIRES2_OFFSET 0x0040 1178230557Sjimharris#define SCU_SAS_ADRSTA_OFFSET 0x0044 1179230557Sjimharris#define SCU_SAS_MAWTTOV_OFFSET 0x0048 1180230557Sjimharris#define SCU_SAS_ECENCR_OFFSET 0x0050 1181230557Sjimharris#define SCU_SAS_FRPLDFIL_OFFSET 0x0054 1182230557Sjimharris#define SCU_SAS_RFCNT_OFFSET 0x0060 1183230557Sjimharris#define SCU_SAS_TFCNT_OFFSET 0x0064 1184230557Sjimharris#define SCU_SAS_RFDCNT_OFFSET 0x0068 1185230557Sjimharris#define SCU_SAS_TFDCNT_OFFSET 0x006C 1186230557Sjimharris#define SCU_SAS_LERCNT_OFFSET 0x0070 1187230557Sjimharris#define SCU_SAS_RDISERRCNT_OFFSET 0x0074 1188230557Sjimharris#define SCU_SAS_CRERCNT_OFFSET 0x0078 1189230557Sjimharris#define SCU_STPCTL_OFFSET 0x007C 1190230557Sjimharris#define SCU_SAS_PCFG_OFFSET 0x0080 1191230557Sjimharris#define SCU_SAS_CLKSM_OFFSET 0x0084 1192230557Sjimharris#define SCU_SAS_TXCOMWAKE_OFFSET 0x0088 1193230557Sjimharris#define SCU_SAS_TXCOMINIT_OFFSET 0x008C 1194230557Sjimharris#define SCU_SAS_TXCOMSAS_OFFSET 0x0090 1195230557Sjimharris#define SCU_SAS_COMINIT_OFFSET 0x0094 1196230557Sjimharris#define SCU_SAS_COMWAKE_OFFSET 0x0098 1197230557Sjimharris#define SCU_SAS_COMSAS_OFFSET 0x009C 1198230557Sjimharris#define SCU_SAS_SFERCNT_OFFSET 0x00A0 1199230557Sjimharris#define SCU_SAS_CDFERCNT_OFFSET 0x00A4 1200230557Sjimharris#define SCU_SAS_DNFERCNT_OFFSET 0x00A8 1201230557Sjimharris#define SCU_SAS_PRSTERCNT_OFFSET 0x00AC 1202230557Sjimharris#define SCU_SAS_CNTCTL_OFFSET 0x00B0 1203230557Sjimharris#define SCU_SAS_SSPTOV_OFFSET 0x00B4 1204230557Sjimharris#define SCU_FTCTL_OFFSET 0x00B8 1205230557Sjimharris#define SCU_FRCTL_OFFSET 0x00BC 1206230557Sjimharris#define SCU_FTWMRK_OFFSET 0x00C0 1207230557Sjimharris#define SCU_ENSPINUP_OFFSET 0x00C4 1208230557Sjimharris#define SCU_SAS_TRNTOV_OFFSET 0x00C8 1209230557Sjimharris#define SCU_SAS_PHYCAP_OFFSET 0x00CC 1210230557Sjimharris#define SCU_SAS_PHYCTL_OFFSET 0x00D0 1211230557Sjimharris#define SCU_SAS_LLCTL_OFFSET 0x00D8 1212230557Sjimharris#define SCU_AFE_XCVRCR_OFFSET 0x00DC 1213230557Sjimharris#define SCU_AFE_LUTCR_OFFSET 0x00E0 1214230557Sjimharris 1215230557Sjimharris#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_SHIFT (0UL) 1216230557Sjimharris#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_MASK (0x000000FFUL) 1217230557Sjimharris#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_SHIFT (8UL) 1218230557Sjimharris#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_MASK (0x0000FF00UL) 1219230557Sjimharris#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_SHIFT (16UL) 1220230557Sjimharris#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_MASK (0x00FF0000UL) 1221230557Sjimharris#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_SHIFT (24UL) 1222230557Sjimharris#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_MASK (0xFF000000UL) 1223230557Sjimharris 1224230557Sjimharris#define SCU_SAS_PHYTOV_GEN_VAL(name, value) \ 1225230557Sjimharris SCU_GEN_VALUE(SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_##name, value) 1226230557Sjimharris 1227230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_SHIFT (0UL) 1228230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_MASK (0x00000003UL) 1229230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1 (0UL) 1230230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2 (1UL) 1231230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3 (2UL) 1232230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_SHIFT (2UL) 1233230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_MASK (0x000003FCUL) 1234230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_SHIFT (16UL) 1235230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_MASK (0x00010000UL) 1236230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_SHIFT (17UL) 1237230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_MASK (0x00020000UL) 1238230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_SHIFT (24UL) 1239230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_MASK (0xFF000000UL) 1240230557Sjimharris#define SCU_SAS_LINK_LAYER_CONTROL_RESERVED (0x00FCFC00UL) 1241230557Sjimharris 1242230557Sjimharris#define SCU_SAS_LLCTL_GEN_VAL(name, value) \ 1243230557Sjimharris SCU_GEN_VALUE(SCU_SAS_LINK_LAYER_CONTROL_##name, value) 1244230557Sjimharris 1245230557Sjimharris#define SCU_SAS_LLCTL_GEN_BIT(name) \ 1246230557Sjimharris SCU_GEN_BIT(SCU_SAS_LINK_LAYER_CONTROL_##name) 1247230557Sjimharris 1248230557Sjimharris//#define SCU_FRXHECR_DCNT_OFFSET 0x00B0 1249230557Sjimharris#define SCU_PSZGCR_OFFSET 0x00E4 1250230557Sjimharris#define SCU_SAS_RECPHYCAP_OFFSET 0x00E8 1251230557Sjimharris//#define SCU_TX_LUTSEL_OFFSET 0x00B8 1252230557Sjimharris 1253230557Sjimharris#define SCU_SAS_PTxC_OFFSET 0x00D4 // Same offset as SAS_TCTSTM 1254230557Sjimharris 1255230557Sjimharris// This macro define the DWORD SYNC ACQUIRED bit in link layer status register. 1256230557Sjimharris#define SCU_SAS_LLSTA_DWORD_SYNCA_BIT 0x4 1257230557Sjimharris 1258230557Sjimharris/** 1259230557Sjimharris * @struct SCU_LINK_LAYER_REGISTERS 1260230557Sjimharris * 1261230557Sjimharris * @brief SCU Link Layer Registers 1262230557Sjimharris * See the SCU SSLL Specification on how these registers are used. 1263230557Sjimharris */ 1264230557Sjimharristypedef struct SCU_LINK_LAYER_REGISTERS 1265230557Sjimharris{ 1266230557Sjimharris// 0x0000 SAS_SPDTOV 1267230557Sjimharris U32 speed_negotiation_timers; 1268230557Sjimharris// 0x0004 SAS_LLSTA 1269230557Sjimharris U32 link_layer_status; 1270230557Sjimharris// 0x0008 SATA_PSELTOV 1271230557Sjimharris U32 port_selector_timeout; 1272230557Sjimharris U32 reserved0C; 1273230557Sjimharris// 0x0010 SAS_TIMETOV 1274230557Sjimharris U32 timeout_unit_value; 1275230557Sjimharris// 0x0014 SAS_RCDTOV 1276230557Sjimharris U32 rcd_timeout; 1277230557Sjimharris// 0x0018 SAS_LNKTOV 1278230557Sjimharris U32 link_timer_timeouts; 1279230557Sjimharris// 0x001C SAS_PHYTOV 1280230557Sjimharris U32 phy_timer_timeout_values; 1281230557Sjimharris// 0x0020 SAS_AFERCNT 1282230557Sjimharris U32 received_address_frame_error_counter; 1283230557Sjimharris// 0x0024 SAS_WERCNT 1284230557Sjimharris U32 invalid_dword_counter; 1285230557Sjimharris// 0x0028 SAS_TIID 1286230557Sjimharris U32 transmit_identification; 1287230557Sjimharris// 0x002C SAS_TIDNH 1288230557Sjimharris U32 sas_device_name_high; 1289230557Sjimharris// 0x0030 SAS_TIDNL 1290230557Sjimharris U32 sas_device_name_low; 1291230557Sjimharris// 0x0034 SAS_TISSAH 1292230557Sjimharris U32 source_sas_address_high; 1293230557Sjimharris// 0x0038 SAS_TISSAL 1294230557Sjimharris U32 source_sas_address_low; 1295230557Sjimharris// 0x003C SAS_TIPID 1296230557Sjimharris U32 identify_frame_phy_id; 1297230557Sjimharris// 0x0040 SAS_TIRES2 1298230557Sjimharris U32 identify_frame_reserved; 1299230557Sjimharris// 0x0044 SAS_ADRSTA 1300230557Sjimharris U32 received_address_frame; 1301230557Sjimharris// 0x0048 SAS_MAWTTOV 1302230557Sjimharris U32 maximum_arbitration_wait_timer_timeout; 1303230557Sjimharris// 0x004C SAS_PTxC 1304230557Sjimharris U32 transmit_primitive; 1305230557Sjimharris// 0x0050 SAS_ECENCR 1306230557Sjimharris U32 error_counter_event_notification_control; 1307230557Sjimharris// 0x0054 SAS_FRPLDFIL 1308230557Sjimharris U32 frxq_payload_fill_threshold; 1309230557Sjimharris// 0x0058 SAS_LLHANG_TOT 1310230557Sjimharris U32 link_layer_hang_detection_timeout; 1311230557Sjimharris U32 reserved_5C; 1312230557Sjimharris// 0x0060 SAS_RFCNT 1313230557Sjimharris U32 received_frame_count; 1314230557Sjimharris// 0x0064 SAS_TFCNT 1315230557Sjimharris U32 transmit_frame_count; 1316230557Sjimharris// 0x0068 SAS_RFDCNT 1317230557Sjimharris U32 received_dword_count; 1318230557Sjimharris// 0x006C SAS_TFDCNT 1319230557Sjimharris U32 transmit_dword_count; 1320230557Sjimharris// 0x0070 SAS_LERCNT 1321230557Sjimharris U32 loss_of_sync_error_count; 1322230557Sjimharris// 0x0074 SAS_RDISERRCNT 1323230557Sjimharris U32 running_disparity_error_count; 1324230557Sjimharris// 0x0078 SAS_CRERCNT 1325230557Sjimharris U32 received_frame_crc_error_count; 1326230557Sjimharris// 0x007C STPCTL 1327230557Sjimharris U32 stp_control; 1328230557Sjimharris// 0x0080 SAS_PCFG 1329230557Sjimharris U32 phy_configuration; 1330230557Sjimharris// 0x0084 SAS_CLKSM 1331230557Sjimharris U32 clock_skew_management; 1332230557Sjimharris// 0x0088 SAS_TXCOMWAKE 1333230557Sjimharris U32 transmit_comwake_signal; 1334230557Sjimharris// 0x008C SAS_TXCOMINIT 1335230557Sjimharris U32 transmit_cominit_signal; 1336230557Sjimharris// 0x0090 SAS_TXCOMSAS 1337230557Sjimharris U32 transmit_comsas_signal; 1338230557Sjimharris// 0x0094 SAS_COMINIT 1339230557Sjimharris U32 cominit_control; 1340230557Sjimharris// 0x0098 SAS_COMWAKE 1341230557Sjimharris U32 comwake_control; 1342230557Sjimharris// 0x009C SAS_COMSAS 1343230557Sjimharris U32 comsas_control; 1344230557Sjimharris// 0x00A0 SAS_SFERCNT 1345230557Sjimharris U32 received_short_frame_count; 1346230557Sjimharris// 0x00A4 SAS_CDFERCNT 1347230557Sjimharris U32 received_frame_without_credit_count; 1348230557Sjimharris// 0x00A8 SAS_DNFERCNT 1349230557Sjimharris U32 received_frame_after_done_count; 1350230557Sjimharris// 0x00AC SAS_PRSTERCNT 1351230557Sjimharris U32 phy_reset_problem_count; 1352230557Sjimharris// 0x00B0 SAS_CNTCTL 1353230557Sjimharris U32 counter_control; 1354230557Sjimharris// 0x00B4 SAS_SSPTOV 1355230557Sjimharris U32 ssp_timer_timeout_values; 1356230557Sjimharris// 0x00B8 FTCTL 1357230557Sjimharris U32 ftx_control; 1358230557Sjimharris// 0x00BC FRCTL 1359230557Sjimharris U32 frx_control; 1360230557Sjimharris// 0x00C0 FTWMRK 1361230557Sjimharris U32 ftx_watermark; 1362230557Sjimharris// 0x00C4 ENSPINUP 1363230557Sjimharris U32 notify_enable_spinup_control; 1364230557Sjimharris// 0x00C8 SAS_TRNTOV 1365230557Sjimharris U32 sas_training_sequence_timer_values; 1366230557Sjimharris// 0x00CC SAS_PHYCAP 1367230557Sjimharris U32 phy_capabilities; 1368230557Sjimharris// 0x00D0 SAS_PHYCTL 1369230557Sjimharris U32 phy_control; 1370230557Sjimharris U32 reserved_d4; 1371230557Sjimharris// 0x00D8 LLCTL 1372230557Sjimharris U32 link_layer_control; 1373230557Sjimharris// 0x00DC AFE_XCVRCR 1374230557Sjimharris U32 afe_xcvr_control; 1375230557Sjimharris// 0x00E0 AFE_LUTCR 1376230557Sjimharris U32 afe_lookup_table_control; 1377230557Sjimharris// 0x00E4 PSZGCR 1378230557Sjimharris U32 phy_source_zone_group_control; 1379230557Sjimharris// 0x00E8 SAS_RECPHYCAP 1380230557Sjimharris U32 receive_phycap; 1381230557Sjimharris U32 reserved_ec; 1382230557Sjimharris// 0x00F0 SNAFERXRSTCTL 1383230557Sjimharris U32 speed_negotiation_afe_rx_reset_control; 1384230557Sjimharris// 0x00F4 SAS_SSIPMCTL 1385230557Sjimharris U32 power_management_control; 1386230557Sjimharris// 0x00F8 SAS_PSPREQ_PRIM 1387230557Sjimharris U32 sas_pm_partial_request_primitive; 1388230557Sjimharris// 0x00FC SAS_PSSREQ_PRIM 1389230557Sjimharris U32 sas_pm_slumber_request_primitive; 1390230557Sjimharris// 0x0100 SAS_PPSACK_PRIM 1391230557Sjimharris U32 sas_pm_ack_primitive_register; 1392230557Sjimharris// 0x0104 SAS_PSNAK_PRIM 1393230557Sjimharris U32 sas_pm_nak_primitive_register; 1394230557Sjimharris// 0x0108 SAS_SSIPMTOV 1395230557Sjimharris U32 sas_primitive_timeout; 1396230557Sjimharris U32 reserved_10c; 1397230557Sjimharris// 0x0110 - 0x011C PLAPRDCTRLxREG 1398230557Sjimharris U32 pla_product_control[4]; 1399230557Sjimharris// 0x0120 PLAPRDSUMREG 1400230557Sjimharris U32 pla_product_sum; 1401230557Sjimharris// 0x0124 PLACONTROLREG 1402230557Sjimharris U32 pla_control; 1403230557Sjimharris// Remainder of memory space 896 bytes 1404230557Sjimharris U32 reserved_0128_037f[0x96]; 1405230557Sjimharris 1406230557Sjimharris} SCU_LINK_LAYER_REGISTERS_T; 1407230557Sjimharris 1408230557Sjimharris// 0x00D4 // Same offset as SAS_TCTSTM SAS_PTxC 1409230557Sjimharris// U32 primitive_transmit_control; 1410230557Sjimharris 1411230557Sjimharris// ---------------------------------------------------------------------------- 1412230557Sjimharris// SGPIO 1413230557Sjimharris// ---------------------------------------------------------------------------- 1414230557Sjimharris#define SCU_SGPIO_OFFSET 0x1400 1415230557Sjimharris 1416230557Sjimharris//#define SCU_SGPIO_OFFSET 0x6000 // later moves to 0x1400 see HSD 652625 1417230557Sjimharris#define SCU_SGPIO_SGICR_OFFSET 0x0000 1418230557Sjimharris#define SCU_SGPIO_SGPBR_OFFSET 0x0004 1419230557Sjimharris#define SCU_SGPIO_SGSDLR_OFFSET 0x0008 1420230557Sjimharris#define SCU_SGPIO_SGSDUR_OFFSET 0x000C 1421230557Sjimharris#define SCU_SGPIO_SGSIDLR_OFFSET 0x0010 1422230557Sjimharris#define SCU_SGPIO_SGSIDUR_OFFSET 0x0014 1423230557Sjimharris#define SCU_SGPIO_SGVSCR_OFFSET 0x0018 1424230557Sjimharris// Address from 0x0820 to 0x083C 1425230557Sjimharris#define SCU_SGPIO_SGODSR_OFFSET 0x0020 1426230557Sjimharris 1427230557Sjimharris/** 1428230557Sjimharris * @struct SCU_SGPIO_REGISTERS 1429230557Sjimharris * 1430230557Sjimharris * @brief SCU SGPIO Registers 1431230557Sjimharris * See the SCU SGPIO Specification on how these registers are used. 1432230557Sjimharris */ 1433230557Sjimharristypedef struct SCU_SGPIO_REGISTERS 1434230557Sjimharris{ 1435230557Sjimharris// 0x0000 SGPIO_SGICR 1436230557Sjimharris U32 interface_control; 1437230557Sjimharris// 0x0004 SGPIO_SGPBR 1438230557Sjimharris U32 blink_rate; 1439230557Sjimharris// 0x0008 SGPIO_SGSDLR 1440230557Sjimharris U32 start_drive_lower; 1441230557Sjimharris// 0x000C SGPIO_SGSDUR 1442230557Sjimharris U32 start_drive_upper; 1443230557Sjimharris// 0x0010 SGPIO_SGSIDLR 1444230557Sjimharris U32 serial_input_lower; 1445230557Sjimharris// 0x0014 SGPIO_SGSIDUR 1446230557Sjimharris U32 serial_input_upper; 1447230557Sjimharris// 0x0018 SGPIO_SGVSCR 1448230557Sjimharris U32 vendor_specific_code; 1449230557Sjimharris// 0x001C Reserved 1450230557Sjimharris U32 reserved_001C; 1451230557Sjimharris// 0x0020 SGPIO_SGODSR 1452230557Sjimharris U32 output_data_select[8]; 1453230557Sjimharris// Remainder of memory space 256 bytes 1454230557Sjimharris U32 reserved_1444_14ff[0x30]; 1455230557Sjimharris 1456230557Sjimharris} SCU_SGPIO_REGISTERS_T; 1457230557Sjimharris 1458230557Sjimharris//***************************************************************************** 1459230557Sjimharris//* Defines for VIIT entry offsets 1460230557Sjimharris//* Access additional entries by SCU_VIIT_BASE + index * 0x10 1461230557Sjimharris//***************************************************************************** 1462230557Sjimharris#define SCU_VIIT_BASE 0x1c00 1463230557Sjimharris 1464230557Sjimharrisstruct SCU_VIIT_REGISTERS 1465230557Sjimharris{ 1466230557Sjimharris U32 registers[256]; 1467230557Sjimharris}; 1468230557Sjimharris 1469230557Sjimharris//***************************************************************************** 1470230557Sjimharris//* SCU PORT TASK SCHEDULER REGISTERS 1471230557Sjimharris//***************************************************************************** 1472230557Sjimharris 1473230557Sjimharris#define SCU_PTSG_BASE 0x1000 1474230557Sjimharris 1475230557Sjimharris#define SCU_PTSG_PTSGCR_OFFSET 0x0000 1476230557Sjimharris#define SCU_PTSG_RTCR_OFFSET 0x0004 1477230557Sjimharris#define SCU_PTSG_RTCCR_OFFSET 0x0008 1478230557Sjimharris#define SCU_PTSG_PTS0CR_OFFSET 0x0010 1479230557Sjimharris#define SCU_PTSG_PTS0SR_OFFSET 0x0014 1480230557Sjimharris#define SCU_PTSG_PTS1CR_OFFSET 0x0018 1481230557Sjimharris#define SCU_PTSG_PTS1SR_OFFSET 0x001C 1482230557Sjimharris#define SCU_PTSG_PTS2CR_OFFSET 0x0020 1483230557Sjimharris#define SCU_PTSG_PTS2SR_OFFSET 0x0024 1484230557Sjimharris#define SCU_PTSG_PTS3CR_OFFSET 0x0028 1485230557Sjimharris#define SCU_PTSG_PTS3SR_OFFSET 0x002C 1486230557Sjimharris#define SCU_PTSG_PCSPE0CR_OFFSET 0x0030 1487230557Sjimharris#define SCU_PTSG_PCSPE1CR_OFFSET 0x0034 1488230557Sjimharris#define SCU_PTSG_PCSPE2CR_OFFSET 0x0038 1489230557Sjimharris#define SCU_PTSG_PCSPE3CR_OFFSET 0x003C 1490230557Sjimharris#define SCU_PTSG_ETMTSCCR_OFFSET 0x0040 1491230557Sjimharris#define SCU_PTSG_ETMRNSCCR_OFFSET 0x0044 1492230557Sjimharris 1493230557Sjimharris/** 1494230557Sjimharris * @struct SCU_PORT_TASK_SCHEDULER_REGISTERS 1495230557Sjimharris * 1496230557Sjimharris * @brief These are the control/stats pairs for each Port Task Scheduler. 1497230557Sjimharris * See the SCU SCHED Specification on how these registers are used. 1498230557Sjimharris */ 1499230557Sjimharristypedef struct SCU_PORT_TASK_SCHEDULER_REGISTERS 1500230557Sjimharris{ 1501230557Sjimharris U32 control; 1502230557Sjimharris U32 status; 1503230557Sjimharris} SCU_PORT_TASK_SCHEDULER_REGISTERS_T; 1504230557Sjimharris 1505230557Sjimharristypedef U32 SCU_PORT_PE_CONFIGURATION_REGISTER_T; 1506230557Sjimharris 1507230557Sjimharris/** 1508230557Sjimharris * @struct SCU_PORT_TASK_SCHEDULER_GROUP_REGISTERS 1509230557Sjimharris * 1510230557Sjimharris * @brief These are the PORT Task Scheduler registers 1511230557Sjimharris * See the SCU SCHED Specification on how these registers are used. 1512230557Sjimharris */ 1513230557Sjimharristypedef struct SCU_PORT_TASK_SCHEDULER_GROUP_REGISTERS 1514230557Sjimharris{ 1515230557Sjimharris// 0x0000 PTSGCR 1516230557Sjimharris U32 control; 1517230557Sjimharris// 0x0004 RTCR 1518230557Sjimharris U32 real_time_clock; 1519230557Sjimharris// 0x0008 RTCCR 1520230557Sjimharris U32 real_time_clock_control; 1521230557Sjimharris// 0x000C 1522230557Sjimharris U32 reserved_0C; 1523230557Sjimharris// 0x0010 PTS0CR 1524230557Sjimharris// 0x0014 PTS0SR 1525230557Sjimharris// 0x0018 PTS1CR 1526230557Sjimharris// 0x001C PTS1SR 1527230557Sjimharris// 0x0020 PTS2CR 1528230557Sjimharris// 0x0024 PTS2SR 1529230557Sjimharris// 0x0028 PTS3CR 1530230557Sjimharris// 0x002C PTS3SR 1531230557Sjimharris SCU_PORT_TASK_SCHEDULER_REGISTERS_T port[4]; 1532230557Sjimharris// 0x0030 PCSPE0CR 1533230557Sjimharris// 0x0034 PCSPE1CR 1534230557Sjimharris// 0x0038 PCSPE2CR 1535230557Sjimharris// 0x003C PCSPE3CR 1536230557Sjimharris SCU_PORT_PE_CONFIGURATION_REGISTER_T protocol_engine[4]; 1537230557Sjimharris// 0x0040 ETMTSCCR 1538230557Sjimharris U32 tc_scanning_interval_control; 1539230557Sjimharris// 0x0044 ETMRNSCCR 1540230557Sjimharris U32 rnc_scanning_interval_control; 1541230557Sjimharris// Remainder of memory space 128 bytes 1542230557Sjimharris U32 reserved_1048_107f[0x0E]; 1543230557Sjimharris 1544230557Sjimharris} SCU_PORT_TASK_SCHEDULER_GROUP_REGISTERS_T; 1545230557Sjimharris 1546230557Sjimharris#define SCU_PTSG_SCUVZECR_OFFSET 0x003C 1547230557Sjimharris 1548230557Sjimharris//***************************************************************************** 1549230557Sjimharris//* AFE REGISTERS 1550230557Sjimharris//***************************************************************************** 1551230557Sjimharris#define SCU_AFE_MMR_BASE 0xE000 1552230557Sjimharris 1553230557Sjimharris#if defined(ARLINGTON_BUILD) 1554230557Sjimharris#define SCU_AFE_PLL_CTL_OFFSET 0x0000 1555230557Sjimharris#define SCU_AFE_RXPI_CTL_OFFSET 0x0004 1556230557Sjimharris#define SCU_AFE_MBIAS_CTL0_OFFSET 0x000C 1557230557Sjimharris#define SCU_AFE_MBIAS_CTL1_OFFSET 0x0010 1558230557Sjimharris#define SCU_AFE_COMM_STA_OFFSET 0x0020 1559230557Sjimharris#define SCU_AFE_RXPI_STA_OFFSET 0x0024 1560230557Sjimharris#define SCU_AFE_XCVR0_CTL0_OFFSET 0x0040 1561230557Sjimharris#define SCU_AFE_XCVR1_CTL0_OFFSET 0x0044 1562230557Sjimharris#define SCU_AFE_XCVR2_CTL0_OFFSET 0x0048 1563230557Sjimharris#define SCU_AFE_XCVR3_CTL0_OFFSET 0x004C 1564230557Sjimharris#define SCU_AFE_XCVR0_CTL1_OFFSET 0x0050 1565230557Sjimharris#define SCU_AFE_XCVR1_CTL1_OFFSET 0x0054 1566230557Sjimharris#define SCU_AFE_XCVR2_CTL1_OFFSET 0x0058 1567230557Sjimharris#define SCU_AFE_XCVR3_CTL1_OFFSET 0x005C 1568230557Sjimharris#define SCU_AFE_XCVR0_RXEQ_CTL_OFFSET 0x0060 1569230557Sjimharris#define SCU_AFE_XCVR1_RXEQ_CTL_OFFSET 0x0064 1570230557Sjimharris#define SCU_AFE_XCVR2_RXEQ_CTL_OFFSET 0x0068 1571230557Sjimharris#define SCU_AFE_XCVR3_RXEQ_CTL_OFFSET 0x006C 1572230557Sjimharris#define SCU_AFE_XCVR0_CDR_STA_OFFSET 0x0080 1573230557Sjimharris#define SCU_AFE_XCVR1_CDR_STA_OFFSET 0x0084 1574230557Sjimharris#define SCU_AFE_XCVR2_CDR_STA_OFFSET 0x0088 1575230557Sjimharris#define SCU_AFE_XCVR3_CDR_STA_OFFSET 0x008C 1576230557Sjimharris#define SCU_AFE_XCVR0_RXEQ_STA0_OFFSET 0x0090 1577230557Sjimharris#define SCU_AFE_XCVR1_RXEQ_STA0_OFFSET 0x0094 1578230557Sjimharris#define SCU_AFE_XCVR2_RXEQ_STA0_OFFSET 0x0098 1579230557Sjimharris#define SCU_AFE_XCVR3_RXEQ_STA0_OFFSET 0x009C 1580230557Sjimharris#define SCU_AFE_XCVR0_RXEQ_STA1_OFFSET 0x00A0 1581230557Sjimharris#define SCU_AFE_XCVR1_RXEQ_STA1_OFFSET 0x00A4 1582230557Sjimharris#define SCU_AFE_XCVR2_RXEQ_STA1_OFFSET 0x00A8 1583230557Sjimharris#define SCU_AFE_XCVR3_RXEQ_STA1_OFFSET 0x00AC 1584230557Sjimharris#define SCU_AFE_DFX_MSTR_CTL_OFFSET 0x0104 1585230557Sjimharris#define SCU_AFE_NTL_CTL_OFFSET 0x010C 1586230557Sjimharris#define SCU_AFE_DFX_XCVR_STA_CLR_OFFSET 0x0120 1587230557Sjimharris#define SCU_AFE_NTL_STA_OFFSET 0x0124 1588230557Sjimharris#define SCU_AFE_DFX_XCVR0_STA0_OFFSET 0x0130 1589230557Sjimharris#define SCU_AFE_DFX_XCVR1_STA0_OFFSET 0x0134 1590230557Sjimharris#define SCU_AFE_DFX_XCVR2_STA0_OFFSET 0x0138 1591230557Sjimharris#define SCU_AFE_DFX_XCVR3_STA0_OFFSET 0x013C 1592230557Sjimharris#define SCU_AFE_DFX_XCVR0_STA1_OFFSET 0x0140 1593230557Sjimharris#define SCU_AFE_DFX_XCVR1_STA1_OFFSET 0x0144 1594230557Sjimharris#define SCU_AFE_DFX_XCVR2_STA1_OFFSET 0x0148 1595230557Sjimharris#define SCU_AFE_DFX_XCVR3_STA1_OFFSET 0x014C 1596230557Sjimharris#define SCU_AFE_DFX_MON_CTL_OFFSET 0x0150 1597230557Sjimharris 1598230557Sjimharris#define SCU_AFE_DFX_RX_CTL0_AFE0_XCVR0_OFFSET 0x0180 1599230557Sjimharris#define SCU_AFE_DFX_RX_CTL0_AFE0_XCVR1_OFFSET 0x0184 1600230557Sjimharris#define SCU_AFE_DFX_RX_CTL0_AFE0_XCVR2_OFFSET 0x0188 1601230557Sjimharris#define SCU_AFE_DFX_RX_CTL0_AFE0_XCVR3_OFFSET 0x018C 1602230557Sjimharris#define SCU_AFE_DFX_RX_CTL0_AFE1_XCVR0_OFFSET 0x0980 1603230557Sjimharris#define SCU_AFE_DFX_RX_CTL0_AFE1_XCVR1_OFFSET 0x0984 1604230557Sjimharris#define SCU_AFE_DFX_RX_CTL0_AFE1_XCVR2_OFFSET 0x0988 1605230557Sjimharris#define SCU_AFE_DFX_RX_CTL0_AFE1_XCVR3_OFFSET 0x098C 1606230557Sjimharris 1607230557Sjimharris#define SCU_AFE_DFX_RX_CTL1_AFE0_XCVR0_OFFSET 0x0190 1608230557Sjimharris#define SCU_AFE_DFX_RX_CTL1_AFE0_XCVR1_OFFSET 0x0194 1609230557Sjimharris#define SCU_AFE_DFX_RX_CTL1_AFE0_XCVR2_OFFSET 0x0198 1610230557Sjimharris#define SCU_AFE_DFX_RX_CTL1_AFE0_XCVR3_OFFSET 0x019C 1611230557Sjimharris#define SCU_AFE_DFX_RX_CTL1_AFE1_XCVR0_OFFSET 0x0990 1612230557Sjimharris#define SCU_AFE_DFX_RX_CTL1_AFE1_XCVR1_OFFSET 0x0994 1613230557Sjimharris#define SCU_AFE_DFX_RX_CTL1_AFE1_XCVR2_OFFSET 0x0998 1614230557Sjimharris#define SCU_AFE_DFX_RX_CTL1_AFE1_XCVR3_OFFSET 0x099C 1615230557Sjimharris 1616230557Sjimharris#define SCU_AFE_PLL_DFX_CTL_OFFSET 0x01C0 1617230557Sjimharris 1618230557Sjimharris#define SCU_AFE_XCVR0_DFX_DATA_OFFSET 0x0200 // [0:0F] 1619230557Sjimharris#define SCU_AFE_XCVR0_CC_OFFSET 0x0240 1620230557Sjimharris#define SCU_AFE_XCVR0_DFX_IR_OFFSET 0x0250 // [0:1F] 1621230557Sjimharris 1622230557Sjimharris#define SCU_AFE_XCVR1_DFX_DATA_OFFSET 0x0300 // [0:0F] 1623230557Sjimharris#define SCU_AFE_XCVR1_CC_OFFSET 0x0340 1624230557Sjimharris#define SCU_AFE_XCVR1_DFX_IR_OFFSET 0x0350 // [0:1F] 1625230557Sjimharris 1626230557Sjimharris#define SCU_AFE_XCVR2_DFX_DATA_OFFSET 0x0400 // [0:0F] 1627230557Sjimharris#define SCU_AFE_XCVR2_CC_OFFSET 0x0440 1628230557Sjimharris#define SCU_AFE_XCVR2_DFX_IR_OFFSET 0x0450 // [0:1F] 1629230557Sjimharris 1630230557Sjimharris#define SCU_AFE_XCVR3_DFX_DATA_OFFSET 0x0500 // [0:0F] 1631230557Sjimharris#define SCU_AFE_XCVR3_CC_OFFSET 0x0540 1632230557Sjimharris#define SCU_AFE_XCVR3_DFX_IR_OFFSET 0x0550 // [0:1F] 1633230557Sjimharris#else // defined(ARLINGTON_BUILD) 1634230557Sjimharris 1635230557Sjimharris#endif // defined(ARLINGTON_BUILD) 1636230557Sjimharris 1637230557Sjimharris/** 1638230557Sjimharris * @struct SCU_AFE_TRANSCEIVER 1639230557Sjimharris * 1640230557Sjimharris * @brief AFE Transceiver Registers 1641230557Sjimharris * See SCU AFE Specification for use of these registers. 1642230557Sjimharris * 1643230557Sjimharris * @note For ARLINGTON_BUILD see the SCU AFE specification. 1644230557Sjimharris * @note For PLEASANT_RIDGE_BUILD build see the Uaoa AFE specification. 1645230557Sjimharris */ 1646230557Sjimharris#if defined(ARLINGTON_BUILD) 1647230557Sjimharris struct SCU_AFE_TRANSCEIVER 1648230557Sjimharris { 1649230557Sjimharris // 0x00 1650230557Sjimharris U32 afe_transceiver_dfx_data[0x10]; 1651230557Sjimharris // 0x40 1652230557Sjimharris U32 afe_transceiver_dpg_cycle_control; 1653230557Sjimharris // 0x44 - 0x4c 1654230557Sjimharris U32 reserved_0044_004c[3]; 1655230557Sjimharris // 0x50 1656230557Sjimharris U32 afe_transceiver_dfx_instruction[0x20]; 1657230557Sjimharris // 0xd0 - 0xfc 1658230557Sjimharris U32 reserved_00d0_00fc[0x0C]; 1659230557Sjimharris }; 1660230557Sjimharris 1661230557Sjimharris#elif defined(PLEASANT_RIDGE_BUILD) \ 1662230557Sjimharris || defined(PBG_HBA_A0_BUILD) \ 1663230557Sjimharris || defined(PBG_HBA_A2_BUILD) \ 1664230557Sjimharris || defined(PBG_HBA_BETA_BUILD) \ 1665230557Sjimharris || defined(PBG_BUILD) 1666230557Sjimharris 1667230557Sjimharris // AFE 0 is at offset 0x0800 1668230557Sjimharris // AFE 1 is at offset 0x0900 1669230557Sjimharris // AFE 2 is at offset 0x0a00 1670230557Sjimharris // AFE 3 is at offset 0x0b00 1671230557Sjimharris struct SCU_AFE_TRANSCEIVER 1672230557Sjimharris { 1673230557Sjimharris // 0x0000 AFE_XCVR_CTRL0 1674230557Sjimharris U32 afe_xcvr_control0; 1675230557Sjimharris // 0x0004 AFE_XCVR_CTRL1 1676230557Sjimharris U32 afe_xcvr_control1; 1677230557Sjimharris // 0x0008 1678230557Sjimharris U32 reserved_0008; 1679230557Sjimharris // 0x000c afe_dfx_rx_control0 1680230557Sjimharris U32 afe_dfx_rx_control0; 1681230557Sjimharris // 0x0010 AFE_DFX_RX_CTRL1 1682230557Sjimharris U32 afe_dfx_rx_control1; 1683230557Sjimharris // 0x0014 1684230557Sjimharris U32 reserved_0014; 1685230557Sjimharris // 0x0018 AFE_DFX_RX_STS0 1686230557Sjimharris U32 afe_dfx_rx_status0; 1687230557Sjimharris // 0x001c AFE_DFX_RX_STS1 1688230557Sjimharris U32 afe_dfx_rx_status1; 1689230557Sjimharris // 0x0020 1690230557Sjimharris U32 reserved_0020; 1691230557Sjimharris // 0x0024 AFE_TX_CTRL 1692230557Sjimharris U32 afe_tx_control; 1693230557Sjimharris // 0x0028 AFE_TX_AMP_CTRL0 1694230557Sjimharris U32 afe_tx_amp_control0; 1695230557Sjimharris // 0x002c AFE_TX_AMP_CTRL1 1696230557Sjimharris U32 afe_tx_amp_control1; 1697230557Sjimharris // 0x0030 AFE_TX_AMP_CTRL2 1698230557Sjimharris U32 afe_tx_amp_control2; 1699230557Sjimharris // 0x0034 AFE_TX_AMP_CTRL3 1700230557Sjimharris U32 afe_tx_amp_control3; 1701230557Sjimharris // 0x0038 afe_tx_ssc_control 1702230557Sjimharris U32 afe_tx_ssc_control; 1703230557Sjimharris // 0x003c 1704230557Sjimharris U32 reserved_003c; 1705230557Sjimharris // 0x0040 AFE_RX_SSC_CTRL0 1706230557Sjimharris U32 afe_rx_ssc_control0; 1707230557Sjimharris // 0x0044 AFE_RX_SSC_CTRL1 1708230557Sjimharris U32 afe_rx_ssc_control1; 1709230557Sjimharris // 0x0048 AFE_RX_SSC_CTRL2 1710230557Sjimharris U32 afe_rx_ssc_control2; 1711230557Sjimharris // 0x004c AFE_RX_EQ_STS0 1712230557Sjimharris U32 afe_rx_eq_status0; 1713230557Sjimharris // 0x0050 AFE_RX_EQ_STS1 1714230557Sjimharris U32 afe_rx_eq_status1; 1715230557Sjimharris // 0x0054 AFE_RX_CDR_STS 1716230557Sjimharris U32 afe_rx_cdr_status; 1717230557Sjimharris // 0x0058 1718230557Sjimharris U32 reserved_0058; 1719230557Sjimharris // 0x005c AFE_CHAN_CTRL 1720230557Sjimharris U32 afe_channel_control; 1721230557Sjimharris // 0x0060-0x006c 1722230557Sjimharris U32 reserved_0060_006c[0x04]; 1723230557Sjimharris // 0x0070 AFE_XCVR_EC_STS0 1724230557Sjimharris U32 afe_xcvr_error_capture_status0; 1725230557Sjimharris // 0x0074 AFE_XCVR_EC_STS1 1726230557Sjimharris U32 afe_xcvr_error_capture_status1; 1727230557Sjimharris // 0x0078 AFE_XCVR_EC_STS2 1728230557Sjimharris U32 afe_xcvr_error_capture_status2; 1729230557Sjimharris // 0x007c afe_xcvr_ec_status3 1730230557Sjimharris U32 afe_xcvr_error_capture_status3; 1731230557Sjimharris // 0x0080 AFE_XCVR_EC_STS4 1732230557Sjimharris U32 afe_xcvr_error_capture_status4; 1733230557Sjimharris // 0x0084 AFE_XCVR_EC_STS5 1734230557Sjimharris U32 afe_xcvr_error_capture_status5; 1735230557Sjimharris // 0x0088-0x00fc 1736230557Sjimharris U32 reserved_008c_00fc[0x1e]; 1737230557Sjimharris }; 1738230557Sjimharris#else // !defined(PLEASANT_RIDGE_BUILD) && !defined(ARLINGTON_BUILD) 1739230557Sjimharris #error "Target platform not defined." 1740230557Sjimharris#endif // defined(PLEASANT_RIDGE_BUILD) || defined(ARLINGTON_BUILD) 1741230557Sjimharris 1742230557Sjimharris/** 1743230557Sjimharris * @struct SCU_AFE_REGISTERS 1744230557Sjimharris * 1745230557Sjimharris * @brief AFE Regsiters 1746230557Sjimharris * See SCU AFE Specification for use of these registers. 1747230557Sjimharris */ 1748230557Sjimharris#if defined(ARLINGTON_BUILD) 1749230557Sjimharris typedef struct SCU_AFE_REGISTERS 1750230557Sjimharris { 1751230557Sjimharris // 0x0000 1752230557Sjimharris U32 afe_pll_control; 1753230557Sjimharris // 0x0004 1754230557Sjimharris U32 afe_phase_interplator_control; 1755230557Sjimharris // 0x0008 1756230557Sjimharris U32 reservd_0008; 1757230557Sjimharris // 0x000C 1758230557Sjimharris U32 afe_bias_control[2]; 1759230557Sjimharris // 0x0014 - 0x001c 1760230557Sjimharris U32 reserved_0014_001c[3]; 1761230557Sjimharris // 0x0020 1762230557Sjimharris U32 afe_common_status; 1763230557Sjimharris // 0x0024 1764230557Sjimharris U32 afe_phase_interpolator_status; 1765230557Sjimharris // 0x0028 - 0x003C 1766230557Sjimharris U32 reserved_0028_003c[6]; 1767230557Sjimharris // 0x0040 1768230557Sjimharris U32 afe_transceiver_control0[4]; 1769230557Sjimharris // 0x0050 1770230557Sjimharris U32 afe_transceiver_control1[4]; 1771230557Sjimharris // 0x0060 1772230557Sjimharris U32 afe_transceiver_equalization_control[4]; 1773230557Sjimharris // 0x0070 - 0x007c 1774230557Sjimharris U32 reserved_0070_007c[4]; 1775230557Sjimharris // 0x0080 1776230557Sjimharris U32 afe_transceiver_cdr_status[4]; 1777230557Sjimharris // 0x0090 1778230557Sjimharris U32 afe_transceiver_rx_equaliation_status_register0[4]; 1779230557Sjimharris // 0x00A0 1780230557Sjimharris U32 afe_transceiver_rx_equaliation_status_register1[4]; 1781230557Sjimharris // 0x00B0 - 0x0100 1782230557Sjimharris U32 reserved_00b0_0100[0x15]; 1783230557Sjimharris // 0x0104 1784230557Sjimharris U32 afe_dfx_master_control; 1785230557Sjimharris // 0x0108 1786230557Sjimharris U32 reserved_0108; 1787230557Sjimharris // 0x010c 1788230557Sjimharris U32 afe_no_touch_leakage_control; 1789230557Sjimharris // 0x0110 - 0x011C 1790230557Sjimharris U32 reserved_0110_011c[4]; 1791230557Sjimharris // 0x0120 1792230557Sjimharris U32 afe_dfx_transceiver_status_clear; 1793230557Sjimharris // 0x0124 1794230557Sjimharris U32 afe_no_touch_leakage_status; 1795230557Sjimharris // 0x0128 - 0x012c 1796230557Sjimharris U32 reserved_0128_012c[2]; 1797230557Sjimharris // 0x0130 1798230557Sjimharris U32 afe_dfx_transceiver_status_register0[4]; 1799230557Sjimharris // 0x0140 1800230557Sjimharris U32 afe_dfx_transceiver_status_register1[4]; 1801230557Sjimharris // 0x0150 1802230557Sjimharris U32 afe_dfx_transmit_monitor_control; 1803230557Sjimharris // 0x0154 - 0x017c 1804230557Sjimharris U32 reserved_0154_017C[0x0B]; 1805230557Sjimharris // 0x0180 1806230557Sjimharris U32 afe_dfx_receive_control_register0[4]; 1807230557Sjimharris // 0x0190 1808230557Sjimharris U32 afe_dfx_receive_control_register1[4]; 1809230557Sjimharris // 0x1A0 1810230557Sjimharris U32 afe_dfx_transmit_control_register[4]; 1811230557Sjimharris // 0x01B0 - 0x01BC 1812230557Sjimharris U32 reserved_01b0_01bc[4]; 1813230557Sjimharris // 0x01C0 1814230557Sjimharris U32 afe_pll_dfx_control; 1815230557Sjimharris // 0x01c4 - 0x01fc 1816230557Sjimharris U32 reserved_01c4_01fc[0x0F]; 1817230557Sjimharris // 0x0200 - 0x05fc 1818230557Sjimharris struct SCU_AFE_TRANSCEIVER afe_transceiver[4]; 1819230557Sjimharris 1820230557Sjimharris // 0x0600 - 0x06FC 1821230557Sjimharris U32 reserved_0600_06FC[0x40]; 1822230557Sjimharris 1823230557Sjimharris // 0x0700 1824230557Sjimharris struct SCU_AFE_TRANSCEIVER afe_all_transceiver; 1825230557Sjimharris 1826230557Sjimharris U32 reserved_0800_2000[0x600]; 1827230557Sjimharris 1828230557Sjimharris } SCU_AFE_REGISTERS_T; 1829230557Sjimharris 1830230557Sjimharris#elif defined(PLEASANT_RIDGE_BUILD) \ 1831230557Sjimharris || defined(PBG_HBA_A0_BUILD) \ 1832230557Sjimharris || defined(PBG_HBA_A2_BUILD) \ 1833230557Sjimharris || defined(PBG_HBA_BETA_BUILD) \ 1834230557Sjimharris || defined(PBG_BUILD) 1835230557Sjimharris 1836230557Sjimharris /* Uaoa AFE registers */ 1837230557Sjimharris typedef struct SCU_AFE_REGISTERS 1838230557Sjimharris { 1839230557Sjimharris // 0Xe000 AFE_BIAS_CTRL 1840230557Sjimharris U32 afe_bias_control; 1841230557Sjimharris U32 reserved_0004; 1842230557Sjimharris // 0x0008 AFE_PLL_CTRL0 1843230557Sjimharris U32 afe_pll_control0; 1844230557Sjimharris // 0x000c AFE_PLL_CTRL1 1845230557Sjimharris U32 afe_pll_control1; 1846230557Sjimharris // 0x0010 AFE_PLL_CTRL2 1847230557Sjimharris U32 afe_pll_control2; 1848230557Sjimharris // 0x0014 AFE_CB_STS 1849230557Sjimharris U32 afe_common_block_status; 1850230557Sjimharris // 0x0018-0x007c 1851230557Sjimharris U32 reserved_18_7c[0x1a]; 1852230557Sjimharris // 0x0080 AFE_PMSN_MCTRL0 1853230557Sjimharris U32 afe_pmsn_master_control0; 1854230557Sjimharris // 0x0084 AFE_PMSN_MCTRL1 1855230557Sjimharris U32 afe_pmsn_master_control1; 1856230557Sjimharris // 0x0088 AFE_PMSN_MCTRL2 1857230557Sjimharris U32 afe_pmsn_master_control2; 1858230557Sjimharris // 0x008C-0x00fc 1859230557Sjimharris U32 reserved_008c_00fc[0x1D]; 1860230557Sjimharris // 0x0100 AFE_DFX_MST_CTRL0 1861230557Sjimharris U32 afe_dfx_master_control0; 1862230557Sjimharris // 0x0104 AFE_DFX_MST_CTRL1 1863230557Sjimharris U32 afe_dfx_master_control1; 1864230557Sjimharris // 0x0108 AFE_DFX_DCL_CTRL 1865230557Sjimharris U32 afe_dfx_dcl_control; 1866230557Sjimharris // 0x010c AFE_DFX_DMON_CTRL 1867230557Sjimharris U32 afe_dfx_digital_monitor_control; 1868230557Sjimharris // 0x0110 AFE_DFX_AMONP_CTRL 1869230557Sjimharris U32 afe_dfx_analog_p_monitor_control; 1870230557Sjimharris // 0x0114 AFE_DFX_AMONN_CTRL 1871230557Sjimharris U32 afe_dfx_analog_n_monitor_control; 1872230557Sjimharris // 0x0118 AFE_DFX_NTL_STS 1873230557Sjimharris U32 afe_dfx_ntl_status; 1874230557Sjimharris // 0x011c AFE_DFX_FIFO_STS0 1875230557Sjimharris U32 afe_dfx_fifo_status0; 1876230557Sjimharris // 0x0120 AFE_DFX_FIFO_STS1 1877230557Sjimharris U32 afe_dfx_fifo_status1; 1878230557Sjimharris // 0x0124 AFE_DFX_MPAT_CTRL 1879230557Sjimharris U32 afe_dfx_master_pattern_control; 1880230557Sjimharris // 0x0128 AFE_DFX_P0_CTRL 1881230557Sjimharris U32 afe_dfx_p0_control; 1882230557Sjimharris // 0x012c-0x01a8 AFE_DFX_P0_DRx 1883230557Sjimharris U32 afe_dfx_p0_data[32]; 1884230557Sjimharris // 0x01ac 1885230557Sjimharris U32 reserved_01ac; 1886230557Sjimharris // 0x01b0-0x020c AFE_DFX_P0_IRx 1887230557Sjimharris U32 afe_dfx_p0_instruction[24]; 1888230557Sjimharris // 0x0210 1889230557Sjimharris U32 reserved_0210; 1890230557Sjimharris // 0x0214 AFE_DFX_P1_CTRL 1891230557Sjimharris U32 afe_dfx_p1_control; 1892230557Sjimharris // 0x0218-0x245 AFE_DFX_P1_DRx 1893230557Sjimharris U32 afe_dfx_p1_data[16]; 1894230557Sjimharris // 0x0258-0x029c 1895230557Sjimharris U32 reserved_0258_029c[0x12]; 1896230557Sjimharris // 0x02a0-0x02bc AFE_DFX_P1_IRx 1897230557Sjimharris U32 afe_dfx_p1_instruction[8]; 1898230557Sjimharris // 0x02c0-0x2fc 1899230557Sjimharris U32 reserved_02c0_02fc[0x10]; 1900230557Sjimharris // 0x0300 AFE_DFX_TX_PMSN_CTRL 1901230557Sjimharris U32 afe_dfx_tx_pmsn_control; 1902230557Sjimharris // 0x0304 AFE_DFX_RX_PMSN_CTRL 1903230557Sjimharris U32 afe_dfx_rx_pmsn_control; 1904230557Sjimharris U32 reserved_0308; 1905230557Sjimharris // 0x030c AFE_DFX_NOA_CTRL0 1906230557Sjimharris U32 afe_dfx_noa_control0; 1907230557Sjimharris // 0x0310 AFE_DFX_NOA_CTRL1 1908230557Sjimharris U32 afe_dfx_noa_control1; 1909230557Sjimharris // 0x0314 AFE_DFX_NOA_CTRL2 1910230557Sjimharris U32 afe_dfx_noa_control2; 1911230557Sjimharris // 0x0318 AFE_DFX_NOA_CTRL3 1912230557Sjimharris U32 afe_dfx_noa_control3; 1913230557Sjimharris // 0x031c AFE_DFX_NOA_CTRL4 1914230557Sjimharris U32 afe_dfx_noa_control4; 1915230557Sjimharris // 0x0320 AFE_DFX_NOA_CTRL5 1916230557Sjimharris U32 afe_dfx_noa_control5; 1917230557Sjimharris // 0x0324 AFE_DFX_NOA_CTRL6 1918230557Sjimharris U32 afe_dfx_noa_control6; 1919230557Sjimharris // 0x0328 AFE_DFX_NOA_CTRL7 1920230557Sjimharris U32 afe_dfx_noa_control7; 1921230557Sjimharris // 0x032c-0x07fc 1922230557Sjimharris U32 reserved_032c_07fc[0x135]; 1923230557Sjimharris 1924230557Sjimharris // 0x0800-0x0bfc 1925230557Sjimharris struct SCU_AFE_TRANSCEIVER scu_afe_xcvr[4]; 1926230557Sjimharris 1927230557Sjimharris // 0x0c00-0x0ffc 1928230557Sjimharris U32 reserved_0c00_0ffc[0x0100]; 1929230557Sjimharris } SCU_AFE_REGISTERS_T; 1930230557Sjimharris#else // !defined(PBG_HBA_BUILD) && defined(PLEASANT_RIDGE_BUILD) && !defined(ARLINGTON_BUILD) 1931230557Sjimharris #error "Target platform not defined." 1932230557Sjimharris#endif // defined(PBG_HBA_BUILD) || defined(PLEASANT_RIDGE_BUILD) || defined(ARLINGTON_BUILD) 1933230557Sjimharris 1934230557Sjimharris 1935230557Sjimharrisstruct SCU_PROTOCOL_ENGINE_GROUP_REGISTERS 1936230557Sjimharris{ 1937230557Sjimharris U32 table[0xE0]; 1938230557Sjimharris}; 1939230557Sjimharris 1940230557Sjimharris 1941230557Sjimharrisstruct SCU_VIIT_IIT 1942230557Sjimharris{ 1943230557Sjimharris U32 table[256]; 1944230557Sjimharris}; 1945230557Sjimharris 1946230557Sjimharris/** 1947230557Sjimharris * @brief Placeholder for the ZONE Partition Table information 1948230557Sjimharris * ZONING will not be included in the 1.1 release. 1949230557Sjimharris * 1950230557Sjimharris */ 1951230557Sjimharrisstruct SCU_ZONE_PARTITION_TABLE 1952230557Sjimharris{ 1953230557Sjimharris U32 table[2048]; 1954230557Sjimharris}; 1955230557Sjimharris 1956230557Sjimharris/** 1957230557Sjimharris * @brief CRAM register. MMR base address for CRAMC is 0x6400 1958230557Sjimharris * relative to SCUBAR. 1959230557Sjimharris * 1960230557Sjimharris */ 1961230557Sjimharrisstruct SCU_COMPLETION_RAM 1962230557Sjimharris{ 1963230557Sjimharris U32 sram_base_address_0; //0x0000 1964230557Sjimharris U32 sram_upper_base_address_0; //0x0004 1965230557Sjimharris U32 sram_ecc_control_0; //0x0008 1966230557Sjimharris U32 sram_ecc_log_0; //0x000c 1967230557Sjimharris U32 sram_ecc_addrress_0; //0x0010 1968230557Sjimharris U32 sram_ecc_context_address_0; //0x0014 1969230557Sjimharris U32 sram_ecc_test_0; //0x0018 1970230557Sjimharris U32 sram_parity_control_and_status_0; //0x001C 1971230557Sjimharris U32 sram_parity_address_0; //0x0020 1972230557Sjimharris U32 sram_parity_upper_address_0; //0x0024 1973230557Sjimharris U32 sram_parity_context_0; //0x0028 1974230557Sjimharris U32 sram_memory_controller_interrupt_status_0; //0x002C 1975230557Sjimharris U32 sram_mcu_read_arbiter_control_0; //0x0030 1976230557Sjimharris U32 sram_mcu_write_arbiter_control_0; //0x0034 1977230557Sjimharris U32 smcu_error_event_counter_0_0; //0x0038 1978230557Sjimharris 1979230557Sjimharris //Remainder CRAM register space 1980230557Sjimharris U32 reserved_003C_0200[113]; 1981230557Sjimharris}; 1982230557Sjimharris 1983230557Sjimharris/** 1984230557Sjimharris * @brief FBRAM registers. MMR base address for FBRAM is 1985230557Sjimharris * 0x6600 relative to SCUBAR. 1986230557Sjimharris */ 1987230557Sjimharrisstruct SCU_FRAME_BUFFER_RAM 1988230557Sjimharris{ 1989230557Sjimharris U32 sram_base_address_1; //0x0000 1990230557Sjimharris U32 sram_upper_base_address_1; //0x0004 1991230557Sjimharris U32 sram_ecc_control_1; //0x0008 1992230557Sjimharris U32 sram_ecc_log_1; //0x000c 1993230557Sjimharris U32 sram_ecc_addrress_1; //0x0010 1994230557Sjimharris U32 sram_ecc_context_address_1; //0x0014 1995230557Sjimharris U32 sram_ecc_test_1; //0x0018 1996230557Sjimharris U32 sram_parity_control_and_status_1; //0x001C 1997230557Sjimharris U32 sram_parity_address_1; //0x0020 1998230557Sjimharris U32 sram_parity_upper_address_1; //0x0024 1999230557Sjimharris U32 sram_parity_context_1; //0x0028 2000230557Sjimharris U32 sram_memory_controller_interrupt_status_1; //0x002C 2001230557Sjimharris U32 sram_mcu_read_arbiter_control_1; //0x0030 2002230557Sjimharris U32 sram_mcu_write_arbiter_control_1; //0x0034 2003230557Sjimharris U32 smcu_error_event_counter_0_1; //0x0038 2004230557Sjimharris 2005230557Sjimharris //Remainder of FBRAM register space 2006230557Sjimharris U32 reserved_003C_0200[113]; 2007230557Sjimharris}; 2008230557Sjimharris 2009230557Sjimharris#define SCU_SCRATCH_RAM_SIZE_IN_DWORDS 256 2010230557Sjimharris 2011230557Sjimharris/** 2012230557Sjimharris* @brief Placeholder for the scratch RAM registers. 2013230557Sjimharris* 2014230557Sjimharris*/ 2015230557Sjimharrisstruct SCU_SCRATCH_RAM 2016230557Sjimharris{ 2017230557Sjimharris U32 ram[SCU_SCRATCH_RAM_SIZE_IN_DWORDS]; 2018230557Sjimharris}; 2019230557Sjimharris 2020230557Sjimharris/** 2021230557Sjimharris * @brief Placeholder since I am not yet sure what these registers are here 2022230557Sjimharris * for. 2023230557Sjimharris * 2024230557Sjimharris */ 2025230557Sjimharrisstruct NOA_PROTOCOL_ENGINE_PARTITION 2026230557Sjimharris{ 2027230557Sjimharris U32 reserved[64]; 2028230557Sjimharris}; 2029230557Sjimharris 2030230557Sjimharris/** 2031230557Sjimharris * @brief Placeholder since I am not yet sure what these registers are here 2032230557Sjimharris * for. 2033230557Sjimharris * 2034230557Sjimharris */ 2035230557Sjimharrisstruct NOA_HUB_PARTITION 2036230557Sjimharris{ 2037230557Sjimharris U32 reserved[64]; 2038230557Sjimharris}; 2039230557Sjimharris 2040230557Sjimharris/** 2041230557Sjimharris * @brief Placeholder since I am not yet sure what these registers are here 2042230557Sjimharris * for. 2043230557Sjimharris * 2044230557Sjimharris */ 2045230557Sjimharrisstruct NOA_HOST_INTERFACE_PARTITION 2046230557Sjimharris{ 2047230557Sjimharris U32 reserved[64]; 2048230557Sjimharris}; 2049230557Sjimharris 2050230557Sjimharris/** 2051230557Sjimharris * @struct TRANSPORT_LINK_LAYER_PAIR 2052230557Sjimharris * 2053230557Sjimharris * @brief The SCU Hardware pairs up the TL registers with the LL registers 2054230557Sjimharris * so we must place them adjcent to make the array of registers in 2055230557Sjimharris * the PEG. 2056230557Sjimharris * 2057230557Sjimharris */ 2058230557Sjimharrisstruct TRANSPORT_LINK_LAYER_PAIR 2059230557Sjimharris{ 2060230557Sjimharris struct SCU_TRANSPORT_LAYER_REGISTERS tl; 2061230557Sjimharris struct SCU_LINK_LAYER_REGISTERS ll; 2062230557Sjimharris}; 2063230557Sjimharris 2064230557Sjimharris/** 2065230557Sjimharris * @struct SCU_PEG_REGISTERS 2066230557Sjimharris * 2067230557Sjimharris * @brief SCU Protocol Engine Memory mapped register space. These 2068230557Sjimharris * registers are unique to each protocol engine group. There can be 2069230557Sjimharris * at most two PEG for a single SCU part. 2070230557Sjimharris * 2071230557Sjimharris */ 2072230557Sjimharrisstruct SCU_PEG_REGISTERS 2073230557Sjimharris{ 2074230557Sjimharris struct TRANSPORT_LINK_LAYER_PAIR pe[4]; 2075230557Sjimharris struct SCU_PORT_TASK_SCHEDULER_GROUP_REGISTERS ptsg; 2076230557Sjimharris struct SCU_PROTOCOL_ENGINE_GROUP_REGISTERS peg; 2077230557Sjimharris struct SCU_SGPIO_REGISTERS sgpio; 2078230557Sjimharris U32 reserved_01500_1BFF[0x1C0]; 2079230557Sjimharris struct SCU_VIIT_ENTRY viit[64]; 2080230557Sjimharris struct SCU_ZONE_PARTITION_TABLE zpt0; 2081230557Sjimharris struct SCU_ZONE_PARTITION_TABLE zpt1; 2082230557Sjimharris}; 2083230557Sjimharris 2084230557Sjimharris/** 2085230557Sjimharris * @struct SCU_REGISTERS 2086230557Sjimharris * 2087230557Sjimharris * @brief SCU regsiters including both PEG registers if we turn on that 2088230557Sjimharris * compile option. 2089230557Sjimharris * All of these registers are in the memory mapped space returned 2090230557Sjimharris * from BAR1. 2091230557Sjimharris * See SCU SMU Specification for how these registers are mapped. 2092230557Sjimharris * 2093230557Sjimharris */ 2094230557Sjimharristypedef struct SCU_REGISTERS 2095230557Sjimharris{ 2096230557Sjimharris // 0x0000 - PEG 0 2097230557Sjimharris struct SCU_PEG_REGISTERS peg0; 2098230557Sjimharris 2099230557Sjimharris // 0x6000 - SDMA and Miscellaneous 2100230557Sjimharris struct SCU_SDMA_REGISTERS sdma; 2101230557Sjimharris struct SCU_COMPLETION_RAM cram; 2102230557Sjimharris struct SCU_FRAME_BUFFER_RAM fbram; 2103230557Sjimharris U32 reserved_6800_69FF[0x80]; 2104230557Sjimharris struct NOA_PROTOCOL_ENGINE_PARTITION noa_pe; 2105230557Sjimharris struct NOA_HUB_PARTITION noa_hub; 2106230557Sjimharris struct NOA_HOST_INTERFACE_PARTITION noa_if; 2107230557Sjimharris U32 reserved_6d00_7fff[0x4c0]; 2108230557Sjimharris 2109230557Sjimharris // 0x8000 - PEG 1 2110230557Sjimharris struct SCU_PEG_REGISTERS peg1; 2111230557Sjimharris 2112230557Sjimharris // 0xE000 - AFE Registers 2113230557Sjimharris struct SCU_AFE_REGISTERS afe; 2114230557Sjimharris 2115230557Sjimharris} SCU_REGISTERS_T; 2116230557Sjimharris 2117230557Sjimharris#ifdef __cplusplus 2118230557Sjimharris} 2119230557Sjimharris#endif 2120230557Sjimharris 2121230557Sjimharris#endif // _SCU_REGISTERS_HEADER_ 2122