1230557Sjimharris/*- 2230557Sjimharris * This file is provided under a dual BSD/GPLv2 license. When using or 3230557Sjimharris * redistributing this file, you may do so under either license. 4230557Sjimharris * 5230557Sjimharris * GPL LICENSE SUMMARY 6230557Sjimharris * 7230557Sjimharris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8230557Sjimharris * 9230557Sjimharris * This program is free software; you can redistribute it and/or modify 10230557Sjimharris * it under the terms of version 2 of the GNU General Public License as 11230557Sjimharris * published by the Free Software Foundation. 12230557Sjimharris * 13230557Sjimharris * This program is distributed in the hope that it will be useful, but 14230557Sjimharris * WITHOUT ANY WARRANTY; without even the implied warranty of 15230557Sjimharris * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16230557Sjimharris * General Public License for more details. 17230557Sjimharris * 18230557Sjimharris * You should have received a copy of the GNU General Public License 19230557Sjimharris * along with this program; if not, write to the Free Software 20230557Sjimharris * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21230557Sjimharris * The full GNU General Public License is included in this distribution 22230557Sjimharris * in the file called LICENSE.GPL. 23230557Sjimharris * 24230557Sjimharris * BSD LICENSE 25230557Sjimharris * 26230557Sjimharris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27230557Sjimharris * All rights reserved. 28230557Sjimharris * 29230557Sjimharris * Redistribution and use in source and binary forms, with or without 30230557Sjimharris * modification, are permitted provided that the following conditions 31230557Sjimharris * are met: 32230557Sjimharris * 33230557Sjimharris * * Redistributions of source code must retain the above copyright 34230557Sjimharris * notice, this list of conditions and the following disclaimer. 35230557Sjimharris * * Redistributions in binary form must reproduce the above copyright 36230557Sjimharris * notice, this list of conditions and the following disclaimer in 37230557Sjimharris * the documentation and/or other materials provided with the 38230557Sjimharris * distribution. 39230557Sjimharris * 40230557Sjimharris * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41230557Sjimharris * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42230557Sjimharris * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43230557Sjimharris * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44230557Sjimharris * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45230557Sjimharris * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46230557Sjimharris * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47230557Sjimharris * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48230557Sjimharris * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49230557Sjimharris * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50230557Sjimharris * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51230557Sjimharris * 52230557Sjimharris * $FreeBSD$ 53230557Sjimharris */ 54230557Sjimharris#ifndef _SCIC_SDS_PORT_REGISTERS_H_ 55230557Sjimharris#define _SCIC_SDS_PORT_REGISTERS_H_ 56230557Sjimharris 57230557Sjimharris/** 58230557Sjimharris * @file 59230557Sjimharris * 60230557Sjimharris * @brief This file contains a set of macros that assist in reading the SCU 61230557Sjimharris * hardware registers. 62230557Sjimharris */ 63230557Sjimharris 64230557Sjimharris#ifdef __cplusplus 65230557Sjimharrisextern "C" { 66230557Sjimharris#endif // __cplusplus 67230557Sjimharris 68230557Sjimharris/** 69230557Sjimharris * Macro to read the port task scheduler register associated with this port 70230557Sjimharris * object 71230557Sjimharris */ 72230557Sjimharris#define scu_port_task_scheduler_read(port, reg) \ 73230557Sjimharris scu_register_read( \ 74230557Sjimharris scic_sds_port_get_controller(port), \ 75230557Sjimharris (port)->port_task_scheduler_registers->reg \ 76230557Sjimharris ) 77230557Sjimharris 78230557Sjimharris/** 79230557Sjimharris * Macro to write the port task scheduler register associated with this 80230557Sjimharris * port object 81230557Sjimharris */ 82230557Sjimharris#define scu_port_task_scheduler_write(port, reg, value) \ 83230557Sjimharris scu_register_write( \ 84230557Sjimharris scic_sds_port_get_controller(port), \ 85230557Sjimharris (port)->port_task_scheduler_registers->reg, \ 86230557Sjimharris (value) \ 87230557Sjimharris ) 88230557Sjimharris 89230557Sjimharris#define scu_port_viit_register_write(port, reg, value) \ 90230557Sjimharris scu_register_write( \ 91230557Sjimharris scic_sds_port_get_controller(port), \ 92230557Sjimharris (port)->viit_registers->reg, \ 93230557Sjimharris (value) \ 94230557Sjimharris ) 95230557Sjimharris 96230557Sjimharris//**************************************************************************** 97230557Sjimharris//* Port Task Scheduler registers controlled by the port object 98230557Sjimharris//**************************************************************************** 99230557Sjimharris 100230557Sjimharris/** 101230557Sjimharris * Macro to read the port task scheduler control register 102230557Sjimharris */ 103230557Sjimharris#define SCU_PTSxCR_READ(port) \ 104230557Sjimharris scu_port_task_scheduler_read(port, control) 105230557Sjimharris 106230557Sjimharris/** 107230557Sjimharris * Macro to write the port task scheduler control regsister 108230557Sjimharris */ 109230557Sjimharris#define SCU_PTSxCR_WRITE(port, value) \ 110230557Sjimharris scu_port_task_scheduler_write(port, control, value) 111230557Sjimharris 112230557Sjimharris//**************************************************************************** 113230557Sjimharris//* Port PE Configuration registers 114230557Sjimharris//**************************************************************************** 115230557Sjimharris 116230557Sjimharris/** 117230557Sjimharris * Macro to write the PE Port Configuration Register 118230557Sjimharris */ 119230557Sjimharris#define SCU_PCSPExCR_WRITE(port, phy_id, value) \ 120230557Sjimharris scu_register_write( \ 121230557Sjimharris scic_sds_port_get_controller(port), \ 122230557Sjimharris (port)->port_pe_configuration_register[phy_id], \ 123230557Sjimharris (value) \ 124230557Sjimharris ) 125230557Sjimharris 126230557Sjimharris/** 127230557Sjimharris * Macro to read the PE Port Configuration Regsiter 128230557Sjimharris */ 129230557Sjimharris#define SCU_PCSPExCR_READ(port, phy_id) \ 130230557Sjimharris scu_register_read( \ 131230557Sjimharris scic_sds_port_get_controller(port), \ 132230557Sjimharris (port)->port_pe_configuration_register[phy_id] \ 133230557Sjimharris ) 134230557Sjimharris 135230557Sjimharris#ifdef __cplusplus 136230557Sjimharris} 137230557Sjimharris#endif // __cplusplus 138230557Sjimharris 139230557Sjimharris#endif // _SCIC_SDS_PORT_REGISTERS_H_ 140