1230557Sjimharris/*- 2230557Sjimharris * This file is provided under a dual BSD/GPLv2 license. When using or 3230557Sjimharris * redistributing this file, you may do so under either license. 4230557Sjimharris * 5230557Sjimharris * GPL LICENSE SUMMARY 6230557Sjimharris * 7230557Sjimharris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8230557Sjimharris * 9230557Sjimharris * This program is free software; you can redistribute it and/or modify 10230557Sjimharris * it under the terms of version 2 of the GNU General Public License as 11230557Sjimharris * published by the Free Software Foundation. 12230557Sjimharris * 13230557Sjimharris * This program is distributed in the hope that it will be useful, but 14230557Sjimharris * WITHOUT ANY WARRANTY; without even the implied warranty of 15230557Sjimharris * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16230557Sjimharris * General Public License for more details. 17230557Sjimharris * 18230557Sjimharris * You should have received a copy of the GNU General Public License 19230557Sjimharris * along with this program; if not, write to the Free Software 20230557Sjimharris * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21230557Sjimharris * The full GNU General Public License is included in this distribution 22230557Sjimharris * in the file called LICENSE.GPL. 23230557Sjimharris * 24230557Sjimharris * BSD LICENSE 25230557Sjimharris * 26230557Sjimharris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27230557Sjimharris * All rights reserved. 28230557Sjimharris * 29230557Sjimharris * Redistribution and use in source and binary forms, with or without 30230557Sjimharris * modification, are permitted provided that the following conditions 31230557Sjimharris * are met: 32230557Sjimharris * 33230557Sjimharris * * Redistributions of source code must retain the above copyright 34230557Sjimharris * notice, this list of conditions and the following disclaimer. 35230557Sjimharris * * Redistributions in binary form must reproduce the above copyright 36230557Sjimharris * notice, this list of conditions and the following disclaimer in 37230557Sjimharris * the documentation and/or other materials provided with the 38230557Sjimharris * distribution. 39230557Sjimharris * 40230557Sjimharris * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41230557Sjimharris * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42230557Sjimharris * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43230557Sjimharris * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44230557Sjimharris * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45230557Sjimharris * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46230557Sjimharris * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47230557Sjimharris * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48230557Sjimharris * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49230557Sjimharris * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50230557Sjimharris * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51230557Sjimharris */ 52230557Sjimharris 53230557Sjimharris#include <sys/cdefs.h> 54230557Sjimharris__FBSDID("$FreeBSD$"); 55230557Sjimharris 56230557Sjimharris/** 57230557Sjimharris * @file 58230557Sjimharris * 59230557Sjimharris * @brief This file contains the method implementations utilized in writing 60230557Sjimharris * out PCI data for the SCI core. 61230557Sjimharris */ 62230557Sjimharris 63230557Sjimharris#include <dev/isci/scil/scic_user_callback.h> 64230557Sjimharris 65230557Sjimharris#include <dev/isci/scil/scic_sds_pci.h> 66230557Sjimharris#include <dev/isci/scil/scic_sds_controller.h> 67230557Sjimharris 68230557Sjimharris/** 69230557Sjimharris * @brief This method reads from the driver the BARs that are needed to 70230557Sjimharris * determine the virtual memory space for the controller registers 71230557Sjimharris * 72230557Sjimharris * @param[in] this_controller The controller for which to read the base 73230557Sjimharris * address registers. 74230557Sjimharris */ 75230557Sjimharrisvoid scic_sds_pci_bar_initialization( 76230557Sjimharris SCIC_SDS_CONTROLLER_T* this_controller 77230557Sjimharris) 78230557Sjimharris{ 79230557Sjimharris#ifdef ARLINGTON_BUILD 80230557Sjimharris 81230557Sjimharris #define ARLINGTON_LEX_BAR 0 82230557Sjimharris #define ARLINGTON_SMU_BAR 1 83230557Sjimharris #define ARLINGTON_SCU_BAR 2 84230557Sjimharris #define LEX_REGISTER_OFFSET 0x40000 85230557Sjimharris 86230557Sjimharris this_controller->lex_registers = 87230557Sjimharris ((char *)scic_cb_pci_get_bar( 88230557Sjimharris this_controller, ARLINGTON_LEX_BAR) + LEX_REGISTER_OFFSET); 89230557Sjimharris this_controller->smu_registers = 90230557Sjimharris (SMU_REGISTERS_T *)scic_cb_pci_get_bar(this_controller, ARLINGTON_SMU_BAR); 91230557Sjimharris this_controller->scu_registers = 92230557Sjimharris (SCU_REGISTERS_T *)scic_cb_pci_get_bar(this_controller, ARLINGTON_SCU_BAR); 93230557Sjimharris 94230557Sjimharris#else // !ARLINGTON_BUILD 95230557Sjimharris 96230557Sjimharris#if !defined(ENABLE_PCI_IO_SPACE_ACCESS) 97230557Sjimharris 98230557Sjimharris this_controller->smu_registers = 99230557Sjimharris (SMU_REGISTERS_T *)( 100230557Sjimharris (char *)scic_cb_pci_get_bar(this_controller, PATSBURG_SMU_BAR) 101230557Sjimharris +(0x4000 * this_controller->controller_index)); 102230557Sjimharris this_controller->scu_registers = 103230557Sjimharris (SCU_REGISTERS_T *)( 104230557Sjimharris (char *)scic_cb_pci_get_bar(this_controller, PATSBURG_SCU_BAR) 105230557Sjimharris +(0x400000 * this_controller->controller_index)); 106230557Sjimharris 107230557Sjimharris#else // !defined(ENABLE_PCI_IO_SPACE_ACCESS) 108230557Sjimharris 109230557Sjimharris if (this_controller->controller_index == 0) 110230557Sjimharris { 111230557Sjimharris this_controller->smu_registers = (SMU_REGISTERS_T *) 112230557Sjimharris scic_cb_pci_get_bar(this_controller, PATSBURG_IO_SPACE_BAR0); 113230557Sjimharris } 114230557Sjimharris else 115230557Sjimharris { 116230557Sjimharris if (this_controller->pci_revision == SCU_PBG_HBA_REV_B0) 117230557Sjimharris { 118230557Sjimharris // SCU B0 violates PCI spec for size of IO bar this is corrected 119230557Sjimharris // in subsequent version of the hardware so we can safely use the 120230557Sjimharris // else condition below. 121230557Sjimharris this_controller->smu_registers = (SMU_REGISTERS_T *) 122230557Sjimharris (scic_cb_pci_get_bar(this_controller, PATSBURG_IO_SPACE_BAR0) + 0x100); 123230557Sjimharris } 124230557Sjimharris else 125230557Sjimharris { 126230557Sjimharris this_controller->smu_registers = (SMU_REGISTERS_T *) 127230557Sjimharris scic_cb_pci_get_bar(this_controller, PATSBURG_IO_SPACE_BAR1); 128230557Sjimharris } 129230557Sjimharris } 130230557Sjimharris 131230557Sjimharris // No need to get the bar. We will be using the offset to write to 132230557Sjimharris // input/output ports via 0xA0 and 0xA4. 133230557Sjimharris this_controller->scu_registers = (SCU_REGISTERS_T *) 0; 134230557Sjimharris 135230557Sjimharris#endif // !defined(ENABLE_PCI_IO_SPACE_ACCESS) 136230557Sjimharris 137230557Sjimharris#endif // ARLINGTON_BUILD 138230557Sjimharris} 139230557Sjimharris 140230557Sjimharris#if defined(ENABLE_PCI_IO_SPACE_ACCESS) && !defined(ARLINGTON_BUILD) 141230557Sjimharris 142230557Sjimharris/** 143230557Sjimharris * @brief This method will read from PCI memory for the SMU register 144230557Sjimharris * space via IO space access. 145230557Sjimharris * 146230557Sjimharris * @param[in] controller The controller for which to read a DWORD. 147230557Sjimharris * @param[in] address This parameter depicts the address from 148230557Sjimharris * which to read. 149230557Sjimharris * 150230557Sjimharris * @return The value being returned from the PCI memory location. 151230557Sjimharris * 152230557Sjimharris * @todo This PCI memory access calls likely need to be optimized into macro? 153230557Sjimharris */ 154230557SjimharrisU32 scic_sds_pci_read_smu_dword( 155230557Sjimharris SCI_CONTROLLER_HANDLE_T controller, 156230557Sjimharris void * address 157230557Sjimharris) 158230557Sjimharris{ 159230557Sjimharris return scic_cb_pci_read_dword(controller, address); 160230557Sjimharris} 161230557Sjimharris 162230557Sjimharris/** 163230557Sjimharris * @brief This method will write to PCI memory for the SMU register 164230557Sjimharris * space via IO space access. 165230557Sjimharris * 166230557Sjimharris * @param[in] controller The controller for which to read a DWORD. 167230557Sjimharris * @param[in] address This parameter depicts the address into 168230557Sjimharris * which to write. 169230557Sjimharris * @param[out] write_value This parameter depicts the value being written 170230557Sjimharris * into the PCI memory location. 171230557Sjimharris * 172230557Sjimharris * @todo This PCI memory access calls likely need to be optimized into macro? 173230557Sjimharris */ 174230557Sjimharrisvoid scic_sds_pci_write_smu_dword( 175230557Sjimharris SCI_CONTROLLER_HANDLE_T controller, 176230557Sjimharris void * address, 177230557Sjimharris U32 write_value 178230557Sjimharris) 179230557Sjimharris{ 180230557Sjimharris scic_cb_pci_write_dword(controller, address, write_value); 181230557Sjimharris} 182230557Sjimharris 183230557Sjimharris/** 184230557Sjimharris * @brief This method will read from PCI memory for the SCU register 185230557Sjimharris * space via IO space access. 186230557Sjimharris * 187230557Sjimharris * @param[in] controller The controller for which to read a DWORD. 188230557Sjimharris * @param[in] address This parameter depicts the address from 189230557Sjimharris * which to read. 190230557Sjimharris * 191230557Sjimharris * @return The value being returned from the PCI memory location. 192230557Sjimharris * 193230557Sjimharris * @todo This PCI memory access calls likely need to be optimized into macro? 194230557Sjimharris */ 195230557SjimharrisU32 scic_sds_pci_read_scu_dword( 196230557Sjimharris SCI_CONTROLLER_HANDLE_T controller, 197230557Sjimharris void * address 198230557Sjimharris) 199230557Sjimharris{ 200230557Sjimharris SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller; 201230557Sjimharris 202230557Sjimharris scic_cb_pci_write_dword( 203230557Sjimharris controller, 204230557Sjimharris (void*) ((char *)(this_controller->smu_registers) + SCU_MMR_ADDRESS_WINDOW_OFFSET), 205230557Sjimharris (U32) address 206230557Sjimharris ); 207230557Sjimharris 208230557Sjimharris return scic_cb_pci_read_dword( 209230557Sjimharris controller, 210230557Sjimharris (void*) ((char *)(this_controller->smu_registers) + SCU_MMR_DATA_WINDOW_OFFSET) 211230557Sjimharris ); 212230557Sjimharris} 213230557Sjimharris 214230557Sjimharris/** 215230557Sjimharris * @brief This method will write to PCI memory for the SCU register 216230557Sjimharris * space via IO space access. 217230557Sjimharris * 218230557Sjimharris * @param[in] controller The controller for which to read a DWORD. 219230557Sjimharris * @param[in] address This parameter depicts the address into 220230557Sjimharris * which to write. 221230557Sjimharris * @param[out] write_value This parameter depicts the value being written 222230557Sjimharris * into the PCI memory location. 223230557Sjimharris * 224230557Sjimharris * @todo This PCI memory access calls likely need to be optimized into macro? 225230557Sjimharris */ 226230557Sjimharrisvoid scic_sds_pci_write_scu_dword( 227230557Sjimharris SCI_CONTROLLER_HANDLE_T controller, 228230557Sjimharris void * address, 229230557Sjimharris U32 write_value 230230557Sjimharris) 231230557Sjimharris{ 232230557Sjimharris SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller; 233230557Sjimharris 234230557Sjimharris scic_cb_pci_write_dword( 235230557Sjimharris controller, 236230557Sjimharris (void*) ((char *)(this_controller->smu_registers) + SCU_MMR_ADDRESS_WINDOW_OFFSET), 237230557Sjimharris (U32) address 238230557Sjimharris ); 239230557Sjimharris 240230557Sjimharris scic_cb_pci_write_dword( 241230557Sjimharris controller, 242230557Sjimharris (void*) ((char *)(this_controller->smu_registers) + SCU_MMR_DATA_WINDOW_OFFSET), 243230557Sjimharris write_value 244230557Sjimharris ); 245230557Sjimharris} 246230557Sjimharris 247230557Sjimharris#endif // defined(ENABLE_PCI_IO_SPACE_ACCESS) 248