1230557Sjimharris/*- 2230557Sjimharris * This file is provided under a dual BSD/GPLv2 license. When using or 3230557Sjimharris * redistributing this file, you may do so under either license. 4230557Sjimharris * 5230557Sjimharris * GPL LICENSE SUMMARY 6230557Sjimharris * 7230557Sjimharris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8230557Sjimharris * 9230557Sjimharris * This program is free software; you can redistribute it and/or modify 10230557Sjimharris * it under the terms of version 2 of the GNU General Public License as 11230557Sjimharris * published by the Free Software Foundation. 12230557Sjimharris * 13230557Sjimharris * This program is distributed in the hope that it will be useful, but 14230557Sjimharris * WITHOUT ANY WARRANTY; without even the implied warranty of 15230557Sjimharris * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16230557Sjimharris * General Public License for more details. 17230557Sjimharris * 18230557Sjimharris * You should have received a copy of the GNU General Public License 19230557Sjimharris * along with this program; if not, write to the Free Software 20230557Sjimharris * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21230557Sjimharris * The full GNU General Public License is included in this distribution 22230557Sjimharris * in the file called LICENSE.GPL. 23230557Sjimharris * 24230557Sjimharris * BSD LICENSE 25230557Sjimharris * 26230557Sjimharris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27230557Sjimharris * All rights reserved. 28230557Sjimharris * 29230557Sjimharris * Redistribution and use in source and binary forms, with or without 30230557Sjimharris * modification, are permitted provided that the following conditions 31230557Sjimharris * are met: 32230557Sjimharris * 33230557Sjimharris * * Redistributions of source code must retain the above copyright 34230557Sjimharris * notice, this list of conditions and the following disclaimer. 35230557Sjimharris * * Redistributions in binary form must reproduce the above copyright 36230557Sjimharris * notice, this list of conditions and the following disclaimer in 37230557Sjimharris * the documentation and/or other materials provided with the 38230557Sjimharris * distribution. 39230557Sjimharris * 40230557Sjimharris * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41230557Sjimharris * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42230557Sjimharris * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43230557Sjimharris * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44230557Sjimharris * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45230557Sjimharris * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46230557Sjimharris * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47230557Sjimharris * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48230557Sjimharris * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49230557Sjimharris * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50230557Sjimharris * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51230557Sjimharris * 52230557Sjimharris * $FreeBSD$ 53230557Sjimharris */ 54230557Sjimharris#ifndef _SCIC_SDS_CONTROLLER_REGISTERS_H_ 55230557Sjimharris#define _SCIC_SDS_CONTROLLER_REGISTERS_H_ 56230557Sjimharris 57230557Sjimharris/** 58230557Sjimharris * @file 59230557Sjimharris * 60230557Sjimharris * @brief This file contains macros used to perform the register reads/writes 61230557Sjimharris * to the SCU hardware. 62230557Sjimharris */ 63230557Sjimharris 64230557Sjimharris#ifdef __cplusplus 65230557Sjimharrisextern "C" { 66230557Sjimharris#endif // __cplusplus 67230557Sjimharris 68230557Sjimharris#include <dev/isci/scil/scu_registers.h> 69230557Sjimharris#include <dev/isci/scil/scic_sds_controller.h> 70230557Sjimharris 71230557Sjimharris/** 72230557Sjimharris * @name SMU_REGISTER_ACCESS_MACROS 73230557Sjimharris */ 74230557Sjimharris/*@{*/ 75230557Sjimharris#define scic_sds_controller_smu_register_read(controller, reg) \ 76230557Sjimharris smu_register_read( \ 77230557Sjimharris (controller), \ 78230557Sjimharris (controller)->smu_registers->reg \ 79230557Sjimharris ) 80230557Sjimharris 81230557Sjimharris#define scic_sds_controller_smu_register_write(controller, reg, value) \ 82230557Sjimharris smu_register_write( \ 83230557Sjimharris (controller), \ 84230557Sjimharris (controller)->smu_registers->reg, \ 85230557Sjimharris (value) \ 86230557Sjimharris ) 87230557Sjimharris/*@}*/ 88230557Sjimharris 89230557Sjimharris/** 90230557Sjimharris * @name AFE_REGISTER_ACCESS_MACROS 91230557Sjimharris */ 92230557Sjimharris/*@{*/ 93230557Sjimharris#define scu_afe_register_write(controller, reg, value) \ 94230557Sjimharris scu_register_write( \ 95230557Sjimharris (controller), \ 96230557Sjimharris (controller)->scu_registers->afe.reg, \ 97230557Sjimharris (value) \ 98230557Sjimharris ) 99230557Sjimharris 100230557Sjimharris#define scu_afe_register_read(controller, reg) \ 101230557Sjimharris scu_register_read( \ 102230557Sjimharris (controller), \ 103230557Sjimharris (controller)->scu_registers->afe.reg \ 104230557Sjimharris ) 105230557Sjimharris/*@}*/ 106230557Sjimharris 107230557Sjimharris/** 108230557Sjimharris * @name SGPIO_PEG0_REGISTER_ACCESS_MACROS 109230557Sjimharris */ 110230557Sjimharris/*@{*/ 111230557Sjimharris#define scu_sgpio_peg0_register_read(controller, reg) \ 112230557Sjimharris scu_register_read( \ 113230557Sjimharris (controller), \ 114230557Sjimharris (controller)->scu_registers->peg0.sgpio.reg \ 115230557Sjimharris ) 116230557Sjimharris 117230557Sjimharris#define scu_sgpio_peg0_register_write(controller, reg, value) \ 118230557Sjimharris scu_register_write( \ 119230557Sjimharris (controller), \ 120230557Sjimharris (controller)->scu_registers->peg0.sgpio.reg, \ 121230557Sjimharris (value) \ 122230557Sjimharris ) 123230557Sjimharris/*@}*/ 124230557Sjimharris 125230557Sjimharris/** 126230557Sjimharris * @name VIIT_REGISTER_ACCESS_MACROS 127230557Sjimharris */ 128230557Sjimharris/*@{*/ 129230557Sjimharris#define scu_controller_viit_register_write(controller, index, reg, value) \ 130230557Sjimharris scu_register_write( \ 131230557Sjimharris (controller), \ 132230557Sjimharris (controller)->scu_registers->peg0.viit[index].reg, \ 133230557Sjimharris value \ 134230557Sjimharris ) 135230557Sjimharris/*@}*/ 136230557Sjimharris 137230557Sjimharris/** 138230557Sjimharris * @name SCRATCH_RAM_REGISTER_ACCESS_MACROS 139230557Sjimharris */ 140230557Sjimharris/*@{*/ 141230557Sjimharris// Scratch RAM access may be needed before the scu_registers pointer 142230557Sjimharris// has been initialized. So instead, explicitly cast BAR1 to a 143230557Sjimharris// SCU_REGISTERS_T data structure. 144230557Sjimharris 145230557Sjimharris// Scratch RAM is stored in the Zoning Permission Table for OROM use. 146230557Sjimharris#define scu_controller_scratch_ram_register_write(controller, index, value) \ 147230557Sjimharris scu_register_write( \ 148230557Sjimharris (controller), \ 149230557Sjimharris ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index], \ 150230557Sjimharris value \ 151230557Sjimharris ) 152230557Sjimharris 153230557Sjimharris#define scu_controller_scratch_ram_register_read(controller, index) \ 154230557Sjimharris scu_register_read( \ 155230557Sjimharris (controller), \ 156230557Sjimharris ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index] \ 157230557Sjimharris ) 158230557Sjimharris 159230557Sjimharris#define scu_controller_scratch_ram_register_write_ext(controller, index, value) \ 160230557Sjimharris scu_register_write( \ 161230557Sjimharris (controller), \ 162230557Sjimharris ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index], \ 163230557Sjimharris value \ 164230557Sjimharris ) 165230557Sjimharris 166230557Sjimharris#define scu_controller_scratch_ram_register_read_ext(controller, index) \ 167230557Sjimharris scu_register_read( \ 168230557Sjimharris (controller), \ 169230557Sjimharris ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index] \ 170230557Sjimharris ) 171230557Sjimharris/*@}*/ 172230557Sjimharris 173230557Sjimharris 174230557Sjimharris//***************************************************************************** 175230557Sjimharris//* SMU REGISTERS 176230557Sjimharris//***************************************************************************** 177230557Sjimharris 178230557Sjimharris/** 179230557Sjimharris * @name SMU_REGISTERS 180230557Sjimharris */ 181230557Sjimharris/*@{*/ 182230557Sjimharris#define SMU_PCP_WRITE(controller, value) \ 183230557Sjimharris scic_sds_controller_smu_register_write( \ 184230557Sjimharris controller, post_context_port, value \ 185230557Sjimharris ) 186230557Sjimharris 187230557Sjimharris#define SMU_TCR_READ(controller, value) \ 188230557Sjimharris scic_sds_controller_smu_register_read( \ 189230557Sjimharris controller, task_context_range \ 190230557Sjimharris ) 191230557Sjimharris 192230557Sjimharris#define SMU_TCR_WRITE(controller, value) \ 193230557Sjimharris scic_sds_controller_smu_register_write( \ 194230557Sjimharris controller, task_context_range, value \ 195230557Sjimharris ) 196230557Sjimharris 197230557Sjimharris#define SMU_HTTBAR_WRITE(controller, address) \ 198230557Sjimharris{ \ 199230557Sjimharris scic_sds_controller_smu_register_write( \ 200230557Sjimharris controller, \ 201230557Sjimharris host_task_table_lower, \ 202230557Sjimharris sci_cb_physical_address_lower(address) \ 203230557Sjimharris );\ 204230557Sjimharris scic_sds_controller_smu_register_write( \ 205230557Sjimharris controller, \ 206230557Sjimharris host_task_table_upper, \ 207230557Sjimharris sci_cb_physical_address_upper(address) \ 208230557Sjimharris ); \ 209230557Sjimharris} 210230557Sjimharris 211230557Sjimharris#define SMU_CQBAR_WRITE(controller, address) \ 212230557Sjimharris{ \ 213230557Sjimharris scic_sds_controller_smu_register_write( \ 214230557Sjimharris controller, \ 215230557Sjimharris completion_queue_lower, \ 216230557Sjimharris sci_cb_physical_address_lower(address) \ 217230557Sjimharris ); \ 218230557Sjimharris scic_sds_controller_smu_register_write( \ 219230557Sjimharris controller, \ 220230557Sjimharris completion_queue_upper, \ 221230557Sjimharris sci_cb_physical_address_upper(address) \ 222230557Sjimharris ); \ 223230557Sjimharris} 224230557Sjimharris 225230557Sjimharris#define SMU_CQGR_WRITE(controller, value) \ 226230557Sjimharris scic_sds_controller_smu_register_write( \ 227230557Sjimharris controller, completion_queue_get, value \ 228230557Sjimharris ) 229230557Sjimharris 230230557Sjimharris#define SMU_CQGR_READ(controller, value) \ 231230557Sjimharris scic_sds_controller_smu_register_read( \ 232230557Sjimharris controller, completion_queue_get \ 233230557Sjimharris ) 234230557Sjimharris 235230557Sjimharris#define SMU_CQPR_WRITE(controller, value) \ 236230557Sjimharris scic_sds_controller_smu_register_write( \ 237230557Sjimharris controller, completion_queue_put, value \ 238230557Sjimharris ) 239230557Sjimharris 240230557Sjimharris#define SMU_RNCBAR_WRITE(controller, address) \ 241230557Sjimharris{ \ 242230557Sjimharris scic_sds_controller_smu_register_write( \ 243230557Sjimharris controller, \ 244230557Sjimharris remote_node_context_lower, \ 245230557Sjimharris sci_cb_physical_address_lower(address) \ 246230557Sjimharris ); \ 247230557Sjimharris scic_sds_controller_smu_register_write( \ 248230557Sjimharris controller, \ 249230557Sjimharris remote_node_context_upper, \ 250230557Sjimharris sci_cb_physical_address_upper(address) \ 251230557Sjimharris ); \ 252230557Sjimharris} 253230557Sjimharris 254230557Sjimharris#define SMU_AMR_READ(controller) \ 255230557Sjimharris scic_sds_controller_smu_register_read( \ 256230557Sjimharris controller, address_modifier \ 257230557Sjimharris ) 258230557Sjimharris 259230557Sjimharris#define SMU_IMR_READ(controller) \ 260230557Sjimharris scic_sds_controller_smu_register_read( \ 261230557Sjimharris controller, interrupt_mask \ 262230557Sjimharris ) 263230557Sjimharris 264230557Sjimharris#define SMU_IMR_WRITE(controller, mask) \ 265230557Sjimharris scic_sds_controller_smu_register_write( \ 266230557Sjimharris controller, interrupt_mask, mask \ 267230557Sjimharris ) 268230557Sjimharris 269230557Sjimharris#define SMU_ISR_READ(controller) \ 270230557Sjimharris scic_sds_controller_smu_register_read( \ 271230557Sjimharris controller, interrupt_status \ 272230557Sjimharris ) 273230557Sjimharris 274230557Sjimharris#define SMU_ISR_WRITE(controller, status) \ 275230557Sjimharris scic_sds_controller_smu_register_write( \ 276230557Sjimharris controller, interrupt_status, status \ 277230557Sjimharris ) 278230557Sjimharris 279230557Sjimharris#define SMU_ICC_READ(controller) \ 280230557Sjimharris scic_sds_controller_smu_register_read( \ 281230557Sjimharris controller, interrupt_coalesce_control \ 282230557Sjimharris ) 283230557Sjimharris 284230557Sjimharris#define SMU_ICC_WRITE(controller, value) \ 285230557Sjimharris scic_sds_controller_smu_register_write( \ 286230557Sjimharris controller, interrupt_coalesce_control, value \ 287230557Sjimharris ) 288230557Sjimharris 289230557Sjimharris#define SMU_CQC_WRITE(controller, value) \ 290230557Sjimharris scic_sds_controller_smu_register_write( \ 291230557Sjimharris controller, completion_queue_control, value \ 292230557Sjimharris ) 293230557Sjimharris 294230557Sjimharris#define SMU_SMUSRCR_WRITE(controller, value) \ 295230557Sjimharris scic_sds_controller_smu_register_write( \ 296230557Sjimharris controller, soft_reset_control, value \ 297230557Sjimharris ) 298230557Sjimharris 299230557Sjimharris#define SMU_TCA_WRITE(controller, index, value) \ 300230557Sjimharris scic_sds_controller_smu_register_write( \ 301230557Sjimharris controller, task_context_assignment[index], value \ 302230557Sjimharris ) 303230557Sjimharris 304230557Sjimharris#define SMU_TCA_READ(controller, index) \ 305230557Sjimharris scic_sds_controller_smu_register_read( \ 306230557Sjimharris controller, task_context_assignment[index] \ 307230557Sjimharris ) 308230557Sjimharris 309230557Sjimharris#define SMU_DCC_READ(controller) \ 310230557Sjimharris scic_sds_controller_smu_register_read( \ 311230557Sjimharris controller, device_context_capacity \ 312230557Sjimharris ) 313230557Sjimharris 314230557Sjimharris#define SMU_DFC_READ(controller) \ 315230557Sjimharris scic_sds_controller_smu_register_read( \ 316230557Sjimharris controller, device_function_capacity \ 317230557Sjimharris ) 318230557Sjimharris 319230557Sjimharris#define SMU_SMUCSR_READ(controller) \ 320230557Sjimharris scic_sds_controller_smu_register_read( \ 321230557Sjimharris controller, control_status \ 322230557Sjimharris ) 323230557Sjimharris 324230557Sjimharris#define SMU_CGUCR_READ(controller) \ 325230557Sjimharris scic_sds_controller_smu_register_read( \ 326230557Sjimharris controller, clock_gating_control \ 327230557Sjimharris ) 328230557Sjimharris 329230557Sjimharris#define SMU_CGUCR_WRITE(controller, value) \ 330230557Sjimharris scic_sds_controller_smu_register_write( \ 331230557Sjimharris controller, clock_gating_control, value \ 332230557Sjimharris ) 333230557Sjimharris 334230557Sjimharris#define SMU_CQPR_READ(controller) \ 335230557Sjimharris scic_sds_controller_smu_register_read( \ 336230557Sjimharris controller, completion_queue_put \ 337230557Sjimharris ) 338230557Sjimharris 339230557Sjimharris/*@}*/ 340230557Sjimharris 341230557Sjimharris/** 342230557Sjimharris * @name SCU_REGISTER_ACCESS_MACROS 343230557Sjimharris */ 344230557Sjimharris/*@{*/ 345230557Sjimharris#define scic_sds_controller_scu_register_read(controller, reg) \ 346230557Sjimharris scu_register_read( \ 347230557Sjimharris (controller), \ 348230557Sjimharris (controller)->scu_registers->reg \ 349230557Sjimharris ) 350230557Sjimharris 351230557Sjimharris#define scic_sds_controller_scu_register_write(controller, reg, value) \ 352230557Sjimharris scu_register_write( \ 353230557Sjimharris (controller), \ 354230557Sjimharris (controller)->scu_registers->reg, \ 355230557Sjimharris (value) \ 356230557Sjimharris ) 357230557Sjimharris/*@}*/ 358230557Sjimharris 359230557Sjimharris 360230557Sjimharris//**************************************************************************** 361230557Sjimharris//* SCU SDMA REGISTERS 362230557Sjimharris//**************************************************************************** 363230557Sjimharris 364230557Sjimharris/** 365230557Sjimharris * @name SCU_SDMA_REGISTER_ACCESS_MACROS 366230557Sjimharris */ 367230557Sjimharris/*@{*/ 368230557Sjimharris#define scu_sdma_register_read(controller, reg) \ 369230557Sjimharris scu_register_read( \ 370230557Sjimharris (controller), \ 371230557Sjimharris (controller)->scu_registers->sdma.reg \ 372230557Sjimharris ) 373230557Sjimharris 374230557Sjimharris#define scu_sdma_register_write(controller, reg, value) \ 375230557Sjimharris scu_register_write( \ 376230557Sjimharris (controller), \ 377230557Sjimharris (controller)->scu_registers->sdma.reg, \ 378230557Sjimharris (value) \ 379230557Sjimharris ) 380230557Sjimharris/*@}*/ 381230557Sjimharris 382230557Sjimharris/** 383230557Sjimharris * @name SCU_SDMA_REGISTERS 384230557Sjimharris */ 385230557Sjimharris/*@{*/ 386230557Sjimharris#define SCU_PUFATHAR_WRITE(controller, address) \ 387230557Sjimharris{ \ 388230557Sjimharris scu_sdma_register_write( \ 389230557Sjimharris controller, \ 390230557Sjimharris uf_address_table_lower, \ 391230557Sjimharris sci_cb_physical_address_lower(address) \ 392230557Sjimharris ); \ 393230557Sjimharris scu_sdma_register_write( \ 394230557Sjimharris controller, \ 395230557Sjimharris uf_address_table_upper, \ 396230557Sjimharris sci_cb_physical_address_upper(address) \ 397230557Sjimharris ); \ 398230557Sjimharris} 399230557Sjimharris 400230557Sjimharris#define SCU_UFHBAR_WRITE(controller, address) \ 401230557Sjimharris{ \ 402230557Sjimharris scu_sdma_register_write( \ 403230557Sjimharris controller, \ 404230557Sjimharris uf_header_base_address_lower, \ 405230557Sjimharris sci_cb_physical_address_lower(address) \ 406230557Sjimharris ); \ 407230557Sjimharris scu_sdma_register_write( \ 408230557Sjimharris controller, \ 409230557Sjimharris uf_header_base_address_upper, \ 410230557Sjimharris sci_cb_physical_address_upper(address) \ 411230557Sjimharris ); \ 412230557Sjimharris} 413230557Sjimharris 414230557Sjimharris#define SCU_UFQC_READ(controller) \ 415230557Sjimharris scu_sdma_register_read( \ 416230557Sjimharris controller, \ 417230557Sjimharris unsolicited_frame_queue_control \ 418230557Sjimharris ) 419230557Sjimharris 420230557Sjimharris#define SCU_UFQC_WRITE(controller, value) \ 421230557Sjimharris scu_sdma_register_write( \ 422230557Sjimharris controller, \ 423230557Sjimharris unsolicited_frame_queue_control, \ 424230557Sjimharris value \ 425230557Sjimharris ) 426230557Sjimharris 427230557Sjimharris#define SCU_UFQPP_READ(controller) \ 428230557Sjimharris scu_sdma_register_read( \ 429230557Sjimharris controller, \ 430230557Sjimharris unsolicited_frame_put_pointer \ 431230557Sjimharris ) 432230557Sjimharris 433230557Sjimharris#define SCU_UFQPP_WRITE(controller, value) \ 434230557Sjimharris scu_sdma_register_write( \ 435230557Sjimharris controller, \ 436230557Sjimharris unsolicited_frame_put_pointer, \ 437230557Sjimharris value \ 438230557Sjimharris ) 439230557Sjimharris 440230557Sjimharris#define SCU_UFQGP_WRITE(controller, value) \ 441230557Sjimharris scu_sdma_register_write( \ 442230557Sjimharris controller, \ 443230557Sjimharris unsolicited_frame_get_pointer, \ 444230557Sjimharris value \ 445230557Sjimharris ) 446230557Sjimharris 447230557Sjimharris#define SCU_PDMACR_READ(controller) \ 448230557Sjimharris scu_sdma_register_read( \ 449230557Sjimharris controller, \ 450230557Sjimharris pdma_configuration \ 451230557Sjimharris ) 452230557Sjimharris 453230557Sjimharris#define SCU_PDMACR_WRITE(controller, value) \ 454230557Sjimharris scu_sdma_register_write( \ 455230557Sjimharris controller, \ 456230557Sjimharris pdma_configuration, \ 457230557Sjimharris value \ 458230557Sjimharris ) 459230557Sjimharris 460230557Sjimharris#define SCU_CDMACR_READ(controller) \ 461230557Sjimharris scu_sdma_register_read( \ 462230557Sjimharris controller, \ 463230557Sjimharris cdma_configuration \ 464230557Sjimharris ) 465230557Sjimharris 466230557Sjimharris#define SCU_CDMACR_WRITE(controller, value) \ 467230557Sjimharris scu_sdma_register_write( \ 468230557Sjimharris controller, \ 469230557Sjimharris cdma_configuration, \ 470230557Sjimharris value \ 471230557Sjimharris ) 472230557Sjimharris/*@}*/ 473230557Sjimharris 474230557Sjimharris//***************************************************************************** 475230557Sjimharris//* SCU CRAM AND FBRAM Registers 476230557Sjimharris//***************************************************************************** 477230557Sjimharris/** 478230557Sjimharris * @name SCU_CRAM_REGISTER_ACCESS_MACROS 479230557Sjimharris */ 480230557Sjimharris/*@{*/ 481230557Sjimharris#define scu_cram_register_read(controller, reg) \ 482230557Sjimharris scu_register_read( \ 483230557Sjimharris (controller), \ 484230557Sjimharris (controller)->scu_registers->cram.reg \ 485230557Sjimharris ) 486230557Sjimharris 487230557Sjimharris#define scu_cram_register_write(controller, reg, value) \ 488230557Sjimharris scu_register_write( \ 489230557Sjimharris (controller), \ 490230557Sjimharris (controller)->scu_registers->cram.reg, \ 491230557Sjimharris (value) \ 492230557Sjimharris ) 493230557Sjimharris/*@}*/ 494230557Sjimharris 495230557Sjimharris/** 496230557Sjimharris * @name SCU_FBRAM_REGISTER_ACCESS_MACROS 497230557Sjimharris */ 498230557Sjimharris/*@{*/ 499230557Sjimharris#define scu_fbram_register_read(controller, reg) \ 500230557Sjimharris scu_register_read( \ 501230557Sjimharris (controller), \ 502230557Sjimharris (controller)->scu_registers->fbram.reg \ 503230557Sjimharris ) 504230557Sjimharris 505230557Sjimharris#define scu_fbram_register_write(controller, reg, value) \ 506230557Sjimharris scu_register_write( \ 507230557Sjimharris (controller), \ 508230557Sjimharris (controller)->scu_registers->fbram.reg, \ 509230557Sjimharris (value) \ 510230557Sjimharris ) 511230557Sjimharris/*@}*/ 512230557Sjimharris 513230557Sjimharris 514230557Sjimharris/** 515230557Sjimharris * @name SCU_CRAM_REGISTERS 516230557Sjimharris */ 517230557Sjimharris/*@{*/ 518230557Sjimharris 519230557Sjimharris// SRAM ECC CONTROL REGISTER BITS 520230557Sjimharris#define SIGNLE_BIT_ERROR_CORRECTION_ENABLE 0x00000001 521230557Sjimharris#define MULTI_BIT_ERROR_REPORTING_ENABLE 0x00000002 522230557Sjimharris#define SINGLE_BIT_ERROR_REPORTING_ENABLE 0x00000004 523230557Sjimharris 524230557Sjimharris//SRAM ECC control register (SECR0) 525230557Sjimharris#define SCU_SECR0_WRITE(controller, value) \ 526230557Sjimharris scu_cram_register_write( \ 527230557Sjimharris controller, \ 528230557Sjimharris sram_ecc_control_0, \ 529230557Sjimharris value \ 530230557Sjimharris ) 531230557Sjimharris/*@}*/ 532230557Sjimharris 533230557Sjimharris/** 534230557Sjimharris * @name SCU_FBRAM_REGISTERS 535230557Sjimharris */ 536230557Sjimharris/*@{*/ 537230557Sjimharris 538230557Sjimharris//SRAM ECC control register (SECR1) 539230557Sjimharris#define SCU_SECR1_WRITE(controller, value) \ 540230557Sjimharris scu_fbram_register_write( \ 541230557Sjimharris controller, \ 542230557Sjimharris sram_ecc_control_1, \ 543230557Sjimharris value \ 544230557Sjimharris ) 545230557Sjimharris/*@}*/ 546230557Sjimharris 547230557Sjimharris 548230557Sjimharris//***************************************************************************** 549230557Sjimharris//* SCU Port Task Scheduler Group Registers 550230557Sjimharris//***************************************************************************** 551230557Sjimharris 552230557Sjimharris/** 553230557Sjimharris * @name SCU_PTSG_REGISTER_ACCESS_MACROS 554230557Sjimharris */ 555230557Sjimharris/*@{*/ 556230557Sjimharris#define scu_ptsg_register_read(controller, reg) \ 557230557Sjimharris scu_register_read( \ 558230557Sjimharris (controller), \ 559230557Sjimharris (controller)->scu_registers->peg0.ptsg.reg \ 560230557Sjimharris ) 561230557Sjimharris 562230557Sjimharris#define scu_ptsg_register_write(controller, reg, value) \ 563230557Sjimharris scu_register_write( \ 564230557Sjimharris (controller), \ 565230557Sjimharris (controller)->scu_registers->peg0.ptsg.reg, \ 566230557Sjimharris (value) \ 567230557Sjimharris ) 568230557Sjimharris/*@}*/ 569230557Sjimharris 570230557Sjimharris/** 571230557Sjimharris * @name SCU_PTSG_REGISTERS 572230557Sjimharris */ 573230557Sjimharris/*@{*/ 574230557Sjimharris#define SCU_PTSGCR_READ(controller) \ 575230557Sjimharris scu_ptsg_register_read( \ 576230557Sjimharris (controller), \ 577230557Sjimharris control \ 578230557Sjimharris ) 579230557Sjimharris 580230557Sjimharris#define SCU_PTSGCR_WRITE(controller, value) \ 581230557Sjimharris scu_ptsg_register_write( \ 582230557Sjimharris (controller), \ 583230557Sjimharris control, \ 584230557Sjimharris value \ 585230557Sjimharris ) 586230557Sjimharris 587230557Sjimharris#define SCU_PTSGRTC_READ(controller) \ 588230557Sjimharris scu_ptsg_register_read( \ 589230557Sjimharris contoller, \ 590230557Sjimharris real_time_clock \ 591230557Sjimharris ) 592230557Sjimharris/*@}*/ 593230557Sjimharris 594230557Sjimharris#ifdef __cplusplus 595230557Sjimharris} 596230557Sjimharris#endif // __cplusplus 597230557Sjimharris 598230557Sjimharris#endif // _SCIC_SDS_CONTROLLER_REGISTERS_H_ 599