if_ipw.c revision 145247
1/* $FreeBSD: head/sys/dev/ipw/if_ipw.c 145247 2005-04-18 18:47:38Z damien $ */ 2 3/*- 4 * Copyright (c) 2004, 2005 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ipw/if_ipw.c 145247 2005-04-18 18:47:38Z damien $"); 32 33/*- 34 * Intel(R) PRO/Wireless 2100 MiniPCI driver 35 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 36 */ 37 38#include <sys/param.h> 39#include <sys/sysctl.h> 40#include <sys/sockio.h> 41#include <sys/mbuf.h> 42#include <sys/kernel.h> 43#include <sys/socket.h> 44#include <sys/systm.h> 45#include <sys/malloc.h> 46#include <sys/module.h> 47#include <sys/bus.h> 48#include <sys/endian.h> 49 50#include <machine/bus.h> 51#include <machine/resource.h> 52#include <machine/clock.h> 53#include <sys/rman.h> 54 55#include <dev/pci/pcireg.h> 56#include <dev/pci/pcivar.h> 57 58#include <net/bpf.h> 59#include <net/if.h> 60#include <net/if_arp.h> 61#include <net/ethernet.h> 62#include <net/if_dl.h> 63#include <net/if_media.h> 64#include <net/if_types.h> 65 66#include <netinet/in.h> 67#include <netinet/in_systm.h> 68#include <netinet/in_var.h> 69#include <netinet/ip.h> 70#include <netinet/if_ether.h> 71 72#include <net80211/ieee80211_var.h> 73#include <net80211/ieee80211_radiotap.h> 74 75#include <dev/ipw/if_ipwreg.h> 76#include <dev/ipw/if_ipwvar.h> 77 78#ifdef IPW_DEBUG 79#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 80#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 81int ipw_debug = 0; 82SYSCTL_INT(_debug, OID_AUTO, ipw, CTLFLAG_RW, &ipw_debug, 0, "ipw debug level"); 83#else 84#define DPRINTF(x) 85#define DPRINTFN(n, x) 86#endif 87 88MODULE_DEPEND(ipw, pci, 1, 1, 1); 89MODULE_DEPEND(ipw, wlan, 1, 1, 1); 90 91struct ipw_ident { 92 uint16_t vendor; 93 uint16_t device; 94 const char *name; 95}; 96 97static const struct ipw_ident ipw_ident_table[] = { 98 { 0x8086, 0x1043, "Intel(R) PRO/Wireless 2100 MiniPCI" }, 99 100 { 0, 0, NULL } 101}; 102 103static int ipw_dma_alloc(struct ipw_softc *); 104static void ipw_release(struct ipw_softc *); 105static int ipw_media_change(struct ifnet *); 106static void ipw_media_status(struct ifnet *, struct ifmediareq *); 107static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 108static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 109static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 110static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 111static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 112 struct ipw_soft_bd *, struct ipw_soft_buf *); 113static void ipw_rx_intr(struct ipw_softc *); 114static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 115static void ipw_tx_intr(struct ipw_softc *); 116static void ipw_intr(void *); 117static void ipw_dma_map_addr(void *, bus_dma_segment_t *, int, int); 118static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 119static int ipw_tx_start(struct ifnet *, struct mbuf *, 120 struct ieee80211_node *); 121static void ipw_start(struct ifnet *); 122static void ipw_watchdog(struct ifnet *); 123static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 124static void ipw_stop_master(struct ipw_softc *); 125static int ipw_reset(struct ipw_softc *); 126static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 127static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 128static int ipw_cache_firmware(struct ipw_softc *, void *); 129static void ipw_free_firmware(struct ipw_softc *); 130static int ipw_config(struct ipw_softc *); 131static void ipw_init(void *); 132static void ipw_stop(void *); 133#ifdef IPW_DEBUG 134static int ipw_sysctl_stats(SYSCTL_HANDLER_ARGS); 135#endif 136static int ipw_sysctl_radio(SYSCTL_HANDLER_ARGS); 137static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 138static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 139static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 140 uint32_t *); 141static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 142 bus_size_t); 143static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 144 bus_size_t); 145 146static int ipw_probe(device_t); 147static int ipw_attach(device_t); 148static int ipw_detach(device_t); 149static int ipw_shutdown(device_t); 150static int ipw_suspend(device_t); 151static int ipw_resume(device_t); 152 153static device_method_t ipw_methods[] = { 154 /* Device interface */ 155 DEVMETHOD(device_probe, ipw_probe), 156 DEVMETHOD(device_attach, ipw_attach), 157 DEVMETHOD(device_detach, ipw_detach), 158 DEVMETHOD(device_shutdown, ipw_shutdown), 159 DEVMETHOD(device_suspend, ipw_suspend), 160 DEVMETHOD(device_resume, ipw_resume), 161 162 { 0, 0 } 163}; 164 165static driver_t ipw_driver = { 166 "ipw", 167 ipw_methods, 168 sizeof (struct ipw_softc) 169}; 170 171static devclass_t ipw_devclass; 172 173DRIVER_MODULE(ipw, pci, ipw_driver, ipw_devclass, 0, 0); 174 175/* 176 * Supported rates for 802.11b mode (in 500Kbps unit). 177 */ 178static const struct ieee80211_rateset ipw_rateset_11b = 179 { 4, { 2, 4, 11, 22 } }; 180 181static __inline uint8_t 182MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 183{ 184 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 185 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 186} 187 188static __inline uint32_t 189MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 190{ 191 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 192 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 193} 194 195static int 196ipw_probe(device_t dev) 197{ 198 const struct ipw_ident *ident; 199 200 for (ident = ipw_ident_table; ident->name != NULL; ident++) { 201 if (pci_get_vendor(dev) == ident->vendor && 202 pci_get_device(dev) == ident->device) { 203 device_set_desc(dev, ident->name); 204 return 0; 205 } 206 } 207 return ENXIO; 208} 209 210/* Base Address Register */ 211#define IPW_PCI_BAR0 0x10 212 213static int 214ipw_attach(device_t dev) 215{ 216 struct ipw_softc *sc = device_get_softc(dev); 217 struct ifnet *ifp = &sc->sc_arp.ac_if; 218 struct ieee80211com *ic = &sc->sc_ic; 219 uint16_t val; 220 int error, i; 221 222 sc->sc_dev = dev; 223 224 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 225 MTX_DEF | MTX_RECURSE); 226 227 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 228 device_printf(dev, "chip is in D%d power mode " 229 "-- setting to D0\n", pci_get_powerstate(dev)); 230 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 231 } 232 233 /* enable bus-mastering */ 234 pci_enable_busmaster(dev); 235 236 sc->mem_rid = IPW_PCI_BAR0; 237 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 238 RF_ACTIVE); 239 if (sc->mem == NULL) { 240 device_printf(dev, "could not allocate memory resource\n"); 241 goto fail; 242 } 243 244 sc->sc_st = rman_get_bustag(sc->mem); 245 sc->sc_sh = rman_get_bushandle(sc->mem); 246 247 sc->irq_rid = 0; 248 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 249 RF_ACTIVE | RF_SHAREABLE); 250 if (sc->irq == NULL) { 251 device_printf(dev, "could not allocate interrupt resource\n"); 252 goto fail; 253 } 254 255 if (ipw_reset(sc) != 0) { 256 device_printf(dev, "could not reset adapter\n"); 257 goto fail; 258 } 259 260 if (ipw_dma_alloc(sc) != 0) { 261 device_printf(dev, "could not allocate DMA resources\n"); 262 goto fail; 263 } 264 265 ifp->if_softc = sc; 266 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 267 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 268 ifp->if_init = ipw_init; 269 ifp->if_ioctl = ipw_ioctl; 270 ifp->if_start = ipw_start; 271 ifp->if_watchdog = ipw_watchdog; 272 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 273 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 274 IFQ_SET_READY(&ifp->if_snd); 275 276 ic->ic_ifp = ifp; 277 ic->ic_phytype = IEEE80211_T_DS; 278 ic->ic_opmode = IEEE80211_M_STA; 279 ic->ic_state = IEEE80211_S_INIT; 280 281 /* set device capabilities */ 282 ic->ic_caps = IEEE80211_C_SHPREAMBLE | IEEE80211_C_TXPMGT | 283 IEEE80211_C_PMGT | IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 284 IEEE80211_C_WPA; 285 286 /* read MAC address from EEPROM */ 287 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 288 ic->ic_myaddr[0] = val >> 8; 289 ic->ic_myaddr[1] = val & 0xff; 290 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 291 ic->ic_myaddr[2] = val >> 8; 292 ic->ic_myaddr[3] = val & 0xff; 293 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 294 ic->ic_myaddr[4] = val >> 8; 295 ic->ic_myaddr[5] = val & 0xff; 296 297 /* set supported .11b rates */ 298 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 299 300 /* set supported .11b channels (read from EEPROM) */ 301 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 302 val = 0x7ff; /* default to channels 1-11 */ 303 val <<= 1; 304 for (i = 1; i < 16; i++) { 305 if (val & (1 << i)) { 306 ic->ic_channels[i].ic_freq = 307 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 308 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 309 } 310 } 311 312 /* check support for radio transmitter switch in EEPROM */ 313 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 314 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 315 316 ieee80211_ifattach(ic); 317 /* override state transition machine */ 318 sc->sc_newstate = ic->ic_newstate; 319 ic->ic_newstate = ipw_newstate; 320 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 321 322 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 323 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 324 325 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 326 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 327 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 328 329 sc->sc_txtap_len = sizeof sc->sc_txtapu; 330 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 331 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 332 333 /* 334 * Add a few sysctl knobs. 335 */ 336 sc->dwelltime = 100; 337 338 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 339 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "radio", 340 CTLTYPE_INT | CTLFLAG_RD, sc, 0, ipw_sysctl_radio, "I", 341 "radio transmitter switch state (0=off, 1=on)"); 342 343#ifdef IPW_DEBUG 344 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 345 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "stats", 346 CTLTYPE_OPAQUE | CTLFLAG_RD, sc, 0, ipw_sysctl_stats, "S", 347 "statistics"); 348#endif 349 350 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 351 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", 352 CTLFLAG_RW, &sc->dwelltime, 0, 353 "channel dwell time (ms) for AP/station scanning"); 354 355 /* 356 * Hook our interrupt after all initialization is complete. 357 */ 358 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 359 ipw_intr, sc, &sc->sc_ih); 360 if (error != 0) { 361 device_printf(dev, "could not set up interrupt\n"); 362 goto fail; 363 } 364 365 if (bootverbose) 366 ieee80211_announce(ic); 367 368 return 0; 369 370fail: ipw_detach(dev); 371 return ENXIO; 372} 373 374static int 375ipw_detach(device_t dev) 376{ 377 struct ipw_softc *sc = device_get_softc(dev); 378 struct ieee80211com *ic = &sc->sc_ic; 379 struct ifnet *ifp = ic->ic_ifp; 380 381 IPW_LOCK(sc); 382 383 ipw_stop(sc); 384 ipw_free_firmware(sc); 385 386 IPW_UNLOCK(sc); 387 388 bpfdetach(ifp); 389 ieee80211_ifdetach(ic); 390 391 ipw_release(sc); 392 393 if (sc->irq != NULL) { 394 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 395 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 396 } 397 398 if (sc->mem != NULL) 399 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 400 401 mtx_destroy(&sc->sc_mtx); 402 403 return 0; 404} 405 406static int 407ipw_dma_alloc(struct ipw_softc *sc) 408{ 409 struct ipw_soft_bd *sbd; 410 struct ipw_soft_hdr *shdr; 411 struct ipw_soft_buf *sbuf; 412 bus_addr_t physaddr; 413 int error, i; 414 415 /* 416 * Allocate and map tx ring. 417 */ 418 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 419 BUS_SPACE_MAXADDR, NULL, NULL, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, NULL, 420 NULL, &sc->tbd_dmat); 421 if (error != 0) { 422 device_printf(sc->sc_dev, "could not create tx ring DMA tag\n"); 423 goto fail; 424 } 425 426 error = bus_dmamem_alloc(sc->tbd_dmat, (void **)&sc->tbd_list, 427 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tbd_map); 428 if (error != 0) { 429 device_printf(sc->sc_dev, 430 "could not allocate tx ring DMA memory\n"); 431 goto fail; 432 } 433 434 error = bus_dmamap_load(sc->tbd_dmat, sc->tbd_map, sc->tbd_list, 435 IPW_TBD_SZ, ipw_dma_map_addr, &sc->tbd_phys, 0); 436 if (error != 0) { 437 device_printf(sc->sc_dev, "could not map tx ring DMA memory\n"); 438 goto fail; 439 } 440 441 /* 442 * Allocate and map rx ring. 443 */ 444 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 445 BUS_SPACE_MAXADDR, NULL, NULL, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, NULL, 446 NULL, &sc->rbd_dmat); 447 if (error != 0) { 448 device_printf(sc->sc_dev, "could not create rx ring DMA tag\n"); 449 goto fail; 450 } 451 452 error = bus_dmamem_alloc(sc->rbd_dmat, (void **)&sc->rbd_list, 453 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rbd_map); 454 if (error != 0) { 455 device_printf(sc->sc_dev, 456 "could not allocate rx ring DMA memory\n"); 457 goto fail; 458 } 459 460 error = bus_dmamap_load(sc->rbd_dmat, sc->rbd_map, sc->rbd_list, 461 IPW_RBD_SZ, ipw_dma_map_addr, &sc->rbd_phys, 0); 462 if (error != 0) { 463 device_printf(sc->sc_dev, "could not map rx ring DMA memory\n"); 464 goto fail; 465 } 466 467 /* 468 * Allocate and map status ring. 469 */ 470 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 471 BUS_SPACE_MAXADDR, NULL, NULL, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 0, 472 NULL, NULL, &sc->status_dmat); 473 if (error != 0) { 474 device_printf(sc->sc_dev, 475 "could not create status ring DMA tag\n"); 476 goto fail; 477 } 478 479 error = bus_dmamem_alloc(sc->status_dmat, (void **)&sc->status_list, 480 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->status_map); 481 if (error != 0) { 482 device_printf(sc->sc_dev, 483 "could not allocate status ring DMA memory\n"); 484 goto fail; 485 } 486 487 error = bus_dmamap_load(sc->status_dmat, sc->status_map, 488 sc->status_list, IPW_STATUS_SZ, ipw_dma_map_addr, &sc->status_phys, 489 0); 490 if (error != 0) { 491 device_printf(sc->sc_dev, 492 "could not map status ring DMA memory\n"); 493 goto fail; 494 } 495 496 /* 497 * Allocate command DMA map. 498 */ 499 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 500 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_cmd), 1, 501 sizeof (struct ipw_cmd), 0, NULL, NULL, &sc->cmd_dmat); 502 if (error != 0) { 503 device_printf(sc->sc_dev, "could not create command DMA tag\n"); 504 goto fail; 505 } 506 507 error = bus_dmamap_create(sc->cmd_dmat, 0, &sc->cmd_map); 508 if (error != 0) { 509 device_printf(sc->sc_dev, 510 "could not create command DMA map\n"); 511 goto fail; 512 } 513 514 /* 515 * Allocate headers DMA maps. 516 */ 517 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 518 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_hdr), 1, 519 sizeof (struct ipw_hdr), 0, NULL, NULL, &sc->hdr_dmat); 520 if (error != 0) { 521 device_printf(sc->sc_dev, "could not create header DMA tag\n"); 522 goto fail; 523 } 524 525 SLIST_INIT(&sc->free_shdr); 526 for (i = 0; i < IPW_NDATA; i++) { 527 shdr = &sc->shdr_list[i]; 528 error = bus_dmamap_create(sc->hdr_dmat, 0, &shdr->map); 529 if (error != 0) { 530 device_printf(sc->sc_dev, 531 "could not create header DMA map\n"); 532 goto fail; 533 } 534 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 535 } 536 537 /* 538 * Allocate tx buffers DMA maps. 539 */ 540 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 541 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_MAX_NSEG, MCLBYTES, 0, 542 NULL, NULL, &sc->txbuf_dmat); 543 if (error != 0) { 544 device_printf(sc->sc_dev, "could not create tx DMA tag\n"); 545 goto fail; 546 } 547 548 SLIST_INIT(&sc->free_sbuf); 549 for (i = 0; i < IPW_NDATA; i++) { 550 sbuf = &sc->tx_sbuf_list[i]; 551 error = bus_dmamap_create(sc->txbuf_dmat, 0, &sbuf->map); 552 if (error != 0) { 553 device_printf(sc->sc_dev, 554 "could not create tx DMA map\n"); 555 goto fail; 556 } 557 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 558 } 559 560 /* 561 * Initialize tx ring. 562 */ 563 for (i = 0; i < IPW_NTBD; i++) { 564 sbd = &sc->stbd_list[i]; 565 sbd->bd = &sc->tbd_list[i]; 566 sbd->type = IPW_SBD_TYPE_NOASSOC; 567 } 568 569 /* 570 * Pre-allocate rx buffers and DMA maps. 571 */ 572 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 573 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_NRBD, MCLBYTES, 0, 574 NULL, NULL, &sc->rxbuf_dmat); 575 if (error != 0) { 576 device_printf(sc->sc_dev, "could not create rx DMA tag\n"); 577 goto fail; 578 } 579 580 for (i = 0; i < IPW_NRBD; i++) { 581 sbd = &sc->srbd_list[i]; 582 sbuf = &sc->rx_sbuf_list[i]; 583 sbd->bd = &sc->rbd_list[i]; 584 585 sbuf->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 586 if (sbuf->m == NULL) { 587 device_printf(sc->sc_dev, 588 "could not allocate rx mbuf\n"); 589 error = ENOMEM; 590 goto fail; 591 } 592 593 error = bus_dmamap_create(sc->rxbuf_dmat, 0, &sbuf->map); 594 if (error != 0) { 595 device_printf(sc->sc_dev, 596 "could not create rx DMA map\n"); 597 goto fail; 598 } 599 600 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, 601 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, 602 &physaddr, 0); 603 if (error != 0) { 604 device_printf(sc->sc_dev, 605 "could not map rx DMA memory\n"); 606 goto fail; 607 } 608 609 sbd->type = IPW_SBD_TYPE_DATA; 610 sbd->priv = sbuf; 611 sbd->bd->physaddr = htole32(physaddr); 612 sbd->bd->len = htole32(MCLBYTES); 613 } 614 615 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 616 617 return 0; 618 619fail: ipw_release(sc); 620 return error; 621} 622 623static void 624ipw_release(struct ipw_softc *sc) 625{ 626 struct ipw_soft_buf *sbuf; 627 int i; 628 629 if (sc->tbd_dmat != NULL) { 630 if (sc->stbd_list != NULL) { 631 bus_dmamap_unload(sc->tbd_dmat, sc->tbd_map); 632 bus_dmamem_free(sc->tbd_dmat, sc->tbd_list, 633 sc->tbd_map); 634 } 635 bus_dma_tag_destroy(sc->tbd_dmat); 636 } 637 638 if (sc->rbd_dmat != NULL) { 639 if (sc->rbd_list != NULL) { 640 bus_dmamap_unload(sc->rbd_dmat, sc->rbd_map); 641 bus_dmamem_free(sc->rbd_dmat, sc->rbd_list, 642 sc->rbd_map); 643 } 644 bus_dma_tag_destroy(sc->rbd_dmat); 645 } 646 647 if (sc->status_dmat != NULL) { 648 if (sc->status_list != NULL) { 649 bus_dmamap_unload(sc->status_dmat, sc->status_map); 650 bus_dmamem_free(sc->status_dmat, sc->status_list, 651 sc->status_map); 652 } 653 bus_dma_tag_destroy(sc->status_dmat); 654 } 655 656 for (i = 0; i < IPW_NTBD; i++) 657 ipw_release_sbd(sc, &sc->stbd_list[i]); 658 659 if (sc->cmd_dmat != NULL) { 660 bus_dmamap_destroy(sc->cmd_dmat, sc->cmd_map); 661 bus_dma_tag_destroy(sc->cmd_dmat); 662 } 663 664 if (sc->hdr_dmat != NULL) { 665 for (i = 0; i < IPW_NDATA; i++) 666 bus_dmamap_destroy(sc->hdr_dmat, sc->shdr_list[i].map); 667 bus_dma_tag_destroy(sc->hdr_dmat); 668 } 669 670 if (sc->txbuf_dmat != NULL) { 671 for (i = 0; i < IPW_NDATA; i++) { 672 bus_dmamap_destroy(sc->txbuf_dmat, 673 sc->tx_sbuf_list[i].map); 674 } 675 bus_dma_tag_destroy(sc->txbuf_dmat); 676 } 677 678 if (sc->rxbuf_dmat != NULL) { 679 for (i = 0; i < IPW_NRBD; i++) { 680 sbuf = &sc->rx_sbuf_list[i]; 681 if (sbuf->m != NULL) { 682 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, 683 BUS_DMASYNC_POSTREAD); 684 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 685 m_freem(sbuf->m); 686 } 687 bus_dmamap_destroy(sc->rxbuf_dmat, sbuf->map); 688 } 689 bus_dma_tag_destroy(sc->rxbuf_dmat); 690 } 691} 692 693static int 694ipw_shutdown(device_t dev) 695{ 696 struct ipw_softc *sc = device_get_softc(dev); 697 698 ipw_stop(sc); 699 700 return 0; 701} 702 703static int 704ipw_suspend(device_t dev) 705{ 706 struct ipw_softc *sc = device_get_softc(dev); 707 708 ipw_stop(sc); 709 710 return 0; 711} 712 713static int 714ipw_resume(device_t dev) 715{ 716 struct ipw_softc *sc = device_get_softc(dev); 717 struct ifnet *ifp = sc->sc_ic.ic_ifp; 718 719 IPW_LOCK(sc); 720 721 if (ifp->if_flags & IFF_UP) { 722 ifp->if_init(ifp->if_softc); 723 if (ifp->if_flags & IFF_RUNNING) 724 ifp->if_start(ifp); 725 } 726 727 IPW_UNLOCK(sc); 728 729 return 0; 730} 731 732static int 733ipw_media_change(struct ifnet *ifp) 734{ 735 struct ipw_softc *sc = ifp->if_softc; 736 int error; 737 738 IPW_LOCK(sc); 739 740 error = ieee80211_media_change(ifp); 741 if (error != ENETRESET) { 742 IPW_UNLOCK(sc); 743 return error; 744 } 745 746 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 747 ipw_init(sc); 748 749 IPW_UNLOCK(sc); 750 751 return 0; 752} 753 754/* 755 * The firmware automaticly adapt the transmit speed. We report the current 756 * transmit speed here. 757 */ 758static void 759ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 760{ 761#define N(a) (sizeof (a) / sizeof (a[0])) 762 struct ipw_softc *sc = ifp->if_softc; 763 struct ieee80211com *ic = &sc->sc_ic; 764 static const struct { 765 uint32_t val; 766 int rate; 767 } rates[] = { 768 { IPW_RATE_DS1, 2 }, 769 { IPW_RATE_DS2, 4 }, 770 { IPW_RATE_DS5, 11 }, 771 { IPW_RATE_DS11, 22 }, 772 }; 773 uint32_t val; 774 int rate, i; 775 776 imr->ifm_status = IFM_AVALID; 777 imr->ifm_active = IFM_IEEE80211; 778 if (ic->ic_state == IEEE80211_S_RUN) 779 imr->ifm_status |= IFM_ACTIVE; 780 781 /* read current transmission rate from adapter */ 782 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 783 784 /* convert ipw rate to 802.11 rate */ 785 for (i = 0; i < N(rates) && rates[i].val != val; i++); 786 rate = (i < N(rates)) ? rates[i].rate : 0; 787 788 imr->ifm_active |= IFM_IEEE80211_11B; 789 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 790 switch (ic->ic_opmode) { 791 case IEEE80211_M_STA: 792 break; 793 794 case IEEE80211_M_IBSS: 795 imr->ifm_active |= IFM_IEEE80211_IBSS; 796 break; 797 798 case IEEE80211_M_MONITOR: 799 imr->ifm_active |= IFM_IEEE80211_MONITOR; 800 break; 801 802 case IEEE80211_M_AHDEMO: 803 case IEEE80211_M_HOSTAP: 804 /* should not get there */ 805 break; 806 } 807#undef N 808} 809 810static int 811ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 812{ 813 struct ifnet *ifp = ic->ic_ifp; 814 struct ipw_softc *sc = ifp->if_softc; 815 struct ieee80211_node *ni; 816 uint8_t macaddr[IEEE80211_ADDR_LEN]; 817 uint32_t len; 818 819 switch (nstate) { 820 case IEEE80211_S_RUN: 821 DELAY(200); /* firmware needs a short delay here */ 822 823 len = IEEE80211_ADDR_LEN; 824 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 825 826 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 827 if (ni == NULL) 828 break; 829 830 ieee80211_ref_node(ni); 831 ieee80211_sta_join(ic, ni); 832 ieee80211_node_authorize(ic, ni); 833 834 if (ic->ic_opmode == IEEE80211_M_STA) 835 ieee80211_notify_node_join(ic, ni, 1); 836 break; 837 838 case IEEE80211_S_INIT: 839 case IEEE80211_S_SCAN: 840 case IEEE80211_S_AUTH: 841 case IEEE80211_S_ASSOC: 842 break; 843 } 844 845 ic->ic_state = nstate; 846 return 0; 847} 848 849/* 850 * Read 16 bits at address 'addr' from the serial EEPROM. 851 */ 852static uint16_t 853ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 854{ 855 uint32_t tmp; 856 uint16_t val; 857 int n; 858 859 /* clock C once before the first command */ 860 IPW_EEPROM_CTL(sc, 0); 861 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 862 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 863 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 864 865 /* write start bit (1) */ 866 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 867 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 868 869 /* write READ opcode (10) */ 870 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 871 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 872 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 873 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 874 875 /* write address A7-A0 */ 876 for (n = 7; n >= 0; n--) { 877 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 878 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 879 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 880 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 881 } 882 883 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 884 885 /* read data Q15-Q0 */ 886 val = 0; 887 for (n = 15; n >= 0; n--) { 888 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 889 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 890 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 891 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 892 } 893 894 IPW_EEPROM_CTL(sc, 0); 895 896 /* clear Chip Select and clock C */ 897 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 898 IPW_EEPROM_CTL(sc, 0); 899 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 900 901 return le16toh(val); 902} 903 904static void 905ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 906{ 907 struct ipw_cmd *cmd; 908 909 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 910 911 cmd = mtod(sbuf->m, struct ipw_cmd *); 912 913 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 914 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 915 le32toh(cmd->status))); 916 917 wakeup(sc); 918} 919 920static void 921ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 922{ 923 struct ieee80211com *ic = &sc->sc_ic; 924 uint32_t state; 925 926 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 927 928 state = le32toh(*mtod(sbuf->m, uint32_t *)); 929 930 DPRINTFN(2, ("entering state %u\n", state)); 931 932 switch (state) { 933 case IPW_STATE_ASSOCIATED: 934 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 935 break; 936 937 case IPW_STATE_SCANNING: 938 /* don't leave run state on background scan */ 939 if (ic->ic_state != IEEE80211_S_RUN) 940 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 941 942 ic->ic_flags |= IEEE80211_F_SCAN; 943 break; 944 945 case IPW_STATE_SCAN_COMPLETE: 946 ieee80211_notify_scan_done(ic); 947 ic->ic_flags &= ~IEEE80211_F_SCAN; 948 break; 949 950 case IPW_STATE_ASSOCIATION_LOST: 951 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 952 break; 953 954 case IPW_STATE_RADIO_DISABLED: 955 ic->ic_ifp->if_flags &= ~IFF_UP; 956 ipw_stop(sc); 957 break; 958 } 959} 960 961/* 962 * XXX: Hack to set the current channel to the value advertised in beacons or 963 * probe responses. Only used during AP detection. 964 */ 965static void 966ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 967{ 968 struct ieee80211_frame *wh; 969 uint8_t subtype; 970 uint8_t *frm, *efrm; 971 972 wh = mtod(m, struct ieee80211_frame *); 973 974 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 975 return; 976 977 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 978 979 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 980 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 981 return; 982 983 frm = (uint8_t *)(wh + 1); 984 efrm = mtod(m, uint8_t *) + m->m_len; 985 986 frm += 12; /* skip tstamp, bintval and capinfo fields */ 987 while (frm < efrm) { 988 if (*frm == IEEE80211_ELEMID_DSPARMS) 989#if IEEE80211_CHAN_MAX < 255 990 if (frm[2] <= IEEE80211_CHAN_MAX) 991#endif 992 ic->ic_bss->ni_chan = &ic->ic_channels[frm[2]]; 993 994 frm += frm[1] + 2; 995 } 996} 997 998static void 999ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1000 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1001{ 1002 struct ieee80211com *ic = &sc->sc_ic; 1003 struct ifnet *ifp = ic->ic_ifp; 1004 struct mbuf *m; 1005 struct ieee80211_frame *wh; 1006 struct ieee80211_node *ni; 1007 bus_addr_t physaddr; 1008 int error; 1009 1010 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 1011 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 1012 1013 /* finalize mbuf */ 1014 m = sbuf->m; 1015 m->m_pkthdr.rcvif = ifp; 1016 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1017 1018 if (sc->sc_drvbpf != NULL) { 1019 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1020 1021 tap->wr_flags = 0; 1022 tap->wr_antsignal = status->rssi; 1023 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1024 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1025 1026 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1027 } 1028 1029 if (ic->ic_state == IEEE80211_S_SCAN) 1030 ipw_fix_channel(ic, m); 1031 1032 wh = mtod(m, struct ieee80211_frame *); 1033 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1034 1035 /* send the frame to the 802.11 layer */ 1036 ieee80211_input(ic, m, ni, status->rssi, 0); 1037 1038 /* node is no longer needed */ 1039 ieee80211_free_node(ni); 1040 1041 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1042 if (m == NULL) { 1043 device_printf(sc->sc_dev, "could not allocate rx mbuf\n"); 1044 sbuf->m = NULL; 1045 return; 1046 } 1047 1048 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, mtod(m, void *), 1049 MCLBYTES, ipw_dma_map_addr, &physaddr, 0); 1050 if (error != 0) { 1051 device_printf(sc->sc_dev, "could not map rx DMA memory\n"); 1052 m_freem(m); 1053 sbuf->m = NULL; 1054 return; 1055 } 1056 1057 sbuf->m = m; 1058 sbd->bd->physaddr = htole32(physaddr); 1059 1060 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1061 status->rssi)); 1062 1063 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1064} 1065 1066static void 1067ipw_rx_intr(struct ipw_softc *sc) 1068{ 1069 struct ipw_status *status; 1070 struct ipw_soft_bd *sbd; 1071 struct ipw_soft_buf *sbuf; 1072 uint32_t r, i; 1073 1074 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1075 return; 1076 1077 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1078 1079 bus_dmamap_sync(sc->status_dmat, sc->status_map, BUS_DMASYNC_POSTREAD); 1080 1081 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1082 status = &sc->status_list[i]; 1083 sbd = &sc->srbd_list[i]; 1084 sbuf = sbd->priv; 1085 1086 switch (le16toh(status->code) & 0xf) { 1087 case IPW_STATUS_CODE_COMMAND: 1088 ipw_command_intr(sc, sbuf); 1089 break; 1090 1091 case IPW_STATUS_CODE_NEWSTATE: 1092 ipw_newstate_intr(sc, sbuf); 1093 break; 1094 1095 case IPW_STATUS_CODE_DATA_802_3: 1096 case IPW_STATUS_CODE_DATA_802_11: 1097 ipw_data_intr(sc, status, sbd, sbuf); 1098 break; 1099 1100 case IPW_STATUS_CODE_NOTIFICATION: 1101 DPRINTFN(2, ("received notification\n")); 1102 break; 1103 1104 default: 1105 device_printf(sc->sc_dev, "unknown status code %u\n", 1106 le16toh(status->code)); 1107 } 1108 1109 /* firmware was killed, stop processing received frames */ 1110 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1111 return; 1112 1113 sbd->bd->flags = 0; 1114 } 1115 1116 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1117 1118 /* kick the firmware */ 1119 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1120 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1121} 1122 1123static void 1124ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1125{ 1126 struct ipw_soft_hdr *shdr; 1127 struct ipw_soft_buf *sbuf; 1128 1129 switch (sbd->type) { 1130 case IPW_SBD_TYPE_COMMAND: 1131 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, 1132 BUS_DMASYNC_POSTWRITE); 1133 bus_dmamap_unload(sc->cmd_dmat, sc->cmd_map); 1134 break; 1135 1136 case IPW_SBD_TYPE_HEADER: 1137 shdr = sbd->priv; 1138 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_POSTWRITE); 1139 bus_dmamap_unload(sc->hdr_dmat, shdr->map); 1140 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1141 break; 1142 1143 case IPW_SBD_TYPE_DATA: 1144 sbuf = sbd->priv; 1145 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, 1146 BUS_DMASYNC_POSTWRITE); 1147 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1148 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1149 1150 m_freem(sbuf->m); 1151 ieee80211_free_node(sbuf->ni); 1152 1153 sc->sc_tx_timer = 0; 1154 break; 1155 } 1156 1157 sbd->type = IPW_SBD_TYPE_NOASSOC; 1158} 1159 1160static void 1161ipw_tx_intr(struct ipw_softc *sc) 1162{ 1163 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1164 struct ipw_soft_bd *sbd; 1165 uint32_t r, i; 1166 1167 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1168 return; 1169 1170 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1171 1172 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1173 sbd = &sc->stbd_list[i]; 1174 1175 if (sbd->type == IPW_SBD_TYPE_DATA) 1176 ifp->if_opackets++; 1177 1178 ipw_release_sbd(sc, sbd); 1179 sc->txfree++; 1180 } 1181 1182 /* remember what the firmware has processed */ 1183 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1184 1185 ifp->if_flags &= ~IFF_OACTIVE; 1186 ipw_start(ifp); 1187} 1188 1189static void 1190ipw_intr(void *arg) 1191{ 1192 struct ipw_softc *sc = arg; 1193 uint32_t r; 1194 1195 IPW_LOCK(sc); 1196 1197 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) { 1198 IPW_UNLOCK(sc); 1199 return; 1200 } 1201 1202 /* disable interrupts */ 1203 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1204 1205 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1206 device_printf(sc->sc_dev, "fatal error\n"); 1207 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1208 ipw_stop(sc); 1209 } 1210 1211 if (r & IPW_INTR_FW_INIT_DONE) { 1212 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1213 wakeup(sc); 1214 } 1215 1216 if (r & IPW_INTR_RX_TRANSFER) 1217 ipw_rx_intr(sc); 1218 1219 if (r & IPW_INTR_TX_TRANSFER) 1220 ipw_tx_intr(sc); 1221 1222 /* acknowledge all interrupts */ 1223 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1224 1225 /* re-enable interrupts */ 1226 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1227 1228 IPW_UNLOCK(sc); 1229} 1230 1231static void 1232ipw_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1233{ 1234 if (error != 0) 1235 return; 1236 1237 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1238 1239 *(bus_addr_t *)arg = segs[0].ds_addr; 1240} 1241 1242/* 1243 * Send a command to the firmware and wait for the acknowledgement. 1244 */ 1245static int 1246ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1247{ 1248 struct ipw_soft_bd *sbd; 1249 bus_addr_t physaddr; 1250 int error; 1251 1252 sbd = &sc->stbd_list[sc->txcur]; 1253 1254 error = bus_dmamap_load(sc->cmd_dmat, sc->cmd_map, &sc->cmd, 1255 sizeof (struct ipw_cmd), ipw_dma_map_addr, &physaddr, 0); 1256 if (error != 0) { 1257 device_printf(sc->sc_dev, "could not map command DMA memory\n"); 1258 return error; 1259 } 1260 1261 sc->cmd.type = htole32(type); 1262 sc->cmd.subtype = 0; 1263 sc->cmd.len = htole32(len); 1264 sc->cmd.seq = 0; 1265 bcopy(data, sc->cmd.data, len); 1266 1267 sbd->type = IPW_SBD_TYPE_COMMAND; 1268 sbd->bd->physaddr = htole32(physaddr); 1269 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1270 sbd->bd->nfrag = 1; 1271 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1272 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1273 1274 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, BUS_DMASYNC_PREWRITE); 1275 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1276 1277 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1278 1279 /* kick firmware */ 1280 sc->txfree--; 1281 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1282 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1283 1284 /* wait at most one second for command to complete */ 1285 return msleep(sc, &sc->sc_mtx, 0, "ipwcmd", hz); 1286} 1287 1288static int 1289ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1290{ 1291 struct ipw_softc *sc = ifp->if_softc; 1292 struct ieee80211com *ic = &sc->sc_ic; 1293 struct ieee80211_frame *wh; 1294 struct ipw_soft_bd *sbd; 1295 struct ipw_soft_hdr *shdr; 1296 struct ipw_soft_buf *sbuf; 1297 struct ieee80211_key *k; 1298 struct mbuf *mnew; 1299 bus_dma_segment_t segs[IPW_MAX_NSEG]; 1300 bus_addr_t physaddr; 1301 int nsegs, error, i; 1302 1303 wh = mtod(m0, struct ieee80211_frame *); 1304 1305 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1306 k = ieee80211_crypto_encap(ic, ni, m0); 1307 if (k == NULL) 1308 return ENOBUFS; 1309 1310 /* packet header may have moved, reset our local pointer */ 1311 wh = mtod(m0, struct ieee80211_frame *); 1312 } 1313 1314 if (sc->sc_drvbpf != NULL) { 1315 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1316 1317 tap->wt_flags = 0; 1318 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1319 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1320 1321 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1322 } 1323 1324 shdr = SLIST_FIRST(&sc->free_shdr); 1325 sbuf = SLIST_FIRST(&sc->free_sbuf); 1326 KASSERT(shdr != NULL && sbuf != NULL, ("empty sw hdr/buf pool")); 1327 1328 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1329 shdr->hdr.subtype = 0; 1330 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1331 shdr->hdr.encrypt = 0; 1332 shdr->hdr.keyidx = 0; 1333 shdr->hdr.keysz = 0; 1334 shdr->hdr.fragmentsz = 0; 1335 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1336 if (ic->ic_opmode == IEEE80211_M_STA) 1337 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1338 else 1339 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1340 1341 /* trim IEEE802.11 header */ 1342 m_adj(m0, sizeof (struct ieee80211_frame)); 1343 1344 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, segs, 1345 &nsegs, 0); 1346 if (error != 0 && error != EFBIG) { 1347 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1348 error); 1349 m_freem(m0); 1350 return error; 1351 } 1352 if (error != 0) { 1353 mnew = m_defrag(m0, M_DONTWAIT); 1354 if (mnew == NULL) { 1355 device_printf(sc->sc_dev, 1356 "could not defragment mbuf\n"); 1357 m_freem(m0); 1358 return ENOBUFS; 1359 } 1360 m0 = mnew; 1361 1362 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, 1363 segs, &nsegs, 0); 1364 if (error != 0) { 1365 device_printf(sc->sc_dev, 1366 "could not map mbuf (error %d)\n", error); 1367 m_freem(m0); 1368 return error; 1369 } 1370 } 1371 1372 error = bus_dmamap_load(sc->hdr_dmat, shdr->map, &shdr->hdr, 1373 sizeof (struct ipw_hdr), ipw_dma_map_addr, &physaddr, 0); 1374 if (error != 0) { 1375 device_printf(sc->sc_dev, "could not map header DMA memory\n"); 1376 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1377 m_freem(m0); 1378 return error; 1379 } 1380 1381 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1382 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1383 1384 sbd = &sc->stbd_list[sc->txcur]; 1385 sbd->type = IPW_SBD_TYPE_HEADER; 1386 sbd->priv = shdr; 1387 sbd->bd->physaddr = htole32(physaddr); 1388 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1389 sbd->bd->nfrag = 1 + nsegs; 1390 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1391 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1392 1393 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, %6D, %6D)\n", 1394 shdr->hdr.type, shdr->hdr.subtype, shdr->hdr.encrypted, 1395 shdr->hdr.encrypt, shdr->hdr.src_addr, ":", shdr->hdr.dst_addr, 1396 ":")); 1397 1398 sc->txfree--; 1399 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1400 1401 sbuf->m = m0; 1402 sbuf->ni = ni; 1403 1404 for (i = 0; i < nsegs; i++) { 1405 sbd = &sc->stbd_list[sc->txcur]; 1406 1407 sbd->bd->physaddr = htole32(segs[i].ds_addr); 1408 sbd->bd->len = htole32(segs[i].ds_len); 1409 sbd->bd->nfrag = 0; 1410 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1411 if (i == nsegs - 1) { 1412 sbd->type = IPW_SBD_TYPE_DATA; 1413 sbd->priv = sbuf; 1414 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1415 } else { 1416 sbd->type = IPW_SBD_TYPE_NOASSOC; 1417 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1418 } 1419 1420 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, segs[i].ds_len)); 1421 1422 sc->txfree--; 1423 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1424 } 1425 1426 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_PREWRITE); 1427 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, BUS_DMASYNC_PREWRITE); 1428 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1429 1430 /* kick firmware */ 1431 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1432 1433 return 0; 1434} 1435 1436static void 1437ipw_start(struct ifnet *ifp) 1438{ 1439 struct ipw_softc *sc = ifp->if_softc; 1440 struct ieee80211com *ic = &sc->sc_ic; 1441 struct mbuf *m0; 1442 struct ether_header *eh; 1443 struct ieee80211_node *ni; 1444 1445 IPW_LOCK(sc); 1446 1447 if (ic->ic_state != IEEE80211_S_RUN) { 1448 IPW_UNLOCK(sc); 1449 return; 1450 } 1451 1452 for (;;) { 1453 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1454 if (m0 == NULL) 1455 break; 1456 1457 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1458 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1459 ifp->if_flags |= IFF_OACTIVE; 1460 break; 1461 } 1462 1463 if (m0->m_len < sizeof (struct ether_header) && 1464 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1465 continue; 1466 1467 eh = mtod(m0, struct ether_header *); 1468 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1469 if (ni == NULL) { 1470 m_freem(m0); 1471 continue; 1472 } 1473 BPF_MTAP(ifp, m0); 1474 1475 m0 = ieee80211_encap(ic, m0, ni); 1476 if (m0 == NULL) { 1477 ieee80211_free_node(ni); 1478 continue; 1479 } 1480 1481 if (ic->ic_rawbpf != NULL) 1482 bpf_mtap(ic->ic_rawbpf, m0); 1483 1484 if (ipw_tx_start(ifp, m0, ni) != 0) { 1485 ieee80211_free_node(ni); 1486 ifp->if_oerrors++; 1487 break; 1488 } 1489 1490 /* start watchdog timer */ 1491 sc->sc_tx_timer = 5; 1492 ifp->if_timer = 1; 1493 } 1494 1495 IPW_UNLOCK(sc); 1496} 1497 1498static void 1499ipw_watchdog(struct ifnet *ifp) 1500{ 1501 struct ipw_softc *sc = ifp->if_softc; 1502 struct ieee80211com *ic = &sc->sc_ic; 1503 1504 ifp->if_timer = 0; 1505 1506 if (sc->sc_tx_timer > 0) { 1507 if (--sc->sc_tx_timer == 0) { 1508 if_printf(ifp, "device timeout\n"); 1509 ifp->if_oerrors++; 1510 ifp->if_flags &= ~IFF_UP; 1511 ipw_stop(sc); 1512 return; 1513 } 1514 ifp->if_timer = 1; 1515 } 1516 1517 ieee80211_watchdog(ic); 1518} 1519 1520static int 1521ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1522{ 1523 struct ipw_softc *sc = ifp->if_softc; 1524 struct ieee80211com *ic = &sc->sc_ic; 1525 struct ifreq *ifr; 1526 int error = 0; 1527 1528 IPW_LOCK(sc); 1529 1530 switch (cmd) { 1531 case SIOCSIFFLAGS: 1532 if (ifp->if_flags & IFF_UP) { 1533 if (!(ifp->if_flags & IFF_RUNNING)) 1534 ipw_init(sc); 1535 } else { 1536 if (ifp->if_flags & IFF_RUNNING) 1537 ipw_stop(sc); 1538 } 1539 break; 1540 1541 case SIOCSLOADFW: 1542 /* only super-user can do that! */ 1543 if ((error = suser(curthread)) != 0) 1544 break; 1545 1546 ifr = (struct ifreq *)data; 1547 error = ipw_cache_firmware(sc, ifr->ifr_data); 1548 break; 1549 1550 case SIOCSKILLFW: 1551 /* only super-user can do that! */ 1552 if ((error = suser(curthread)) != 0) 1553 break; 1554 1555 ifp->if_flags &= ~IFF_UP; 1556 ipw_stop(sc); 1557 ipw_free_firmware(sc); 1558 break; 1559 1560 default: 1561 error = ieee80211_ioctl(ic, cmd, data); 1562 } 1563 1564 if (error == ENETRESET) { 1565 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1566 (IFF_UP | IFF_RUNNING)) 1567 ipw_init(sc); 1568 error = 0; 1569 } 1570 1571 IPW_UNLOCK(sc); 1572 1573 return error; 1574} 1575 1576static void 1577ipw_stop_master(struct ipw_softc *sc) 1578{ 1579 int ntries; 1580 1581 /* disable interrupts */ 1582 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1583 1584 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1585 for (ntries = 0; ntries < 50; ntries++) { 1586 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1587 break; 1588 DELAY(10); 1589 } 1590 if (ntries == 50) 1591 device_printf(sc->sc_dev, "timeout waiting for master\n"); 1592 1593 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1594 IPW_RST_PRINCETON_RESET); 1595 1596 sc->flags &= ~IPW_FLAG_FW_INITED; 1597} 1598 1599static int 1600ipw_reset(struct ipw_softc *sc) 1601{ 1602 int ntries; 1603 1604 ipw_stop_master(sc); 1605 1606 /* move adapter to D0 state */ 1607 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1608 IPW_CTL_INIT); 1609 1610 /* wait for clock stabilization */ 1611 for (ntries = 0; ntries < 1000; ntries++) { 1612 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1613 break; 1614 DELAY(200); 1615 } 1616 if (ntries == 1000) 1617 return EIO; 1618 1619 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1620 IPW_RST_SW_RESET); 1621 1622 DELAY(10); 1623 1624 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1625 IPW_CTL_INIT); 1626 1627 return 0; 1628} 1629 1630/* 1631 * Upload the microcode to the device. 1632 */ 1633static int 1634ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1635{ 1636 int ntries; 1637 1638 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1639 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1640 1641 MEM_WRITE_2(sc, 0x220000, 0x0703); 1642 MEM_WRITE_2(sc, 0x220000, 0x0707); 1643 1644 MEM_WRITE_1(sc, 0x210014, 0x72); 1645 MEM_WRITE_1(sc, 0x210014, 0x72); 1646 1647 MEM_WRITE_1(sc, 0x210000, 0x40); 1648 MEM_WRITE_1(sc, 0x210000, 0x00); 1649 MEM_WRITE_1(sc, 0x210000, 0x40); 1650 1651 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1652 1653 MEM_WRITE_1(sc, 0x210000, 0x00); 1654 MEM_WRITE_1(sc, 0x210000, 0x00); 1655 MEM_WRITE_1(sc, 0x210000, 0x80); 1656 1657 MEM_WRITE_2(sc, 0x220000, 0x0703); 1658 MEM_WRITE_2(sc, 0x220000, 0x0707); 1659 1660 MEM_WRITE_1(sc, 0x210014, 0x72); 1661 MEM_WRITE_1(sc, 0x210014, 0x72); 1662 1663 MEM_WRITE_1(sc, 0x210000, 0x00); 1664 MEM_WRITE_1(sc, 0x210000, 0x80); 1665 1666 for (ntries = 0; ntries < 10; ntries++) { 1667 if (MEM_READ_1(sc, 0x210000) & 1) 1668 break; 1669 DELAY(10); 1670 } 1671 if (ntries == 10) { 1672 device_printf(sc->sc_dev, 1673 "timeout waiting for ucode to initialize\n"); 1674 return EIO; 1675 } 1676 1677 MEM_WRITE_4(sc, 0x3000e0, 0); 1678 1679 return 0; 1680} 1681 1682/* set of macros to handle unaligned little endian data in firmware image */ 1683#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1684#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1685static int 1686ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1687{ 1688 u_char *p, *end; 1689 uint32_t dst; 1690 uint16_t len; 1691 int error; 1692 1693 p = fw; 1694 end = fw + size; 1695 while (p < end) { 1696 dst = GETLE32(p); p += 4; 1697 len = GETLE16(p); p += 2; 1698 1699 ipw_write_mem_1(sc, dst, p, len); 1700 p += len; 1701 } 1702 1703 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1704 IPW_IO_LED_OFF); 1705 1706 /* enable interrupts */ 1707 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1708 1709 /* kick the firmware */ 1710 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1711 1712 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1713 IPW_CTL_ALLOW_STANDBY); 1714 1715 /* wait at most one second for firmware initialization to complete */ 1716 if ((error = msleep(sc, &sc->sc_mtx, 0, "ipwinit", hz)) != 0) { 1717 device_printf(sc->sc_dev, "timeout waiting for firmware " 1718 "initialization to complete\n"); 1719 return error; 1720 } 1721 1722 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1723 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1724 1725 return 0; 1726} 1727 1728/* 1729 * Store firmware into kernel memory so we can download it when we need to, 1730 * e.g when the adapter wakes up from suspend mode. 1731 */ 1732static int 1733ipw_cache_firmware(struct ipw_softc *sc, void *data) 1734{ 1735 struct ipw_firmware *fw = &sc->fw; 1736 struct ipw_firmware_hdr hdr; 1737 u_char *p = data; 1738 int error; 1739 1740 ipw_free_firmware(sc); 1741 1742 IPW_UNLOCK(sc); 1743 1744 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1745 goto fail1; 1746 1747 fw->main_size = le32toh(hdr.main_size); 1748 fw->ucode_size = le32toh(hdr.ucode_size); 1749 p += sizeof hdr; 1750 1751 fw->main = malloc(fw->main_size, M_DEVBUF, M_NOWAIT); 1752 if (fw->main == NULL) { 1753 error = ENOMEM; 1754 goto fail1; 1755 } 1756 1757 fw->ucode = malloc(fw->ucode_size, M_DEVBUF, M_NOWAIT); 1758 if (fw->ucode == NULL) { 1759 error = ENOMEM; 1760 goto fail2; 1761 } 1762 1763 if ((error = copyin(p, fw->main, fw->main_size)) != 0) 1764 goto fail3; 1765 1766 p += fw->main_size; 1767 if ((error = copyin(p, fw->ucode, fw->ucode_size)) != 0) 1768 goto fail3; 1769 1770 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1771 fw->ucode_size)); 1772 1773 IPW_LOCK(sc); 1774 1775 sc->flags |= IPW_FLAG_FW_CACHED; 1776 1777 return 0; 1778 1779fail3: free(fw->ucode, M_DEVBUF); 1780fail2: free(fw->main, M_DEVBUF); 1781fail1: IPW_LOCK(sc); 1782 1783 return error; 1784} 1785 1786static void 1787ipw_free_firmware(struct ipw_softc *sc) 1788{ 1789 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1790 return; 1791 1792 free(sc->fw.main, M_DEVBUF); 1793 free(sc->fw.ucode, M_DEVBUF); 1794 1795 sc->flags &= ~IPW_FLAG_FW_CACHED; 1796} 1797 1798static int 1799ipw_config(struct ipw_softc *sc) 1800{ 1801 struct ieee80211com *ic = &sc->sc_ic; 1802 struct ifnet *ifp = ic->ic_ifp; 1803 struct ipw_security security; 1804 struct ieee80211_key *k; 1805 struct ipw_wep_key wepkey; 1806 struct ipw_scan_options options; 1807 struct ipw_configuration config; 1808 uint32_t data; 1809 int error, i; 1810 1811 switch (ic->ic_opmode) { 1812 case IEEE80211_M_STA: 1813 case IEEE80211_M_HOSTAP: 1814 data = htole32(IPW_MODE_BSS); 1815 break; 1816 1817 case IEEE80211_M_IBSS: 1818 case IEEE80211_M_AHDEMO: 1819 data = htole32(IPW_MODE_IBSS); 1820 break; 1821 1822 case IEEE80211_M_MONITOR: 1823 data = htole32(IPW_MODE_MONITOR); 1824 break; 1825 } 1826 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1827 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1828 if (error != 0) 1829 return error; 1830 1831 if (ic->ic_opmode == IEEE80211_M_IBSS || 1832 ic->ic_opmode == IEEE80211_M_MONITOR) { 1833 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1834 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1835 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1836 if (error != 0) 1837 return error; 1838 } 1839 1840 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1841 DPRINTF(("Enabling adapter\n")); 1842 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1843 } 1844 1845 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 1846 DPRINTF(("Setting MAC address to %6D\n", ic->ic_myaddr, ":")); 1847 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1848 IEEE80211_ADDR_LEN); 1849 if (error != 0) 1850 return error; 1851 1852 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1853 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1854 if (ic->ic_opmode == IEEE80211_M_IBSS) 1855 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1856 if (ifp->if_flags & IFF_PROMISC) 1857 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1858 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1859 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1860 DPRINTF(("Setting configuration to 0x%x\n", le32toh(config.flags))); 1861 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1862 if (error != 0) 1863 return error; 1864 1865 data = htole32(0x3); /* 1, 2 */ 1866 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 1867 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1868 if (error != 0) 1869 return error; 1870 1871 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1872 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 1873 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1874 if (error != 0) 1875 return error; 1876 1877 data = htole32(IPW_POWER_MODE_CAM); 1878 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 1879 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1880 if (error != 0) 1881 return error; 1882 1883 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1884 data = htole32(32); /* default value */ 1885 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 1886 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1887 sizeof data); 1888 if (error != 0) 1889 return error; 1890 } 1891 1892 data = htole32(ic->ic_rtsthreshold); 1893 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 1894 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1895 if (error != 0) 1896 return error; 1897 1898 data = htole32(ic->ic_fragthreshold); 1899 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 1900 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1901 if (error != 0) 1902 return error; 1903 1904#ifdef IPW_DEBUG 1905 if (ipw_debug > 0) { 1906 printf("Setting ESSID to "); 1907 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1908 printf("\n"); 1909 } 1910#endif 1911 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1912 ic->ic_des_esslen); 1913 if (error != 0) 1914 return error; 1915 1916 /* no mandatory BSSID */ 1917 DPRINTF(("Setting mandatory BSSID to null\n")); 1918 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1919 if (error != 0) 1920 return error; 1921 1922 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1923 DPRINTF(("Setting desired BSSID to %6D\n", ic->ic_des_bssid, 1924 ":")); 1925 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1926 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1927 if (error != 0) 1928 return error; 1929 } 1930 1931 bzero(&security, sizeof security); 1932 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 1933 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 1934 security.ciphers = htole32(IPW_CIPHER_NONE); 1935 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1936 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1937 sizeof security); 1938 if (error != 0) 1939 return error; 1940 1941 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1942 k = ic->ic_crypto.cs_nw_keys; 1943 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1944 if (k->wk_keylen == 0) 1945 continue; 1946 1947 wepkey.idx = i; 1948 wepkey.len = k->wk_keylen; 1949 bzero(wepkey.key, sizeof wepkey.key); 1950 bcopy(k->wk_key, wepkey.key, k->wk_keylen); 1951 DPRINTF(("Setting wep key index %u len %u\n", 1952 wepkey.idx, wepkey.len)); 1953 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1954 sizeof wepkey); 1955 if (error != 0) 1956 return error; 1957 } 1958 1959 data = htole32(ic->ic_crypto.cs_def_txkey); 1960 DPRINTF(("Setting wep tx key index to %u\n", le32toh(data))); 1961 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1962 sizeof data); 1963 if (error != 0) 1964 return error; 1965 } 1966 1967 data = htole32((ic->ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 1968 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 1969 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1970 if (error != 0) 1971 return error; 1972 1973#if 0 1974 struct ipw_wpa_ie ie; 1975 1976 bzero(&ie, sizeof ie); 1977 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 1978 DPRINTF(("Setting wpa ie\n")); 1979 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 1980 if (error != 0) 1981 return error; 1982#endif 1983 1984 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1985 data = htole32(ic->ic_lintval); 1986 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 1987 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1988 sizeof data); 1989 if (error != 0) 1990 return error; 1991 } 1992 1993 options.flags = 0; 1994 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1995 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 1996 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1997 if (error != 0) 1998 return error; 1999 2000 /* finally, enable adapter (start scanning for an access point) */ 2001 DPRINTF(("Enabling adapter\n")); 2002 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2003} 2004 2005static void 2006ipw_init(void *priv) 2007{ 2008 struct ipw_softc *sc = priv; 2009 struct ieee80211com *ic = &sc->sc_ic; 2010 struct ifnet *ifp = ic->ic_ifp; 2011 struct ipw_firmware *fw = &sc->fw; 2012 2013 /* exit immediately if firmware has not been ioctl'd */ 2014 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2015 ifp->if_flags &= ~IFF_UP; 2016 return; 2017 } 2018 2019 ipw_stop(sc); 2020 2021 if (ipw_reset(sc) != 0) { 2022 device_printf(sc->sc_dev, "could not reset adapter\n"); 2023 goto fail; 2024 } 2025 2026 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2027 device_printf(sc->sc_dev, "could not load microcode\n"); 2028 goto fail; 2029 } 2030 2031 ipw_stop_master(sc); 2032 2033 /* 2034 * Setup tx, rx and status rings. 2035 */ 2036 sc->txold = IPW_NTBD - 1; 2037 sc->txcur = 0; 2038 sc->txfree = IPW_NTBD - 2; 2039 sc->rxcur = IPW_NRBD - 1; 2040 2041 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_phys); 2042 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2043 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2044 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2045 2046 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_phys); 2047 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2048 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2049 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2050 2051 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_phys); 2052 2053 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2054 device_printf(sc->sc_dev, "could not load firmware\n"); 2055 goto fail; 2056 } 2057 2058 sc->flags |= IPW_FLAG_FW_INITED; 2059 2060 /* retrieve information tables base addresses */ 2061 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2062 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2063 2064 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2065 2066 if (ipw_config(sc) != 0) { 2067 device_printf(sc->sc_dev, "device configuration failed\n"); 2068 goto fail; 2069 } 2070 2071 ifp->if_flags &= ~IFF_OACTIVE; 2072 ifp->if_flags |= IFF_RUNNING; 2073 2074 return; 2075 2076fail: ifp->if_flags &= ~IFF_UP; 2077 ipw_stop(sc); 2078} 2079 2080static void 2081ipw_stop(void *priv) 2082{ 2083 struct ipw_softc *sc = priv; 2084 struct ieee80211com *ic = &sc->sc_ic; 2085 struct ifnet *ifp = ic->ic_ifp; 2086 int i; 2087 2088 ipw_stop_master(sc); 2089 2090 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2091 2092 /* 2093 * Release tx buffers. 2094 */ 2095 for (i = 0; i < IPW_NTBD; i++) 2096 ipw_release_sbd(sc, &sc->stbd_list[i]); 2097 2098 sc->sc_tx_timer = 0; 2099 ifp->if_timer = 0; 2100 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2101 2102 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2103} 2104 2105#ifdef IPW_DEBUG 2106static int 2107ipw_sysctl_stats(SYSCTL_HANDLER_ARGS) 2108{ 2109 struct ipw_softc *sc = arg1; 2110 uint32_t i, size, buf[256]; 2111 2112 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 2113 bzero(buf, sizeof buf); 2114 return SYSCTL_OUT(req, buf, sizeof buf); 2115 } 2116 2117 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 2118 2119 size = min(CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA), 256); 2120 for (i = 1; i < size; i++) 2121 buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA)); 2122 2123 return SYSCTL_OUT(req, buf, sizeof buf); 2124} 2125#endif 2126 2127static int 2128ipw_sysctl_radio(SYSCTL_HANDLER_ARGS) 2129{ 2130 struct ipw_softc *sc = arg1; 2131 int val; 2132 2133 val = !((sc->flags & IPW_FLAG_HAS_RADIO_SWITCH) && 2134 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED)); 2135 2136 return SYSCTL_OUT(req, &val, sizeof val); 2137} 2138 2139static uint32_t 2140ipw_read_table1(struct ipw_softc *sc, uint32_t off) 2141{ 2142 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 2143} 2144 2145static void 2146ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 2147{ 2148 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 2149} 2150 2151static int 2152ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 2153{ 2154 uint32_t addr, info; 2155 uint16_t count, size; 2156 uint32_t total; 2157 2158 /* addr[4] + count[2] + size[2] */ 2159 addr = MEM_READ_4(sc, sc->table2_base + off); 2160 info = MEM_READ_4(sc, sc->table2_base + off + 4); 2161 2162 count = info >> 16; 2163 size = info & 0xffff; 2164 total = count * size; 2165 2166 if (total > *len) { 2167 *len = total; 2168 return EINVAL; 2169 } 2170 2171 *len = total; 2172 ipw_read_mem_1(sc, addr, buf, total); 2173 2174 return 0; 2175} 2176 2177static void 2178ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2179 bus_size_t count) 2180{ 2181 for (; count > 0; offset++, datap++, count--) { 2182 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2183 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2184 } 2185} 2186 2187static void 2188ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2189 bus_size_t count) 2190{ 2191 for (; count > 0; offset++, datap++, count--) { 2192 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2193 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2194 } 2195} 2196