cd180.h revision 9232
155625Sache/* 255625Sache * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 386796Sache * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 486796Sache * All rights reserved. 586796Sache * 686796Sache * Redistribution and use in source and binary forms, with or without 786796Sache * modification, are permitted provided that the following conditions 886796Sache * are met: 986796Sache * 1. Redistributions of source code must retain the above copyright 1086796Sache * notice, this list of conditions and the following disclaimer. 1186796Sache * 2. Redistributions in binary form must reproduce the above copyright 1286796Sache * notice, this list of conditions and the following disclaimer in the 1386796Sache * documentation and/or other materials provided with the distribution. 1486796Sache * 1555625Sache * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 1655625Sache * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1755625Sache * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1855625Sache * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 1955625Sache * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2055625Sache * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2155625Sache * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2255625Sache * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2355625Sache * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2455625Sache * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2555625Sache * SUCH DAMAGE. 2655625Sache */ 2755625Sache 2855625Sache/* 2955625Sache * Cirrus Logic CD180 registers 3055625Sache */ 3155625Sache 3255625Sache/* Global registers */ 3355625Sache#define CD180_GIVR 0x40 /* Global Interrupt Verctor Register */ 3455625Sache#define CD180_GICR 0x41 /* Global Interrupting Channel Register */ 3555625Sache#define CD180_PILR1 0x61 /* Priority Interrupt Level Register 1 */ 3655625Sache#define CD180_PILR2 0x62 /* Priority Interrupt Level Register 2 */ 3755625Sache#define CD180_PILR3 0x63 /* Priority Interrupt Level Register 3 */ 3855625Sache#define CD180_CAR 0x64 /* Channel Access Register */ 3955625Sache#define CD180_GFRCR 0x6B /* Global Firmware Revision Code Register */ 4055625Sache#define CD180_PPRH 0x70 /* Prescaler Period Register MSB */ 4155625Sache#define CD180_PPRL 0x71 /* Prescaler Period Register LSB */ 4255625Sache#define CD180_RDR 0x78 /* Receiver Data Register */ 4355625Sache#define CD180_RCSR 0x7A /* Receiver Character Status Register */ 4455625Sache#define CD180_TDR 0x7B /* Transmit Data Register */ 45250553Seadler#define CD180_EOIR 0x7F /* End of Interrupt Register */ 4655625Sache 4755625Sache/* Channel Registers */ 4886796Sache#define CD180_CCR 0x01 /* Channel Command Register */ 4986796Sache#define CD180_IER 0x02 /* Interrupt Enable Register */ 5086796Sache#define CD180_COR1 0x03 /* Channel Option Register 1 */ 5186796Sache#define CD180_COR2 0x04 /* Channel Option Register 1 */ 5286796Sache#define CD180_COR3 0x05 /* Channel Option Register 1 */ 5386796Sache#define CD180_CCSR 0x06 /* Channel Control STatus Register */ 5486796Sache#define CD180_RDCR 0x07 /* Receive Data Count Register */ 5586796Sache#define CD180_SCHR1 0x09 /* Special Character Register 1 */ 5686796Sache#define CD180_SCHR2 0x0A /* Special Character Register 2 */ 5786796Sache#define CD180_SCHR3 0x0B /* Special Character Register 3 */ 5886796Sache#define CD180_SCHR4 0x0C /* Special Character Register 4 */ 5986796Sache#define CD180_MCOR1 0x10 /* Modem Change Option 1 Register */ 6055625Sache#define CD180_MCOR2 0x11 /* Modem Change Option 2 Register */ 6155625Sache#define CD180_MCR 0x12 /* Modem Change Register */ 6255625Sache#define CD180_RTPR 0x18 /* Receive Timeout Period Register */ 6355625Sache#define CD180_MSVR 0x28 /* Modem Signal Value Register */ 6455625Sache#define CD180_RBPRH 0x31 /* Receive Baud Rate Period Register MSB */ 6555625Sache#define CD180_RBPRL 0x32 /* Receive Baud Rate Period Register LSB */ 6655625Sache#define CD180_TBPRH 0x39 /* Transmit Baud Rate Period Register MSB */ 6755625Sache#define CD180_TBPRL 0x3A /* Transmit Baud Rate Period Register LSB */ 6855625Sache 6955625Sache/** Register descritpions **/ 7055625Sache 7155625Sache/* Global Interrupt Vector Register */ 7255625Sache#define GIVR_IT_MSCI 0x01 /* Modem Signal Change Interrupt */ 7355625Sache#define GIVR_IT_TDI 0x02 /* Transmit Data Interrupt */ 7455625Sache#define GIVR_IT_RGDI 0x03 /* Receive Good Data Interrupt */ 7555625Sache#define GIVR_IT_REI 0x07 /* Receive Exception Interrupt */ 7655625Sache 7755625Sache/* Global Interrupt Channel Register */ 7855625Sache#define GICR_CHAN 0x1C /* Channel Number Mask */ 7955625Sache#define GICR_LSH 2 /* Channel Number Shift */ 8055625Sache 8155625Sache/* Channel Address Register */ 8255625Sache#define CAR_CHAN 0x07 /* Channel Number Mask */ 8355625Sache#define CAR_A7 0x08 /* Addres bit 7 (unused) */ 8455625Sache 8555625Sache/* Receive Character Status Register */ 8655625Sache#define RCSR_OE 0x01 /* Overrun Error */ 8755625Sache#define RCSR_FE 0x02 /* Frame Error */ 8855625Sache#define RCSR_PE 0x04 /* Parity Error */ 8955625Sache#define RCSR_Break 0x08 /* Break detected */ 9055625Sache#define RCSR_Timeout 0x80 /* Rx Timeout */ 9155625Sache#define RCSR_SCMASK 0x70 /* Special Character Detected Mask */ 9255625Sache#define RCSR_SC1 0x10 /* Special Char 1 (or 1 & 3 seq matched) */ 9355625Sache#define RCSR_SC2 0x20 /* Special Char 2 (or 2 & 4 seq matched) */ 9486796Sache#define RCSR_SC3 0x30 /* Special Char 3 */ 9555625Sache#define RCSR_SC4 0x40 /* Special Char 4 */ 9655625Sache 97/* Channel Command Register */ 98#define CCR_ResetChan 0x80 /* Reset Channel */ 99#define CCR_HWRESET 0x81 /* Hardware Reset (all channels) */ 100#define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */ 101#define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */ 102#define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */ 103#define CCR_SENDSPCH1 0x21 /* Send Special Character 1 */ 104#define CCR_SENDSPCH2 0x22 /* Send Special Character 2 */ 105#define CCR_SENDSPCH3 0x23 /* Send Special Character 3 */ 106#define CCR_SENDSPCH4 0x24 /* Send Special Character 4 */ 107#define CCR_RCVRDIS 0x11 /* Receiver Disable */ 108#define CCR_RCVREN 0x12 /* Receiver Enable */ 109#define CCR_XMTRDIS 0x14 /* Transmitter Disable */ 110#define CCR_XMTREN 0x18 /* Transmitter Enable */ 111 112/* Interrupt Enable Register */ 113#define IER_DSR 0x80 /* Enable interrupt on DSR change */ 114#define IER_CD 0x40 /* Enable interrupt on CD change */ 115#define IER_CTS 0x20 /* Enable interrupt on CTS change */ 116#define IER_RxData 0x10 /* Enable interrupt on Receive Data */ 117#define IER_RxSC 0x08 /* Enable interrupt on Receive Spec. Char */ 118#define IER_TxRdy 0x04 /* Enable interrupt on TX FIFO empty */ 119#define IER_TxMpty 0x02 /* Enable interrupt on TX completely empty*/ 120#define IER_RET 0x01 /* Enable interrupt on RX Except. Timeout */ 121 122/* Channel Option Register 1 */ 123#define COR1_ODDP 0x80 /* Odd Parity */ 124#define COR1_ParMMASK 0x60 /* Parity Mode mask */ 125#define COR1_NOPAR 0x02 /* No Parity */ 126#define COR1_FORCEPAR 0x20 /* Force Parity */ 127#define COR1_NORMPAR 0x40 /* Normal Parity */ 128#define COR1_Ignore 0x10 /* Ignore Parity on RX */ 129#define COR1_StopMASK 0x0C /* Stop Bits mode mask */ 130#define COR1_1SB 0x00 /* 1 Stop Bit */ 131#define COR1_15SB 0x04 /* 1.5 Stop Bits */ 132#define COR1_2SB 0x08 /* 2 Stop Bits */ 133#define COR1_CHLMASK 0x03 /* Character Length mask */ 134#define COR1_5BITS 0x00 /* 5 bits */ 135#define COR1_6BITS 0x01 /* 6 bits */ 136#define COR1_7BITS 0x02 /* 7 bits */ 137#define COR1_8BITS 0x03 /* 8 bits */ 138 139/* Channel Option Register 2 */ 140#define COR2_IXM 0x80 /* Implied XON mode */ 141#define COR2_TxIBE 0x40 /* Enable In-Band XON/XOFF Flow Control */ 142#define COR2_ETC 0x20 /* Embedded Tx Commands Enable */ 143#define COR2_LLM 0x10 /* Local Loopback Mode */ 144#define COR2_RLM 0x08 /* Remote Loopback Mode */ 145#define COR2_RtsAO 0x04 /* RTS Automatic Output Enable */ 146#define COR2_CtsAE 0x02 /* CTS Automatic Enable */ 147#define COR2_DsrAE 0x01 /* DSR Automatic Enable */ 148 149/* Channel Option Register 3 */ 150#define COR3_XonCH 0x80 /* XON is a double seq (1 & 3) */ 151#define COR3_XoffCH 0x40 /* XOFF is a double seq (1 & 3) */ 152#define COR3_FCT 0x20 /* Flow-Control Transparency Mode */ 153#define COR3_SCDE 0x10 /* Special Character Detection Enable */ 154#define COR3_RxTHMASK 0x0F /* RX FIFO Threshold value (1-8) */ 155 156/* Channel Control Status Register */ 157#define CCSR_RxEn 0x80 /* Revceiver Enabled */ 158#define CCSR_RxFloff 0x40 /* Receive Flow Off (XOFF sent) */ 159#define CCSR_RxFlon 0x20 /* Receive Flow On (XON sent) */ 160#define CCSR_TxEn 0x08 /* Transmitter Enabled */ 161#define CCSR_TxFloff 0x04 /* Transmit Flow Off (got XOFF) */ 162#define CCSR_TxFlon 0x02 /* Transmit Flow On (got XON) */ 163 164/* Modem Change Option Register 1 */ 165#define MCOR1_DSRzd 0x80 /* Detect 0->1 transition of DSR */ 166#define MCOR1_CDzd 0x40 /* Detect 0->1 transition of CD */ 167#define MCOR1_CTSzd 0x20 /* Detect 0->1 transition of CTS */ 168#define MCOR1_DTRthMASK 0x0F /* Automatic DTR FC Threshold (1-8) chars */ 169 170/* Modem Change Option Register 2 */ 171#define MCOR2_DSRod 0x80 /* Detect 1->0 transition of DSR */ 172#define MCOR2_CDod 0x40 /* Detect 1->0 transition of CD */ 173#define MCOR2_CTSod 0x20 /* Detect 1->0 transition of CTS */ 174 175/* Modem Change Register */ 176#define MCR_DSRchg 0x80 /* DSR Changed */ 177#define MCR_CDchg 0x40 /* CD Changed */ 178#define MCR_CTSchg 0x20 /* CTS Changed */ 179 180/* Modem Signal Value Register */ 181#define MSVR_DSR 0x80 /* Current state of DSR input */ 182#define MSVR_CD 0x40 /* Current state of DSR input */ 183#define MSVR_CTS 0x20 /* Current state of CTS input */ 184#define MSVR_DTR 0x02 /* Current state of DTR output */ 185#define MSVR_RTS 0x01 /* Current state of RTS output */ 186 187/* Escape characters */ 188#define CD180_C_ESC 0x00 /* Escape character */ 189#define CD180_C_SBRK 0x81 /* Start sending BREAK */ 190#define CD180_C_DELAY 0x82 /* Delay output */ 191#define CD180_C_EBRK 0x83 /* Stop sending BREAK */ 192 193/* Miscellaneous */ 194#define CD180_NCHAN 8 /* 8 channels per chip */ 195#define CD180_CTICKS 16 /* 16 ticks for character processing */ 196#define CD180_NFIFO 8 /* 8 bytes in FIFO */ 197