1228940Sdelphij/*- 2228940Sdelphij * Copyright (c) 2011 HighPoint Technologies, Inc. 3228940Sdelphij * All rights reserved. 4228940Sdelphij * 5228940Sdelphij * Redistribution and use in source and binary forms, with or without 6228940Sdelphij * modification, are permitted provided that the following conditions 7228940Sdelphij * are met: 8228940Sdelphij * 1. Redistributions of source code must retain the above copyright 9228940Sdelphij * notice, this list of conditions and the following disclaimer. 10228940Sdelphij * 2. Redistributions in binary form must reproduce the above copyright 11228940Sdelphij * notice, this list of conditions and the following disclaimer in the 12228940Sdelphij * documentation and/or other materials provided with the distribution. 13228940Sdelphij * 14228940Sdelphij * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15228940Sdelphij * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16228940Sdelphij * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17228940Sdelphij * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18228940Sdelphij * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19228940Sdelphij * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20228940Sdelphij * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21228940Sdelphij * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22228940Sdelphij * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23228940Sdelphij * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24228940Sdelphij * SUCH DAMAGE. 25228940Sdelphij * 26228940Sdelphij * $FreeBSD$ 27228940Sdelphij */ 28228940Sdelphij 29228940Sdelphij#include <dev/hpt27xx/hpt27xx_config.h> 30228940Sdelphij 31228940Sdelphij#ifndef _HPT_HIM_H_ 32228940Sdelphij#define _HPT_HIM_H_ 33228940Sdelphij 34228940Sdelphij#define VERMAGIC_HIM 55 35228940Sdelphij 36228940Sdelphij#if defined(__cplusplus) 37228940Sdelphijextern "C" { 38228940Sdelphij#endif 39228940Sdelphij 40228940Sdelphij#include <dev/hpt27xx/list.h> 41228940Sdelphij 42228940Sdelphij#define SECTOR_TO_BYTE_SHIFT 9 43228940Sdelphij#define SECTOR_TO_BYTE(x) ((HPT_U32)(x) << SECTOR_TO_BYTE_SHIFT) 44228940Sdelphij#define BYTE_TO_SECTOR(x) ((x)>>SECTOR_TO_BYTE_SHIFT) 45228940Sdelphij 46228940Sdelphijtypedef struct _PCI_ID 47228940Sdelphij{ 48228940Sdelphij HPT_U16 vid; 49228940Sdelphij HPT_U16 did; 50228940Sdelphij HPT_U32 subsys; 51228940Sdelphij HPT_U8 rev; 52228940Sdelphij HPT_U8 nbase; 53228940Sdelphij HPT_U16 reserve; 54228940Sdelphij} 55228940SdelphijPCI_ID; 56228940Sdelphij 57228940Sdelphijtypedef struct _PCI_ADDRESS 58228940Sdelphij{ 59228940Sdelphij HPT_U8 tree; 60228940Sdelphij HPT_U8 bus; 61228940Sdelphij HPT_U8 device; 62228940Sdelphij HPT_U8 function; 63228940Sdelphij} 64228940SdelphijPCI_ADDRESS; 65228940Sdelphij 66228940Sdelphijtypedef struct _HIM_ADAPTER_CONFIG 67228940Sdelphij{ 68228940Sdelphij PCI_ADDRESS pci_addr; 69228940Sdelphij PCI_ID pci_id; 70228940Sdelphij 71228940Sdelphij HPT_U8 max_devices; 72228940Sdelphij 73228940Sdelphij HPT_U8 bProbeInInitializing:1; 74228940Sdelphij 75228940Sdelphij HPT_U8 bSpinupOneDevEachTime:1; 76228940Sdelphij 77228940Sdelphij HPT_U8 bGlobalNcq:1; 78228940Sdelphij HPT_U8 bSGPIOPartSupport:1; 79228940Sdelphij 80228940Sdelphij HPT_U8 bNeedSASIdleTimer:1; 81228940Sdelphij HPT_U8 reserved:3; 82228940Sdelphij 83228940Sdelphij HPT_U8 bDevsPerBus; 84228940Sdelphij HPT_U8 first_on_slot; 85228940Sdelphij 86228940Sdelphij HPT_U8 bChipType; 87228940Sdelphij HPT_U8 bChipIntrNum; 88228940Sdelphij HPT_U8 bChipFlags; 89228940Sdelphij HPT_U8 bNumBuses; 90228940Sdelphij 91228940Sdelphij HPT_U8 szVendorID[36]; 92228940Sdelphij HPT_U8 szProductID[36]; 93228940Sdelphij HPT_U32 nvramSize; 94228940Sdelphij HPT_U64 nvramAddress; 95228940Sdelphij HPT_U8 slot_index; 96228940Sdelphij HPT_U8 reserved2[11]; 97228940Sdelphij} 98228940SdelphijHIM_ADAPTER_CONFIG, *PHIM_ADAPTER_CONFIG; 99228940Sdelphij 100228940Sdelphijtypedef struct _HIM_CHANNEL_CONFIG 101228940Sdelphij{ 102228940Sdelphij HPT_U32 io_port; 103228940Sdelphij HPT_U32 ctl_port; 104228940Sdelphij} HIM_CHANNEL_CONFIG, *PHIM_CHANNEL_CONFIG; 105228940Sdelphij 106228940Sdelphijtypedef struct _HIM_DEVICE_FLAGS 107228940Sdelphij{ 108228940Sdelphij HPT_UINT df_atapi :1; 109228940Sdelphij HPT_UINT df_removable_drive :1; 110228940Sdelphij HPT_UINT df_on_line :1; 111228940Sdelphij HPT_UINT df_reduce_mode :1; 112228940Sdelphij HPT_UINT df_sata :1; 113228940Sdelphij HPT_UINT df_on_pm_port :1; 114228940Sdelphij HPT_UINT df_support_read_ahead :1; 115228940Sdelphij HPT_UINT df_read_ahead_enabled :1; 116228940Sdelphij HPT_UINT df_support_write_cache :1; 117228940Sdelphij HPT_UINT df_write_cache_enabled :1; 118228940Sdelphij HPT_UINT df_cdrom_device :1; 119228940Sdelphij HPT_UINT df_tape_device :1; 120228940Sdelphij HPT_UINT df_support_tcq :1; 121228940Sdelphij HPT_UINT df_tcq_enabled :1; 122228940Sdelphij HPT_UINT df_support_ncq :1; 123228940Sdelphij HPT_UINT df_ncq_enabled :1; 124228940Sdelphij HPT_UINT df_sas :1; 125228940Sdelphij HPT_UINT df_in_enclosure :1; 126228940Sdelphij HPT_UINT df_ssd :1; 127228940Sdelphij} DEVICE_FLAGS, *PDEVICE_FLAGS; 128228940Sdelphij 129228940Sdelphij#pragma pack(1) 130228940Sdelphijtypedef struct _IDENTIFY_DATA { 131228940Sdelphij HPT_U16 GeneralConfiguration; 132228940Sdelphij HPT_U16 NumberOfCylinders; 133228940Sdelphij HPT_U16 Reserved1; 134228940Sdelphij HPT_U16 NumberOfHeads; 135228940Sdelphij HPT_U16 UnformattedBytesPerTrack; 136228940Sdelphij HPT_U16 UnformattedBytesPerSector; 137228940Sdelphij HPT_U8 SasAddress[8]; 138228940Sdelphij HPT_U16 SerialNumber[10]; 139228940Sdelphij HPT_U16 BufferType; 140228940Sdelphij HPT_U16 BufferSectorSize; 141228940Sdelphij HPT_U16 NumberOfEccBytes; 142228940Sdelphij HPT_U16 FirmwareRevision[4]; 143228940Sdelphij HPT_U16 ModelNumber[20]; 144228940Sdelphij HPT_U8 MaximumBlockTransfer; 145228940Sdelphij HPT_U8 VendorUnique2; 146228940Sdelphij HPT_U16 DoubleWordIo; 147228940Sdelphij HPT_U16 Capabilities; 148228940Sdelphij HPT_U16 Reserved2; 149228940Sdelphij HPT_U8 VendorUnique3; 150228940Sdelphij HPT_U8 PioCycleTimingMode; 151228940Sdelphij HPT_U8 VendorUnique4; 152228940Sdelphij HPT_U8 DmaCycleTimingMode; 153228940Sdelphij HPT_U16 TranslationFieldsValid; 154228940Sdelphij HPT_U16 NumberOfCurrentCylinders; 155228940Sdelphij HPT_U16 NumberOfCurrentHeads; 156228940Sdelphij HPT_U16 CurrentSectorsPerTrack; 157228940Sdelphij HPT_U32 CurrentSectorCapacity; 158228940Sdelphij HPT_U16 CurrentMultiSectorSetting; 159228940Sdelphij HPT_U32 UserAddressableSectors; 160228940Sdelphij HPT_U8 SingleWordDMASupport; 161228940Sdelphij HPT_U8 SingleWordDMAActive; 162228940Sdelphij HPT_U8 MultiWordDMASupport; 163228940Sdelphij HPT_U8 MultiWordDMAActive; 164228940Sdelphij HPT_U8 AdvancedPIOModes; 165228940Sdelphij HPT_U8 Reserved4; 166228940Sdelphij HPT_U16 MinimumMWXferCycleTime; 167228940Sdelphij HPT_U16 RecommendedMWXferCycleTime; 168228940Sdelphij HPT_U16 MinimumPIOCycleTime; 169228940Sdelphij HPT_U16 MinimumPIOCycleTimeIORDY; 170228940Sdelphij HPT_U16 Reserved5[2]; 171228940Sdelphij HPT_U16 ReleaseTimeOverlapped; 172228940Sdelphij HPT_U16 ReleaseTimeServiceCommand; 173228940Sdelphij HPT_U16 MajorRevision; 174228940Sdelphij HPT_U16 MinorRevision; 175228940Sdelphij HPT_U16 MaxQueueDepth; 176228940Sdelphij HPT_U16 SataCapability; 177228940Sdelphij HPT_U16 Reserved6[9]; 178228940Sdelphij HPT_U16 CommandSupport; 179228940Sdelphij HPT_U16 CommandEnable; 180228940Sdelphij HPT_U16 UtralDmaMode; 181228940Sdelphij HPT_U16 Reserved7[11]; 182228940Sdelphij HPT_U32 Lba48BitLow; 183228940Sdelphij HPT_U32 Lba48BitHigh; 184228940Sdelphij HPT_U16 Reserved8[23]; 185228940Sdelphij HPT_U16 SpecialFunctionsEnabled; 186228940Sdelphij HPT_U16 Reserved9[128]; 187228940Sdelphij} 188228940Sdelphij#ifdef __GNUC__ 189228940Sdelphij__attribute__((packed)) 190228940Sdelphij#endif 191228940SdelphijIDENTIFY_DATA, *PIDENTIFY_DATA; 192228940Sdelphij#pragma pack() 193228940Sdelphij 194228940Sdelphijtypedef struct _HIM_DEVICE_CONFIG 195228940Sdelphij{ 196228940Sdelphij HPT_U64 capacity; 197228940Sdelphij 198228940Sdelphij DEVICE_FLAGS flags; 199228940Sdelphij 200228940Sdelphij HPT_U8 path_id; 201228940Sdelphij HPT_U8 target_id; 202228940Sdelphij HPT_U8 max_queue_depth; 203228940Sdelphij HPT_U8 spin_up_mode; 204228940Sdelphij 205228940Sdelphij HPT_U8 reserved; 206228940Sdelphij HPT_U8 transfer_mode; 207228940Sdelphij HPT_U8 bMaxShowMode; 208228940Sdelphij HPT_U8 bDeUsable_Mode; 209228940Sdelphij 210228940Sdelphij HPT_U16 max_sectors_per_cmd; 211228940Sdelphij 212228940Sdelphij PIDENTIFY_DATA pIdentifyData; 213228940Sdelphij 214228940Sdelphij 215228940Sdelphij HPT_U8 fixed_path_id; /*equals to phy id */ 216228940Sdelphij} 217228940SdelphijHIM_DEVICE_CONFIG, *PHIM_DEVICE_CONFIG; 218228940Sdelphij 219228940Sdelphij 220228940Sdelphij#define _DIT_MODE 0 221228940Sdelphij#define _DIT_601 1 222228940Sdelphij#define _DIT_READ_AHEAD 2 223228940Sdelphij#define _DIT_WRITE_CACHE 3 224228940Sdelphij#define _DIT_TCQ 4 225228940Sdelphij#define _DIT_NCQ 5 226228940Sdelphij#define _DIT_BEEP_OFF 6 227228940Sdelphij#define _DIT_SPIN_UP_MODE 7 228228940Sdelphij#define _DIT_IDLE_STANDBY 8 229228940Sdelphij#define _DIT_IDENTIFY 9 230228940Sdelphij 231228940Sdelphij#define SPIN_UP_MODE_NOSUPPORT 0 232228940Sdelphij#define SPIN_UP_MODE_FULL 1 233228940Sdelphij#define SPIN_UP_MODE_STANDBY 2 234228940Sdelphij 235228940Sdelphijstruct tcq_control { 236228940Sdelphij HPT_U8 enable; 237228940Sdelphij HPT_U8 depth; 238228940Sdelphij}; 239228940Sdelphij 240228940Sdelphijstruct ncq_control { 241228940Sdelphij HPT_U8 enable; 242228940Sdelphij HPT_U8 depth; 243228940Sdelphij}; 244228940Sdelphij 245228940Sdelphijtypedef struct _HIM_ALTERABLE_DEV_INFO{ 246228940Sdelphij HPT_U8 type; 247228940Sdelphij union { 248228940Sdelphij HPT_U8 mode; 249228940Sdelphij HPT_U8 enable_read_ahead; 250228940Sdelphij HPT_U8 enable_read_cache; 251228940Sdelphij HPT_U8 enable_write_cache; 252228940Sdelphij struct tcq_control tcq; 253228940Sdelphij struct ncq_control ncq; 254228940Sdelphij void * adapter; 255228940Sdelphij HPT_U8 spin_up_mode; 256228940Sdelphij HPT_U8 idle_standby_timeout; 257228940Sdelphij HPT_U8 identify_indicator; 258228940Sdelphij }u; 259228940Sdelphij} HIM_ALTERABLE_DEV_INFO, *PHIM_ALTERABLE_DEV_INFO; 260228940Sdelphij 261228940Sdelphijstruct _COMMAND; 262228940Sdelphijstruct _IOCTL_ARG; 263228940Sdelphij 264228940Sdelphijtypedef void (*PROBE_CALLBACK)(void *arg, void *dev, int index); 265228940Sdelphij 266228940Sdelphijtypedef struct _HIM { 267228940Sdelphij char *name; 268228940Sdelphij struct _HIM *next; 269228940Sdelphij HPT_UINT max_sg_descriptors; 270228940Sdelphij #define _HIM_INTERFACE(_type, _fn, _args) _type (* _fn) _args; 271228940Sdelphij #include <dev/hpt27xx/himfuncs.h> 272228940Sdelphij} 273228940SdelphijHIM, *PHIM; 274228940Sdelphij 275228940Sdelphij 276228940Sdelphij#pragma pack(1) 277228940Sdelphij#ifdef SG_FLAG_EOT 278228940Sdelphij#error "don't use SG_FLAG_EOT with _SG.eot. clean the code!" 279228940Sdelphij#endif 280228940Sdelphij 281228940Sdelphijtypedef struct _SG { 282228940Sdelphij HPT_U32 size; 283228940Sdelphij HPT_UINT eot; 284228940Sdelphij union { 285228940Sdelphij HPT_U8 FAR * _logical; 286228940Sdelphij BUS_ADDRESS bus; 287228940Sdelphij } 288228940Sdelphij addr; 289228940Sdelphij} 290228940SdelphijSG, *PSG; 291228940Sdelphij#pragma pack() 292228940Sdelphij 293228940Sdelphijtypedef struct _AtaCommand 294228940Sdelphij{ 295228940Sdelphij HPT_U64 Lba; 296228940Sdelphij HPT_U16 nSectors; 297228940Sdelphij HPT_U16 pad; 298228940Sdelphij} AtaComm, *PAtaComm; 299228940Sdelphij 300228940Sdelphij#define ATA_CMD_NOP 0x0 301228940Sdelphij 302228940Sdelphij#define ATA_CMD_SET_FEATURES 0xef 303228940Sdelphij#define ATA_CMD_FLUSH 0xE7 304228940Sdelphij#define ATA_CMD_VERIFY 0x40 305228940Sdelphij#define ATA_CMD_STANDBY 0xe2 306228940Sdelphij#define ATA_CMD_READ_MULTI 0xC4 307228940Sdelphij#define ATA_CMD_READ_MULTI_EXT 0x29 308228940Sdelphij#define ATA_CMD_WRITE_MULTI 0xC5 309228940Sdelphij#define ATA_CMD_WRITE_MULTI_EXT 0x39 310228940Sdelphij#define ATA_CMD_WRITE_MULTI_FUA_EXT 0xCE 311228940Sdelphij 312228940Sdelphij#define ATA_CMD_READ_DMA 0xc8 /* IDE DMA read command */ 313228940Sdelphij#define ATA_CMD_WRITE_DMA 0xca /* IDE DMA write command */ 314228940Sdelphij#define ATA_CMD_READ_DMA_EXT 0x25 315228940Sdelphij#define ATA_CMD_READ_QUEUE_EXT 0x26 316228940Sdelphij#define ATA_CMD_READ_MAX_ADDR 0x27 317228940Sdelphij#define ATA_CMD_READ_EXT 0x24 318228940Sdelphij#define ATA_CMD_VERIFY_EXT 0x42 319228940Sdelphij#define ATA_CMD_WRITE_DMA_EXT 0x35 320228940Sdelphij#define ATA_CMD_WRITE_QUEUE_EXT 0x36 321228940Sdelphij#define ATA_CMD_WRITE_EXT 0x34 322228940Sdelphij 323228940Sdelphij#define ATA_SET_FEATURES_XFER 0x3 324228940Sdelphij#define ATA_SECTOR_SIZE 512 325228940Sdelphij 326228940Sdelphijtypedef struct _PassthroughCmd { 327228940Sdelphij HPT_U16 bFeaturesReg; 328228940Sdelphij HPT_U16 bSectorCountReg; 329228940Sdelphij HPT_U16 bLbaLowReg; 330228940Sdelphij HPT_U16 bLbaMidReg; 331228940Sdelphij HPT_U16 bLbaHighReg; 332228940Sdelphij HPT_U8 bDriveHeadReg; 333228940Sdelphij HPT_U8 bCommandReg; 334228940Sdelphij HPT_U16 nSectors; 335228940Sdelphij HPT_U8 *pDataBuffer; 336228940Sdelphij} 337228940SdelphijPassthroughCmd; 338228940Sdelphij 339228940Sdelphijtypedef struct _ScsiComm { 340228940Sdelphij HPT_U8 cdbLength; 341228940Sdelphij HPT_U8 senseLength; 342228940Sdelphij HPT_U8 scsiStatus; 343228940Sdelphij HPT_U8 reserve1; 344228940Sdelphij HPT_U32 dataLength; 345228940Sdelphij HPT_U8 *cdb; 346228940Sdelphij HPT_U8 *senseBuffer; 347228940Sdelphij} 348228940SdelphijScsiComm; 349228940Sdelphij 350228940Sdelphij 351228940Sdelphij#define CTRL_CMD_REBUILD 1 352228940Sdelphij#define CTRL_CMD_VERIFY 2 353228940Sdelphij#define CTRL_CMD_INIT 3 354228940Sdelphij 355228940Sdelphij 356228940Sdelphijtypedef struct _R5ControlCmd { 357228940Sdelphij HPT_U64 StripeLine; 358228940Sdelphij HPT_U16 Offset; 359228940Sdelphij HPT_U8 Command; 360228940Sdelphij HPT_U8 reserve1; 361228940Sdelphij} 362228940SdelphijR5ControlCmd, *PR5ControlCmd; 363228940Sdelphij 364228940Sdelphijtypedef struct _HPT_ADDRESS 365228940Sdelphij{ 366228940Sdelphij HPT_U8 * logical; 367228940Sdelphij BUS_ADDRESS bus; 368228940Sdelphij} 369228940SdelphijHPT_ADDRESS; 370228940Sdelphij 371228940Sdelphij 372228940Sdelphijtypedef struct ctl_pages { 373228940Sdelphij HPT_ADDRESS *pages; 374228940Sdelphij HPT_UINT page_size; 375228940Sdelphij HPT_UINT npages; 376228940Sdelphij HPT_UINT min_sg_descriptors; 377228940Sdelphij} CONTROL_PAGES, *PCONTROL_PAGES; 378228940Sdelphij 379228940Sdelphijtypedef struct _R1ControlCmd { 380228940Sdelphij HPT_U64 Lba; 381228940Sdelphij HPT_U16 nSectors; 382228940Sdelphij HPT_U8 Command; /* CTRL_CMD_XXX */ 383228940Sdelphij HPT_U8 reserve1; 384228940Sdelphij PCONTROL_PAGES ctl_pages; 385228940Sdelphij} 386228940SdelphijR1ControlCmd, *PR1ControlCmd; 387228940Sdelphij 388228940Sdelphijtypedef void (*TQ_PROC)(void *arg); 389228940Sdelphij 390228940Sdelphijstruct tq_item { 391228940Sdelphij TQ_PROC proc; 392228940Sdelphij void *arg; 393228940Sdelphij struct tq_item *next; 394228940Sdelphij}; 395228940Sdelphij 396228940Sdelphij#define INIT_TQ_ITEM(t, p, a) \ 397228940Sdelphij do { (t)->proc = p; (t)->arg = a; (t)->next = 0; } while (0) 398228940Sdelphij 399228940Sdelphijtypedef struct _COMMAND 400228940Sdelphij{ 401228940Sdelphij 402228940Sdelphij struct _VBUS * vbus; 403228940Sdelphij 404228940Sdelphij struct freelist *grplist; 405228940Sdelphij HPT_UINT grpcnt; 406228940Sdelphij 407228940Sdelphij 408228940Sdelphij struct list_head q_link; 409228940Sdelphij struct tq_item done_dpc; 410228940Sdelphij 411228940Sdelphij HPT_UINT extsize; 412228940Sdelphij void *ext; 413228940Sdelphij 414228940Sdelphij 415228940Sdelphij 416228940Sdelphij void *target; 417228940Sdelphij void *priv; 418228940Sdelphij HPT_UPTR priv2; 419228940Sdelphij 420228940Sdelphij int priority; 421228940Sdelphij struct lock_request *owned_lock; 422228940Sdelphij struct lock_request *lock_req; 423228940Sdelphij void (*dtor)(struct _COMMAND *, void *); 424228940Sdelphij void *dtor_arg; 425228940Sdelphij 426228940Sdelphij union{ 427228940Sdelphij AtaComm Ide; 428228940Sdelphij PassthroughCmd Passthrough; 429228940Sdelphij ScsiComm Scsi; 430228940Sdelphij R5ControlCmd R5Control; 431228940Sdelphij R1ControlCmd R1Control; 432228940Sdelphij } uCmd; 433228940Sdelphij 434228940Sdelphij HPT_U8 type; /* CMD_TYPE_* */ 435228940Sdelphij 436228940Sdelphij struct { 437228940Sdelphij HPT_U8 physical_sg: 1; 438228940Sdelphij HPT_U8 data_in: 1; 439228940Sdelphij HPT_U8 data_out: 1; 440228940Sdelphij HPT_U8 transform : 1; 441228940Sdelphij HPT_U8 hard_flush: 2; 442228940Sdelphij HPT_U8 from_cc: 1; 443228940Sdelphij HPT_U8 force_cc: 1; 444228940Sdelphij } flags; 445228940Sdelphij 446228940Sdelphij /* return status */ 447228940Sdelphij HPT_U8 Result; 448228940Sdelphij /* retry count */ 449228940Sdelphij HPT_U8 RetryCount; 450228940Sdelphij 451228940Sdelphij 452228940Sdelphij PSG psg; 453228940Sdelphij 454228940Sdelphij 455228940Sdelphij int (*buildsgl)(struct _COMMAND *cmd, PSG psg, int logical); 456228940Sdelphij void (*done)(struct _COMMAND *cmd); 457228940Sdelphij} 458228940SdelphijCOMMAND, *PCOMMAND; 459228940Sdelphij 460228940Sdelphij/* command types */ 461228940Sdelphij#define CMD_TYPE_IO 0 462228940Sdelphij#define CMD_TYPE_CONTROL 1 463228940Sdelphij#define CMD_TYPE_ATAPI 2 464228940Sdelphij#define CMD_TYPE_SCSI CMD_TYPE_ATAPI 465228940Sdelphij#define CMD_TYPE_PASSTHROUGH 3 466228940Sdelphij#define CMD_TYPE_FLUSH 4 467228940Sdelphij#define CMD_TYPE_IO_INDIRECT 0x80 468228940Sdelphij 469228940Sdelphij/* flush command flags */ 470228940Sdelphij#define CF_HARD_FLUSH_CACHE 1 471228940Sdelphij#define CF_HARD_FLUSH_STANDBY 2 472228940Sdelphij 473228940Sdelphij/* command return values */ 474228940Sdelphij#define RETURN_PENDING 0 475228940Sdelphij#define RETURN_SUCCESS 1 476228940Sdelphij#define RETURN_BAD_DEVICE 2 477228940Sdelphij#define RETURN_BAD_PARAMETER 3 478228940Sdelphij#define RETURN_WRITE_NO_DRQ 4 479228940Sdelphij#define RETURN_DEVICE_BUSY 5 480228940Sdelphij#define RETURN_INVALID_REQUEST 6 481228940Sdelphij#define RETURN_SELECTION_TIMEOUT 7 482228940Sdelphij#define RETURN_IDE_ERROR 8 483228940Sdelphij#define RETURN_NEED_LOGICAL_SG 9 484228940Sdelphij#define RETURN_NEED_PHYSICAL_SG 10 485228940Sdelphij#define RETURN_RETRY 11 486228940Sdelphij#define RETURN_DATA_ERROR 12 487228940Sdelphij#define RETURN_BUS_RESET 13 488228940Sdelphij#define RETURN_BAD_TRANSFER_LENGTH 14 489228940Sdelphij#define RETURN_INSUFFICIENT_MEMORY 15 490228940Sdelphij#define RETURN_SECTOR_ERROR 16 491228940Sdelphij#define RETURN_NEED_SPINUP 17 492228940Sdelphij 493228940Sdelphij#if defined(__cplusplus) 494228940Sdelphij} 495228940Sdelphij#endif 496228940Sdelphij#endif 497