if_hatm.c revision 139749
1139749Simp/*- 2116491Sharti * Copyright (c) 2001-2003 3116491Sharti * Fraunhofer Institute for Open Communication Systems (FhG Fokus). 4116491Sharti * All rights reserved. 5116491Sharti * 6116491Sharti * Redistribution and use in source and binary forms, with or without 7116491Sharti * modification, are permitted provided that the following conditions 8116491Sharti * are met: 9116491Sharti * 1. Redistributions of source code must retain the above copyright 10116491Sharti * notice, this list of conditions and the following disclaimer. 11116491Sharti * 2. Redistributions in binary form must reproduce the above copyright 12116491Sharti * notice, this list of conditions and the following disclaimer in the 13116491Sharti * documentation and/or other materials provided with the distribution. 14116491Sharti * 15116491Sharti * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16116491Sharti * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17116491Sharti * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18116491Sharti * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19116491Sharti * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20116491Sharti * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21116491Sharti * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22116491Sharti * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23116491Sharti * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24116491Sharti * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25116491Sharti * SUCH DAMAGE. 26116491Sharti * 27116491Sharti * Author: Hartmut Brandt <harti@freebsd.org> 28116491Sharti * 29116491Sharti * ForeHE driver. 30116491Sharti * 31116491Sharti * This file contains the module and driver infrastructure stuff as well 32116491Sharti * as a couple of utility functions and the entire initialisation. 33116491Sharti */ 34116519Sharti 35116519Sharti#include <sys/cdefs.h> 36116519Sharti__FBSDID("$FreeBSD: head/sys/dev/hatm/if_hatm.c 139749 2005-01-06 01:43:34Z imp $"); 37116519Sharti 38116491Sharti#include "opt_inet.h" 39116491Sharti#include "opt_natm.h" 40116491Sharti 41116491Sharti#include <sys/types.h> 42116491Sharti#include <sys/param.h> 43116491Sharti#include <sys/systm.h> 44116491Sharti#include <sys/malloc.h> 45116491Sharti#include <sys/kernel.h> 46116491Sharti#include <sys/bus.h> 47116491Sharti#include <sys/errno.h> 48116491Sharti#include <sys/conf.h> 49116491Sharti#include <sys/module.h> 50116491Sharti#include <sys/queue.h> 51116491Sharti#include <sys/syslog.h> 52116491Sharti#include <sys/lock.h> 53116491Sharti#include <sys/mutex.h> 54116491Sharti#include <sys/condvar.h> 55116491Sharti#include <sys/sysctl.h> 56116491Sharti#include <vm/uma.h> 57116491Sharti 58116491Sharti#include <sys/sockio.h> 59116491Sharti#include <sys/mbuf.h> 60116491Sharti#include <sys/socket.h> 61116491Sharti 62116491Sharti#include <net/if.h> 63116491Sharti#include <net/if_media.h> 64116491Sharti#include <net/if_atm.h> 65116491Sharti#include <net/route.h> 66116491Sharti#ifdef ENABLE_BPF 67116491Sharti#include <net/bpf.h> 68116491Sharti#endif 69116491Sharti#include <netinet/in.h> 70116491Sharti#include <netinet/if_atm.h> 71116491Sharti 72116491Sharti#include <machine/bus.h> 73116491Sharti#include <machine/resource.h> 74116491Sharti#include <sys/bus.h> 75116491Sharti#include <sys/rman.h> 76119280Simp#include <dev/pci/pcireg.h> 77119280Simp#include <dev/pci/pcivar.h> 78116491Sharti 79116491Sharti#include <dev/utopia/utopia.h> 80116491Sharti#include <dev/hatm/if_hatmconf.h> 81116491Sharti#include <dev/hatm/if_hatmreg.h> 82116491Sharti#include <dev/hatm/if_hatmvar.h> 83116491Sharti 84116491Shartistatic const struct { 85116491Sharti uint16_t vid; 86116491Sharti uint16_t did; 87116491Sharti const char *name; 88116491Sharti} hatm_devs[] = { 89116491Sharti { 0x1127, 0x400, 90116491Sharti "FORE HE" }, 91116491Sharti { 0, 0, NULL } 92116491Sharti}; 93116491Sharti 94116491ShartiSYSCTL_DECL(_hw_atm); 95116491Sharti 96116491ShartiMODULE_DEPEND(hatm, utopia, 1, 1, 1); 97116491ShartiMODULE_DEPEND(hatm, pci, 1, 1, 1); 98116491ShartiMODULE_DEPEND(hatm, atm, 1, 1, 1); 99116491Sharti 100116491Sharti#define EEPROM_DELAY 400 /* microseconds */ 101116491Sharti 102116491Sharti/* Read from EEPROM 0000 0011b */ 103116491Shartistatic const uint32_t readtab[] = { 104116491Sharti HE_REGM_HOST_PROM_SEL | HE_REGM_HOST_PROM_CLOCK, 105116491Sharti 0, 106116491Sharti HE_REGM_HOST_PROM_CLOCK, 107116491Sharti 0, /* 0 */ 108116491Sharti HE_REGM_HOST_PROM_CLOCK, 109116491Sharti 0, /* 0 */ 110116491Sharti HE_REGM_HOST_PROM_CLOCK, 111116491Sharti 0, /* 0 */ 112116491Sharti HE_REGM_HOST_PROM_CLOCK, 113116491Sharti 0, /* 0 */ 114116491Sharti HE_REGM_HOST_PROM_CLOCK, 115116491Sharti 0, /* 0 */ 116116491Sharti HE_REGM_HOST_PROM_CLOCK, 117116491Sharti HE_REGM_HOST_PROM_DATA_IN, /* 0 */ 118116491Sharti HE_REGM_HOST_PROM_CLOCK | HE_REGM_HOST_PROM_DATA_IN, 119116491Sharti HE_REGM_HOST_PROM_DATA_IN, /* 1 */ 120116491Sharti HE_REGM_HOST_PROM_CLOCK | HE_REGM_HOST_PROM_DATA_IN, 121116491Sharti HE_REGM_HOST_PROM_DATA_IN, /* 1 */ 122116491Sharti}; 123116491Shartistatic const uint32_t clocktab[] = { 124116491Sharti 0, HE_REGM_HOST_PROM_CLOCK, 125116491Sharti 0, HE_REGM_HOST_PROM_CLOCK, 126116491Sharti 0, HE_REGM_HOST_PROM_CLOCK, 127116491Sharti 0, HE_REGM_HOST_PROM_CLOCK, 128116491Sharti 0, HE_REGM_HOST_PROM_CLOCK, 129116491Sharti 0, HE_REGM_HOST_PROM_CLOCK, 130116491Sharti 0, HE_REGM_HOST_PROM_CLOCK, 131116491Sharti 0, HE_REGM_HOST_PROM_CLOCK, 132116491Sharti 0 133116491Sharti}; 134116491Sharti 135116491Sharti/* 136116491Sharti * Convert cell rate to ATM Forum format 137116491Sharti */ 138116491Shartiu_int 139116491Shartihatm_cps2atmf(uint32_t pcr) 140116491Sharti{ 141116491Sharti u_int e; 142116491Sharti 143116491Sharti if (pcr == 0) 144116491Sharti return (0); 145116491Sharti pcr <<= 9; 146116491Sharti e = 0; 147116491Sharti while (pcr > (1024 - 1)) { 148116491Sharti e++; 149116491Sharti pcr >>= 1; 150116491Sharti } 151116491Sharti return ((1 << 14) | (e << 9) | (pcr & 0x1ff)); 152116491Sharti} 153116491Shartiu_int 154116491Shartihatm_atmf2cps(uint32_t fcr) 155116491Sharti{ 156116491Sharti fcr &= 0x7fff; 157116491Sharti 158116491Sharti return ((1 << ((fcr >> 9) & 0x1f)) * (512 + (fcr & 0x1ff)) / 512 159116491Sharti * (fcr >> 14)); 160116491Sharti} 161116491Sharti 162116491Sharti/************************************************************ 163116491Sharti * 164116491Sharti * Initialisation 165116491Sharti */ 166116491Sharti/* 167116491Sharti * Probe for a HE controller 168116491Sharti */ 169116491Shartistatic int 170116491Shartihatm_probe(device_t dev) 171116491Sharti{ 172116491Sharti int i; 173116491Sharti 174116491Sharti for (i = 0; hatm_devs[i].name; i++) 175116491Sharti if (pci_get_vendor(dev) == hatm_devs[i].vid && 176116491Sharti pci_get_device(dev) == hatm_devs[i].did) { 177116491Sharti device_set_desc(dev, hatm_devs[i].name); 178116491Sharti return (0); 179116491Sharti } 180116491Sharti return (ENXIO); 181116491Sharti} 182116491Sharti 183116491Sharti/* 184116491Sharti * Allocate and map DMA-able memory. We support only contiguous mappings. 185116491Sharti */ 186116491Shartistatic void 187116491Shartidmaload_helper(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 188116491Sharti{ 189116491Sharti if (error) 190116491Sharti return; 191116491Sharti KASSERT(nsegs == 1, ("too many segments for DMA: %d", nsegs)); 192116491Sharti KASSERT(segs[0].ds_addr <= 0xffffffffUL, 193116491Sharti ("phys addr too large %lx", (u_long)segs[0].ds_addr)); 194116491Sharti 195116491Sharti *(bus_addr_t *)arg = segs[0].ds_addr; 196116491Sharti} 197116491Shartistatic int 198116491Shartihatm_alloc_dmamem(struct hatm_softc *sc, const char *what, struct dmamem *mem) 199116491Sharti{ 200116491Sharti int error; 201116491Sharti 202116491Sharti mem->base = NULL; 203116491Sharti 204116491Sharti /* 205116491Sharti * Alignement does not work in the bus_dmamem_alloc function below 206116491Sharti * on FreeBSD. malloc seems to align objects at least to the object 207116491Sharti * size so increase the size to the alignment if the size is lesser 208116491Sharti * than the alignemnt. 209116491Sharti * XXX on sparc64 this is (probably) not needed. 210116491Sharti */ 211116491Sharti if (mem->size < mem->align) 212116491Sharti mem->size = mem->align; 213116491Sharti 214116491Sharti error = bus_dma_tag_create(sc->parent_tag, mem->align, 0, 215116491Sharti BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 216116491Sharti NULL, NULL, mem->size, 1, 217117126Sscottl BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW, 218117382Sharti NULL, NULL, &mem->tag); 219116491Sharti if (error) { 220116491Sharti if_printf(&sc->ifatm.ifnet, "DMA tag create (%s)\n", what); 221116491Sharti return (error); 222116491Sharti } 223116491Sharti 224116491Sharti error = bus_dmamem_alloc(mem->tag, &mem->base, 0, &mem->map); 225116491Sharti if (error) { 226116491Sharti if_printf(&sc->ifatm.ifnet, "DMA mem alloc (%s): %d\n", 227116491Sharti what, error); 228116491Sharti bus_dma_tag_destroy(mem->tag); 229116491Sharti mem->base = NULL; 230116491Sharti return (error); 231116491Sharti } 232116491Sharti 233116491Sharti error = bus_dmamap_load(mem->tag, mem->map, mem->base, mem->size, 234117382Sharti dmaload_helper, &mem->paddr, BUS_DMA_NOWAIT); 235116491Sharti if (error) { 236116491Sharti if_printf(&sc->ifatm.ifnet, "DMA map load (%s): %d\n", 237116491Sharti what, error); 238116491Sharti bus_dmamem_free(mem->tag, mem->base, mem->map); 239116491Sharti bus_dma_tag_destroy(mem->tag); 240116491Sharti mem->base = NULL; 241116491Sharti return (error); 242116491Sharti } 243116491Sharti 244116491Sharti DBG(sc, DMA, ("%s S/A/V/P 0x%x 0x%x %p 0x%lx", what, mem->size, 245116491Sharti mem->align, mem->base, (u_long)mem->paddr)); 246116491Sharti 247116491Sharti return (0); 248116491Sharti} 249116491Sharti 250116491Sharti/* 251116491Sharti * Destroy all the resources of an DMA-able memory region. 252116491Sharti */ 253116491Shartistatic void 254116491Shartihatm_destroy_dmamem(struct dmamem *mem) 255116491Sharti{ 256116491Sharti if (mem->base != NULL) { 257116491Sharti bus_dmamap_unload(mem->tag, mem->map); 258116491Sharti bus_dmamem_free(mem->tag, mem->base, mem->map); 259116491Sharti (void)bus_dma_tag_destroy(mem->tag); 260116491Sharti mem->base = NULL; 261116491Sharti } 262116491Sharti} 263116491Sharti 264116491Sharti/* 265116491Sharti * Initialize/destroy DMA maps for the large pool 0 266116491Sharti */ 267116491Shartistatic void 268116491Shartihatm_destroy_rmaps(struct hatm_softc *sc) 269116491Sharti{ 270116491Sharti u_int b; 271116491Sharti 272116491Sharti DBG(sc, ATTACH, ("destroying rmaps and lbuf pointers...")); 273116491Sharti if (sc->rmaps != NULL) { 274116491Sharti for (b = 0; b < sc->lbufs_size; b++) 275116491Sharti bus_dmamap_destroy(sc->mbuf_tag, sc->rmaps[b]); 276116491Sharti free(sc->rmaps, M_DEVBUF); 277116491Sharti } 278116491Sharti if (sc->lbufs != NULL) 279116491Sharti free(sc->lbufs, M_DEVBUF); 280116491Sharti} 281116491Sharti 282116491Shartistatic void 283116491Shartihatm_init_rmaps(struct hatm_softc *sc) 284116491Sharti{ 285116491Sharti u_int b; 286116491Sharti int err; 287116491Sharti 288116491Sharti DBG(sc, ATTACH, ("allocating rmaps and lbuf pointers...")); 289116491Sharti sc->lbufs = malloc(sizeof(sc->lbufs[0]) * sc->lbufs_size, 290116491Sharti M_DEVBUF, M_ZERO | M_WAITOK); 291116491Sharti 292116491Sharti /* allocate and create the DMA maps for the large pool */ 293116491Sharti sc->rmaps = malloc(sizeof(sc->rmaps[0]) * sc->lbufs_size, 294116491Sharti M_DEVBUF, M_WAITOK); 295116491Sharti for (b = 0; b < sc->lbufs_size; b++) { 296116491Sharti err = bus_dmamap_create(sc->mbuf_tag, 0, &sc->rmaps[b]); 297116491Sharti if (err != 0) 298116491Sharti panic("bus_dmamap_create: %d\n", err); 299116491Sharti } 300116491Sharti} 301116491Sharti 302116491Sharti/* 303116491Sharti * Initialize and destroy small mbuf page pointers and pages 304116491Sharti */ 305116491Shartistatic void 306116491Shartihatm_destroy_smbufs(struct hatm_softc *sc) 307116491Sharti{ 308116491Sharti u_int i, b; 309116491Sharti struct mbuf_page *pg; 310121729Sharti struct mbuf_chunk_hdr *h; 311116491Sharti 312116491Sharti if (sc->mbuf_pages != NULL) { 313116491Sharti for (i = 0; i < sc->mbuf_npages; i++) { 314116491Sharti pg = sc->mbuf_pages[i]; 315116491Sharti for (b = 0; b < pg->hdr.nchunks; b++) { 316121729Sharti h = (struct mbuf_chunk_hdr *) ((char *)pg + 317121729Sharti b * pg->hdr.chunksize + pg->hdr.hdroff); 318121729Sharti if (h->flags & MBUF_CARD) 319116491Sharti if_printf(&sc->ifatm.ifnet, 320116491Sharti "%s -- mbuf page=%u card buf %u\n", 321116491Sharti __func__, i, b); 322121729Sharti if (h->flags & MBUF_USED) 323121729Sharti if_printf(&sc->ifatm.ifnet, 324121729Sharti "%s -- mbuf page=%u used buf %u\n", 325121729Sharti __func__, i, b); 326116491Sharti } 327116491Sharti bus_dmamap_unload(sc->mbuf_tag, pg->hdr.map); 328116491Sharti bus_dmamap_destroy(sc->mbuf_tag, pg->hdr.map); 329116491Sharti free(pg, M_DEVBUF); 330116491Sharti } 331116491Sharti free(sc->mbuf_pages, M_DEVBUF); 332116491Sharti } 333116491Sharti} 334116491Sharti 335116491Shartistatic void 336116491Shartihatm_init_smbufs(struct hatm_softc *sc) 337116491Sharti{ 338116491Sharti sc->mbuf_pages = malloc(sizeof(sc->mbuf_pages[0]) * 339121685Sharti sc->mbuf_max_pages, M_DEVBUF, M_WAITOK); 340116491Sharti sc->mbuf_npages = 0; 341116491Sharti} 342116491Sharti 343116491Sharti/* 344116491Sharti * Initialize/destroy TPDs. This is called from attach/detach. 345116491Sharti */ 346116491Shartistatic void 347116491Shartihatm_destroy_tpds(struct hatm_softc *sc) 348116491Sharti{ 349116491Sharti struct tpd *t; 350116491Sharti 351116491Sharti if (sc->tpds.base == NULL) 352116491Sharti return; 353116491Sharti 354116491Sharti DBG(sc, ATTACH, ("releasing TPDs ...")); 355116491Sharti if (sc->tpd_nfree != sc->tpd_total) 356116491Sharti if_printf(&sc->ifatm.ifnet, "%u tpds still in use from %u\n", 357116491Sharti sc->tpd_total - sc->tpd_nfree, sc->tpd_total); 358116491Sharti while ((t = SLIST_FIRST(&sc->tpd_free)) != NULL) { 359116491Sharti SLIST_REMOVE_HEAD(&sc->tpd_free, link); 360116491Sharti bus_dmamap_destroy(sc->tx_tag, t->map); 361116491Sharti } 362116491Sharti hatm_destroy_dmamem(&sc->tpds); 363116491Sharti free(sc->tpd_used, M_DEVBUF); 364116491Sharti DBG(sc, ATTACH, ("... done")); 365116491Sharti} 366116491Shartistatic int 367116491Shartihatm_init_tpds(struct hatm_softc *sc) 368116491Sharti{ 369116491Sharti int error; 370116491Sharti u_int i; 371116491Sharti struct tpd *t; 372116491Sharti 373116491Sharti DBG(sc, ATTACH, ("allocating %u TPDs and maps ...", sc->tpd_total)); 374116491Sharti error = hatm_alloc_dmamem(sc, "TPD memory", &sc->tpds); 375116491Sharti if (error != 0) { 376116491Sharti DBG(sc, ATTACH, ("... dmamem error=%d", error)); 377116491Sharti return (error); 378116491Sharti } 379116491Sharti 380116491Sharti /* put all the TPDs on the free list and allocate DMA maps */ 381116491Sharti for (i = 0; i < sc->tpd_total; i++) { 382116491Sharti t = TPD_ADDR(sc, i); 383116491Sharti t->no = i; 384116491Sharti t->mbuf = NULL; 385116491Sharti error = bus_dmamap_create(sc->tx_tag, 0, &t->map); 386116491Sharti if (error != 0) { 387116491Sharti DBG(sc, ATTACH, ("... dmamap error=%d", error)); 388116491Sharti while ((t = SLIST_FIRST(&sc->tpd_free)) != NULL) { 389116491Sharti SLIST_REMOVE_HEAD(&sc->tpd_free, link); 390116491Sharti bus_dmamap_destroy(sc->tx_tag, t->map); 391116491Sharti } 392116491Sharti hatm_destroy_dmamem(&sc->tpds); 393116491Sharti return (error); 394116491Sharti } 395116491Sharti 396116491Sharti SLIST_INSERT_HEAD(&sc->tpd_free, t, link); 397116491Sharti } 398116491Sharti 399116491Sharti /* allocate and zero bitmap */ 400116491Sharti sc->tpd_used = malloc(sizeof(uint8_t) * (sc->tpd_total + 7) / 8, 401116491Sharti M_DEVBUF, M_ZERO | M_WAITOK); 402116491Sharti sc->tpd_nfree = sc->tpd_total; 403116491Sharti 404116491Sharti DBG(sc, ATTACH, ("... done")); 405116491Sharti 406116491Sharti return (0); 407116491Sharti} 408116491Sharti 409116491Sharti/* 410116491Sharti * Free all the TPDs that where given to the card. 411116491Sharti * An mbuf chain may be attached to a TPD - free it also and 412116491Sharti * unload its associated DMA map. 413116491Sharti */ 414116491Shartistatic void 415116491Shartihatm_stop_tpds(struct hatm_softc *sc) 416116491Sharti{ 417116491Sharti u_int i; 418116491Sharti struct tpd *t; 419116491Sharti 420116491Sharti DBG(sc, ATTACH, ("free TPDs ...")); 421116491Sharti for (i = 0; i < sc->tpd_total; i++) { 422116491Sharti if (TPD_TST_USED(sc, i)) { 423116491Sharti t = TPD_ADDR(sc, i); 424116491Sharti if (t->mbuf) { 425116491Sharti m_freem(t->mbuf); 426116491Sharti t->mbuf = NULL; 427116491Sharti bus_dmamap_unload(sc->tx_tag, t->map); 428116491Sharti } 429116491Sharti TPD_CLR_USED(sc, i); 430116491Sharti SLIST_INSERT_HEAD(&sc->tpd_free, t, link); 431116491Sharti sc->tpd_nfree++; 432116491Sharti } 433116491Sharti } 434116491Sharti} 435116491Sharti 436116491Sharti/* 437116491Sharti * This frees ALL resources of this interface and leaves the structure 438116491Sharti * in an indeterminate state. This is called just before detaching or 439116491Sharti * on a failed attach. No lock should be held. 440116491Sharti */ 441116491Shartistatic void 442116491Shartihatm_destroy(struct hatm_softc *sc) 443116491Sharti{ 444118598Sharti u_int cid; 445118598Sharti 446116491Sharti bus_teardown_intr(sc->dev, sc->irqres, sc->ih); 447116491Sharti 448116491Sharti hatm_destroy_rmaps(sc); 449116491Sharti hatm_destroy_smbufs(sc); 450116491Sharti hatm_destroy_tpds(sc); 451116491Sharti 452118598Sharti if (sc->vcc_zone != NULL) { 453118598Sharti for (cid = 0; cid < HE_MAX_VCCS; cid++) 454118598Sharti if (sc->vccs[cid] != NULL) 455118598Sharti uma_zfree(sc->vcc_zone, sc->vccs[cid]); 456116491Sharti uma_zdestroy(sc->vcc_zone); 457118598Sharti } 458116491Sharti 459116491Sharti /* 460116491Sharti * Release all memory allocated to the various queues and 461116491Sharti * Status pages. These have there own flag which shows whether 462116491Sharti * they are really allocated. 463116491Sharti */ 464116491Sharti hatm_destroy_dmamem(&sc->irq_0.mem); 465116491Sharti hatm_destroy_dmamem(&sc->rbp_s0.mem); 466116491Sharti hatm_destroy_dmamem(&sc->rbp_l0.mem); 467116491Sharti hatm_destroy_dmamem(&sc->rbp_s1.mem); 468116491Sharti hatm_destroy_dmamem(&sc->rbrq_0.mem); 469116491Sharti hatm_destroy_dmamem(&sc->rbrq_1.mem); 470116491Sharti hatm_destroy_dmamem(&sc->tbrq.mem); 471116491Sharti hatm_destroy_dmamem(&sc->tpdrq.mem); 472116491Sharti hatm_destroy_dmamem(&sc->hsp_mem); 473116491Sharti 474116491Sharti if (sc->irqres != NULL) 475116491Sharti bus_release_resource(sc->dev, SYS_RES_IRQ, 476116491Sharti sc->irqid, sc->irqres); 477116491Sharti 478116491Sharti if (sc->tx_tag != NULL) 479116491Sharti if (bus_dma_tag_destroy(sc->tx_tag)) 480116491Sharti if_printf(&sc->ifatm.ifnet, "mbuf DMA tag busy\n"); 481116491Sharti 482116491Sharti if (sc->mbuf_tag != NULL) 483116491Sharti if (bus_dma_tag_destroy(sc->mbuf_tag)) 484116491Sharti if_printf(&sc->ifatm.ifnet, "mbuf DMA tag busy\n"); 485116491Sharti 486116491Sharti if (sc->parent_tag != NULL) 487116491Sharti if (bus_dma_tag_destroy(sc->parent_tag)) 488116491Sharti if_printf(&sc->ifatm.ifnet, "parent DMA tag busy\n"); 489116491Sharti 490116491Sharti if (sc->memres != NULL) 491116491Sharti bus_release_resource(sc->dev, SYS_RES_MEMORY, 492116491Sharti sc->memid, sc->memres); 493116491Sharti 494116491Sharti sysctl_ctx_free(&sc->sysctl_ctx); 495116491Sharti 496116491Sharti cv_destroy(&sc->cv_rcclose); 497116491Sharti cv_destroy(&sc->vcc_cv); 498116491Sharti mtx_destroy(&sc->mtx); 499116491Sharti} 500116491Sharti 501116491Sharti/* 502116491Sharti * 4.4 Card reset 503116491Sharti */ 504116491Shartistatic int 505116491Shartihatm_reset(struct hatm_softc *sc) 506116491Sharti{ 507116491Sharti u_int v, count; 508116491Sharti 509116491Sharti WRITE4(sc, HE_REGO_RESET_CNTL, 0x00); 510116491Sharti BARRIER_W(sc); 511116491Sharti WRITE4(sc, HE_REGO_RESET_CNTL, 0xff); 512116491Sharti BARRIER_RW(sc); 513116491Sharti count = 0; 514116491Sharti while (((v = READ4(sc, HE_REGO_RESET_CNTL)) & HE_REGM_RESET_STATE) == 0) { 515116491Sharti BARRIER_R(sc); 516116491Sharti if (++count == 100) { 517116491Sharti if_printf(&sc->ifatm.ifnet, "reset failed\n"); 518116491Sharti return (ENXIO); 519116491Sharti } 520116491Sharti DELAY(1000); 521116491Sharti } 522116491Sharti return (0); 523116491Sharti} 524116491Sharti 525116491Sharti/* 526116491Sharti * 4.5 Set Bus Width 527116491Sharti */ 528116491Shartistatic void 529116491Shartihatm_init_bus_width(struct hatm_softc *sc) 530116491Sharti{ 531116491Sharti uint32_t v, v1; 532116491Sharti 533116491Sharti v = READ4(sc, HE_REGO_HOST_CNTL); 534116491Sharti BARRIER_R(sc); 535116491Sharti if (v & HE_REGM_HOST_BUS64) { 536116491Sharti sc->pci64 = 1; 537116491Sharti v1 = pci_read_config(sc->dev, HE_PCIR_GEN_CNTL_0, 4); 538116491Sharti v1 |= HE_PCIM_CTL0_64BIT; 539116491Sharti pci_write_config(sc->dev, HE_PCIR_GEN_CNTL_0, v1, 4); 540116491Sharti 541116491Sharti v |= HE_REGM_HOST_DESC_RD64 542116491Sharti | HE_REGM_HOST_DATA_RD64 543116491Sharti | HE_REGM_HOST_DATA_WR64; 544116491Sharti WRITE4(sc, HE_REGO_HOST_CNTL, v); 545116491Sharti BARRIER_W(sc); 546116491Sharti } else { 547116491Sharti sc->pci64 = 0; 548116491Sharti v = pci_read_config(sc->dev, HE_PCIR_GEN_CNTL_0, 4); 549116491Sharti v &= ~HE_PCIM_CTL0_64BIT; 550116491Sharti pci_write_config(sc->dev, HE_PCIR_GEN_CNTL_0, v, 4); 551116491Sharti } 552116491Sharti} 553116491Sharti 554116491Sharti/* 555116491Sharti * 4.6 Set Host Endianess 556116491Sharti */ 557116491Shartistatic void 558116491Shartihatm_init_endianess(struct hatm_softc *sc) 559116491Sharti{ 560116491Sharti uint32_t v; 561116491Sharti 562116491Sharti v = READ4(sc, HE_REGO_LB_SWAP); 563116491Sharti BARRIER_R(sc); 564116491Sharti#if BYTE_ORDER == BIG_ENDIAN 565116491Sharti v |= HE_REGM_LBSWAP_INTR_SWAP | 566116491Sharti HE_REGM_LBSWAP_DESC_WR_SWAP | 567116491Sharti HE_REGM_LBSWAP_BIG_ENDIAN; 568116491Sharti v &= ~(HE_REGM_LBSWAP_DATA_WR_SWAP | 569116491Sharti HE_REGM_LBSWAP_DESC_RD_SWAP | 570116491Sharti HE_REGM_LBSWAP_DATA_RD_SWAP); 571116491Sharti#else 572116491Sharti v &= ~(HE_REGM_LBSWAP_DATA_WR_SWAP | 573116491Sharti HE_REGM_LBSWAP_DESC_RD_SWAP | 574116491Sharti HE_REGM_LBSWAP_DATA_RD_SWAP | 575116491Sharti HE_REGM_LBSWAP_INTR_SWAP | 576116491Sharti HE_REGM_LBSWAP_DESC_WR_SWAP | 577116491Sharti HE_REGM_LBSWAP_BIG_ENDIAN); 578116491Sharti#endif 579116491Sharti 580116491Sharti if (sc->he622) 581116491Sharti v |= HE_REGM_LBSWAP_XFER_SIZE; 582116491Sharti 583116491Sharti WRITE4(sc, HE_REGO_LB_SWAP, v); 584116491Sharti BARRIER_W(sc); 585116491Sharti} 586116491Sharti 587116491Sharti/* 588116491Sharti * 4.7 Read EEPROM 589116491Sharti */ 590116491Shartistatic uint8_t 591116491Shartihatm_read_prom_byte(struct hatm_softc *sc, u_int addr) 592116491Sharti{ 593116491Sharti uint32_t val, tmp_read, byte_read; 594116491Sharti u_int i, j; 595116491Sharti int n; 596116491Sharti 597116491Sharti val = READ4(sc, HE_REGO_HOST_CNTL); 598116491Sharti val &= HE_REGM_HOST_PROM_BITS; 599116491Sharti BARRIER_R(sc); 600116491Sharti 601116491Sharti val |= HE_REGM_HOST_PROM_WREN; 602116491Sharti WRITE4(sc, HE_REGO_HOST_CNTL, val); 603116491Sharti BARRIER_W(sc); 604116491Sharti 605116491Sharti /* send READ */ 606116491Sharti for (i = 0; i < sizeof(readtab) / sizeof(readtab[0]); i++) { 607116491Sharti WRITE4(sc, HE_REGO_HOST_CNTL, val | readtab[i]); 608116491Sharti BARRIER_W(sc); 609116491Sharti DELAY(EEPROM_DELAY); 610116491Sharti } 611116491Sharti 612116491Sharti /* send ADDRESS */ 613116491Sharti for (n = 7, j = 0; n >= 0; n--) { 614116491Sharti WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++] | 615116491Sharti (((addr >> n) & 1 ) << HE_REGS_HOST_PROM_DATA_IN)); 616116491Sharti BARRIER_W(sc); 617116491Sharti DELAY(EEPROM_DELAY); 618116491Sharti WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++] | 619116491Sharti (((addr >> n) & 1 ) << HE_REGS_HOST_PROM_DATA_IN)); 620116491Sharti BARRIER_W(sc); 621116491Sharti DELAY(EEPROM_DELAY); 622116491Sharti } 623116491Sharti 624116491Sharti val &= ~HE_REGM_HOST_PROM_WREN; 625116491Sharti WRITE4(sc, HE_REGO_HOST_CNTL, val); 626116491Sharti BARRIER_W(sc); 627116491Sharti 628116491Sharti /* read DATA */ 629116491Sharti byte_read = 0; 630116491Sharti for (n = 7, j = 0; n >= 0; n--) { 631116491Sharti WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++]); 632116491Sharti BARRIER_W(sc); 633116491Sharti DELAY(EEPROM_DELAY); 634116491Sharti tmp_read = READ4(sc, HE_REGO_HOST_CNTL); 635116491Sharti byte_read |= (uint8_t)(((tmp_read & HE_REGM_HOST_PROM_DATA_OUT) 636116491Sharti >> HE_REGS_HOST_PROM_DATA_OUT) << n); 637116491Sharti WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++]); 638116491Sharti BARRIER_W(sc); 639116491Sharti DELAY(EEPROM_DELAY); 640116491Sharti } 641116491Sharti WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++]); 642116491Sharti BARRIER_W(sc); 643116491Sharti DELAY(EEPROM_DELAY); 644116491Sharti 645116491Sharti return (byte_read); 646116491Sharti} 647116491Sharti 648116491Shartistatic void 649116491Shartihatm_init_read_eeprom(struct hatm_softc *sc) 650116491Sharti{ 651116491Sharti u_int n, count; 652116491Sharti u_char byte; 653116491Sharti uint32_t v; 654116491Sharti 655116491Sharti for (n = count = 0; count < HE_EEPROM_PROD_ID_LEN; count++) { 656116491Sharti byte = hatm_read_prom_byte(sc, HE_EEPROM_PROD_ID + count); 657116491Sharti if (n > 0 || byte != ' ') 658116491Sharti sc->prod_id[n++] = byte; 659116491Sharti } 660116491Sharti while (n > 0 && sc->prod_id[n-1] == ' ') 661116491Sharti n--; 662116491Sharti sc->prod_id[n] = '\0'; 663116491Sharti 664116491Sharti for (n = count = 0; count < HE_EEPROM_REV_LEN; count++) { 665116491Sharti byte = hatm_read_prom_byte(sc, HE_EEPROM_REV + count); 666116491Sharti if (n > 0 || byte != ' ') 667116491Sharti sc->rev[n++] = byte; 668116491Sharti } 669116491Sharti while (n > 0 && sc->rev[n-1] == ' ') 670116491Sharti n--; 671116491Sharti sc->rev[n] = '\0'; 672116491Sharti sc->ifatm.mib.hw_version = sc->rev[0]; 673116491Sharti 674116491Sharti sc->ifatm.mib.serial = hatm_read_prom_byte(sc, HE_EEPROM_M_SN + 0) << 0; 675116491Sharti sc->ifatm.mib.serial |= hatm_read_prom_byte(sc, HE_EEPROM_M_SN + 1) << 8; 676116491Sharti sc->ifatm.mib.serial |= hatm_read_prom_byte(sc, HE_EEPROM_M_SN + 2) << 16; 677116491Sharti sc->ifatm.mib.serial |= hatm_read_prom_byte(sc, HE_EEPROM_M_SN + 3) << 24; 678116491Sharti 679116491Sharti v = hatm_read_prom_byte(sc, HE_EEPROM_MEDIA + 0) << 0; 680116491Sharti v |= hatm_read_prom_byte(sc, HE_EEPROM_MEDIA + 1) << 8; 681116491Sharti v |= hatm_read_prom_byte(sc, HE_EEPROM_MEDIA + 2) << 16; 682116491Sharti v |= hatm_read_prom_byte(sc, HE_EEPROM_MEDIA + 3) << 24; 683116491Sharti 684116491Sharti switch (v) { 685116491Sharti case HE_MEDIA_UTP155: 686116491Sharti sc->ifatm.mib.media = IFM_ATM_UTP_155; 687116491Sharti sc->ifatm.mib.pcr = ATM_RATE_155M; 688116491Sharti break; 689116491Sharti 690116491Sharti case HE_MEDIA_MMF155: 691116491Sharti sc->ifatm.mib.media = IFM_ATM_MM_155; 692116491Sharti sc->ifatm.mib.pcr = ATM_RATE_155M; 693116491Sharti break; 694116491Sharti 695116491Sharti case HE_MEDIA_MMF622: 696116491Sharti sc->ifatm.mib.media = IFM_ATM_MM_622; 697116491Sharti sc->ifatm.mib.device = ATM_DEVICE_HE622; 698116491Sharti sc->ifatm.mib.pcr = ATM_RATE_622M; 699116491Sharti sc->he622 = 1; 700116491Sharti break; 701116491Sharti 702116491Sharti case HE_MEDIA_SMF155: 703116491Sharti sc->ifatm.mib.media = IFM_ATM_SM_155; 704116491Sharti sc->ifatm.mib.pcr = ATM_RATE_155M; 705116491Sharti break; 706116491Sharti 707116491Sharti case HE_MEDIA_SMF622: 708116491Sharti sc->ifatm.mib.media = IFM_ATM_SM_622; 709116491Sharti sc->ifatm.mib.device = ATM_DEVICE_HE622; 710116491Sharti sc->ifatm.mib.pcr = ATM_RATE_622M; 711116491Sharti sc->he622 = 1; 712116491Sharti break; 713116491Sharti } 714116491Sharti 715116491Sharti sc->ifatm.mib.esi[0] = hatm_read_prom_byte(sc, HE_EEPROM_MAC + 0); 716116491Sharti sc->ifatm.mib.esi[1] = hatm_read_prom_byte(sc, HE_EEPROM_MAC + 1); 717116491Sharti sc->ifatm.mib.esi[2] = hatm_read_prom_byte(sc, HE_EEPROM_MAC + 2); 718116491Sharti sc->ifatm.mib.esi[3] = hatm_read_prom_byte(sc, HE_EEPROM_MAC + 3); 719116491Sharti sc->ifatm.mib.esi[4] = hatm_read_prom_byte(sc, HE_EEPROM_MAC + 4); 720116491Sharti sc->ifatm.mib.esi[5] = hatm_read_prom_byte(sc, HE_EEPROM_MAC + 5); 721116491Sharti} 722116491Sharti 723116491Sharti/* 724116491Sharti * Clear unused interrupt queue 725116491Sharti */ 726116491Shartistatic void 727116491Shartihatm_clear_irq(struct hatm_softc *sc, u_int group) 728116491Sharti{ 729116491Sharti WRITE4(sc, HE_REGO_IRQ_BASE(group), 0); 730116491Sharti WRITE4(sc, HE_REGO_IRQ_HEAD(group), 0); 731116491Sharti WRITE4(sc, HE_REGO_IRQ_CNTL(group), 0); 732116491Sharti WRITE4(sc, HE_REGO_IRQ_DATA(group), 0); 733116491Sharti} 734116491Sharti 735116491Sharti/* 736116491Sharti * 4.10 Initialize interrupt queues 737116491Sharti */ 738116491Shartistatic void 739116491Shartihatm_init_irq(struct hatm_softc *sc, struct heirq *q, u_int group) 740116491Sharti{ 741116491Sharti u_int i; 742116491Sharti 743116491Sharti if (q->size == 0) { 744116491Sharti hatm_clear_irq(sc, group); 745116491Sharti return; 746116491Sharti } 747116491Sharti 748116491Sharti q->group = group; 749116491Sharti q->sc = sc; 750116491Sharti q->irq = q->mem.base; 751116491Sharti q->head = 0; 752116491Sharti q->tailp = q->irq + (q->size - 1); 753116491Sharti *q->tailp = 0; 754116491Sharti 755116491Sharti for (i = 0; i < q->size; i++) 756116491Sharti q->irq[i] = HE_REGM_ITYPE_INVALID; 757116491Sharti 758116491Sharti WRITE4(sc, HE_REGO_IRQ_BASE(group), q->mem.paddr); 759116491Sharti WRITE4(sc, HE_REGO_IRQ_HEAD(group), 760116491Sharti ((q->size - 1) << HE_REGS_IRQ_HEAD_SIZE) | 761116491Sharti (q->thresh << HE_REGS_IRQ_HEAD_THRESH)); 762116491Sharti WRITE4(sc, HE_REGO_IRQ_CNTL(group), q->line); 763116491Sharti WRITE4(sc, HE_REGO_IRQ_DATA(group), 0); 764116491Sharti} 765116491Sharti 766116491Sharti/* 767116491Sharti * 5.1.3 Initialize connection memory 768116491Sharti */ 769116491Shartistatic void 770116491Shartihatm_init_cm(struct hatm_softc *sc) 771116491Sharti{ 772116491Sharti u_int rsra, mlbm, rabr, numbuffs; 773116491Sharti u_int tsra, tabr, mtpd; 774116491Sharti u_int n; 775116491Sharti 776116491Sharti for (n = 0; n < HE_CONFIG_TXMEM; n++) 777116491Sharti WRITE_TCM4(sc, n, 0); 778116491Sharti for (n = 0; n < HE_CONFIG_RXMEM; n++) 779116491Sharti WRITE_RCM4(sc, n, 0); 780116491Sharti 781116491Sharti numbuffs = sc->r0_numbuffs + sc->r1_numbuffs + sc->tx_numbuffs; 782116491Sharti 783116491Sharti rsra = 0; 784116491Sharti mlbm = ((rsra + sc->ifatm.mib.max_vccs * 8) + 0x7ff) & ~0x7ff; 785116491Sharti rabr = ((mlbm + numbuffs * 2) + 0x7ff) & ~0x7ff; 786116491Sharti sc->rsrb = ((rabr + 2048) + (2 * sc->ifatm.mib.max_vccs - 1)) & 787116491Sharti ~(2 * sc->ifatm.mib.max_vccs - 1); 788116491Sharti 789116491Sharti tsra = 0; 790116491Sharti sc->tsrb = tsra + sc->ifatm.mib.max_vccs * 8; 791116491Sharti sc->tsrc = sc->tsrb + sc->ifatm.mib.max_vccs * 4; 792116491Sharti sc->tsrd = sc->tsrc + sc->ifatm.mib.max_vccs * 2; 793116491Sharti tabr = sc->tsrd + sc->ifatm.mib.max_vccs * 1; 794116491Sharti mtpd = ((tabr + 1024) + (16 * sc->ifatm.mib.max_vccs - 1)) & 795116491Sharti ~(16 * sc->ifatm.mib.max_vccs - 1); 796116491Sharti 797116491Sharti DBG(sc, ATTACH, ("rsra=%x mlbm=%x rabr=%x rsrb=%x", 798116491Sharti rsra, mlbm, rabr, sc->rsrb)); 799116491Sharti DBG(sc, ATTACH, ("tsra=%x tsrb=%x tsrc=%x tsrd=%x tabr=%x mtpd=%x", 800116491Sharti tsra, sc->tsrb, sc->tsrc, sc->tsrd, tabr, mtpd)); 801116491Sharti 802116491Sharti WRITE4(sc, HE_REGO_TSRB_BA, sc->tsrb); 803116491Sharti WRITE4(sc, HE_REGO_TSRC_BA, sc->tsrc); 804116491Sharti WRITE4(sc, HE_REGO_TSRD_BA, sc->tsrd); 805116491Sharti WRITE4(sc, HE_REGO_TMABR_BA, tabr); 806116491Sharti WRITE4(sc, HE_REGO_TPD_BA, mtpd); 807116491Sharti 808116491Sharti WRITE4(sc, HE_REGO_RCMRSRB_BA, sc->rsrb); 809116491Sharti WRITE4(sc, HE_REGO_RCMLBM_BA, mlbm); 810116491Sharti WRITE4(sc, HE_REGO_RCMABR_BA, rabr); 811116491Sharti 812116491Sharti BARRIER_W(sc); 813116491Sharti} 814116491Sharti 815116491Sharti/* 816116491Sharti * 5.1.4 Initialize Local buffer Pools 817116491Sharti */ 818116491Shartistatic void 819116491Shartihatm_init_rx_buffer_pool(struct hatm_softc *sc, 820116491Sharti u_int num, /* bank */ 821116491Sharti u_int start, /* start row */ 822116491Sharti u_int numbuffs /* number of entries */ 823116491Sharti) 824116491Sharti{ 825116491Sharti u_int row_size; /* bytes per row */ 826116491Sharti uint32_t row_addr; /* start address of this row */ 827116491Sharti u_int lbuf_size; /* bytes per lbuf */ 828116491Sharti u_int lbufs_per_row; /* number of lbufs per memory row */ 829116491Sharti uint32_t lbufd_index; /* index of lbuf descriptor */ 830116491Sharti uint32_t lbufd_addr; /* address of lbuf descriptor */ 831116491Sharti u_int lbuf_row_cnt; /* current lbuf in current row */ 832116491Sharti uint32_t lbuf_addr; /* address of current buffer */ 833116491Sharti u_int i; 834116491Sharti 835116491Sharti row_size = sc->bytes_per_row;; 836116491Sharti row_addr = start * row_size; 837116491Sharti lbuf_size = sc->cells_per_lbuf * 48; 838116491Sharti lbufs_per_row = sc->cells_per_row / sc->cells_per_lbuf; 839116491Sharti 840116491Sharti /* descriptor index */ 841116491Sharti lbufd_index = num; 842116491Sharti 843116491Sharti /* 2 words per entry */ 844116491Sharti lbufd_addr = READ4(sc, HE_REGO_RCMLBM_BA) + lbufd_index * 2; 845116491Sharti 846116491Sharti /* write head of queue */ 847116491Sharti WRITE4(sc, HE_REGO_RLBF_H(num), lbufd_index); 848116491Sharti 849116491Sharti lbuf_row_cnt = 0; 850116491Sharti for (i = 0; i < numbuffs; i++) { 851116491Sharti lbuf_addr = (row_addr + lbuf_row_cnt * lbuf_size) / 32; 852116491Sharti 853116491Sharti WRITE_RCM4(sc, lbufd_addr, lbuf_addr); 854116491Sharti 855116491Sharti lbufd_index += 2; 856116491Sharti WRITE_RCM4(sc, lbufd_addr + 1, lbufd_index); 857116491Sharti 858116491Sharti if (++lbuf_row_cnt == lbufs_per_row) { 859116491Sharti lbuf_row_cnt = 0; 860116491Sharti row_addr += row_size; 861116491Sharti } 862116491Sharti 863116491Sharti lbufd_addr += 2 * 2; 864116491Sharti } 865116491Sharti 866116491Sharti WRITE4(sc, HE_REGO_RLBF_T(num), lbufd_index - 2); 867116491Sharti WRITE4(sc, HE_REGO_RLBF_C(num), numbuffs); 868116491Sharti 869116491Sharti BARRIER_W(sc); 870116491Sharti} 871116491Sharti 872116491Shartistatic void 873116491Shartihatm_init_tx_buffer_pool(struct hatm_softc *sc, 874116491Sharti u_int start, /* start row */ 875116491Sharti u_int numbuffs /* number of entries */ 876116491Sharti) 877116491Sharti{ 878116491Sharti u_int row_size; /* bytes per row */ 879116491Sharti uint32_t row_addr; /* start address of this row */ 880116491Sharti u_int lbuf_size; /* bytes per lbuf */ 881116491Sharti u_int lbufs_per_row; /* number of lbufs per memory row */ 882116491Sharti uint32_t lbufd_index; /* index of lbuf descriptor */ 883116491Sharti uint32_t lbufd_addr; /* address of lbuf descriptor */ 884116491Sharti u_int lbuf_row_cnt; /* current lbuf in current row */ 885116491Sharti uint32_t lbuf_addr; /* address of current buffer */ 886116491Sharti u_int i; 887116491Sharti 888116491Sharti row_size = sc->bytes_per_row;; 889116491Sharti row_addr = start * row_size; 890116491Sharti lbuf_size = sc->cells_per_lbuf * 48; 891116491Sharti lbufs_per_row = sc->cells_per_row / sc->cells_per_lbuf; 892116491Sharti 893116491Sharti /* descriptor index */ 894116491Sharti lbufd_index = sc->r0_numbuffs + sc->r1_numbuffs; 895116491Sharti 896116491Sharti /* 2 words per entry */ 897116491Sharti lbufd_addr = READ4(sc, HE_REGO_RCMLBM_BA) + lbufd_index * 2; 898116491Sharti 899116491Sharti /* write head of queue */ 900116491Sharti WRITE4(sc, HE_REGO_TLBF_H, lbufd_index); 901116491Sharti 902116491Sharti lbuf_row_cnt = 0; 903116491Sharti for (i = 0; i < numbuffs; i++) { 904116491Sharti lbuf_addr = (row_addr + lbuf_row_cnt * lbuf_size) / 32; 905116491Sharti 906116491Sharti WRITE_RCM4(sc, lbufd_addr, lbuf_addr); 907116491Sharti lbufd_index++; 908116491Sharti WRITE_RCM4(sc, lbufd_addr + 1, lbufd_index); 909116491Sharti 910116491Sharti if (++lbuf_row_cnt == lbufs_per_row) { 911116491Sharti lbuf_row_cnt = 0; 912116491Sharti row_addr += row_size; 913116491Sharti } 914116491Sharti 915116491Sharti lbufd_addr += 2; 916116491Sharti } 917116491Sharti 918116491Sharti WRITE4(sc, HE_REGO_TLBF_T, lbufd_index - 1); 919116491Sharti BARRIER_W(sc); 920116491Sharti} 921116491Sharti 922116491Sharti/* 923116491Sharti * 5.1.5 Initialize Intermediate Receive Queues 924116491Sharti */ 925116491Shartistatic void 926116491Shartihatm_init_imed_queues(struct hatm_softc *sc) 927116491Sharti{ 928116491Sharti u_int n; 929116491Sharti 930116491Sharti if (sc->he622) { 931116491Sharti for (n = 0; n < 8; n++) { 932116491Sharti WRITE4(sc, HE_REGO_INMQ_S(n), 0x10*n+0x000f); 933116491Sharti WRITE4(sc, HE_REGO_INMQ_L(n), 0x10*n+0x200f); 934116491Sharti } 935116491Sharti } else { 936116491Sharti for (n = 0; n < 8; n++) { 937116491Sharti WRITE4(sc, HE_REGO_INMQ_S(n), n); 938116491Sharti WRITE4(sc, HE_REGO_INMQ_L(n), n+0x8); 939116491Sharti } 940116491Sharti } 941116491Sharti} 942116491Sharti 943116491Sharti/* 944116491Sharti * 5.1.7 Init CS block 945116491Sharti */ 946116491Shartistatic void 947116491Shartihatm_init_cs_block(struct hatm_softc *sc) 948116491Sharti{ 949116491Sharti u_int n, i; 950116491Sharti u_int clkfreg, cellrate, decr, tmp; 951116491Sharti static const uint32_t erthr[2][5][3] = HE_REGT_CS_ERTHR; 952116491Sharti static const uint32_t erctl[2][3] = HE_REGT_CS_ERCTL; 953116491Sharti static const uint32_t erstat[2][2] = HE_REGT_CS_ERSTAT; 954116491Sharti static const uint32_t rtfwr[2] = HE_REGT_CS_RTFWR; 955116491Sharti static const uint32_t rtatr[2] = HE_REGT_CS_RTATR; 956116491Sharti static const uint32_t bwalloc[2][6] = HE_REGT_CS_BWALLOC; 957116491Sharti static const uint32_t orcf[2][2] = HE_REGT_CS_ORCF; 958116491Sharti 959116491Sharti /* Clear Rate Controller Start Times and Occupied Flags */ 960116491Sharti for (n = 0; n < 32; n++) 961116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_STTIM(n), 0); 962116491Sharti 963116491Sharti clkfreg = sc->he622 ? HE_622_CLOCK : HE_155_CLOCK; 964116491Sharti cellrate = sc->he622 ? ATM_RATE_622M : ATM_RATE_155M; 965116491Sharti decr = cellrate / 32; 966116491Sharti 967116491Sharti for (n = 0; n < 16; n++) { 968116491Sharti tmp = clkfreg / cellrate; 969116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_TGRLD(n), tmp - 1); 970116491Sharti cellrate -= decr; 971116491Sharti } 972116491Sharti 973116491Sharti i = (sc->cells_per_lbuf == 2) ? 0 974116491Sharti :(sc->cells_per_lbuf == 4) ? 1 975116491Sharti : 2; 976116491Sharti 977116491Sharti /* table 5.2 */ 978116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_ERTHR0, erthr[sc->he622][0][i]); 979116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_ERTHR1, erthr[sc->he622][1][i]); 980116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_ERTHR2, erthr[sc->he622][2][i]); 981116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_ERTHR3, erthr[sc->he622][3][i]); 982116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_ERTHR4, erthr[sc->he622][4][i]); 983116491Sharti 984116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_ERCTL0, erctl[sc->he622][0]); 985116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_ERCTL1, erctl[sc->he622][1]); 986116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_ERCTL2, erctl[sc->he622][2]); 987116491Sharti 988116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_ERSTAT0, erstat[sc->he622][0]); 989116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_ERSTAT1, erstat[sc->he622][1]); 990116491Sharti 991116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_RTFWR, rtfwr[sc->he622]); 992116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_RTATR, rtatr[sc->he622]); 993116491Sharti 994116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_TFBSET, bwalloc[sc->he622][0]); 995116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_WCRMAX, bwalloc[sc->he622][1]); 996116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_WCRMIN, bwalloc[sc->he622][2]); 997116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_WCRINC, bwalloc[sc->he622][3]); 998116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_WCRDEC, bwalloc[sc->he622][4]); 999116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_WCRCEIL, bwalloc[sc->he622][5]); 1000116491Sharti 1001116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_OTPPER, orcf[sc->he622][0]); 1002116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_OTWPER, orcf[sc->he622][1]); 1003116491Sharti 1004116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_OTTLIM, 8); 1005116491Sharti 1006116491Sharti for (n = 0; n < 8; n++) 1007116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_HGRRT(n), 0); 1008116491Sharti} 1009116491Sharti 1010116491Sharti/* 1011116491Sharti * 5.1.8 CS Block Connection Memory Initialisation 1012116491Sharti */ 1013116491Shartistatic void 1014116491Shartihatm_init_cs_block_cm(struct hatm_softc *sc) 1015116491Sharti{ 1016116491Sharti u_int n, i; 1017116491Sharti u_int expt, mant, etrm, wcr, ttnrm, tnrm; 1018116491Sharti uint32_t rate; 1019116491Sharti uint32_t clkfreq, cellrate, decr; 1020116491Sharti uint32_t *rg, rtg, val = 0; 1021116491Sharti uint64_t drate; 1022116491Sharti u_int buf, buf_limit; 1023116491Sharti uint32_t base = READ4(sc, HE_REGO_RCMABR_BA); 1024116491Sharti 1025116491Sharti for (n = 0; n < HE_REGL_CM_GQTBL; n++) 1026116491Sharti WRITE_RCM4(sc, base + HE_REGO_CM_GQTBL + n, 0); 1027116491Sharti for (n = 0; n < HE_REGL_CM_RGTBL; n++) 1028116491Sharti WRITE_RCM4(sc, base + HE_REGO_CM_RGTBL + n, 0); 1029116491Sharti 1030116491Sharti tnrm = 0; 1031116491Sharti for (n = 0; n < HE_REGL_CM_TNRMTBL * 4; n++) { 1032116491Sharti expt = (n >> 5) & 0x1f; 1033116491Sharti mant = ((n & 0x18) << 4) | 0x7f; 1034116491Sharti wcr = (1 << expt) * (mant + 512) / 512; 1035116491Sharti etrm = n & 0x7; 1036116491Sharti ttnrm = wcr / 10 / (1 << etrm); 1037116491Sharti if (ttnrm > 255) 1038116491Sharti ttnrm = 255; 1039116491Sharti else if(ttnrm < 2) 1040116491Sharti ttnrm = 2; 1041116491Sharti tnrm = (tnrm << 8) | (ttnrm & 0xff); 1042116491Sharti if (n % 4 == 0) 1043116491Sharti WRITE_RCM4(sc, base + HE_REGO_CM_TNRMTBL + (n/4), tnrm); 1044116491Sharti } 1045116491Sharti 1046116491Sharti clkfreq = sc->he622 ? HE_622_CLOCK : HE_155_CLOCK; 1047116491Sharti buf_limit = 4; 1048116491Sharti 1049116491Sharti cellrate = sc->he622 ? ATM_RATE_622M : ATM_RATE_155M; 1050116491Sharti decr = cellrate / 32; 1051116491Sharti 1052116491Sharti /* compute GRID top row in 1000 * cps */ 1053116491Sharti for (n = 0; n < 16; n++) { 1054116491Sharti u_int interval = clkfreq / cellrate; 1055116491Sharti sc->rate_grid[0][n] = (u_int64_t)clkfreq * 1000 / interval; 1056116491Sharti cellrate -= decr; 1057116491Sharti } 1058116491Sharti 1059116491Sharti /* compute the other rows according to 2.4 */ 1060116491Sharti for (i = 1; i < 16; i++) 1061116491Sharti for (n = 0; n < 16; n++) 1062116491Sharti sc->rate_grid[i][n] = sc->rate_grid[i-1][n] / 1063116491Sharti ((i < 14) ? 2 : 4); 1064116491Sharti 1065116491Sharti /* first entry is line rate */ 1066116491Sharti n = hatm_cps2atmf(sc->he622 ? ATM_RATE_622M : ATM_RATE_155M); 1067116491Sharti expt = (n >> 9) & 0x1f; 1068116491Sharti mant = n & 0x1f0; 1069116491Sharti sc->rate_grid[0][0] = (u_int64_t)(1<<expt) * 1000 * (mant+512) / 512; 1070116491Sharti 1071116491Sharti /* now build the conversion table - each 32 bit word contains 1072116491Sharti * two entries - this gives a total of 0x400 16 bit entries. 1073116491Sharti * This table maps the truncated ATMF rate version into a grid index */ 1074116491Sharti cellrate = sc->he622 ? ATM_RATE_622M : ATM_RATE_155M; 1075116491Sharti rg = &sc->rate_grid[15][15]; 1076116491Sharti 1077116491Sharti for (rate = 0; rate < 2 * HE_REGL_CM_RTGTBL; rate++) { 1078116491Sharti /* unpack the ATMF rate */ 1079116491Sharti expt = rate >> 5; 1080116491Sharti mant = (rate & 0x1f) << 4; 1081116491Sharti 1082116491Sharti /* get the cell rate - minimum is 10 per second */ 1083116491Sharti drate = (uint64_t)(1 << expt) * 1000 * (mant + 512) / 512; 1084116491Sharti if (drate < 10 * 1000) 1085116491Sharti drate = 10 * 1000; 1086116491Sharti 1087116491Sharti /* now look up the grid index */ 1088116491Sharti while (drate >= *rg && rg-- > &sc->rate_grid[0][0]) 1089116491Sharti ; 1090116491Sharti rg++; 1091116491Sharti rtg = rg - &sc->rate_grid[0][0]; 1092116491Sharti 1093116491Sharti /* now compute the buffer limit */ 1094116491Sharti buf = drate * sc->tx_numbuffs / (cellrate * 2) / 1000; 1095116491Sharti if (buf == 0) 1096116491Sharti buf = 1; 1097116491Sharti else if (buf > buf_limit) 1098116491Sharti buf = buf_limit; 1099116491Sharti 1100116491Sharti /* make value */ 1101116491Sharti val = (val << 16) | (rtg << 8) | buf; 1102116491Sharti 1103116491Sharti /* write */ 1104116491Sharti if (rate % 2 == 1) 1105116491Sharti WRITE_RCM4(sc, base + HE_REGO_CM_RTGTBL + rate/2, val); 1106116491Sharti } 1107116491Sharti} 1108116491Sharti 1109116491Sharti/* 1110116491Sharti * Clear an unused receive group buffer pool 1111116491Sharti */ 1112116491Shartistatic void 1113116491Shartihatm_clear_rpool(struct hatm_softc *sc, u_int group, u_int large) 1114116491Sharti{ 1115116491Sharti WRITE4(sc, HE_REGO_RBP_S(large, group), 0); 1116116491Sharti WRITE4(sc, HE_REGO_RBP_T(large, group), 0); 1117116491Sharti WRITE4(sc, HE_REGO_RBP_QI(large, group), 1); 1118116491Sharti WRITE4(sc, HE_REGO_RBP_BL(large, group), 0); 1119116491Sharti} 1120116491Sharti 1121116491Sharti/* 1122116491Sharti * Initialize a receive group buffer pool 1123116491Sharti */ 1124116491Shartistatic void 1125116491Shartihatm_init_rpool(struct hatm_softc *sc, struct herbp *q, u_int group, 1126116491Sharti u_int large) 1127116491Sharti{ 1128116491Sharti if (q->size == 0) { 1129116491Sharti hatm_clear_rpool(sc, group, large); 1130116491Sharti return; 1131116491Sharti } 1132116491Sharti 1133116491Sharti bzero(q->mem.base, q->mem.size); 1134116491Sharti q->rbp = q->mem.base; 1135116491Sharti q->head = q->tail = 0; 1136116491Sharti 1137116491Sharti DBG(sc, ATTACH, ("RBP%u%c=0x%lx", group, "SL"[large], 1138116491Sharti (u_long)q->mem.paddr)); 1139116491Sharti 1140116491Sharti WRITE4(sc, HE_REGO_RBP_S(large, group), q->mem.paddr); 1141116491Sharti WRITE4(sc, HE_REGO_RBP_T(large, group), 0); 1142116491Sharti WRITE4(sc, HE_REGO_RBP_QI(large, group), 1143116491Sharti ((q->size - 1) << HE_REGS_RBP_SIZE) | 1144116491Sharti HE_REGM_RBP_INTR_ENB | 1145116491Sharti (q->thresh << HE_REGS_RBP_THRESH)); 1146116491Sharti WRITE4(sc, HE_REGO_RBP_BL(large, group), (q->bsize >> 2) & ~1); 1147116491Sharti} 1148116491Sharti 1149116491Sharti/* 1150116491Sharti * Clear an unused receive buffer return queue 1151116491Sharti */ 1152116491Shartistatic void 1153116491Shartihatm_clear_rbrq(struct hatm_softc *sc, u_int group) 1154116491Sharti{ 1155116491Sharti WRITE4(sc, HE_REGO_RBRQ_ST(group), 0); 1156116491Sharti WRITE4(sc, HE_REGO_RBRQ_H(group), 0); 1157116491Sharti WRITE4(sc, HE_REGO_RBRQ_Q(group), (1 << HE_REGS_RBRQ_THRESH)); 1158116491Sharti WRITE4(sc, HE_REGO_RBRQ_I(group), 0); 1159116491Sharti} 1160116491Sharti 1161116491Sharti/* 1162116491Sharti * Initialize receive buffer return queue 1163116491Sharti */ 1164116491Shartistatic void 1165116491Shartihatm_init_rbrq(struct hatm_softc *sc, struct herbrq *rq, u_int group) 1166116491Sharti{ 1167116491Sharti if (rq->size == 0) { 1168116491Sharti hatm_clear_rbrq(sc, group); 1169116491Sharti return; 1170116491Sharti } 1171116491Sharti 1172116491Sharti rq->rbrq = rq->mem.base; 1173116491Sharti rq->head = 0; 1174116491Sharti 1175116491Sharti DBG(sc, ATTACH, ("RBRQ%u=0x%lx", group, (u_long)rq->mem.paddr)); 1176116491Sharti 1177116491Sharti WRITE4(sc, HE_REGO_RBRQ_ST(group), rq->mem.paddr); 1178116491Sharti WRITE4(sc, HE_REGO_RBRQ_H(group), 0); 1179116491Sharti WRITE4(sc, HE_REGO_RBRQ_Q(group), 1180116491Sharti (rq->thresh << HE_REGS_RBRQ_THRESH) | 1181116491Sharti ((rq->size - 1) << HE_REGS_RBRQ_SIZE)); 1182116491Sharti WRITE4(sc, HE_REGO_RBRQ_I(group), 1183116491Sharti (rq->tout << HE_REGS_RBRQ_TIME) | 1184116491Sharti (rq->pcnt << HE_REGS_RBRQ_COUNT)); 1185116491Sharti} 1186116491Sharti 1187116491Sharti/* 1188116491Sharti * Clear an unused transmit buffer return queue N 1189116491Sharti */ 1190116491Shartistatic void 1191116491Shartihatm_clear_tbrq(struct hatm_softc *sc, u_int group) 1192116491Sharti{ 1193116491Sharti WRITE4(sc, HE_REGO_TBRQ_B_T(group), 0); 1194116491Sharti WRITE4(sc, HE_REGO_TBRQ_H(group), 0); 1195116491Sharti WRITE4(sc, HE_REGO_TBRQ_S(group), 0); 1196116491Sharti WRITE4(sc, HE_REGO_TBRQ_THRESH(group), 1); 1197116491Sharti} 1198116491Sharti 1199116491Sharti/* 1200116491Sharti * Initialize transmit buffer return queue N 1201116491Sharti */ 1202116491Shartistatic void 1203116491Shartihatm_init_tbrq(struct hatm_softc *sc, struct hetbrq *tq, u_int group) 1204116491Sharti{ 1205116491Sharti if (tq->size == 0) { 1206116491Sharti hatm_clear_tbrq(sc, group); 1207116491Sharti return; 1208116491Sharti } 1209116491Sharti 1210116491Sharti tq->tbrq = tq->mem.base; 1211116491Sharti tq->head = 0; 1212116491Sharti 1213116491Sharti DBG(sc, ATTACH, ("TBRQ%u=0x%lx", group, (u_long)tq->mem.paddr)); 1214116491Sharti 1215116491Sharti WRITE4(sc, HE_REGO_TBRQ_B_T(group), tq->mem.paddr); 1216116491Sharti WRITE4(sc, HE_REGO_TBRQ_H(group), 0); 1217116491Sharti WRITE4(sc, HE_REGO_TBRQ_S(group), tq->size - 1); 1218116491Sharti WRITE4(sc, HE_REGO_TBRQ_THRESH(group), tq->thresh); 1219116491Sharti} 1220116491Sharti 1221116491Sharti/* 1222116491Sharti * Initialize TPDRQ 1223116491Sharti */ 1224116491Shartistatic void 1225116491Shartihatm_init_tpdrq(struct hatm_softc *sc) 1226116491Sharti{ 1227116491Sharti struct hetpdrq *tq; 1228116491Sharti 1229116491Sharti tq = &sc->tpdrq; 1230116491Sharti tq->tpdrq = tq->mem.base; 1231116491Sharti tq->tail = tq->head = 0; 1232116491Sharti 1233116491Sharti DBG(sc, ATTACH, ("TPDRQ=0x%lx", (u_long)tq->mem.paddr)); 1234116491Sharti 1235116491Sharti WRITE4(sc, HE_REGO_TPDRQ_H, tq->mem.paddr); 1236116491Sharti WRITE4(sc, HE_REGO_TPDRQ_T, 0); 1237116491Sharti WRITE4(sc, HE_REGO_TPDRQ_S, tq->size - 1); 1238116491Sharti} 1239116491Sharti 1240116491Sharti/* 1241116491Sharti * Function can be called by the infrastructure to start the card. 1242116491Sharti */ 1243116491Shartistatic void 1244116491Shartihatm_init(void *p) 1245116491Sharti{ 1246116491Sharti struct hatm_softc *sc = p; 1247116491Sharti 1248116491Sharti mtx_lock(&sc->mtx); 1249116491Sharti hatm_stop(sc); 1250116491Sharti hatm_initialize(sc); 1251116491Sharti mtx_unlock(&sc->mtx); 1252116491Sharti} 1253116491Sharti 1254116491Shartienum { 1255116491Sharti CTL_ISTATS, 1256116491Sharti}; 1257116491Sharti 1258116491Sharti/* 1259116491Sharti * Sysctl handler 1260116491Sharti */ 1261116491Shartistatic int 1262116491Shartihatm_sysctl(SYSCTL_HANDLER_ARGS) 1263116491Sharti{ 1264116491Sharti struct hatm_softc *sc = arg1; 1265116491Sharti uint32_t *ret; 1266116491Sharti int error; 1267116491Sharti size_t len; 1268116491Sharti 1269116491Sharti switch (arg2) { 1270116491Sharti 1271116491Sharti case CTL_ISTATS: 1272116491Sharti len = sizeof(sc->istats); 1273116491Sharti break; 1274116491Sharti 1275116491Sharti default: 1276116491Sharti panic("bad control code"); 1277116491Sharti } 1278116491Sharti 1279116491Sharti ret = malloc(len, M_TEMP, M_WAITOK); 1280116491Sharti mtx_lock(&sc->mtx); 1281116491Sharti 1282116491Sharti switch (arg2) { 1283116491Sharti 1284116491Sharti case CTL_ISTATS: 1285118169Sharti sc->istats.mcc += READ4(sc, HE_REGO_MCC); 1286118169Sharti sc->istats.oec += READ4(sc, HE_REGO_OEC); 1287118169Sharti sc->istats.dcc += READ4(sc, HE_REGO_DCC); 1288118169Sharti sc->istats.cec += READ4(sc, HE_REGO_CEC); 1289116491Sharti bcopy(&sc->istats, ret, sizeof(sc->istats)); 1290116491Sharti break; 1291116491Sharti } 1292116491Sharti mtx_unlock(&sc->mtx); 1293116491Sharti 1294116491Sharti error = SYSCTL_OUT(req, ret, len); 1295116491Sharti free(ret, M_TEMP); 1296116491Sharti 1297116491Sharti return (error); 1298116491Sharti} 1299116491Sharti 1300116491Shartistatic int 1301116491Shartikenv_getuint(struct hatm_softc *sc, const char *var, 1302116491Sharti u_int *ptr, u_int def, int rw) 1303116491Sharti{ 1304116491Sharti char full[IFNAMSIZ + 3 + 20]; 1305116491Sharti char *val, *end; 1306116491Sharti u_int u; 1307116491Sharti 1308116491Sharti *ptr = def; 1309116491Sharti 1310116491Sharti if (SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 1311116491Sharti OID_AUTO, var, rw ? CTLFLAG_RW : CTLFLAG_RD, ptr, 0, "") == NULL) 1312116491Sharti return (ENOMEM); 1313116491Sharti 1314116491Sharti snprintf(full, sizeof(full), "hw.%s.%s", 1315116491Sharti device_get_nameunit(sc->dev), var); 1316116491Sharti 1317116491Sharti if ((val = getenv(full)) == NULL) 1318116491Sharti return (0); 1319116491Sharti u = strtoul(val, &end, 0); 1320116491Sharti if (end == val || *end != '\0') { 1321116491Sharti freeenv(val); 1322116491Sharti return (EINVAL); 1323116491Sharti } 1324116491Sharti if (bootverbose) 1325116491Sharti if_printf(&sc->ifatm.ifnet, "%s=%u\n", full, u); 1326116491Sharti *ptr = u; 1327116491Sharti return (0); 1328116491Sharti} 1329116491Sharti 1330116491Sharti/* 1331116491Sharti * Set configurable parameters. Many of these are configurable via 1332116491Sharti * kenv. 1333116491Sharti */ 1334116491Shartistatic int 1335116491Shartihatm_configure(struct hatm_softc *sc) 1336116491Sharti{ 1337116491Sharti /* Receive buffer pool 0 small */ 1338121469Sharti kenv_getuint(sc, "rbps0_size", &sc->rbp_s0.size, 1339116491Sharti HE_CONFIG_RBPS0_SIZE, 0); 1340121469Sharti kenv_getuint(sc, "rbps0_thresh", &sc->rbp_s0.thresh, 1341116491Sharti HE_CONFIG_RBPS0_THRESH, 0); 1342116491Sharti sc->rbp_s0.bsize = MBUF0_SIZE; 1343116491Sharti 1344116491Sharti /* Receive buffer pool 0 large */ 1345121469Sharti kenv_getuint(sc, "rbpl0_size", &sc->rbp_l0.size, 1346116491Sharti HE_CONFIG_RBPL0_SIZE, 0); 1347121469Sharti kenv_getuint(sc, "rbpl0_thresh", &sc->rbp_l0.thresh, 1348116491Sharti HE_CONFIG_RBPL0_THRESH, 0); 1349116491Sharti sc->rbp_l0.bsize = MCLBYTES - MBUFL_OFFSET; 1350116491Sharti 1351116491Sharti /* Receive buffer return queue 0 */ 1352121469Sharti kenv_getuint(sc, "rbrq0_size", &sc->rbrq_0.size, 1353116491Sharti HE_CONFIG_RBRQ0_SIZE, 0); 1354121469Sharti kenv_getuint(sc, "rbrq0_thresh", &sc->rbrq_0.thresh, 1355116491Sharti HE_CONFIG_RBRQ0_THRESH, 0); 1356121469Sharti kenv_getuint(sc, "rbrq0_tout", &sc->rbrq_0.tout, 1357116491Sharti HE_CONFIG_RBRQ0_TOUT, 0); 1358121469Sharti kenv_getuint(sc, "rbrq0_pcnt", &sc->rbrq_0.pcnt, 1359116491Sharti HE_CONFIG_RBRQ0_PCNT, 0); 1360116491Sharti 1361116491Sharti /* Receive buffer pool 1 small */ 1362121469Sharti kenv_getuint(sc, "rbps1_size", &sc->rbp_s1.size, 1363116491Sharti HE_CONFIG_RBPS1_SIZE, 0); 1364121469Sharti kenv_getuint(sc, "rbps1_thresh", &sc->rbp_s1.thresh, 1365116491Sharti HE_CONFIG_RBPS1_THRESH, 0); 1366116491Sharti sc->rbp_s1.bsize = MBUF1_SIZE; 1367116491Sharti 1368116491Sharti /* Receive buffer return queue 1 */ 1369121469Sharti kenv_getuint(sc, "rbrq1_size", &sc->rbrq_1.size, 1370116491Sharti HE_CONFIG_RBRQ1_SIZE, 0); 1371121469Sharti kenv_getuint(sc, "rbrq1_thresh", &sc->rbrq_1.thresh, 1372116491Sharti HE_CONFIG_RBRQ1_THRESH, 0); 1373121469Sharti kenv_getuint(sc, "rbrq1_tout", &sc->rbrq_1.tout, 1374116491Sharti HE_CONFIG_RBRQ1_TOUT, 0); 1375121469Sharti kenv_getuint(sc, "rbrq1_pcnt", &sc->rbrq_1.pcnt, 1376116491Sharti HE_CONFIG_RBRQ1_PCNT, 0); 1377116491Sharti 1378116491Sharti /* Interrupt queue 0 */ 1379121469Sharti kenv_getuint(sc, "irq0_size", &sc->irq_0.size, 1380116491Sharti HE_CONFIG_IRQ0_SIZE, 0); 1381121469Sharti kenv_getuint(sc, "irq0_thresh", &sc->irq_0.thresh, 1382116491Sharti HE_CONFIG_IRQ0_THRESH, 0); 1383116491Sharti sc->irq_0.line = HE_CONFIG_IRQ0_LINE; 1384116491Sharti 1385116491Sharti /* Transmit buffer return queue 0 */ 1386121469Sharti kenv_getuint(sc, "tbrq0_size", &sc->tbrq.size, 1387116491Sharti HE_CONFIG_TBRQ_SIZE, 0); 1388121469Sharti kenv_getuint(sc, "tbrq0_thresh", &sc->tbrq.thresh, 1389116491Sharti HE_CONFIG_TBRQ_THRESH, 0); 1390116491Sharti 1391116491Sharti /* Transmit buffer ready queue */ 1392121469Sharti kenv_getuint(sc, "tpdrq_size", &sc->tpdrq.size, 1393116491Sharti HE_CONFIG_TPDRQ_SIZE, 0); 1394116491Sharti /* Max TPDs per VCC */ 1395116491Sharti kenv_getuint(sc, "tpdmax", &sc->max_tpd, 1396116491Sharti HE_CONFIG_TPD_MAXCC, 0); 1397116491Sharti 1398121685Sharti /* external mbuf pages */ 1399121685Sharti kenv_getuint(sc, "max_mbuf_pages", &sc->mbuf_max_pages, 1400121685Sharti HE_CONFIG_MAX_MBUF_PAGES, 0); 1401121685Sharti 1402122113Sharti /* mpsafe */ 1403122113Sharti kenv_getuint(sc, "mpsafe", &sc->mpsafe, 0, 0); 1404122113Sharti if (sc->mpsafe != 0) 1405122113Sharti sc->mpsafe = INTR_MPSAFE; 1406122113Sharti 1407116491Sharti return (0); 1408116491Sharti} 1409116491Sharti 1410116491Sharti#ifdef HATM_DEBUG 1411116491Sharti 1412116491Sharti/* 1413116491Sharti * Get TSRs from connection memory 1414116491Sharti */ 1415116491Shartistatic int 1416116491Shartihatm_sysctl_tsr(SYSCTL_HANDLER_ARGS) 1417116491Sharti{ 1418116491Sharti struct hatm_softc *sc = arg1; 1419116491Sharti int error, i, j; 1420116491Sharti uint32_t *val; 1421116491Sharti 1422116491Sharti val = malloc(sizeof(uint32_t) * HE_MAX_VCCS * 15, M_TEMP, M_WAITOK); 1423116491Sharti 1424116491Sharti mtx_lock(&sc->mtx); 1425116491Sharti for (i = 0; i < HE_MAX_VCCS; i++) 1426116491Sharti for (j = 0; j <= 14; j++) 1427116491Sharti val[15 * i + j] = READ_TSR(sc, i, j); 1428116491Sharti mtx_unlock(&sc->mtx); 1429116491Sharti 1430116491Sharti error = SYSCTL_OUT(req, val, sizeof(uint32_t) * HE_MAX_VCCS * 15); 1431116491Sharti free(val, M_TEMP); 1432116491Sharti if (error != 0 || req->newptr == NULL) 1433116491Sharti return (error); 1434116491Sharti 1435116491Sharti return (EPERM); 1436116491Sharti} 1437116491Sharti 1438116491Sharti/* 1439116491Sharti * Get TPDs from connection memory 1440116491Sharti */ 1441116491Shartistatic int 1442116491Shartihatm_sysctl_tpd(SYSCTL_HANDLER_ARGS) 1443116491Sharti{ 1444116491Sharti struct hatm_softc *sc = arg1; 1445116491Sharti int error, i, j; 1446116491Sharti uint32_t *val; 1447116491Sharti 1448116491Sharti val = malloc(sizeof(uint32_t) * HE_MAX_VCCS * 16, M_TEMP, M_WAITOK); 1449116491Sharti 1450116491Sharti mtx_lock(&sc->mtx); 1451116491Sharti for (i = 0; i < HE_MAX_VCCS; i++) 1452116491Sharti for (j = 0; j < 16; j++) 1453116491Sharti val[16 * i + j] = READ_TCM4(sc, 16 * i + j); 1454116491Sharti mtx_unlock(&sc->mtx); 1455116491Sharti 1456116491Sharti error = SYSCTL_OUT(req, val, sizeof(uint32_t) * HE_MAX_VCCS * 16); 1457116491Sharti free(val, M_TEMP); 1458116491Sharti if (error != 0 || req->newptr == NULL) 1459116491Sharti return (error); 1460116491Sharti 1461116491Sharti return (EPERM); 1462116491Sharti} 1463116491Sharti 1464116491Sharti/* 1465116491Sharti * Get mbox registers 1466116491Sharti */ 1467116491Shartistatic int 1468116491Shartihatm_sysctl_mbox(SYSCTL_HANDLER_ARGS) 1469116491Sharti{ 1470116491Sharti struct hatm_softc *sc = arg1; 1471116491Sharti int error, i; 1472116491Sharti uint32_t *val; 1473116491Sharti 1474116491Sharti val = malloc(sizeof(uint32_t) * HE_REGO_CS_END, M_TEMP, M_WAITOK); 1475116491Sharti 1476116491Sharti mtx_lock(&sc->mtx); 1477116491Sharti for (i = 0; i < HE_REGO_CS_END; i++) 1478116491Sharti val[i] = READ_MBOX4(sc, i); 1479116491Sharti mtx_unlock(&sc->mtx); 1480116491Sharti 1481116491Sharti error = SYSCTL_OUT(req, val, sizeof(uint32_t) * HE_REGO_CS_END); 1482116491Sharti free(val, M_TEMP); 1483116491Sharti if (error != 0 || req->newptr == NULL) 1484116491Sharti return (error); 1485116491Sharti 1486116491Sharti return (EPERM); 1487116491Sharti} 1488116491Sharti 1489116491Sharti/* 1490116491Sharti * Get connection memory 1491116491Sharti */ 1492116491Shartistatic int 1493116491Shartihatm_sysctl_cm(SYSCTL_HANDLER_ARGS) 1494116491Sharti{ 1495116491Sharti struct hatm_softc *sc = arg1; 1496116491Sharti int error, i; 1497116491Sharti uint32_t *val; 1498116491Sharti 1499116491Sharti val = malloc(sizeof(uint32_t) * (HE_CONFIG_RXMEM + 1), M_TEMP, M_WAITOK); 1500116491Sharti 1501116491Sharti mtx_lock(&sc->mtx); 1502116491Sharti val[0] = READ4(sc, HE_REGO_RCMABR_BA); 1503116491Sharti for (i = 0; i < HE_CONFIG_RXMEM; i++) 1504116491Sharti val[i + 1] = READ_RCM4(sc, i); 1505116491Sharti mtx_unlock(&sc->mtx); 1506116491Sharti 1507116491Sharti error = SYSCTL_OUT(req, val, sizeof(uint32_t) * (HE_CONFIG_RXMEM + 1)); 1508116491Sharti free(val, M_TEMP); 1509116491Sharti if (error != 0 || req->newptr == NULL) 1510116491Sharti return (error); 1511116491Sharti 1512116491Sharti return (EPERM); 1513116491Sharti} 1514116491Sharti 1515116491Sharti/* 1516116491Sharti * Get local buffer memory 1517116491Sharti */ 1518116491Shartistatic int 1519116491Shartihatm_sysctl_lbmem(SYSCTL_HANDLER_ARGS) 1520116491Sharti{ 1521116491Sharti struct hatm_softc *sc = arg1; 1522116491Sharti int error, i; 1523116491Sharti uint32_t *val; 1524116491Sharti u_int bytes = (1 << 21); 1525116491Sharti 1526116491Sharti val = malloc(bytes, M_TEMP, M_WAITOK); 1527116491Sharti 1528116491Sharti mtx_lock(&sc->mtx); 1529116491Sharti for (i = 0; i < bytes / 4; i++) 1530116491Sharti val[i] = READ_LB4(sc, i); 1531116491Sharti mtx_unlock(&sc->mtx); 1532116491Sharti 1533116491Sharti error = SYSCTL_OUT(req, val, bytes); 1534116491Sharti free(val, M_TEMP); 1535116491Sharti if (error != 0 || req->newptr == NULL) 1536116491Sharti return (error); 1537116491Sharti 1538116491Sharti return (EPERM); 1539116491Sharti} 1540116491Sharti 1541116491Sharti/* 1542116491Sharti * Get all card registers 1543116491Sharti */ 1544116491Shartistatic int 1545116491Shartihatm_sysctl_heregs(SYSCTL_HANDLER_ARGS) 1546116491Sharti{ 1547116491Sharti struct hatm_softc *sc = arg1; 1548116491Sharti int error, i; 1549116491Sharti uint32_t *val; 1550116491Sharti 1551116491Sharti val = malloc(HE_REGO_END, M_TEMP, M_WAITOK); 1552116491Sharti 1553116491Sharti mtx_lock(&sc->mtx); 1554116491Sharti for (i = 0; i < HE_REGO_END; i += 4) 1555116491Sharti val[i / 4] = READ4(sc, i); 1556116491Sharti mtx_unlock(&sc->mtx); 1557116491Sharti 1558116491Sharti error = SYSCTL_OUT(req, val, HE_REGO_END); 1559116491Sharti free(val, M_TEMP); 1560116491Sharti if (error != 0 || req->newptr == NULL) 1561116491Sharti return (error); 1562116491Sharti 1563116491Sharti return (EPERM); 1564116491Sharti} 1565116491Sharti#endif 1566116491Sharti 1567116491Sharti/* 1568116491Sharti * Suni register access 1569116491Sharti */ 1570116491Sharti/* 1571116491Sharti * read at most n SUNI registers starting at reg into val 1572116491Sharti */ 1573116491Shartistatic int 1574116491Shartihatm_utopia_readregs(struct ifatm *ifatm, u_int reg, uint8_t *val, u_int *n) 1575116491Sharti{ 1576116491Sharti u_int i; 1577116491Sharti struct hatm_softc *sc = (struct hatm_softc *)ifatm; 1578116491Sharti 1579116491Sharti if (reg >= (HE_REGO_SUNI_END - HE_REGO_SUNI) / 4) 1580116491Sharti return (EINVAL); 1581116491Sharti if (reg + *n > (HE_REGO_SUNI_END - HE_REGO_SUNI) / 4) 1582116491Sharti *n = reg - (HE_REGO_SUNI_END - HE_REGO_SUNI) / 4; 1583116491Sharti 1584116491Sharti mtx_assert(&sc->mtx, MA_OWNED); 1585116491Sharti for (i = 0; i < *n; i++) 1586116491Sharti val[i] = READ4(sc, HE_REGO_SUNI + 4 * (reg + i)); 1587116491Sharti 1588116491Sharti return (0); 1589116491Sharti} 1590116491Sharti 1591116491Sharti/* 1592116491Sharti * change the bits given by mask to them in val in register reg 1593116491Sharti */ 1594116491Shartistatic int 1595116491Shartihatm_utopia_writereg(struct ifatm *ifatm, u_int reg, u_int mask, u_int val) 1596116491Sharti{ 1597116491Sharti uint32_t regval; 1598116491Sharti struct hatm_softc *sc = (struct hatm_softc *)ifatm; 1599116491Sharti 1600116491Sharti if (reg >= (HE_REGO_SUNI_END - HE_REGO_SUNI) / 4) 1601116491Sharti return (EINVAL); 1602116491Sharti 1603116491Sharti mtx_assert(&sc->mtx, MA_OWNED); 1604116491Sharti regval = READ4(sc, HE_REGO_SUNI + 4 * reg); 1605116491Sharti regval = (regval & ~mask) | (val & mask); 1606116491Sharti WRITE4(sc, HE_REGO_SUNI + 4 * reg, regval); 1607116491Sharti 1608116491Sharti return (0); 1609116491Sharti} 1610116491Sharti 1611116491Shartistatic struct utopia_methods hatm_utopia_methods = { 1612116491Sharti hatm_utopia_readregs, 1613116491Sharti hatm_utopia_writereg, 1614116491Sharti}; 1615116491Sharti 1616116491Sharti/* 1617116491Sharti * Detach - if it is running, stop. Destroy. 1618116491Sharti */ 1619116491Shartistatic int 1620116491Shartihatm_detach(device_t dev) 1621116491Sharti{ 1622116491Sharti struct hatm_softc *sc = (struct hatm_softc *)device_get_softc(dev); 1623116491Sharti 1624116491Sharti mtx_lock(&sc->mtx); 1625116491Sharti hatm_stop(sc); 1626116491Sharti if (sc->utopia.state & UTP_ST_ATTACHED) { 1627116491Sharti utopia_stop(&sc->utopia); 1628116491Sharti utopia_detach(&sc->utopia); 1629116491Sharti } 1630116491Sharti mtx_unlock(&sc->mtx); 1631116491Sharti 1632116491Sharti atm_ifdetach(&sc->ifatm.ifnet); 1633116491Sharti 1634116491Sharti hatm_destroy(sc); 1635116491Sharti 1636116491Sharti return (0); 1637116491Sharti} 1638116491Sharti 1639116491Sharti/* 1640116491Sharti * Attach to the device. Assume that no locking is needed here. 1641116491Sharti * All resource we allocate here are freed by calling hatm_destroy. 1642116491Sharti */ 1643116491Shartistatic int 1644116491Shartihatm_attach(device_t dev) 1645116491Sharti{ 1646116491Sharti struct hatm_softc *sc; 1647116491Sharti int error; 1648116491Sharti uint32_t v; 1649116491Sharti struct ifnet *ifp; 1650116491Sharti 1651116491Sharti sc = device_get_softc(dev); 1652116491Sharti 1653116491Sharti sc->dev = dev; 1654116491Sharti sc->ifatm.mib.device = ATM_DEVICE_HE155; 1655116491Sharti sc->ifatm.mib.serial = 0; 1656116491Sharti sc->ifatm.mib.hw_version = 0; 1657116491Sharti sc->ifatm.mib.sw_version = 0; 1658116491Sharti sc->ifatm.mib.vpi_bits = HE_CONFIG_VPI_BITS; 1659116491Sharti sc->ifatm.mib.vci_bits = HE_CONFIG_VCI_BITS; 1660116491Sharti sc->ifatm.mib.max_vpcs = 0; 1661116491Sharti sc->ifatm.mib.max_vccs = HE_MAX_VCCS; 1662116491Sharti sc->ifatm.mib.media = IFM_ATM_UNKNOWN; 1663116491Sharti sc->he622 = 0; 1664116491Sharti sc->ifatm.phy = &sc->utopia; 1665116491Sharti 1666116491Sharti SLIST_INIT(&sc->tpd_free); 1667116491Sharti 1668116491Sharti mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 1669116491Sharti cv_init(&sc->vcc_cv, "HEVCCcv"); 1670116491Sharti cv_init(&sc->cv_rcclose, "RCClose"); 1671116491Sharti 1672116491Sharti sysctl_ctx_init(&sc->sysctl_ctx); 1673116491Sharti 1674116491Sharti /* 1675116491Sharti * 4.2 BIOS Configuration 1676116491Sharti */ 1677116491Sharti v = pci_read_config(dev, PCIR_COMMAND, 2); 1678116491Sharti v |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN; 1679116491Sharti pci_write_config(dev, PCIR_COMMAND, v, 2); 1680116491Sharti 1681116491Sharti /* 1682116491Sharti * 4.3 PCI Bus Controller-Specific Initialisation 1683116491Sharti */ 1684116491Sharti v = pci_read_config(dev, HE_PCIR_GEN_CNTL_0, 4); 1685116491Sharti v |= HE_PCIM_CTL0_MRL | HE_PCIM_CTL0_MRM | HE_PCIM_CTL0_IGNORE_TIMEOUT; 1686116491Sharti#if BYTE_ORDER == BIG_ENDIAN && 0 1687116491Sharti v |= HE_PCIM_CTL0_BIGENDIAN; 1688116491Sharti#endif 1689116491Sharti pci_write_config(dev, HE_PCIR_GEN_CNTL_0, v, 4); 1690116491Sharti 1691116491Sharti /* 1692116491Sharti * Map memory 1693116491Sharti */ 1694116491Sharti v = pci_read_config(dev, PCIR_COMMAND, 2); 1695116491Sharti if (!(v & PCIM_CMD_MEMEN)) { 1696116491Sharti device_printf(dev, "failed to enable memory\n"); 1697116491Sharti error = ENXIO; 1698116491Sharti goto failed; 1699116491Sharti } 1700119690Sjhb sc->memid = PCIR_BAR(0); 1701127135Snjl sc->memres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->memid, 1702127135Snjl RF_ACTIVE); 1703116491Sharti if (sc->memres == NULL) { 1704116491Sharti device_printf(dev, "could not map memory\n"); 1705116491Sharti error = ENXIO; 1706116491Sharti goto failed; 1707116491Sharti } 1708116491Sharti sc->memh = rman_get_bushandle(sc->memres); 1709116491Sharti sc->memt = rman_get_bustag(sc->memres); 1710116491Sharti 1711116491Sharti /* 1712116491Sharti * ALlocate a DMA tag for subsequent allocations 1713116491Sharti */ 1714116491Sharti if (bus_dma_tag_create(NULL, 1, 0, 1715116491Sharti BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1716116491Sharti NULL, NULL, 1717116491Sharti BUS_SPACE_MAXSIZE_32BIT, 1, 1718117126Sscottl BUS_SPACE_MAXSIZE_32BIT, 0, 1719117382Sharti NULL, NULL, &sc->parent_tag)) { 1720116491Sharti device_printf(dev, "could not allocate DMA tag\n"); 1721116491Sharti error = ENOMEM; 1722116491Sharti goto failed; 1723116491Sharti } 1724116491Sharti 1725116491Sharti if (bus_dma_tag_create(sc->parent_tag, 1, 0, 1726116491Sharti BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1727116491Sharti NULL, NULL, 1728116491Sharti MBUF_ALLOC_SIZE, 1, 1729117126Sscottl MBUF_ALLOC_SIZE, 0, 1730117382Sharti NULL, NULL, &sc->mbuf_tag)) { 1731116491Sharti device_printf(dev, "could not allocate mbuf DMA tag\n"); 1732116491Sharti error = ENOMEM; 1733116491Sharti goto failed; 1734116491Sharti } 1735116491Sharti 1736116491Sharti /* 1737116491Sharti * Allocate a DMA tag for packets to send. Here we have a problem with 1738116491Sharti * the specification of the maximum number of segments. Theoretically 1739116491Sharti * this would be the size of the transmit ring - 1 multiplied by 3, 1740116491Sharti * but this would not work. So make the maximum number of TPDs 1741116491Sharti * occupied by one packet a configuration parameter. 1742116491Sharti */ 1743116491Sharti if (bus_dma_tag_create(NULL, 1, 0, 1744116491Sharti BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1745116491Sharti HE_MAX_PDU, 3 * HE_CONFIG_MAX_TPD_PER_PACKET, HE_MAX_PDU, 0, 1746117382Sharti NULL, NULL, &sc->tx_tag)) { 1747116491Sharti device_printf(dev, "could not allocate TX tag\n"); 1748116491Sharti error = ENOMEM; 1749116491Sharti goto failed; 1750116491Sharti } 1751116491Sharti 1752116491Sharti /* 1753116491Sharti * Setup the interrupt 1754116491Sharti */ 1755116491Sharti sc->irqid = 0; 1756127135Snjl sc->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 1757127135Snjl RF_SHAREABLE | RF_ACTIVE); 1758116491Sharti if (sc->irqres == 0) { 1759116491Sharti device_printf(dev, "could not allocate irq\n"); 1760116491Sharti error = ENXIO; 1761116491Sharti goto failed; 1762116491Sharti } 1763116491Sharti 1764116491Sharti ifp = &sc->ifatm.ifnet; 1765116491Sharti ifp->if_softc = sc; 1766121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1767116491Sharti 1768116491Sharti /* 1769116491Sharti * Make the sysctl tree 1770116491Sharti */ 1771116491Sharti error = ENOMEM; 1772116491Sharti if ((sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 1773116491Sharti SYSCTL_STATIC_CHILDREN(_hw_atm), OID_AUTO, 1774116491Sharti device_get_nameunit(dev), CTLFLAG_RD, 0, "")) == NULL) 1775116491Sharti goto failed; 1776116491Sharti 1777116491Sharti if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 1778116491Sharti OID_AUTO, "istats", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, CTL_ISTATS, 1779116491Sharti hatm_sysctl, "LU", "internal statistics") == NULL) 1780116491Sharti goto failed; 1781116491Sharti 1782116491Sharti#ifdef HATM_DEBUG 1783116491Sharti if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 1784116491Sharti OID_AUTO, "tsr", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, 0, 1785116491Sharti hatm_sysctl_tsr, "S", "transmission status registers") == NULL) 1786116491Sharti goto failed; 1787116491Sharti 1788116491Sharti if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 1789116491Sharti OID_AUTO, "tpd", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, 0, 1790116491Sharti hatm_sysctl_tpd, "S", "transmission packet descriptors") == NULL) 1791116491Sharti goto failed; 1792116491Sharti 1793116491Sharti if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 1794116491Sharti OID_AUTO, "mbox", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, 0, 1795116491Sharti hatm_sysctl_mbox, "S", "mbox registers") == NULL) 1796116491Sharti goto failed; 1797116491Sharti 1798116491Sharti if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 1799116491Sharti OID_AUTO, "cm", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, 0, 1800116491Sharti hatm_sysctl_cm, "S", "connection memory") == NULL) 1801116491Sharti goto failed; 1802116491Sharti 1803116491Sharti if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 1804116491Sharti OID_AUTO, "heregs", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, 0, 1805116491Sharti hatm_sysctl_heregs, "S", "card registers") == NULL) 1806116491Sharti goto failed; 1807116491Sharti 1808116491Sharti if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 1809116491Sharti OID_AUTO, "lbmem", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, 0, 1810116491Sharti hatm_sysctl_lbmem, "S", "local memory") == NULL) 1811116491Sharti goto failed; 1812116491Sharti 1813121681Sharti kenv_getuint(sc, "debug", &sc->debug, HATM_DEBUG, 1); 1814116491Sharti#endif 1815116491Sharti 1816116491Sharti /* 1817116491Sharti * Configure 1818116491Sharti */ 1819116491Sharti if ((error = hatm_configure(sc)) != 0) 1820116491Sharti goto failed; 1821116491Sharti 1822116491Sharti /* 1823116491Sharti * Compute memory parameters 1824116491Sharti */ 1825116491Sharti if (sc->rbp_s0.size != 0) { 1826116491Sharti sc->rbp_s0.mask = (sc->rbp_s0.size - 1) << 3; 1827116491Sharti sc->rbp_s0.mem.size = sc->rbp_s0.size * 8; 1828116491Sharti sc->rbp_s0.mem.align = sc->rbp_s0.mem.size; 1829116491Sharti } 1830116491Sharti if (sc->rbp_l0.size != 0) { 1831116491Sharti sc->rbp_l0.mask = (sc->rbp_l0.size - 1) << 3; 1832116491Sharti sc->rbp_l0.mem.size = sc->rbp_l0.size * 8; 1833116491Sharti sc->rbp_l0.mem.align = sc->rbp_l0.mem.size; 1834116491Sharti } 1835116491Sharti if (sc->rbp_s1.size != 0) { 1836116491Sharti sc->rbp_s1.mask = (sc->rbp_s1.size - 1) << 3; 1837116491Sharti sc->rbp_s1.mem.size = sc->rbp_s1.size * 8; 1838116491Sharti sc->rbp_s1.mem.align = sc->rbp_s1.mem.size; 1839116491Sharti } 1840116491Sharti if (sc->rbrq_0.size != 0) { 1841116491Sharti sc->rbrq_0.mem.size = sc->rbrq_0.size * 8; 1842116491Sharti sc->rbrq_0.mem.align = sc->rbrq_0.mem.size; 1843116491Sharti } 1844116491Sharti if (sc->rbrq_1.size != 0) { 1845116491Sharti sc->rbrq_1.mem.size = sc->rbrq_1.size * 8; 1846116491Sharti sc->rbrq_1.mem.align = sc->rbrq_1.mem.size; 1847116491Sharti } 1848116491Sharti 1849116491Sharti sc->irq_0.mem.size = sc->irq_0.size * sizeof(uint32_t); 1850116491Sharti sc->irq_0.mem.align = 4 * 1024; 1851116491Sharti 1852116491Sharti sc->tbrq.mem.size = sc->tbrq.size * 4; 1853116491Sharti sc->tbrq.mem.align = 2 * sc->tbrq.mem.size; /* ZZZ */ 1854116491Sharti 1855116491Sharti sc->tpdrq.mem.size = sc->tpdrq.size * 8; 1856116491Sharti sc->tpdrq.mem.align = sc->tpdrq.mem.size; 1857116491Sharti 1858116491Sharti sc->hsp_mem.size = sizeof(struct he_hsp); 1859116491Sharti sc->hsp_mem.align = 1024; 1860116491Sharti 1861116491Sharti sc->lbufs_size = sc->rbp_l0.size + sc->rbrq_0.size; 1862116491Sharti sc->tpd_total = sc->tbrq.size + sc->tpdrq.size; 1863116491Sharti sc->tpds.align = 64; 1864116491Sharti sc->tpds.size = sc->tpd_total * HE_TPD_SIZE; 1865116491Sharti 1866116491Sharti hatm_init_rmaps(sc); 1867116491Sharti hatm_init_smbufs(sc); 1868116491Sharti if ((error = hatm_init_tpds(sc)) != 0) 1869116491Sharti goto failed; 1870116491Sharti 1871116491Sharti /* 1872116491Sharti * Allocate memory 1873116491Sharti */ 1874116491Sharti if ((error = hatm_alloc_dmamem(sc, "IRQ", &sc->irq_0.mem)) != 0 || 1875116491Sharti (error = hatm_alloc_dmamem(sc, "TBRQ0", &sc->tbrq.mem)) != 0 || 1876116491Sharti (error = hatm_alloc_dmamem(sc, "TPDRQ", &sc->tpdrq.mem)) != 0 || 1877116491Sharti (error = hatm_alloc_dmamem(sc, "HSP", &sc->hsp_mem)) != 0) 1878116491Sharti goto failed; 1879116491Sharti 1880116491Sharti if (sc->rbp_s0.mem.size != 0 && 1881116491Sharti (error = hatm_alloc_dmamem(sc, "RBPS0", &sc->rbp_s0.mem))) 1882116491Sharti goto failed; 1883116491Sharti if (sc->rbp_l0.mem.size != 0 && 1884116491Sharti (error = hatm_alloc_dmamem(sc, "RBPL0", &sc->rbp_l0.mem))) 1885116491Sharti goto failed; 1886116491Sharti if (sc->rbp_s1.mem.size != 0 && 1887116491Sharti (error = hatm_alloc_dmamem(sc, "RBPS1", &sc->rbp_s1.mem))) 1888116491Sharti goto failed; 1889116491Sharti 1890116491Sharti if (sc->rbrq_0.mem.size != 0 && 1891116491Sharti (error = hatm_alloc_dmamem(sc, "RBRQ0", &sc->rbrq_0.mem))) 1892116491Sharti goto failed; 1893116491Sharti if (sc->rbrq_1.mem.size != 0 && 1894116491Sharti (error = hatm_alloc_dmamem(sc, "RBRQ1", &sc->rbrq_1.mem))) 1895116491Sharti goto failed; 1896116491Sharti 1897116491Sharti if ((sc->vcc_zone = uma_zcreate("HE vccs", sizeof(struct hevcc), 1898116491Sharti NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 0)) == NULL) { 1899116491Sharti device_printf(dev, "cannot allocate zone for vccs\n"); 1900116491Sharti goto failed; 1901116491Sharti } 1902116491Sharti 1903116491Sharti /* 1904116491Sharti * 4.4 Reset the card. 1905116491Sharti */ 1906116491Sharti if ((error = hatm_reset(sc)) != 0) 1907116491Sharti goto failed; 1908116491Sharti 1909116491Sharti /* 1910116491Sharti * Read the prom. 1911116491Sharti */ 1912116491Sharti hatm_init_bus_width(sc); 1913116491Sharti hatm_init_read_eeprom(sc); 1914116491Sharti hatm_init_endianess(sc); 1915116491Sharti 1916116491Sharti /* 1917116491Sharti * Initialize interface 1918116491Sharti */ 1919116491Sharti ifp->if_flags = IFF_SIMPLEX; 1920116491Sharti ifp->if_ioctl = hatm_ioctl; 1921116491Sharti ifp->if_start = hatm_start; 1922116491Sharti ifp->if_watchdog = NULL; 1923116491Sharti ifp->if_init = hatm_init; 1924116491Sharti 1925116491Sharti utopia_attach(&sc->utopia, &sc->ifatm, &sc->media, &sc->mtx, 1926116491Sharti &sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 1927116491Sharti &hatm_utopia_methods); 1928116491Sharti utopia_init_media(&sc->utopia); 1929116491Sharti 1930116491Sharti /* these two SUNI routines need the lock */ 1931116491Sharti mtx_lock(&sc->mtx); 1932116491Sharti /* poll while we are not running */ 1933116491Sharti sc->utopia.flags |= UTP_FL_POLL_CARRIER; 1934116491Sharti utopia_start(&sc->utopia); 1935116491Sharti utopia_reset(&sc->utopia); 1936116491Sharti mtx_unlock(&sc->mtx); 1937116491Sharti 1938116491Sharti atm_ifattach(ifp); 1939116491Sharti 1940116491Sharti#ifdef ENABLE_BPF 1941116491Sharti bpfattach(ifp, DLT_ATM_RFC1483, sizeof(struct atmllc)); 1942116491Sharti#endif 1943116491Sharti 1944122113Sharti error = bus_setup_intr(dev, sc->irqres, sc->mpsafe | INTR_TYPE_NET, 1945122113Sharti hatm_intr, &sc->irq_0, &sc->ih); 1946116491Sharti if (error != 0) { 1947116491Sharti device_printf(dev, "could not setup interrupt\n"); 1948116491Sharti hatm_detach(dev); 1949116491Sharti return (error); 1950116491Sharti } 1951116491Sharti 1952116491Sharti return (0); 1953116491Sharti 1954116491Sharti failed: 1955116491Sharti hatm_destroy(sc); 1956116491Sharti return (error); 1957116491Sharti} 1958116491Sharti 1959116491Sharti/* 1960116491Sharti * Start the interface. Assume a state as from attach(). 1961116491Sharti */ 1962116491Shartivoid 1963116491Shartihatm_initialize(struct hatm_softc *sc) 1964116491Sharti{ 1965116491Sharti uint32_t v; 1966118598Sharti u_int cid; 1967116491Sharti static const u_int layout[2][7] = HE_CONFIG_MEM_LAYOUT; 1968116491Sharti 1969116491Sharti if (sc->ifatm.ifnet.if_flags & IFF_RUNNING) 1970116491Sharti return; 1971116491Sharti 1972116491Sharti hatm_init_bus_width(sc); 1973116491Sharti hatm_init_endianess(sc); 1974116491Sharti 1975116491Sharti if_printf(&sc->ifatm.ifnet, "%s, Rev. %s, S/N %u, " 1976116491Sharti "MAC=%02x:%02x:%02x:%02x:%02x:%02x (%ubit PCI)\n", 1977116491Sharti sc->prod_id, sc->rev, sc->ifatm.mib.serial, 1978116491Sharti sc->ifatm.mib.esi[0], sc->ifatm.mib.esi[1], sc->ifatm.mib.esi[2], 1979116491Sharti sc->ifatm.mib.esi[3], sc->ifatm.mib.esi[4], sc->ifatm.mib.esi[5], 1980116491Sharti sc->pci64 ? 64 : 32); 1981116491Sharti 1982116491Sharti /* 1983116491Sharti * 4.8 SDRAM Controller Initialisation 1984116491Sharti * 4.9 Initialize RNUM value 1985116491Sharti */ 1986116491Sharti if (sc->he622) 1987116491Sharti WRITE4(sc, HE_REGO_SDRAM_CNTL, HE_REGM_SDRAM_64BIT); 1988116491Sharti else 1989116491Sharti WRITE4(sc, HE_REGO_SDRAM_CNTL, 0); 1990116491Sharti BARRIER_W(sc); 1991116491Sharti 1992116491Sharti v = READ4(sc, HE_REGO_LB_SWAP); 1993116491Sharti BARRIER_R(sc); 1994116491Sharti v |= 0xf << HE_REGS_LBSWAP_RNUM; 1995116491Sharti WRITE4(sc, HE_REGO_LB_SWAP, v); 1996116491Sharti BARRIER_W(sc); 1997116491Sharti 1998116491Sharti hatm_init_irq(sc, &sc->irq_0, 0); 1999116491Sharti hatm_clear_irq(sc, 1); 2000116491Sharti hatm_clear_irq(sc, 2); 2001116491Sharti hatm_clear_irq(sc, 3); 2002116491Sharti 2003116491Sharti WRITE4(sc, HE_REGO_GRP_1_0_MAP, 0); 2004116491Sharti WRITE4(sc, HE_REGO_GRP_3_2_MAP, 0); 2005116491Sharti WRITE4(sc, HE_REGO_GRP_5_4_MAP, 0); 2006116491Sharti WRITE4(sc, HE_REGO_GRP_7_6_MAP, 0); 2007116491Sharti BARRIER_W(sc); 2008116491Sharti 2009116491Sharti /* 2010116491Sharti * 4.11 Enable PCI Bus Controller State Machine 2011116491Sharti */ 2012116491Sharti v = READ4(sc, HE_REGO_HOST_CNTL); 2013116491Sharti BARRIER_R(sc); 2014116491Sharti v |= HE_REGM_HOST_OUTFF_ENB | HE_REGM_HOST_CMDFF_ENB | 2015116491Sharti HE_REGM_HOST_QUICK_RD | HE_REGM_HOST_QUICK_WR; 2016116491Sharti WRITE4(sc, HE_REGO_HOST_CNTL, v); 2017116491Sharti BARRIER_W(sc); 2018116491Sharti 2019116491Sharti /* 2020116491Sharti * 5.1.1 Generic configuration state 2021116491Sharti */ 2022116491Sharti sc->cells_per_row = layout[sc->he622][0]; 2023116491Sharti sc->bytes_per_row = layout[sc->he622][1]; 2024116491Sharti sc->r0_numrows = layout[sc->he622][2]; 2025116491Sharti sc->tx_numrows = layout[sc->he622][3]; 2026116491Sharti sc->r1_numrows = layout[sc->he622][4]; 2027116491Sharti sc->r0_startrow = layout[sc->he622][5]; 2028116491Sharti sc->tx_startrow = sc->r0_startrow + sc->r0_numrows; 2029116491Sharti sc->r1_startrow = sc->tx_startrow + sc->tx_numrows; 2030116491Sharti sc->cells_per_lbuf = layout[sc->he622][6]; 2031116491Sharti 2032116491Sharti sc->r0_numbuffs = sc->r0_numrows * (sc->cells_per_row / 2033116491Sharti sc->cells_per_lbuf); 2034116491Sharti sc->r1_numbuffs = sc->r1_numrows * (sc->cells_per_row / 2035116491Sharti sc->cells_per_lbuf); 2036116491Sharti sc->tx_numbuffs = sc->tx_numrows * (sc->cells_per_row / 2037116491Sharti sc->cells_per_lbuf); 2038116491Sharti 2039116491Sharti if (sc->r0_numbuffs > 2560) 2040116491Sharti sc->r0_numbuffs = 2560; 2041116491Sharti if (sc->r1_numbuffs > 2560) 2042116491Sharti sc->r1_numbuffs = 2560; 2043116491Sharti if (sc->tx_numbuffs > 5120) 2044116491Sharti sc->tx_numbuffs = 5120; 2045116491Sharti 2046116491Sharti DBG(sc, ATTACH, ("cells_per_row=%u bytes_per_row=%u r0_numrows=%u " 2047116491Sharti "tx_numrows=%u r1_numrows=%u r0_startrow=%u tx_startrow=%u " 2048116491Sharti "r1_startrow=%u cells_per_lbuf=%u\nr0_numbuffs=%u r1_numbuffs=%u " 2049116491Sharti "tx_numbuffs=%u\n", sc->cells_per_row, sc->bytes_per_row, 2050116491Sharti sc->r0_numrows, sc->tx_numrows, sc->r1_numrows, sc->r0_startrow, 2051116491Sharti sc->tx_startrow, sc->r1_startrow, sc->cells_per_lbuf, 2052116491Sharti sc->r0_numbuffs, sc->r1_numbuffs, sc->tx_numbuffs)); 2053116491Sharti 2054116491Sharti /* 2055116491Sharti * 5.1.2 Configure Hardware dependend registers 2056116491Sharti */ 2057116491Sharti if (sc->he622) { 2058116491Sharti WRITE4(sc, HE_REGO_LBARB, 2059116491Sharti (0x2 << HE_REGS_LBARB_SLICE) | 2060116491Sharti (0xf << HE_REGS_LBARB_RNUM) | 2061116491Sharti (0x3 << HE_REGS_LBARB_THPRI) | 2062116491Sharti (0x3 << HE_REGS_LBARB_RHPRI) | 2063116491Sharti (0x2 << HE_REGS_LBARB_TLPRI) | 2064116491Sharti (0x1 << HE_REGS_LBARB_RLPRI) | 2065116491Sharti (0x28 << HE_REGS_LBARB_BUS_MULT) | 2066116491Sharti (0x50 << HE_REGS_LBARB_NET_PREF)); 2067116491Sharti BARRIER_W(sc); 2068116491Sharti WRITE4(sc, HE_REGO_SDRAMCON, 2069116491Sharti /* HW bug: don't use banking */ 2070116491Sharti /* HE_REGM_SDRAMCON_BANK | */ 2071116491Sharti HE_REGM_SDRAMCON_WIDE | 2072116491Sharti (0x384 << HE_REGS_SDRAMCON_REF)); 2073116491Sharti BARRIER_W(sc); 2074116491Sharti WRITE4(sc, HE_REGO_RCMCONFIG, 2075116491Sharti (0x1 << HE_REGS_RCMCONFIG_BANK_WAIT) | 2076116491Sharti (0x1 << HE_REGS_RCMCONFIG_RW_WAIT) | 2077116491Sharti (0x0 << HE_REGS_RCMCONFIG_TYPE)); 2078116491Sharti WRITE4(sc, HE_REGO_TCMCONFIG, 2079116491Sharti (0x2 << HE_REGS_TCMCONFIG_BANK_WAIT) | 2080116491Sharti (0x1 << HE_REGS_TCMCONFIG_RW_WAIT) | 2081116491Sharti (0x0 << HE_REGS_TCMCONFIG_TYPE)); 2082116491Sharti } else { 2083116491Sharti WRITE4(sc, HE_REGO_LBARB, 2084116491Sharti (0x2 << HE_REGS_LBARB_SLICE) | 2085116491Sharti (0xf << HE_REGS_LBARB_RNUM) | 2086116491Sharti (0x3 << HE_REGS_LBARB_THPRI) | 2087116491Sharti (0x3 << HE_REGS_LBARB_RHPRI) | 2088116491Sharti (0x2 << HE_REGS_LBARB_TLPRI) | 2089116491Sharti (0x1 << HE_REGS_LBARB_RLPRI) | 2090116491Sharti (0x46 << HE_REGS_LBARB_BUS_MULT) | 2091116491Sharti (0x8C << HE_REGS_LBARB_NET_PREF)); 2092116491Sharti BARRIER_W(sc); 2093116491Sharti WRITE4(sc, HE_REGO_SDRAMCON, 2094116491Sharti /* HW bug: don't use banking */ 2095116491Sharti /* HE_REGM_SDRAMCON_BANK | */ 2096116491Sharti (0x150 << HE_REGS_SDRAMCON_REF)); 2097116491Sharti BARRIER_W(sc); 2098116491Sharti WRITE4(sc, HE_REGO_RCMCONFIG, 2099116491Sharti (0x0 << HE_REGS_RCMCONFIG_BANK_WAIT) | 2100116491Sharti (0x1 << HE_REGS_RCMCONFIG_RW_WAIT) | 2101116491Sharti (0x0 << HE_REGS_RCMCONFIG_TYPE)); 2102116491Sharti WRITE4(sc, HE_REGO_TCMCONFIG, 2103116491Sharti (0x1 << HE_REGS_TCMCONFIG_BANK_WAIT) | 2104116491Sharti (0x1 << HE_REGS_TCMCONFIG_RW_WAIT) | 2105116491Sharti (0x0 << HE_REGS_TCMCONFIG_TYPE)); 2106116491Sharti } 2107116491Sharti WRITE4(sc, HE_REGO_LBCONFIG, (sc->cells_per_lbuf * 48)); 2108116491Sharti 2109116491Sharti WRITE4(sc, HE_REGO_RLBC_H, 0); 2110116491Sharti WRITE4(sc, HE_REGO_RLBC_T, 0); 2111116491Sharti WRITE4(sc, HE_REGO_RLBC_H2, 0); 2112116491Sharti 2113116491Sharti WRITE4(sc, HE_REGO_RXTHRSH, 512); 2114116491Sharti WRITE4(sc, HE_REGO_LITHRSH, 256); 2115116491Sharti 2116116491Sharti WRITE4(sc, HE_REGO_RLBF0_C, sc->r0_numbuffs); 2117116491Sharti WRITE4(sc, HE_REGO_RLBF1_C, sc->r1_numbuffs); 2118116491Sharti 2119116491Sharti if (sc->he622) { 2120116491Sharti WRITE4(sc, HE_REGO_RCCONFIG, 2121116491Sharti (8 << HE_REGS_RCCONFIG_UTDELAY) | 2122116491Sharti (sc->ifatm.mib.vpi_bits << HE_REGS_RCCONFIG_VP) | 2123116491Sharti (sc->ifatm.mib.vci_bits << HE_REGS_RCCONFIG_VC)); 2124116491Sharti WRITE4(sc, HE_REGO_TXCONFIG, 2125116491Sharti (32 << HE_REGS_TXCONFIG_THRESH) | 2126116491Sharti (sc->ifatm.mib.vci_bits << HE_REGS_TXCONFIG_VCI_MASK) | 2127116491Sharti (sc->tx_numbuffs << HE_REGS_TXCONFIG_LBFREE)); 2128116491Sharti } else { 2129116491Sharti WRITE4(sc, HE_REGO_RCCONFIG, 2130116491Sharti (0 << HE_REGS_RCCONFIG_UTDELAY) | 2131116491Sharti HE_REGM_RCCONFIG_UT_MODE | 2132116491Sharti (sc->ifatm.mib.vpi_bits << HE_REGS_RCCONFIG_VP) | 2133116491Sharti (sc->ifatm.mib.vci_bits << HE_REGS_RCCONFIG_VC)); 2134116491Sharti WRITE4(sc, HE_REGO_TXCONFIG, 2135116491Sharti (32 << HE_REGS_TXCONFIG_THRESH) | 2136116491Sharti HE_REGM_TXCONFIG_UTMODE | 2137116491Sharti (sc->ifatm.mib.vci_bits << HE_REGS_TXCONFIG_VCI_MASK) | 2138116491Sharti (sc->tx_numbuffs << HE_REGS_TXCONFIG_LBFREE)); 2139116491Sharti } 2140116491Sharti 2141116491Sharti WRITE4(sc, HE_REGO_TXAAL5_PROTO, 0); 2142116491Sharti 2143117382Sharti if (sc->rbp_s1.size != 0) { 2144117382Sharti WRITE4(sc, HE_REGO_RHCONFIG, 2145117382Sharti HE_REGM_RHCONFIG_PHYENB | 2146117382Sharti ((sc->he622 ? 0x41 : 0x31) << HE_REGS_RHCONFIG_PTMR_PRE) | 2147117382Sharti (1 << HE_REGS_RHCONFIG_OAM_GID)); 2148117382Sharti } else { 2149117382Sharti WRITE4(sc, HE_REGO_RHCONFIG, 2150117382Sharti HE_REGM_RHCONFIG_PHYENB | 2151117382Sharti ((sc->he622 ? 0x41 : 0x31) << HE_REGS_RHCONFIG_PTMR_PRE) | 2152117382Sharti (0 << HE_REGS_RHCONFIG_OAM_GID)); 2153117382Sharti } 2154116491Sharti BARRIER_W(sc); 2155116491Sharti 2156116491Sharti hatm_init_cm(sc); 2157116491Sharti 2158116491Sharti hatm_init_rx_buffer_pool(sc, 0, sc->r0_startrow, sc->r0_numbuffs); 2159116491Sharti hatm_init_rx_buffer_pool(sc, 1, sc->r1_startrow, sc->r1_numbuffs); 2160116491Sharti hatm_init_tx_buffer_pool(sc, sc->tx_startrow, sc->tx_numbuffs); 2161116491Sharti 2162116491Sharti hatm_init_imed_queues(sc); 2163116491Sharti 2164116491Sharti /* 2165116491Sharti * 5.1.6 Application tunable Parameters 2166116491Sharti */ 2167116491Sharti WRITE4(sc, HE_REGO_MCC, 0); 2168116491Sharti WRITE4(sc, HE_REGO_OEC, 0); 2169116491Sharti WRITE4(sc, HE_REGO_DCC, 0); 2170116491Sharti WRITE4(sc, HE_REGO_CEC, 0); 2171116491Sharti 2172116491Sharti hatm_init_cs_block(sc); 2173116491Sharti hatm_init_cs_block_cm(sc); 2174116491Sharti 2175116491Sharti hatm_init_rpool(sc, &sc->rbp_s0, 0, 0); 2176116491Sharti hatm_init_rpool(sc, &sc->rbp_l0, 0, 1); 2177116491Sharti hatm_init_rpool(sc, &sc->rbp_s1, 1, 0); 2178116491Sharti hatm_clear_rpool(sc, 1, 1); 2179116491Sharti hatm_clear_rpool(sc, 2, 0); 2180116491Sharti hatm_clear_rpool(sc, 2, 1); 2181116491Sharti hatm_clear_rpool(sc, 3, 0); 2182116491Sharti hatm_clear_rpool(sc, 3, 1); 2183116491Sharti hatm_clear_rpool(sc, 4, 0); 2184116491Sharti hatm_clear_rpool(sc, 4, 1); 2185116491Sharti hatm_clear_rpool(sc, 5, 0); 2186116491Sharti hatm_clear_rpool(sc, 5, 1); 2187116491Sharti hatm_clear_rpool(sc, 6, 0); 2188116491Sharti hatm_clear_rpool(sc, 6, 1); 2189116491Sharti hatm_clear_rpool(sc, 7, 0); 2190116491Sharti hatm_clear_rpool(sc, 7, 1); 2191116491Sharti hatm_init_rbrq(sc, &sc->rbrq_0, 0); 2192116491Sharti hatm_init_rbrq(sc, &sc->rbrq_1, 1); 2193116491Sharti hatm_clear_rbrq(sc, 2); 2194116491Sharti hatm_clear_rbrq(sc, 3); 2195116491Sharti hatm_clear_rbrq(sc, 4); 2196116491Sharti hatm_clear_rbrq(sc, 5); 2197116491Sharti hatm_clear_rbrq(sc, 6); 2198116491Sharti hatm_clear_rbrq(sc, 7); 2199116491Sharti 2200116491Sharti sc->lbufs_next = 0; 2201116491Sharti bzero(sc->lbufs, sizeof(sc->lbufs[0]) * sc->lbufs_size); 2202116491Sharti 2203116491Sharti hatm_init_tbrq(sc, &sc->tbrq, 0); 2204116491Sharti hatm_clear_tbrq(sc, 1); 2205116491Sharti hatm_clear_tbrq(sc, 2); 2206116491Sharti hatm_clear_tbrq(sc, 3); 2207116491Sharti hatm_clear_tbrq(sc, 4); 2208116491Sharti hatm_clear_tbrq(sc, 5); 2209116491Sharti hatm_clear_tbrq(sc, 6); 2210116491Sharti hatm_clear_tbrq(sc, 7); 2211116491Sharti 2212116491Sharti hatm_init_tpdrq(sc); 2213116491Sharti 2214116491Sharti WRITE4(sc, HE_REGO_UBUFF_BA, (sc->he622 ? 0x104780 : 0x800)); 2215116491Sharti 2216116491Sharti /* 2217116491Sharti * Initialize HSP 2218116491Sharti */ 2219116491Sharti bzero(sc->hsp_mem.base, sc->hsp_mem.size); 2220116491Sharti sc->hsp = sc->hsp_mem.base; 2221116491Sharti WRITE4(sc, HE_REGO_HSP_BA, sc->hsp_mem.paddr); 2222116491Sharti 2223116491Sharti /* 2224116491Sharti * 5.1.12 Enable transmit and receive 2225116491Sharti * Enable bus master and interrupts 2226116491Sharti */ 2227116491Sharti v = READ_MBOX4(sc, HE_REGO_CS_ERCTL0); 2228116491Sharti v |= 0x18000000; 2229116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_ERCTL0, v); 2230116491Sharti 2231116491Sharti v = READ4(sc, HE_REGO_RCCONFIG); 2232116491Sharti v |= HE_REGM_RCCONFIG_RXENB; 2233116491Sharti WRITE4(sc, HE_REGO_RCCONFIG, v); 2234116491Sharti 2235116491Sharti v = pci_read_config(sc->dev, HE_PCIR_GEN_CNTL_0, 4); 2236116491Sharti v |= HE_PCIM_CTL0_INIT_ENB | HE_PCIM_CTL0_INT_PROC_ENB; 2237116491Sharti pci_write_config(sc->dev, HE_PCIR_GEN_CNTL_0, v, 4); 2238116491Sharti 2239116491Sharti sc->ifatm.ifnet.if_flags |= IFF_RUNNING; 2240116491Sharti sc->ifatm.ifnet.if_baudrate = 53 * 8 * sc->ifatm.mib.pcr; 2241116491Sharti 2242116491Sharti sc->utopia.flags &= ~UTP_FL_POLL_CARRIER; 2243118170Sharti 2244118598Sharti /* reopen vccs */ 2245118598Sharti for (cid = 0; cid < HE_MAX_VCCS; cid++) 2246118598Sharti if (sc->vccs[cid] != NULL) 2247118598Sharti hatm_load_vc(sc, cid, 1); 2248118598Sharti 2249118170Sharti ATMEV_SEND_IFSTATE_CHANGED(&sc->ifatm, 2250118170Sharti sc->utopia.carrier == UTP_CARR_OK); 2251116491Sharti} 2252116491Sharti 2253116491Sharti/* 2254116491Sharti * This functions stops the card and frees all resources allocated after 2255116491Sharti * the attach. Must have the global lock. 2256116491Sharti */ 2257116491Shartivoid 2258116491Shartihatm_stop(struct hatm_softc *sc) 2259116491Sharti{ 2260116491Sharti uint32_t v; 2261116491Sharti u_int i, p, cid; 2262116491Sharti struct mbuf_chunk_hdr *ch; 2263116491Sharti struct mbuf_page *pg; 2264116491Sharti 2265116491Sharti mtx_assert(&sc->mtx, MA_OWNED); 2266116491Sharti 2267116491Sharti if (!(sc->ifatm.ifnet.if_flags & IFF_RUNNING)) 2268116491Sharti return; 2269116491Sharti sc->ifatm.ifnet.if_flags &= ~IFF_RUNNING; 2270116491Sharti 2271118170Sharti ATMEV_SEND_IFSTATE_CHANGED(&sc->ifatm, 2272118170Sharti sc->utopia.carrier == UTP_CARR_OK); 2273118170Sharti 2274116491Sharti sc->utopia.flags |= UTP_FL_POLL_CARRIER; 2275116491Sharti 2276116491Sharti /* 2277116491Sharti * Stop and reset the hardware so that everything remains 2278116491Sharti * stable. 2279116491Sharti */ 2280116491Sharti v = READ_MBOX4(sc, HE_REGO_CS_ERCTL0); 2281116491Sharti v &= ~0x18000000; 2282116491Sharti WRITE_MBOX4(sc, HE_REGO_CS_ERCTL0, v); 2283116491Sharti 2284116491Sharti v = READ4(sc, HE_REGO_RCCONFIG); 2285116491Sharti v &= ~HE_REGM_RCCONFIG_RXENB; 2286116491Sharti WRITE4(sc, HE_REGO_RCCONFIG, v); 2287116491Sharti 2288116491Sharti WRITE4(sc, HE_REGO_RHCONFIG, (0x2 << HE_REGS_RHCONFIG_PTMR_PRE)); 2289116491Sharti BARRIER_W(sc); 2290116491Sharti 2291116491Sharti v = READ4(sc, HE_REGO_HOST_CNTL); 2292116491Sharti BARRIER_R(sc); 2293116491Sharti v &= ~(HE_REGM_HOST_OUTFF_ENB | HE_REGM_HOST_CMDFF_ENB); 2294116491Sharti WRITE4(sc, HE_REGO_HOST_CNTL, v); 2295116491Sharti BARRIER_W(sc); 2296116491Sharti 2297116491Sharti /* 2298116491Sharti * Disable bust master and interrupts 2299116491Sharti */ 2300116491Sharti v = pci_read_config(sc->dev, HE_PCIR_GEN_CNTL_0, 4); 2301116491Sharti v &= ~(HE_PCIM_CTL0_INIT_ENB | HE_PCIM_CTL0_INT_PROC_ENB); 2302116491Sharti pci_write_config(sc->dev, HE_PCIR_GEN_CNTL_0, v, 4); 2303116491Sharti 2304116491Sharti (void)hatm_reset(sc); 2305116491Sharti 2306116491Sharti /* 2307117687Sharti * Card resets the SUNI when resetted, so re-initialize it 2308117687Sharti */ 2309117687Sharti utopia_reset(&sc->utopia); 2310117687Sharti 2311117687Sharti /* 2312116491Sharti * Give any waiters on closing a VCC a chance. They will stop 2313116491Sharti * to wait if they see that IFF_RUNNING disappeared. 2314116491Sharti */ 2315126396Sscottl cv_broadcast(&sc->vcc_cv); 2316126396Sscottl cv_broadcast(&sc->cv_rcclose); 2317116491Sharti 2318116491Sharti /* 2319116491Sharti * Now free all resources. 2320116491Sharti */ 2321116491Sharti 2322116491Sharti /* 2323116491Sharti * Free the large mbufs that are given to the card. 2324116491Sharti */ 2325116491Sharti for (i = 0 ; i < sc->lbufs_size; i++) { 2326116491Sharti if (sc->lbufs[i] != NULL) { 2327116491Sharti bus_dmamap_unload(sc->mbuf_tag, sc->rmaps[i]); 2328116491Sharti m_freem(sc->lbufs[i]); 2329116491Sharti sc->lbufs[i] = NULL; 2330116491Sharti } 2331116491Sharti } 2332116491Sharti 2333116491Sharti /* 2334116491Sharti * Free small buffers 2335116491Sharti */ 2336116491Sharti for (p = 0; p < sc->mbuf_npages; p++) { 2337116491Sharti pg = sc->mbuf_pages[p]; 2338116491Sharti for (i = 0; i < pg->hdr.nchunks; i++) { 2339121729Sharti ch = (struct mbuf_chunk_hdr *) ((char *)pg + 2340121729Sharti i * pg->hdr.chunksize + pg->hdr.hdroff); 2341121729Sharti if (ch->flags & MBUF_CARD) { 2342121729Sharti ch->flags &= ~MBUF_CARD; 2343121729Sharti ch->flags |= MBUF_USED; 2344121729Sharti hatm_ext_free(&sc->mbuf_list[pg->hdr.pool], 2345121729Sharti (struct mbufx_free *)((u_char *)ch - 2346121729Sharti pg->hdr.hdroff)); 2347116491Sharti } 2348116491Sharti } 2349116491Sharti } 2350116491Sharti 2351116491Sharti hatm_stop_tpds(sc); 2352116491Sharti 2353116491Sharti /* 2354116491Sharti * Free all partial reassembled PDUs on any VCC. 2355116491Sharti */ 2356116491Sharti for (cid = 0; cid < HE_MAX_VCCS; cid++) { 2357116491Sharti if (sc->vccs[cid] != NULL) { 2358118598Sharti if (sc->vccs[cid]->chain != NULL) { 2359116491Sharti m_freem(sc->vccs[cid]->chain); 2360118598Sharti sc->vccs[cid]->chain = NULL; 2361118598Sharti sc->vccs[cid]->last = NULL; 2362118598Sharti } 2363118598Sharti if (!(sc->vccs[cid]->vflags & (HE_VCC_RX_OPEN | 2364118598Sharti HE_VCC_TX_OPEN))) { 2365118598Sharti hatm_tx_vcc_closed(sc, cid); 2366118598Sharti uma_zfree(sc->vcc_zone, sc->vccs[cid]); 2367118598Sharti sc->vccs[cid] = NULL; 2368118598Sharti sc->open_vccs--; 2369118598Sharti } else { 2370118598Sharti sc->vccs[cid]->vflags = 0; 2371118598Sharti sc->vccs[cid]->ntpds = 0; 2372118598Sharti } 2373116491Sharti } 2374116491Sharti } 2375116491Sharti 2376116491Sharti if (sc->rbp_s0.size != 0) 2377116491Sharti bzero(sc->rbp_s0.mem.base, sc->rbp_s0.mem.size); 2378116491Sharti if (sc->rbp_l0.size != 0) 2379116491Sharti bzero(sc->rbp_l0.mem.base, sc->rbp_l0.mem.size); 2380116491Sharti if (sc->rbp_s1.size != 0) 2381116491Sharti bzero(sc->rbp_s1.mem.base, sc->rbp_s1.mem.size); 2382116491Sharti if (sc->rbrq_0.size != 0) 2383116491Sharti bzero(sc->rbrq_0.mem.base, sc->rbrq_0.mem.size); 2384116491Sharti if (sc->rbrq_1.size != 0) 2385116491Sharti bzero(sc->rbrq_1.mem.base, sc->rbrq_1.mem.size); 2386116491Sharti 2387116491Sharti bzero(sc->tbrq.mem.base, sc->tbrq.mem.size); 2388116491Sharti bzero(sc->tpdrq.mem.base, sc->tpdrq.mem.size); 2389116491Sharti bzero(sc->hsp_mem.base, sc->hsp_mem.size); 2390116491Sharti} 2391116491Sharti 2392116491Sharti/************************************************************ 2393116491Sharti * 2394116491Sharti * Driver infrastructure 2395116491Sharti */ 2396116491Shartidevclass_t hatm_devclass; 2397116491Sharti 2398116491Shartistatic device_method_t hatm_methods[] = { 2399116491Sharti DEVMETHOD(device_probe, hatm_probe), 2400116491Sharti DEVMETHOD(device_attach, hatm_attach), 2401116491Sharti DEVMETHOD(device_detach, hatm_detach), 2402116491Sharti {0,0} 2403116491Sharti}; 2404116491Shartistatic driver_t hatm_driver = { 2405116491Sharti "hatm", 2406116491Sharti hatm_methods, 2407116491Sharti sizeof(struct hatm_softc), 2408116491Sharti}; 2409116491ShartiDRIVER_MODULE(hatm, pci, hatm_driver, hatm_devclass, NULL, 0); 2410