if_exreg.h revision 21769
1/* 2 * Copyright (c) 1996, Javier Mart�n Rueda (jmrueda@diatel.upm.es) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel EtherExpress Pro/10 Ethernet driver 30 */ 31 32/* 33 * Several constants. 34 */ 35 36/* Length of an ethernet address. */ 37#define ETHER_ADDR_LEN 6 38/* Default RAM size in board. */ 39#define CARD_RAM_SIZE 0x8000 40/* Number of I/O ports used. */ 41#define EX_IOSIZE 16 42 43/* 44 * Intel EtherExpress Pro (i82595 based) registers 45 */ 46 47/* Common registers to all banks. */ 48 49#define CMD_REG 0 50#define REG1 1 51#define REG2 2 52#define REG3 3 53#define REG4 4 54#define REG5 5 55#define REG6 6 56#define REG7 7 57#define REG8 8 58#define REG9 9 59#define REG10 10 60#define REG11 11 61#define REG12 12 62#define REG13 13 63#define REG14 14 64#define REG15 15 65 66/* Definitions for command register (CMD_REG). */ 67 68#define Switch_Bank_CMD 0 69#define MC_Setup_CMD 3 70#define Transmit_CMD 4 71#define Diagnose_CMD 7 72#define Rcv_Enable_CMD 8 73#define Rcv_Stop 11 74#define Reset_CMD 14 75#define Resume_XMT_List_CMD 28 76#define Sel_Reset_CMD 30 77#define Abort 0x20 78#define Bank0_Sel 0x00 79#define Bank1_Sel 0x40 80#define Bank2_Sel 0x80 81 82/* Bank 0 specific registers. */ 83 84#define STATUS_REG 1 85#define ID_REG 2 86#define Id_Mask 0x2c 87#define Id_Sig 0x24 88#define Counter_bits 0xc0 89#define MASK_REG 3 90#define Exec_Int 0x08 91#define Tx_Int 0x04 92#define Rx_Int 0x02 93#define Rx_Stp_Int 0x01 94#define All_Int 0x0f 95#define RCV_BAR 4 96#define RCV_BAR_Lo 4 97#define RCV_BAR_Hi 5 98#define RCV_STOP_REG 6 99#define XMT_BAR 10 100#define HOST_ADDR_REG 12 /* 16-bit register */ 101#define IO_PORT_REG 14 /* 16-bit register */ 102 103/* Bank 1 specific registers. */ 104 105#define TriST_INT 0x80 106#define INT_NO_REG 2 107#define RCV_LOWER_LIMIT_REG 8 108#define RCV_UPPER_LIMIT_REG 9 109#define XMT_LOWER_LIMIT_REG 10 110#define XMT_UPPER_LIMIT_REG 11 111 112/* Bank 2 specific registers. */ 113 114#define Disc_Bad_Fr 0x80 115#define Tx_Chn_ErStp 0x40 116#define Tx_Chn_Int_Md 0x20 117#define No_SA_Ins 0x10 118#define RX_CRC_InMem 0x04 119#define BNC_bit 0x20 120#define TPE_bit 0x04 121#define I_ADDR_REG0 4 122#define EEPROM_REG 10 123#define Trnoff_Enable 0x10 124 125/* EEPROM memory positions (16-bit wide). */ 126 127#define EE_IRQ_No 1 128#define IRQ_No_Mask 0x07 129#define EE_Eth_Addr_Lo 2 130#define EE_Eth_Addr_Mid 3 131#define EE_Eth_Addr_Hi 4 132 133/* EEPROM serial interface. */ 134 135#define EESK 0x01 136#define EECS 0x02 137#define EEDI 0x04 138#define EEDO 0x08 139#define EE_READ_CMD (6 << 6) 140 141/* Frame chain constants. */ 142 143/* Transmit header length (in board's ring buffer). */ 144#define XMT_HEADER_LEN 8 145#define XMT_Chain_Point 4 146#define XMT_Byte_Count 6 147#define Done_bit 0x0080 148#define Ch_bit 0x8000 149/* Transmit result bits. */ 150#define No_Collisions_bits 0x000f 151#define TX_OK_bit 0x2000 152/* Receive result bits. */ 153#define RCV_Done 8 154#define RCV_OK_bit 0x2000 155