arswitchreg.h revision 253572
1139749Simp/*- 285459Sjlemon * Copyright (c) 2011 Aleksandr Rybalko. 385459Sjlemon * All rights reserved. 485459Sjlemon * 585459Sjlemon * Redistribution and use in source and binary forms, with or without 685459Sjlemon * modification, are permitted provided that the following conditions 785459Sjlemon * are met: 885459Sjlemon * 1. Redistributions of source code must retain the above copyright 985459Sjlemon * notice, this list of conditions and the following disclaimer. 1085459Sjlemon * 2. Redistributions in binary form must reproduce the above copyright 1185459Sjlemon * notice, this list of conditions and the following disclaimer in the 1285459Sjlemon * documentation and/or other materials provided with the distribution. 1385459Sjlemon * 1485459Sjlemon * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1585459Sjlemon * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1685459Sjlemon * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1785459Sjlemon * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1885459Sjlemon * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1985459Sjlemon * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2085459Sjlemon * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2185459Sjlemon * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2285459Sjlemon * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2385459Sjlemon * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2485459Sjlemon * SUCH DAMAGE. 2585459Sjlemon * 2685459Sjlemon * $FreeBSD: head/sys/dev/etherswitch/arswitch/arswitchreg.h 253572 2013-07-23 14:24:22Z loos $ 2785459Sjlemon */ 2885459Sjlemon 2985459Sjlemon#ifndef __AR8X16_SWITCHREG_H__ 3085459Sjlemon#define __AR8X16_SWITCHREG_H__ 3185459Sjlemon 3285459Sjlemon/* XXX doesn't belong here; stolen shamelessly from ath_hal/ah_internal.h */ 3385459Sjlemon/* 3485459Sjlemon * Register manipulation macros that expect bit field defines 3585459Sjlemon * to follow the convention that an _S suffix is appended for 3685459Sjlemon * a shift count, while the field mask has no suffix. 3785459Sjlemon */ 3885459Sjlemon#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 3985459Sjlemon#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 4085459Sjlemon 4185459Sjlemon/* Atheros specific MII registers */ 4285459Sjlemon#define MII_ATH_DBG_ADDR 0x1d 4385459Sjlemon#define MII_ATH_DBG_DATA 0x1e 4485459Sjlemon 4585459Sjlemon#define AR8X16_REG_MASK_CTRL 0x0000 4685459Sjlemon#define AR8X16_MASK_CTRL_REV_MASK 0x000000ff 4785459Sjlemon#define AR8X16_MASK_CTRL_VER_MASK 0x0000ff00 4885459Sjlemon#define AR8X16_MASK_CTRL_VER_SHIFT 8 4985459Sjlemon#define AR8X16_MASK_CTRL_SOFT_RESET (1 << 31) 5085459Sjlemon 5185459Sjlemon#define AR8X16_REG_MODE 0x0008 5285459Sjlemon/* DIR-615 E4 U-Boot */ 5385459Sjlemon#define AR8X16_MODE_DIR_615_UBOOT 0x8d1003e0 5485459Sjlemon/* From Ubiquiti RSPRO */ 5585459Sjlemon#define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea 5685459Sjlemon#define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2 5785459Sjlemon/* AVM Fritz!Box 7390 */ 5885459Sjlemon#define AR8X16_MODE_GMII 0x010e5b71 5985459Sjlemon/* from avm_cpmac/linux_ar_reg.h */ 6085459Sjlemon#define AR8X16_MODE_RESERVED 0x000e1b20 6185459Sjlemon#define AR8X16_MODE_MAC0_GMII_EN (1u << 0) 6285459Sjlemon#define AR8X16_MODE_MAC0_RGMII_EN (1u << 1) 6385459Sjlemon#define AR8X16_MODE_PHY4_GMII_EN (1u << 2) 6485459Sjlemon#define AR8X16_MODE_PHY4_RGMII_EN (1u << 3) 6585459Sjlemon#define AR8X16_MODE_MAC0_MAC_MODE (1u << 4) 6685459Sjlemon#define AR8X16_MODE_RGMII_RXCLK_DELAY_EN (1u << 6) 6785459Sjlemon#define AR8X16_MODE_RGMII_TXCLK_DELAY_EN (1u << 7) 6885459Sjlemon#define AR8X16_MODE_MAC5_MAC_MODE (1u << 14) 6985459Sjlemon#define AR8X16_MODE_MAC5_PHY_MODE (1u << 15) 7085459Sjlemon#define AR8X16_MODE_TXDELAY_S0 (1u << 21) 7185459Sjlemon#define AR8X16_MODE_TXDELAY_S1 (1u << 22) 7285459Sjlemon#define AR8X16_MODE_RXDELAY_S0 (1u << 23) 7385459Sjlemon#define AR8X16_MODE_LED_OPEN_EN (1u << 24) 7485459Sjlemon#define AR8X16_MODE_SPI_EN (1u << 25) 7585459Sjlemon#define AR8X16_MODE_RXDELAY_S1 (1u << 26) 7685459Sjlemon#define AR8X16_MODE_POWER_ON_SEL (1u << 31) 7785459Sjlemon 7885459Sjlemon#define AR8X16_REG_ISR 0x0010 7985459Sjlemon#define AR8X16_REG_IMR 0x0014 8085459Sjlemon 8185459Sjlemon#define AR8X16_REG_SW_MAC_ADDR0 0x0020 8285459Sjlemon#define AR8X16_REG_SW_MAC_ADDR1 0x0024 8385459Sjlemon 8485459Sjlemon#define AR8X16_REG_FLOOD_MASK 0x002c 8585459Sjlemon#define AR8X16_FLOOD_MASK_BCAST_TO_CPU (1 << 26) 8685459Sjlemon 8785459Sjlemon#define AR8X16_REG_GLOBAL_CTRL 0x0030 8885459Sjlemon#define AR8216_GLOBAL_CTRL_MTU_MASK 0x00000fff 8985459Sjlemon#define AR8216_GLOBAL_CTRL_MTU_MASK_S 0 9085459Sjlemon#define AR8316_GLOBAL_CTRL_MTU_MASK 0x00007fff 9185459Sjlemon#define AR8316_GLOBAL_CTRL_MTU_MASK_S 0 9285459Sjlemon#define AR8236_GLOBAL_CTRL_MTU_MASK 0x00007fff 9385459Sjlemon#define AR8236_GLOBAL_CTRL_MTU_MASK_S 0 9485459Sjlemon#define AR7240_GLOBAL_CTRL_MTU_MASK 0x00003fff 9585459Sjlemon#define AR7240_GLOBAL_CTRL_MTU_MASK_S 0 9685459Sjlemon 9785459Sjlemon#define AR8X16_REG_VLAN_CTRL 0x0040 9885459Sjlemon#define AR8X16_VLAN_OP 0x00000007 9985459Sjlemon#define AR8X16_VLAN_OP_NOOP 0x0 10085459Sjlemon#define AR8X16_VLAN_OP_FLUSH 0x1 10185459Sjlemon#define AR8X16_VLAN_OP_LOAD 0x2 10285459Sjlemon#define AR8X16_VLAN_OP_PURGE 0x3 10385459Sjlemon#define AR8X16_VLAN_OP_REMOVE_PORT 0x4 10485459Sjlemon#define AR8X16_VLAN_OP_GET_NEXT 0x5 10585459Sjlemon#define AR8X16_VLAN_OP_GET 0x6 10685459Sjlemon#define AR8X16_VLAN_ACTIVE (1 << 3) 10785459Sjlemon#define AR8X16_VLAN_FULL (1 << 4) 10885459Sjlemon#define AR8X16_VLAN_PORT 0x00000f00 10985459Sjlemon#define AR8X16_VLAN_PORT_SHIFT 8 11085459Sjlemon#define AR8X16_VLAN_VID 0x0fff0000 11185459Sjlemon#define AR8X16_VLAN_VID_SHIFT 16 11285459Sjlemon#define AR8X16_VLAN_PRIO 0x70000000 11385459Sjlemon#define AR8X16_VLAN_PRIO_SHIFT 28 11485459Sjlemon#define AR8X16_VLAN_PRIO_EN (1 << 31) 11585459Sjlemon 11685459Sjlemon#define AR8X16_REG_VLAN_DATA 0x0044 11785459Sjlemon#define AR8X16_VLAN_MEMBER 0x0000003f 11885459Sjlemon#define AR8X16_VLAN_VALID (1 << 11) 11985459Sjlemon 12085459Sjlemon#define AR8X16_REG_ARL_CTRL0 0x0050 12185459Sjlemon#define AR8X16_REG_ARL_CTRL1 0x0054 12285459Sjlemon#define AR8X16_REG_ARL_CTRL2 0x0058 12385459Sjlemon 12485459Sjlemon#define AR8X16_REG_AT_CTRL 0x005c 12585459Sjlemon#define AR8X16_AT_CTRL_ARP_EN (1 << 20) 12685459Sjlemon 12785459Sjlemon#define AR8X16_REG_IP_PRIORITY_1 0x0060 12885459Sjlemon#define AR8X16_REG_IP_PRIORITY_2 0x0064 12985459Sjlemon#define AR8X16_REG_IP_PRIORITY_3 0x0068 13085459Sjlemon#define AR8X16_REG_IP_PRIORITY_4 0x006C 13185459Sjlemon 13285459Sjlemon#define AR8X16_REG_TAG_PRIO 0x0070 13385459Sjlemon 13485459Sjlemon#define AR8X16_REG_SERVICE_TAG 0x0074 13585459Sjlemon#define AR8X16_SERVICE_TAG_MASK 0x0000ffff 13685459Sjlemon 13785459Sjlemon#define AR8X16_REG_CPU_PORT 0x0078 13885459Sjlemon#define AR8X16_MIRROR_PORT_SHIFT 4 13985459Sjlemon#define AR8X16_MIRROR_PORT_MASK (0xf << AR8X16_MIRROR_PORT_SHIFT) 14085459Sjlemon#define AR8X16_CPU_MIRROR_PORT(_p) ((_p) << AR8X16_MIRROR_PORT_SHIFT) 14185459Sjlemon#define AR8X16_CPU_MIRROR_DIS AR8X16_CPU_MIRROR_PORT(0xf) 14285459Sjlemon#define AR8X16_CPU_PORT_EN (1 << 8) 14385459Sjlemon 14485459Sjlemon#define AR8X16_REG_MIB_FUNC0 0x0080 14585459Sjlemon#define AR8X16_MIB_TIMER_MASK 0x0000ffff 14685459Sjlemon#define AR8X16_MIB_AT_HALF_EN (1 << 16) 14785459Sjlemon#define AR8X16_MIB_BUSY (1 << 17) 14885459Sjlemon#define AR8X16_MIB_FUNC_SHIFT 24 14985459Sjlemon#define AR8X16_MIB_FUNC_NO_OP 0x0 15085459Sjlemon#define AR8X16_MIB_FUNC_FLUSH 0x1 15185459Sjlemon#define AR8X16_MIB_FUNC_CAPTURE 0x3 15285459Sjlemon#define AR8X16_MIB_FUNC_XXX (1 << 30) /* 0x40000000 */ 15385459Sjlemon 15485459Sjlemon#define AR8X16_REG_MDIO_HIGH_ADDR 0x0094 15585459Sjlemon 15685459Sjlemon#define AR8X16_REG_MDIO_CTRL 0x0098 15785459Sjlemon#define AR8X16_MDIO_CTRL_DATA_MASK 0x0000ffff 15885459Sjlemon#define AR8X16_MDIO_CTRL_REG_ADDR_SHIFT 16 15985459Sjlemon#define AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT 21 16085459Sjlemon#define AR8X16_MDIO_CTRL_CMD_WRITE 0 16185459Sjlemon#define AR8X16_MDIO_CTRL_CMD_READ (1 << 27) 16285459Sjlemon#define AR8X16_MDIO_CTRL_MASTER_EN (1 << 30) 16385459Sjlemon#define AR8X16_MDIO_CTRL_BUSY (1 << 31) 16485459Sjlemon 16585459Sjlemon#define AR8X16_REG_PORT_BASE(_p) (0x0100 + (_p) * 0x0100) 16685459Sjlemon 16785459Sjlemon#define AR8X16_REG_PORT_STS(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0000) 16885459Sjlemon#define AR8X16_PORT_STS_SPEED_MASK 0x00000003 16985459Sjlemon#define AR8X16_PORT_STS_SPEED_10 0 17085459Sjlemon#define AR8X16_PORT_STS_SPEED_100 1 17185459Sjlemon#define AR8X16_PORT_STS_SPEED_1000 2 17285459Sjlemon#define AR8X16_PORT_STS_TXMAC (1 << 2) 17385459Sjlemon#define AR8X16_PORT_STS_RXMAC (1 << 3) 17485459Sjlemon#define AR8X16_PORT_STS_TXFLOW (1 << 4) 17585459Sjlemon#define AR8X16_PORT_STS_RXFLOW (1 << 5) 17685459Sjlemon#define AR8X16_PORT_STS_DUPLEX (1 << 6) 17785459Sjlemon#define AR8X16_PORT_STS_LINK_UP (1 << 8) 17885459Sjlemon#define AR8X16_PORT_STS_LINK_AUTO (1 << 9) 17985459Sjlemon#define AR8X16_PORT_STS_LINK_PAUSE (1 << 10) 18085459Sjlemon 18185459Sjlemon#define AR8X16_REG_PORT_CTRL(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0004) 18285459Sjlemon#define AR8X16_PORT_CTRL_STATE_MASK 0x00000007 18385459Sjlemon#define AR8X16_PORT_CTRL_STATE_DISABLED 0 18485459Sjlemon#define AR8X16_PORT_CTRL_STATE_BLOCK 1 18585459Sjlemon#define AR8X16_PORT_CTRL_STATE_LISTEN 2 18685459Sjlemon#define AR8X16_PORT_CTRL_STATE_LEARN 3 18785459Sjlemon#define AR8X16_PORT_CTRL_STATE_FORWARD 4 18885459Sjlemon#define AR8X16_PORT_CTRL_LEARN_LOCK (1 << 7) 18985459Sjlemon#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT 8 19085459Sjlemon#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_KEEP 0 19185459Sjlemon#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP 1 19285459Sjlemon#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD 2 19385459Sjlemon#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_DOUBLE_TAG 3 19485459Sjlemon#define AR8X16_PORT_CTRL_IGMP_SNOOP (1 << 10) 19585459Sjlemon#define AR8X16_PORT_CTRL_HEADER (1 << 11) 19685459Sjlemon#define AR8X16_PORT_CTRL_MAC_LOOP (1 << 12) 19785459Sjlemon#define AR8X16_PORT_CTRL_SINGLE_VLAN (1 << 13) 19885459Sjlemon#define AR8X16_PORT_CTRL_LEARN (1 << 14) 19985459Sjlemon#define AR8X16_PORT_CTRL_DOUBLE_TAG (1 << 15) 20085459Sjlemon#define AR8X16_PORT_CTRL_MIRROR_TX (1 << 16) 20185459Sjlemon#define AR8X16_PORT_CTRL_MIRROR_RX (1 << 17) 20285459Sjlemon 20385459Sjlemon#define AR8X16_REG_PORT_VLAN(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0008) 20485459Sjlemon 20585459Sjlemon#define AR8X16_PORT_VLAN_DEFAULT_ID_SHIFT 0 20685459Sjlemon#define AR8X16_PORT_VLAN_DEST_PORTS_SHIFT 16 20785459Sjlemon#define AR8X16_PORT_VLAN_MODE_MASK 0xc0000000 20885459Sjlemon#define AR8X16_PORT_VLAN_MODE_SHIFT 30 20985459Sjlemon#define AR8X16_PORT_VLAN_MODE_PORT_ONLY 0 21085459Sjlemon#define AR8X16_PORT_VLAN_MODE_PORT_FALLBACK 1 21185459Sjlemon#define AR8X16_PORT_VLAN_MODE_VLAN_ONLY 2 21285459Sjlemon#define AR8X16_PORT_VLAN_MODE_SECURE 3 21385459Sjlemon 21485459Sjlemon#define AR8X16_REG_PORT_RATE_LIM(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x000c) 21585459Sjlemon#define AR8X16_PORT_RATE_LIM_128KB 0 21685459Sjlemon#define AR8X16_PORT_RATE_LIM_256KB 1 21785459Sjlemon#define AR8X16_PORT_RATE_LIM_512KB 2 21885459Sjlemon#define AR8X16_PORT_RATE_LIM_1MB 3 21985459Sjlemon#define AR8X16_PORT_RATE_LIM_2MB 4 22085459Sjlemon#define AR8X16_PORT_RATE_LIM_4MB 5 22185459Sjlemon#define AR8X16_PORT_RATE_LIM_8MB 6 22285459Sjlemon#define AR8X16_PORT_RATE_LIM_16MB 7 22385459Sjlemon#define AR8X16_PORT_RATE_LIM_32MB 8 22485459Sjlemon#define AR8X16_PORT_RATE_LIM_64MB 9 22585459Sjlemon#define AR8X16_PORT_RATE_LIM_IN_EN (1 << 24) 22685459Sjlemon#define AR8X16_PORT_RATE_LIM_OUT_EN (1 << 23) 22785459Sjlemon#define AR8X16_PORT_RATE_LIM_IN_MASK 0x000f0000 22885459Sjlemon#define AR8X16_PORT_RATE_LIM_IN_SHIFT 16 22985459Sjlemon#define AR8X16_PORT_RATE_LIM_OUT_MASK 0x0000000f 23085459Sjlemon#define AR8X16_PORT_RATE_LIM_OUT_SHIFT 0 23185459Sjlemon 23285459Sjlemon#define AR8X16_REG_PORT_PRIORITY(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0010) 23385459Sjlemon 23485459Sjlemon#define AR8X16_REG_STATS_BASE(_p) (0x20000 + (_p) * 0x100) 23585459Sjlemon 23685459Sjlemon#define AR8X16_STATS_RXBROAD 0x0000 23785459Sjlemon#define AR8X16_STATS_RXPAUSE 0x0004 23885459Sjlemon#define AR8X16_STATS_RXMULTI 0x0008 23985459Sjlemon#define AR8X16_STATS_RXFCSERR 0x000c 24085459Sjlemon#define AR8X16_STATS_RXALIGNERR 0x0010 24185459Sjlemon#define AR8X16_STATS_RXRUNT 0x0014 24285459Sjlemon#define AR8X16_STATS_RXFRAGMENT 0x0018 24385459Sjlemon#define AR8X16_STATS_RX64BYTE 0x001c 24485459Sjlemon#define AR8X16_STATS_RX128BYTE 0x0020 24585459Sjlemon#define AR8X16_STATS_RX256BYTE 0x0024 24685459Sjlemon#define AR8X16_STATS_RX512BYTE 0x0028 24785459Sjlemon#define AR8X16_STATS_RX1024BYTE 0x002c 24885459Sjlemon#define AR8X16_STATS_RX1518BYTE 0x0030 24985459Sjlemon#define AR8X16_STATS_RXMAXBYTE 0x0034 25085459Sjlemon#define AR8X16_STATS_RXTOOLONG 0x0038 25185459Sjlemon#define AR8X16_STATS_RXGOODBYTE 0x003c 25285459Sjlemon#define AR8X16_STATS_RXBADBYTE 0x0044 25385459Sjlemon#define AR8X16_STATS_RXOVERFLOW 0x004c 25485459Sjlemon#define AR8X16_STATS_FILTERED 0x0050 25585459Sjlemon#define AR8X16_STATS_TXBROAD 0x0054 25685459Sjlemon#define AR8X16_STATS_TXPAUSE 0x0058 25785459Sjlemon#define AR8X16_STATS_TXMULTI 0x005c 25885459Sjlemon#define AR8X16_STATS_TXUNDERRUN 0x0060 25985459Sjlemon#define AR8X16_STATS_TX64BYTE 0x0064 26085459Sjlemon#define AR8X16_STATS_TX128BYTE 0x0068 26185459Sjlemon#define AR8X16_STATS_TX256BYTE 0x006c 26285459Sjlemon#define AR8X16_STATS_TX512BYTE 0x0070 26385459Sjlemon#define AR8X16_STATS_TX1024BYTE 0x0074 26485459Sjlemon#define AR8X16_STATS_TX1518BYTE 0x0078 26585459Sjlemon#define AR8X16_STATS_TXMAXBYTE 0x007c 26685459Sjlemon#define AR8X16_STATS_TXOVERSIZE 0x0080 26785459Sjlemon#define AR8X16_STATS_TXBYTE 0x0084 26885459Sjlemon#define AR8X16_STATS_TXCOLLISION 0x008c 26985459Sjlemon#define AR8X16_STATS_TXABORTCOL 0x0090 27085459Sjlemon#define AR8X16_STATS_TXMULTICOL 0x0094 27185459Sjlemon#define AR8X16_STATS_TXSINGLECOL 0x0098 27285459Sjlemon#define AR8X16_STATS_TXEXCDEFER 0x009c 27385459Sjlemon#define AR8X16_STATS_TXDEFER 0x00a0 27485459Sjlemon#define AR8X16_STATS_TXLATECOL 0x00a4 27585459Sjlemon 27685459Sjlemon#define AR8X16_PORT_CPU 0 27785459Sjlemon#define AR8X16_NUM_PORTS 6 27885459Sjlemon#define AR8X16_NUM_PHYS 5 27985459Sjlemon#define AR8X16_MAGIC 0xc000050e 28085459Sjlemon 28185459Sjlemon#define AR8X16_PHY_ID1 0x004d 28285459Sjlemon#define AR8X16_PHY_ID2 0xd041 28385459Sjlemon 28485459Sjlemon#define AR8X16_PORT_MASK(_port) (1 << (_port)) 28585459Sjlemon#define AR8X16_PORT_MASK_ALL ((1<<AR8X16_NUM_PORTS)-1) 28685459Sjlemon#define AR8X16_PORT_MASK_BUT(_port) (AR8X16_PORT_MASK_ALL & ~(1 << (_port))) 28785459Sjlemon 28885459Sjlemon#define AR8X16_MAX_VLANS 16 28985459Sjlemon 29085459Sjlemon#endif /* __AR8X16_SWITCHREG_H__ */ 29185459Sjlemon 29285459Sjlemon