1235288Sadrian/*- 2235288Sadrian * Copyright (c) 2011 Aleksandr Rybalko. 3235288Sadrian * All rights reserved. 4235288Sadrian * 5235288Sadrian * Redistribution and use in source and binary forms, with or without 6235288Sadrian * modification, are permitted provided that the following conditions 7235288Sadrian * are met: 8235288Sadrian * 1. Redistributions of source code must retain the above copyright 9235288Sadrian * notice, this list of conditions and the following disclaimer. 10235288Sadrian * 2. Redistributions in binary form must reproduce the above copyright 11235288Sadrian * notice, this list of conditions and the following disclaimer in the 12235288Sadrian * documentation and/or other materials provided with the distribution. 13235288Sadrian * 14235288Sadrian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15235288Sadrian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16235288Sadrian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17235288Sadrian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18235288Sadrian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19235288Sadrian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20235288Sadrian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21235288Sadrian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22235288Sadrian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23235288Sadrian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24235288Sadrian * SUCH DAMAGE. 25235288Sadrian * 26235288Sadrian * $FreeBSD$ 27235288Sadrian */ 28235288Sadrian 29235288Sadrian#ifndef __AR8X16_SWITCHREG_H__ 30235288Sadrian#define __AR8X16_SWITCHREG_H__ 31235288Sadrian 32235367Sadrian/* XXX doesn't belong here; stolen shamelessly from ath_hal/ah_internal.h */ 33235367Sadrian/* 34235367Sadrian * Register manipulation macros that expect bit field defines 35235367Sadrian * to follow the convention that an _S suffix is appended for 36235367Sadrian * a shift count, while the field mask has no suffix. 37235367Sadrian */ 38235367Sadrian#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 39235367Sadrian#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 40235367Sadrian 41235288Sadrian/* Atheros specific MII registers */ 42235288Sadrian#define MII_ATH_DBG_ADDR 0x1d 43235288Sadrian#define MII_ATH_DBG_DATA 0x1e 44235288Sadrian 45235288Sadrian#define AR8X16_REG_MASK_CTRL 0x0000 46235288Sadrian#define AR8X16_MASK_CTRL_REV_MASK 0x000000ff 47235288Sadrian#define AR8X16_MASK_CTRL_VER_MASK 0x0000ff00 48235288Sadrian#define AR8X16_MASK_CTRL_VER_SHIFT 8 49235288Sadrian#define AR8X16_MASK_CTRL_SOFT_RESET (1 << 31) 50235288Sadrian 51235288Sadrian#define AR8X16_REG_MODE 0x0008 52235288Sadrian/* DIR-615 E4 U-Boot */ 53235288Sadrian#define AR8X16_MODE_DIR_615_UBOOT 0x8d1003e0 54235288Sadrian/* From Ubiquiti RSPRO */ 55235288Sadrian#define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea 56235288Sadrian#define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2 57235288Sadrian/* AVM Fritz!Box 7390 */ 58235288Sadrian#define AR8X16_MODE_GMII 0x010e5b71 59235288Sadrian/* from avm_cpmac/linux_ar_reg.h */ 60235288Sadrian#define AR8X16_MODE_RESERVED 0x000e1b20 61235288Sadrian#define AR8X16_MODE_MAC0_GMII_EN (1u << 0) 62235288Sadrian#define AR8X16_MODE_MAC0_RGMII_EN (1u << 1) 63235288Sadrian#define AR8X16_MODE_PHY4_GMII_EN (1u << 2) 64235288Sadrian#define AR8X16_MODE_PHY4_RGMII_EN (1u << 3) 65235288Sadrian#define AR8X16_MODE_MAC0_MAC_MODE (1u << 4) 66235288Sadrian#define AR8X16_MODE_RGMII_RXCLK_DELAY_EN (1u << 6) 67235288Sadrian#define AR8X16_MODE_RGMII_TXCLK_DELAY_EN (1u << 7) 68235288Sadrian#define AR8X16_MODE_MAC5_MAC_MODE (1u << 14) 69235288Sadrian#define AR8X16_MODE_MAC5_PHY_MODE (1u << 15) 70235288Sadrian#define AR8X16_MODE_TXDELAY_S0 (1u << 21) 71235288Sadrian#define AR8X16_MODE_TXDELAY_S1 (1u << 22) 72235288Sadrian#define AR8X16_MODE_RXDELAY_S0 (1u << 23) 73235288Sadrian#define AR8X16_MODE_LED_OPEN_EN (1u << 24) 74235288Sadrian#define AR8X16_MODE_SPI_EN (1u << 25) 75235288Sadrian#define AR8X16_MODE_RXDELAY_S1 (1u << 26) 76235288Sadrian#define AR8X16_MODE_POWER_ON_SEL (1u << 31) 77235288Sadrian 78235288Sadrian#define AR8X16_REG_ISR 0x0010 79235288Sadrian#define AR8X16_REG_IMR 0x0014 80235288Sadrian 81235288Sadrian#define AR8X16_REG_SW_MAC_ADDR0 0x0020 82235288Sadrian#define AR8X16_REG_SW_MAC_ADDR1 0x0024 83235288Sadrian 84235288Sadrian#define AR8X16_REG_FLOOD_MASK 0x002c 85235288Sadrian#define AR8X16_FLOOD_MASK_BCAST_TO_CPU (1 << 26) 86235288Sadrian 87235288Sadrian#define AR8X16_REG_GLOBAL_CTRL 0x0030 88235288Sadrian#define AR8216_GLOBAL_CTRL_MTU_MASK 0x00000fff 89235367Sadrian#define AR8216_GLOBAL_CTRL_MTU_MASK_S 0 90235288Sadrian#define AR8316_GLOBAL_CTRL_MTU_MASK 0x00007fff 91235367Sadrian#define AR8316_GLOBAL_CTRL_MTU_MASK_S 0 92235288Sadrian#define AR8236_GLOBAL_CTRL_MTU_MASK 0x00007fff 93235367Sadrian#define AR8236_GLOBAL_CTRL_MTU_MASK_S 0 94235367Sadrian#define AR7240_GLOBAL_CTRL_MTU_MASK 0x00003fff 95235367Sadrian#define AR7240_GLOBAL_CTRL_MTU_MASK_S 0 96235288Sadrian 97235288Sadrian#define AR8X16_REG_VLAN_CTRL 0x0040 98235288Sadrian#define AR8X16_VLAN_OP 0x00000007 99235288Sadrian#define AR8X16_VLAN_OP_NOOP 0x0 100235288Sadrian#define AR8X16_VLAN_OP_FLUSH 0x1 101235288Sadrian#define AR8X16_VLAN_OP_LOAD 0x2 102235288Sadrian#define AR8X16_VLAN_OP_PURGE 0x3 103235288Sadrian#define AR8X16_VLAN_OP_REMOVE_PORT 0x4 104235288Sadrian#define AR8X16_VLAN_OP_GET_NEXT 0x5 105235288Sadrian#define AR8X16_VLAN_OP_GET 0x6 106235288Sadrian#define AR8X16_VLAN_ACTIVE (1 << 3) 107235288Sadrian#define AR8X16_VLAN_FULL (1 << 4) 108235288Sadrian#define AR8X16_VLAN_PORT 0x00000f00 109235288Sadrian#define AR8X16_VLAN_PORT_SHIFT 8 110235288Sadrian#define AR8X16_VLAN_VID 0x0fff0000 111235288Sadrian#define AR8X16_VLAN_VID_SHIFT 16 112235288Sadrian#define AR8X16_VLAN_PRIO 0x70000000 113235288Sadrian#define AR8X16_VLAN_PRIO_SHIFT 28 114235288Sadrian#define AR8X16_VLAN_PRIO_EN (1 << 31) 115235288Sadrian 116235288Sadrian#define AR8X16_REG_VLAN_DATA 0x0044 117253572Sloos#define AR8X16_VLAN_MEMBER 0x0000003f 118235288Sadrian#define AR8X16_VLAN_VALID (1 << 11) 119235288Sadrian 120235288Sadrian#define AR8X16_REG_ARL_CTRL0 0x0050 121235288Sadrian#define AR8X16_REG_ARL_CTRL1 0x0054 122235288Sadrian#define AR8X16_REG_ARL_CTRL2 0x0058 123235288Sadrian 124235288Sadrian#define AR8X16_REG_AT_CTRL 0x005c 125235288Sadrian#define AR8X16_AT_CTRL_ARP_EN (1 << 20) 126235288Sadrian 127235288Sadrian#define AR8X16_REG_IP_PRIORITY_1 0x0060 128235288Sadrian#define AR8X16_REG_IP_PRIORITY_2 0x0064 129235288Sadrian#define AR8X16_REG_IP_PRIORITY_3 0x0068 130235288Sadrian#define AR8X16_REG_IP_PRIORITY_4 0x006C 131235288Sadrian 132235288Sadrian#define AR8X16_REG_TAG_PRIO 0x0070 133235288Sadrian 134235288Sadrian#define AR8X16_REG_SERVICE_TAG 0x0074 135235288Sadrian#define AR8X16_SERVICE_TAG_MASK 0x0000ffff 136235288Sadrian 137235288Sadrian#define AR8X16_REG_CPU_PORT 0x0078 138235288Sadrian#define AR8X16_MIRROR_PORT_SHIFT 4 139235325Sadrian#define AR8X16_MIRROR_PORT_MASK (0xf << AR8X16_MIRROR_PORT_SHIFT) 140235325Sadrian#define AR8X16_CPU_MIRROR_PORT(_p) ((_p) << AR8X16_MIRROR_PORT_SHIFT) 141235325Sadrian#define AR8X16_CPU_MIRROR_DIS AR8X16_CPU_MIRROR_PORT(0xf) 142235288Sadrian#define AR8X16_CPU_PORT_EN (1 << 8) 143235288Sadrian 144235288Sadrian#define AR8X16_REG_MIB_FUNC0 0x0080 145235288Sadrian#define AR8X16_MIB_TIMER_MASK 0x0000ffff 146235288Sadrian#define AR8X16_MIB_AT_HALF_EN (1 << 16) 147235288Sadrian#define AR8X16_MIB_BUSY (1 << 17) 148235288Sadrian#define AR8X16_MIB_FUNC_SHIFT 24 149235288Sadrian#define AR8X16_MIB_FUNC_NO_OP 0x0 150235288Sadrian#define AR8X16_MIB_FUNC_FLUSH 0x1 151235288Sadrian#define AR8X16_MIB_FUNC_CAPTURE 0x3 152235288Sadrian#define AR8X16_MIB_FUNC_XXX (1 << 30) /* 0x40000000 */ 153235288Sadrian 154235288Sadrian#define AR8X16_REG_MDIO_HIGH_ADDR 0x0094 155235288Sadrian 156235288Sadrian#define AR8X16_REG_MDIO_CTRL 0x0098 157235288Sadrian#define AR8X16_MDIO_CTRL_DATA_MASK 0x0000ffff 158235288Sadrian#define AR8X16_MDIO_CTRL_REG_ADDR_SHIFT 16 159235288Sadrian#define AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT 21 160235288Sadrian#define AR8X16_MDIO_CTRL_CMD_WRITE 0 161235288Sadrian#define AR8X16_MDIO_CTRL_CMD_READ (1 << 27) 162235288Sadrian#define AR8X16_MDIO_CTRL_MASTER_EN (1 << 30) 163235288Sadrian#define AR8X16_MDIO_CTRL_BUSY (1 << 31) 164235288Sadrian 165235288Sadrian#define AR8X16_REG_PORT_BASE(_p) (0x0100 + (_p) * 0x0100) 166235288Sadrian 167235288Sadrian#define AR8X16_REG_PORT_STS(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0000) 168235288Sadrian#define AR8X16_PORT_STS_SPEED_MASK 0x00000003 169235288Sadrian#define AR8X16_PORT_STS_SPEED_10 0 170235288Sadrian#define AR8X16_PORT_STS_SPEED_100 1 171235288Sadrian#define AR8X16_PORT_STS_SPEED_1000 2 172235288Sadrian#define AR8X16_PORT_STS_TXMAC (1 << 2) 173235288Sadrian#define AR8X16_PORT_STS_RXMAC (1 << 3) 174235288Sadrian#define AR8X16_PORT_STS_TXFLOW (1 << 4) 175235288Sadrian#define AR8X16_PORT_STS_RXFLOW (1 << 5) 176235288Sadrian#define AR8X16_PORT_STS_DUPLEX (1 << 6) 177235288Sadrian#define AR8X16_PORT_STS_LINK_UP (1 << 8) 178235288Sadrian#define AR8X16_PORT_STS_LINK_AUTO (1 << 9) 179235288Sadrian#define AR8X16_PORT_STS_LINK_PAUSE (1 << 10) 180235288Sadrian 181235288Sadrian#define AR8X16_REG_PORT_CTRL(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0004) 182235288Sadrian#define AR8X16_PORT_CTRL_STATE_MASK 0x00000007 183235288Sadrian#define AR8X16_PORT_CTRL_STATE_DISABLED 0 184235288Sadrian#define AR8X16_PORT_CTRL_STATE_BLOCK 1 185235288Sadrian#define AR8X16_PORT_CTRL_STATE_LISTEN 2 186235288Sadrian#define AR8X16_PORT_CTRL_STATE_LEARN 3 187235288Sadrian#define AR8X16_PORT_CTRL_STATE_FORWARD 4 188235288Sadrian#define AR8X16_PORT_CTRL_LEARN_LOCK (1 << 7) 189235288Sadrian#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT 8 190235288Sadrian#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_KEEP 0 191235288Sadrian#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP 1 192235288Sadrian#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD 2 193235288Sadrian#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_DOUBLE_TAG 3 194235288Sadrian#define AR8X16_PORT_CTRL_IGMP_SNOOP (1 << 10) 195235288Sadrian#define AR8X16_PORT_CTRL_HEADER (1 << 11) 196235288Sadrian#define AR8X16_PORT_CTRL_MAC_LOOP (1 << 12) 197235288Sadrian#define AR8X16_PORT_CTRL_SINGLE_VLAN (1 << 13) 198235288Sadrian#define AR8X16_PORT_CTRL_LEARN (1 << 14) 199235288Sadrian#define AR8X16_PORT_CTRL_DOUBLE_TAG (1 << 15) 200235288Sadrian#define AR8X16_PORT_CTRL_MIRROR_TX (1 << 16) 201235288Sadrian#define AR8X16_PORT_CTRL_MIRROR_RX (1 << 17) 202235288Sadrian 203235288Sadrian#define AR8X16_REG_PORT_VLAN(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0008) 204235288Sadrian 205235288Sadrian#define AR8X16_PORT_VLAN_DEFAULT_ID_SHIFT 0 206235288Sadrian#define AR8X16_PORT_VLAN_DEST_PORTS_SHIFT 16 207235288Sadrian#define AR8X16_PORT_VLAN_MODE_MASK 0xc0000000 208235288Sadrian#define AR8X16_PORT_VLAN_MODE_SHIFT 30 209235288Sadrian#define AR8X16_PORT_VLAN_MODE_PORT_ONLY 0 210235288Sadrian#define AR8X16_PORT_VLAN_MODE_PORT_FALLBACK 1 211235288Sadrian#define AR8X16_PORT_VLAN_MODE_VLAN_ONLY 2 212235288Sadrian#define AR8X16_PORT_VLAN_MODE_SECURE 3 213235288Sadrian 214235288Sadrian#define AR8X16_REG_PORT_RATE_LIM(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x000c) 215235288Sadrian#define AR8X16_PORT_RATE_LIM_128KB 0 216235288Sadrian#define AR8X16_PORT_RATE_LIM_256KB 1 217235288Sadrian#define AR8X16_PORT_RATE_LIM_512KB 2 218235288Sadrian#define AR8X16_PORT_RATE_LIM_1MB 3 219235288Sadrian#define AR8X16_PORT_RATE_LIM_2MB 4 220235288Sadrian#define AR8X16_PORT_RATE_LIM_4MB 5 221235288Sadrian#define AR8X16_PORT_RATE_LIM_8MB 6 222235288Sadrian#define AR8X16_PORT_RATE_LIM_16MB 7 223235288Sadrian#define AR8X16_PORT_RATE_LIM_32MB 8 224235288Sadrian#define AR8X16_PORT_RATE_LIM_64MB 9 225235288Sadrian#define AR8X16_PORT_RATE_LIM_IN_EN (1 << 24) 226235288Sadrian#define AR8X16_PORT_RATE_LIM_OUT_EN (1 << 23) 227235288Sadrian#define AR8X16_PORT_RATE_LIM_IN_MASK 0x000f0000 228235288Sadrian#define AR8X16_PORT_RATE_LIM_IN_SHIFT 16 229235288Sadrian#define AR8X16_PORT_RATE_LIM_OUT_MASK 0x0000000f 230235288Sadrian#define AR8X16_PORT_RATE_LIM_OUT_SHIFT 0 231235288Sadrian 232235288Sadrian#define AR8X16_REG_PORT_PRIORITY(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0010) 233235288Sadrian 234235288Sadrian#define AR8X16_REG_STATS_BASE(_p) (0x20000 + (_p) * 0x100) 235235288Sadrian 236235288Sadrian#define AR8X16_STATS_RXBROAD 0x0000 237235288Sadrian#define AR8X16_STATS_RXPAUSE 0x0004 238235288Sadrian#define AR8X16_STATS_RXMULTI 0x0008 239235288Sadrian#define AR8X16_STATS_RXFCSERR 0x000c 240235288Sadrian#define AR8X16_STATS_RXALIGNERR 0x0010 241235288Sadrian#define AR8X16_STATS_RXRUNT 0x0014 242235288Sadrian#define AR8X16_STATS_RXFRAGMENT 0x0018 243235288Sadrian#define AR8X16_STATS_RX64BYTE 0x001c 244235288Sadrian#define AR8X16_STATS_RX128BYTE 0x0020 245235288Sadrian#define AR8X16_STATS_RX256BYTE 0x0024 246235288Sadrian#define AR8X16_STATS_RX512BYTE 0x0028 247235288Sadrian#define AR8X16_STATS_RX1024BYTE 0x002c 248235288Sadrian#define AR8X16_STATS_RX1518BYTE 0x0030 249235288Sadrian#define AR8X16_STATS_RXMAXBYTE 0x0034 250235288Sadrian#define AR8X16_STATS_RXTOOLONG 0x0038 251235288Sadrian#define AR8X16_STATS_RXGOODBYTE 0x003c 252235288Sadrian#define AR8X16_STATS_RXBADBYTE 0x0044 253235288Sadrian#define AR8X16_STATS_RXOVERFLOW 0x004c 254235288Sadrian#define AR8X16_STATS_FILTERED 0x0050 255235288Sadrian#define AR8X16_STATS_TXBROAD 0x0054 256235288Sadrian#define AR8X16_STATS_TXPAUSE 0x0058 257235288Sadrian#define AR8X16_STATS_TXMULTI 0x005c 258235288Sadrian#define AR8X16_STATS_TXUNDERRUN 0x0060 259235288Sadrian#define AR8X16_STATS_TX64BYTE 0x0064 260235288Sadrian#define AR8X16_STATS_TX128BYTE 0x0068 261235288Sadrian#define AR8X16_STATS_TX256BYTE 0x006c 262235288Sadrian#define AR8X16_STATS_TX512BYTE 0x0070 263235288Sadrian#define AR8X16_STATS_TX1024BYTE 0x0074 264235288Sadrian#define AR8X16_STATS_TX1518BYTE 0x0078 265235288Sadrian#define AR8X16_STATS_TXMAXBYTE 0x007c 266235288Sadrian#define AR8X16_STATS_TXOVERSIZE 0x0080 267235288Sadrian#define AR8X16_STATS_TXBYTE 0x0084 268235288Sadrian#define AR8X16_STATS_TXCOLLISION 0x008c 269235288Sadrian#define AR8X16_STATS_TXABORTCOL 0x0090 270235288Sadrian#define AR8X16_STATS_TXMULTICOL 0x0094 271235288Sadrian#define AR8X16_STATS_TXSINGLECOL 0x0098 272235288Sadrian#define AR8X16_STATS_TXEXCDEFER 0x009c 273235288Sadrian#define AR8X16_STATS_TXDEFER 0x00a0 274235288Sadrian#define AR8X16_STATS_TXLATECOL 0x00a4 275235288Sadrian 276235288Sadrian#define AR8X16_PORT_CPU 0 277235288Sadrian#define AR8X16_NUM_PORTS 6 278235288Sadrian#define AR8X16_NUM_PHYS 5 279235288Sadrian#define AR8X16_MAGIC 0xc000050e 280235288Sadrian 281235288Sadrian#define AR8X16_PHY_ID1 0x004d 282235288Sadrian#define AR8X16_PHY_ID2 0xd041 283235288Sadrian 284235288Sadrian#define AR8X16_PORT_MASK(_port) (1 << (_port)) 285235288Sadrian#define AR8X16_PORT_MASK_ALL ((1<<AR8X16_NUM_PORTS)-1) 286235288Sadrian#define AR8X16_PORT_MASK_BUT(_port) (AR8X16_PORT_MASK_ALL & ~(1 << (_port))) 287235288Sadrian 288235288Sadrian#define AR8X16_MAX_VLANS 16 289235288Sadrian 290235288Sadrian#endif /* __AR8X16_SWITCHREG_H__ */ 291235288Sadrian 292