1179895Sdelphij/*- 2210661Sdelphij * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 3179895Sdelphij * 4179895Sdelphij * This code is derived from software contributed to The DragonFly Project 5179895Sdelphij * by Sepherosa Ziehau <sepherosa@gmail.com> 6179895Sdelphij * 7179895Sdelphij * Redistribution and use in source and binary forms, with or without 8179895Sdelphij * modification, are permitted provided that the following conditions 9179895Sdelphij * are met: 10179895Sdelphij * 11179895Sdelphij * 1. Redistributions of source code must retain the above copyright 12179895Sdelphij * notice, this list of conditions and the following disclaimer. 13179895Sdelphij * 2. Redistributions in binary form must reproduce the above copyright 14179895Sdelphij * notice, this list of conditions and the following disclaimer in 15179895Sdelphij * the documentation and/or other materials provided with the 16179895Sdelphij * distribution. 17179895Sdelphij * 3. Neither the name of The DragonFly Project nor the names of its 18179895Sdelphij * contributors may be used to endorse or promote products derived 19179895Sdelphij * from this software without specific, prior written permission. 20179895Sdelphij * 21179895Sdelphij * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22179895Sdelphij * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23179895Sdelphij * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24179895Sdelphij * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25179895Sdelphij * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26179895Sdelphij * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27179895Sdelphij * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28179895Sdelphij * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29179895Sdelphij * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30179895Sdelphij * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31179895Sdelphij * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32179895Sdelphij * SUCH DAMAGE. 33179895Sdelphij * 34179895Sdelphij * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $ 35179895Sdelphij */ 36179895Sdelphij 37199612Syongari#include <sys/cdefs.h> 38199612Syongari__FBSDID("$FreeBSD$"); 39199612Syongari 40179895Sdelphij#include <sys/param.h> 41179895Sdelphij#include <sys/systm.h> 42179895Sdelphij#include <sys/endian.h> 43179895Sdelphij#include <sys/kernel.h> 44179895Sdelphij#include <sys/bus.h> 45179895Sdelphij#include <sys/malloc.h> 46179895Sdelphij#include <sys/mbuf.h> 47179895Sdelphij#include <sys/proc.h> 48179895Sdelphij#include <sys/rman.h> 49179895Sdelphij#include <sys/module.h> 50179895Sdelphij#include <sys/socket.h> 51179895Sdelphij#include <sys/sockio.h> 52179895Sdelphij#include <sys/sysctl.h> 53179895Sdelphij 54179895Sdelphij#include <net/ethernet.h> 55179895Sdelphij#include <net/if.h> 56179895Sdelphij#include <net/if_dl.h> 57179895Sdelphij#include <net/if_types.h> 58179895Sdelphij#include <net/bpf.h> 59179895Sdelphij#include <net/if_arp.h> 60179895Sdelphij#include <net/if_media.h> 61179895Sdelphij#include <net/if_vlan_var.h> 62179895Sdelphij 63179895Sdelphij#include <machine/bus.h> 64179895Sdelphij 65213894Smarius#include <dev/mii/mii.h> 66179895Sdelphij#include <dev/mii/miivar.h> 67179895Sdelphij 68179895Sdelphij#include <dev/pci/pcireg.h> 69179895Sdelphij#include <dev/pci/pcivar.h> 70179895Sdelphij 71179895Sdelphij#include <dev/et/if_etreg.h> 72179895Sdelphij#include <dev/et/if_etvar.h> 73179895Sdelphij 74179895Sdelphij#include "miibus_if.h" 75179895Sdelphij 76179895SdelphijMODULE_DEPEND(et, pci, 1, 1, 1); 77179895SdelphijMODULE_DEPEND(et, ether, 1, 1, 1); 78179895SdelphijMODULE_DEPEND(et, miibus, 1, 1, 1); 79179895Sdelphij 80199552Syongari/* Tunables. */ 81199552Syongaristatic int msi_disable = 0; 82199563SyongariTUNABLE_INT("hw.et.msi_disable", &msi_disable); 83199552Syongari 84199611Syongari#define ET_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 85199611Syongari 86179895Sdelphijstatic int et_probe(device_t); 87179895Sdelphijstatic int et_attach(device_t); 88179895Sdelphijstatic int et_detach(device_t); 89179895Sdelphijstatic int et_shutdown(device_t); 90228292Syongaristatic int et_suspend(device_t); 91228292Syongaristatic int et_resume(device_t); 92179895Sdelphij 93179895Sdelphijstatic int et_miibus_readreg(device_t, int, int); 94179895Sdelphijstatic int et_miibus_writereg(device_t, int, int, int); 95179895Sdelphijstatic void et_miibus_statchg(device_t); 96179895Sdelphij 97179895Sdelphijstatic void et_init_locked(struct et_softc *); 98179895Sdelphijstatic void et_init(void *); 99179895Sdelphijstatic int et_ioctl(struct ifnet *, u_long, caddr_t); 100179895Sdelphijstatic void et_start_locked(struct ifnet *); 101179895Sdelphijstatic void et_start(struct ifnet *); 102228325Syongaristatic int et_watchdog(struct et_softc *); 103179895Sdelphijstatic int et_ifmedia_upd_locked(struct ifnet *); 104179895Sdelphijstatic int et_ifmedia_upd(struct ifnet *); 105179895Sdelphijstatic void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 106179895Sdelphij 107179895Sdelphijstatic void et_add_sysctls(struct et_softc *); 108179895Sdelphijstatic int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 109179895Sdelphijstatic int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 110179895Sdelphij 111179895Sdelphijstatic void et_intr(void *); 112179895Sdelphijstatic void et_rxeof(struct et_softc *); 113179895Sdelphijstatic void et_txeof(struct et_softc *); 114179895Sdelphij 115228325Syongaristatic int et_dma_alloc(struct et_softc *); 116228325Syongaristatic void et_dma_free(struct et_softc *); 117228325Syongaristatic void et_dma_map_addr(void *, bus_dma_segment_t *, int, int); 118228325Syongaristatic int et_dma_ring_alloc(struct et_softc *, bus_size_t, bus_size_t, 119228325Syongari bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, 120228325Syongari const char *); 121228325Syongaristatic void et_dma_ring_free(struct et_softc *, bus_dma_tag_t *, uint8_t **, 122228325Syongari bus_dmamap_t *); 123228325Syongaristatic void et_init_tx_ring(struct et_softc *); 124179895Sdelphijstatic int et_init_rx_ring(struct et_softc *); 125179895Sdelphijstatic void et_free_tx_ring(struct et_softc *); 126179895Sdelphijstatic void et_free_rx_ring(struct et_softc *); 127179895Sdelphijstatic int et_encap(struct et_softc *, struct mbuf **); 128228325Syongaristatic int et_newbuf_cluster(struct et_rxbuf_data *, int); 129228325Syongaristatic int et_newbuf_hdr(struct et_rxbuf_data *, int); 130228325Syongaristatic void et_rxbuf_discard(struct et_rxbuf_data *, int); 131179895Sdelphij 132179895Sdelphijstatic void et_stop(struct et_softc *); 133179895Sdelphijstatic int et_chip_init(struct et_softc *); 134179895Sdelphijstatic void et_chip_attach(struct et_softc *); 135179895Sdelphijstatic void et_init_mac(struct et_softc *); 136179895Sdelphijstatic void et_init_rxmac(struct et_softc *); 137179895Sdelphijstatic void et_init_txmac(struct et_softc *); 138179895Sdelphijstatic int et_init_rxdma(struct et_softc *); 139179895Sdelphijstatic int et_init_txdma(struct et_softc *); 140179895Sdelphijstatic int et_start_rxdma(struct et_softc *); 141179895Sdelphijstatic int et_start_txdma(struct et_softc *); 142179895Sdelphijstatic int et_stop_rxdma(struct et_softc *); 143179895Sdelphijstatic int et_stop_txdma(struct et_softc *); 144179895Sdelphijstatic void et_reset(struct et_softc *); 145199561Syongaristatic int et_bus_config(struct et_softc *); 146179895Sdelphijstatic void et_get_eaddr(device_t, uint8_t[]); 147179895Sdelphijstatic void et_setmulti(struct et_softc *); 148179895Sdelphijstatic void et_tick(void *); 149228332Syongaristatic void et_stats_update(struct et_softc *); 150179895Sdelphij 151179895Sdelphijstatic const struct et_dev { 152179895Sdelphij uint16_t vid; 153179895Sdelphij uint16_t did; 154179895Sdelphij const char *desc; 155179895Sdelphij} et_devices[] = { 156179895Sdelphij { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 157179895Sdelphij "Agere ET1310 Gigabit Ethernet" }, 158179895Sdelphij { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 159179895Sdelphij "Agere ET1310 Fast Ethernet" }, 160179895Sdelphij { 0, 0, NULL } 161179895Sdelphij}; 162179895Sdelphij 163179895Sdelphijstatic device_method_t et_methods[] = { 164179895Sdelphij DEVMETHOD(device_probe, et_probe), 165179895Sdelphij DEVMETHOD(device_attach, et_attach), 166179895Sdelphij DEVMETHOD(device_detach, et_detach), 167179895Sdelphij DEVMETHOD(device_shutdown, et_shutdown), 168228292Syongari DEVMETHOD(device_suspend, et_suspend), 169228292Syongari DEVMETHOD(device_resume, et_resume), 170179895Sdelphij 171179895Sdelphij DEVMETHOD(miibus_readreg, et_miibus_readreg), 172179895Sdelphij DEVMETHOD(miibus_writereg, et_miibus_writereg), 173179895Sdelphij DEVMETHOD(miibus_statchg, et_miibus_statchg), 174179895Sdelphij 175227843Smarius DEVMETHOD_END 176179895Sdelphij}; 177179895Sdelphij 178179895Sdelphijstatic driver_t et_driver = { 179179895Sdelphij "et", 180179895Sdelphij et_methods, 181179895Sdelphij sizeof(struct et_softc) 182179895Sdelphij}; 183179895Sdelphij 184179895Sdelphijstatic devclass_t et_devclass; 185179895Sdelphij 186179895SdelphijDRIVER_MODULE(et, pci, et_driver, et_devclass, 0, 0); 187179895SdelphijDRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, 0, 0); 188179895Sdelphij 189179895Sdelphijstatic int et_rx_intr_npkts = 32; 190179895Sdelphijstatic int et_rx_intr_delay = 20; /* x10 usec */ 191179895Sdelphijstatic int et_tx_intr_nsegs = 126; 192179895Sdelphijstatic uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 193179895Sdelphij 194179895SdelphijTUNABLE_INT("hw.et.timer", &et_timer); 195179895SdelphijTUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 196179895SdelphijTUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 197179895SdelphijTUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 198179895Sdelphij 199179895Sdelphijstatic int 200179895Sdelphijet_probe(device_t dev) 201179895Sdelphij{ 202179895Sdelphij const struct et_dev *d; 203179895Sdelphij uint16_t did, vid; 204179895Sdelphij 205179895Sdelphij vid = pci_get_vendor(dev); 206179895Sdelphij did = pci_get_device(dev); 207179895Sdelphij 208179895Sdelphij for (d = et_devices; d->desc != NULL; ++d) { 209179895Sdelphij if (vid == d->vid && did == d->did) { 210179895Sdelphij device_set_desc(dev, d->desc); 211228298Syongari return (BUS_PROBE_DEFAULT); 212179895Sdelphij } 213179895Sdelphij } 214199556Syongari return (ENXIO); 215179895Sdelphij} 216179895Sdelphij 217179895Sdelphijstatic int 218179895Sdelphijet_attach(device_t dev) 219179895Sdelphij{ 220179895Sdelphij struct et_softc *sc; 221179895Sdelphij struct ifnet *ifp; 222179895Sdelphij uint8_t eaddr[ETHER_ADDR_LEN]; 223228336Syongari uint32_t pmcfg; 224199552Syongari int cap, error, msic; 225179895Sdelphij 226179895Sdelphij sc = device_get_softc(dev); 227179895Sdelphij sc->dev = dev; 228179895Sdelphij mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 229179895Sdelphij MTX_DEF); 230228297Syongari callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); 231179895Sdelphij 232179895Sdelphij ifp = sc->ifp = if_alloc(IFT_ETHER); 233179895Sdelphij if (ifp == NULL) { 234179895Sdelphij device_printf(dev, "can not if_alloc()\n"); 235179895Sdelphij error = ENOSPC; 236179895Sdelphij goto fail; 237179895Sdelphij } 238179895Sdelphij 239179895Sdelphij /* 240179895Sdelphij * Initialize tunables 241179895Sdelphij */ 242179895Sdelphij sc->sc_rx_intr_npkts = et_rx_intr_npkts; 243179895Sdelphij sc->sc_rx_intr_delay = et_rx_intr_delay; 244179895Sdelphij sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 245179895Sdelphij sc->sc_timer = et_timer; 246179895Sdelphij 247179895Sdelphij /* Enable bus mastering */ 248179895Sdelphij pci_enable_busmaster(dev); 249179895Sdelphij 250179895Sdelphij /* 251179895Sdelphij * Allocate IO memory 252179895Sdelphij */ 253228368Syongari sc->sc_mem_rid = PCIR_BAR(0); 254179895Sdelphij sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 255228368Syongari &sc->sc_mem_rid, RF_ACTIVE); 256179895Sdelphij if (sc->sc_mem_res == NULL) { 257179895Sdelphij device_printf(dev, "can't allocate IO memory\n"); 258199556Syongari return (ENXIO); 259179895Sdelphij } 260179895Sdelphij 261199552Syongari msic = 0; 262219902Sjhb if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 263199552Syongari sc->sc_expcap = cap; 264199552Syongari sc->sc_flags |= ET_FLAG_PCIE; 265199552Syongari msic = pci_msi_count(dev); 266199552Syongari if (bootverbose) 267199563Syongari device_printf(dev, "MSI count: %d\n", msic); 268199552Syongari } 269199552Syongari if (msic > 0 && msi_disable == 0) { 270199552Syongari msic = 1; 271199552Syongari if (pci_alloc_msi(dev, &msic) == 0) { 272199552Syongari if (msic == 1) { 273199552Syongari device_printf(dev, "Using %d MSI message\n", 274199552Syongari msic); 275199552Syongari sc->sc_flags |= ET_FLAG_MSI; 276199552Syongari } else 277199552Syongari pci_release_msi(dev); 278199552Syongari } 279199552Syongari } 280199552Syongari 281179895Sdelphij /* 282179895Sdelphij * Allocate IRQ 283179895Sdelphij */ 284199552Syongari if ((sc->sc_flags & ET_FLAG_MSI) == 0) { 285199552Syongari sc->sc_irq_rid = 0; 286199552Syongari sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 287199552Syongari &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 288199552Syongari } else { 289199552Syongari sc->sc_irq_rid = 1; 290199552Syongari sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 291199552Syongari &sc->sc_irq_rid, RF_ACTIVE); 292199552Syongari } 293179895Sdelphij if (sc->sc_irq_res == NULL) { 294179895Sdelphij device_printf(dev, "can't allocate irq\n"); 295179895Sdelphij error = ENXIO; 296179895Sdelphij goto fail; 297179895Sdelphij } 298179895Sdelphij 299228331Syongari if (pci_get_device(dev) == PCI_PRODUCT_LUCENT_ET1310_FAST) 300228331Syongari sc->sc_flags |= ET_FLAG_FASTETHER; 301228331Syongari 302199561Syongari error = et_bus_config(sc); 303179895Sdelphij if (error) 304179895Sdelphij goto fail; 305179895Sdelphij 306179895Sdelphij et_get_eaddr(dev, eaddr); 307179895Sdelphij 308228336Syongari /* Take PHY out of COMA and enable clocks. */ 309228336Syongari pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 310228336Syongari if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 311228336Syongari pmcfg |= EM_PM_GIGEPHY_ENB; 312228336Syongari CSR_WRITE_4(sc, ET_PM, pmcfg); 313179895Sdelphij 314179895Sdelphij et_reset(sc); 315179895Sdelphij 316228325Syongari error = et_dma_alloc(sc); 317179895Sdelphij if (error) 318179895Sdelphij goto fail; 319179895Sdelphij 320179895Sdelphij ifp->if_softc = sc; 321179895Sdelphij if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 322179895Sdelphij ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 323179895Sdelphij ifp->if_init = et_init; 324179895Sdelphij ifp->if_ioctl = et_ioctl; 325179895Sdelphij ifp->if_start = et_start; 326199613Syongari ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU; 327179895Sdelphij ifp->if_capenable = ifp->if_capabilities; 328228293Syongari ifp->if_snd.ifq_drv_maxlen = ET_TX_NDESC - 1; 329228293Syongari IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC - 1); 330179895Sdelphij IFQ_SET_READY(&ifp->if_snd); 331179895Sdelphij 332179895Sdelphij et_chip_attach(sc); 333179895Sdelphij 334213894Smarius error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd, 335228369Syongari et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 336228369Syongari MIIF_DOPAUSE); 337179895Sdelphij if (error) { 338213894Smarius device_printf(dev, "attaching PHYs failed\n"); 339179895Sdelphij goto fail; 340179895Sdelphij } 341179895Sdelphij 342179895Sdelphij ether_ifattach(ifp, eaddr); 343179895Sdelphij 344228297Syongari /* Tell the upper layer(s) we support long frames. */ 345228297Syongari ifp->if_hdrlen = sizeof(struct ether_vlan_header); 346228297Syongari 347179895Sdelphij error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE, 348199552Syongari NULL, et_intr, sc, &sc->sc_irq_handle); 349179895Sdelphij if (error) { 350179895Sdelphij ether_ifdetach(ifp); 351179895Sdelphij device_printf(dev, "can't setup intr\n"); 352179895Sdelphij goto fail; 353179895Sdelphij } 354179895Sdelphij 355179895Sdelphij et_add_sysctls(sc); 356179895Sdelphij 357199556Syongari return (0); 358179895Sdelphijfail: 359179895Sdelphij et_detach(dev); 360199556Syongari return (error); 361179895Sdelphij} 362179895Sdelphij 363179895Sdelphijstatic int 364179895Sdelphijet_detach(device_t dev) 365179895Sdelphij{ 366229940Syongari struct et_softc *sc; 367179895Sdelphij 368229940Syongari sc = device_get_softc(dev); 369179895Sdelphij if (device_is_attached(dev)) { 370228298Syongari ether_ifdetach(sc->ifp); 371179895Sdelphij ET_LOCK(sc); 372179895Sdelphij et_stop(sc); 373179895Sdelphij ET_UNLOCK(sc); 374228298Syongari callout_drain(&sc->sc_tick); 375179895Sdelphij } 376179895Sdelphij 377179895Sdelphij if (sc->sc_miibus != NULL) 378179895Sdelphij device_delete_child(dev, sc->sc_miibus); 379179895Sdelphij bus_generic_detach(dev); 380179895Sdelphij 381228298Syongari if (sc->sc_irq_handle != NULL) 382228298Syongari bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 383228298Syongari if (sc->sc_irq_res != NULL) 384228298Syongari bus_release_resource(dev, SYS_RES_IRQ, 385228298Syongari rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 386199552Syongari if ((sc->sc_flags & ET_FLAG_MSI) != 0) 387199552Syongari pci_release_msi(dev); 388228298Syongari if (sc->sc_mem_res != NULL) 389228298Syongari bus_release_resource(dev, SYS_RES_MEMORY, 390228298Syongari rman_get_rid(sc->sc_mem_res), sc->sc_mem_res); 391179895Sdelphij 392179895Sdelphij if (sc->ifp != NULL) 393179895Sdelphij if_free(sc->ifp); 394179895Sdelphij 395228325Syongari et_dma_free(sc); 396179895Sdelphij 397199551Syongari mtx_destroy(&sc->sc_mtx); 398199551Syongari 399199556Syongari return (0); 400179895Sdelphij} 401179895Sdelphij 402179895Sdelphijstatic int 403179895Sdelphijet_shutdown(device_t dev) 404179895Sdelphij{ 405229940Syongari struct et_softc *sc; 406179895Sdelphij 407229940Syongari sc = device_get_softc(dev); 408179895Sdelphij ET_LOCK(sc); 409179895Sdelphij et_stop(sc); 410179895Sdelphij ET_UNLOCK(sc); 411199556Syongari return (0); 412179895Sdelphij} 413179895Sdelphij 414179895Sdelphijstatic int 415179895Sdelphijet_miibus_readreg(device_t dev, int phy, int reg) 416179895Sdelphij{ 417229940Syongari struct et_softc *sc; 418179895Sdelphij uint32_t val; 419179895Sdelphij int i, ret; 420179895Sdelphij 421229940Syongari sc = device_get_softc(dev); 422179895Sdelphij /* Stop any pending operations */ 423179895Sdelphij CSR_WRITE_4(sc, ET_MII_CMD, 0); 424179895Sdelphij 425199548Syongari val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 426199548Syongari val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 427179895Sdelphij CSR_WRITE_4(sc, ET_MII_ADDR, val); 428179895Sdelphij 429179895Sdelphij /* Start reading */ 430179895Sdelphij CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 431179895Sdelphij 432179895Sdelphij#define NRETRY 50 433179895Sdelphij 434179895Sdelphij for (i = 0; i < NRETRY; ++i) { 435179895Sdelphij val = CSR_READ_4(sc, ET_MII_IND); 436179895Sdelphij if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 437179895Sdelphij break; 438179895Sdelphij DELAY(50); 439179895Sdelphij } 440179895Sdelphij if (i == NRETRY) { 441179895Sdelphij if_printf(sc->ifp, 442179895Sdelphij "read phy %d, reg %d timed out\n", phy, reg); 443179895Sdelphij ret = 0; 444179895Sdelphij goto back; 445179895Sdelphij } 446179895Sdelphij 447179895Sdelphij#undef NRETRY 448179895Sdelphij 449179895Sdelphij val = CSR_READ_4(sc, ET_MII_STAT); 450199548Syongari ret = val & ET_MII_STAT_VALUE_MASK; 451179895Sdelphij 452179895Sdelphijback: 453179895Sdelphij /* Make sure that the current operation is stopped */ 454179895Sdelphij CSR_WRITE_4(sc, ET_MII_CMD, 0); 455199556Syongari return (ret); 456179895Sdelphij} 457179895Sdelphij 458179895Sdelphijstatic int 459179895Sdelphijet_miibus_writereg(device_t dev, int phy, int reg, int val0) 460179895Sdelphij{ 461229940Syongari struct et_softc *sc; 462179895Sdelphij uint32_t val; 463179895Sdelphij int i; 464179895Sdelphij 465229940Syongari sc = device_get_softc(dev); 466179895Sdelphij /* Stop any pending operations */ 467179895Sdelphij CSR_WRITE_4(sc, ET_MII_CMD, 0); 468179895Sdelphij 469199548Syongari val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 470199548Syongari val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 471179895Sdelphij CSR_WRITE_4(sc, ET_MII_ADDR, val); 472179895Sdelphij 473179895Sdelphij /* Start writing */ 474199548Syongari CSR_WRITE_4(sc, ET_MII_CTRL, 475199548Syongari (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK); 476179895Sdelphij 477179895Sdelphij#define NRETRY 100 478179895Sdelphij 479179895Sdelphij for (i = 0; i < NRETRY; ++i) { 480179895Sdelphij val = CSR_READ_4(sc, ET_MII_IND); 481179895Sdelphij if ((val & ET_MII_IND_BUSY) == 0) 482179895Sdelphij break; 483179895Sdelphij DELAY(50); 484179895Sdelphij } 485179895Sdelphij if (i == NRETRY) { 486179895Sdelphij if_printf(sc->ifp, 487179895Sdelphij "write phy %d, reg %d timed out\n", phy, reg); 488179895Sdelphij et_miibus_readreg(dev, phy, reg); 489179895Sdelphij } 490179895Sdelphij 491179895Sdelphij#undef NRETRY 492179895Sdelphij 493179895Sdelphij /* Make sure that the current operation is stopped */ 494179895Sdelphij CSR_WRITE_4(sc, ET_MII_CMD, 0); 495199556Syongari return (0); 496179895Sdelphij} 497179895Sdelphij 498179895Sdelphijstatic void 499179895Sdelphijet_miibus_statchg(device_t dev) 500179895Sdelphij{ 501228331Syongari struct et_softc *sc; 502228331Syongari struct mii_data *mii; 503228331Syongari struct ifnet *ifp; 504228331Syongari uint32_t cfg1, cfg2, ctrl; 505228331Syongari int i; 506228331Syongari 507228331Syongari sc = device_get_softc(dev); 508228331Syongari 509228331Syongari mii = device_get_softc(sc->sc_miibus); 510228331Syongari ifp = sc->ifp; 511228331Syongari if (mii == NULL || ifp == NULL || 512228331Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 513228331Syongari return; 514228331Syongari 515228331Syongari sc->sc_flags &= ~ET_FLAG_LINK; 516228331Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 517228331Syongari (IFM_ACTIVE | IFM_AVALID)) { 518228331Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 519228331Syongari case IFM_10_T: 520228331Syongari case IFM_100_TX: 521228331Syongari sc->sc_flags |= ET_FLAG_LINK; 522228331Syongari break; 523228331Syongari case IFM_1000_T: 524228331Syongari if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 525228331Syongari sc->sc_flags |= ET_FLAG_LINK; 526228331Syongari break; 527228331Syongari } 528228331Syongari } 529228331Syongari 530228331Syongari /* XXX Stop TX/RX MAC? */ 531228331Syongari if ((sc->sc_flags & ET_FLAG_LINK) == 0) 532228331Syongari return; 533228331Syongari 534228331Syongari /* Program MACs with resolved speed/duplex/flow-control. */ 535228331Syongari ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 536228331Syongari ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 537228331Syongari cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 538228331Syongari cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 539228331Syongari ET_MAC_CFG1_LOOPBACK); 540228331Syongari cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 541228331Syongari cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 542228331Syongari ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 543228331Syongari cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 544228331Syongari ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) & 545228331Syongari ET_MAC_CFG2_PREAMBLE_LEN_MASK); 546228331Syongari 547228331Syongari if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 548228331Syongari cfg2 |= ET_MAC_CFG2_MODE_GMII; 549228331Syongari else { 550228331Syongari cfg2 |= ET_MAC_CFG2_MODE_MII; 551228331Syongari ctrl |= ET_MAC_CTRL_MODE_MII; 552228331Syongari } 553228331Syongari 554228331Syongari if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) { 555228331Syongari cfg2 |= ET_MAC_CFG2_FDX; 556228369Syongari /* 557228369Syongari * Controller lacks automatic TX pause frame 558228369Syongari * generation so it should be handled by driver. 559228369Syongari * Even though driver can send pause frame with 560228369Syongari * arbitrary pause time, controller does not 561228369Syongari * provide a way that tells how many free RX 562228369Syongari * buffers are available in controller. This 563228369Syongari * limitation makes it hard to generate XON frame 564228369Syongari * in time on driver side so don't enable TX flow 565228369Syongari * control. 566228369Syongari */ 567228331Syongari#ifdef notyet 568228331Syongari if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) 569228331Syongari cfg1 |= ET_MAC_CFG1_TXFLOW; 570228369Syongari#endif 571228331Syongari if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) 572228331Syongari cfg1 |= ET_MAC_CFG1_RXFLOW; 573228331Syongari } else 574228331Syongari ctrl |= ET_MAC_CTRL_GHDX; 575228331Syongari 576228331Syongari CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 577228331Syongari CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 578228331Syongari cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 579228331Syongari CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); 580228331Syongari 581228331Syongari#define NRETRY 50 582228331Syongari 583228331Syongari for (i = 0; i < NRETRY; ++i) { 584228331Syongari cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 585228331Syongari if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 586228331Syongari (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 587228331Syongari break; 588228331Syongari DELAY(100); 589228331Syongari } 590228331Syongari if (i == NRETRY) 591228331Syongari if_printf(ifp, "can't enable RX/TX\n"); 592228331Syongari sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 593228331Syongari 594228331Syongari#undef NRETRY 595179895Sdelphij} 596179895Sdelphij 597179895Sdelphijstatic int 598179895Sdelphijet_ifmedia_upd_locked(struct ifnet *ifp) 599179895Sdelphij{ 600229940Syongari struct et_softc *sc; 601229940Syongari struct mii_data *mii; 602221407Smarius struct mii_softc *miisc; 603179895Sdelphij 604229940Syongari sc = ifp->if_softc; 605229940Syongari mii = device_get_softc(sc->sc_miibus); 606221407Smarius LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 607221407Smarius PHY_RESET(miisc); 608226481Syongari return (mii_mediachg(mii)); 609179895Sdelphij} 610179895Sdelphij 611179895Sdelphijstatic int 612179895Sdelphijet_ifmedia_upd(struct ifnet *ifp) 613179895Sdelphij{ 614229940Syongari struct et_softc *sc; 615179895Sdelphij int res; 616179895Sdelphij 617229940Syongari sc = ifp->if_softc; 618179895Sdelphij ET_LOCK(sc); 619179895Sdelphij res = et_ifmedia_upd_locked(ifp); 620179895Sdelphij ET_UNLOCK(sc); 621179895Sdelphij 622199556Syongari return (res); 623179895Sdelphij} 624179895Sdelphij 625179895Sdelphijstatic void 626179895Sdelphijet_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 627179895Sdelphij{ 628228331Syongari struct et_softc *sc; 629228331Syongari struct mii_data *mii; 630179895Sdelphij 631228331Syongari sc = ifp->if_softc; 632226480Syongari ET_LOCK(sc); 633228331Syongari if ((ifp->if_flags & IFF_UP) == 0) { 634228331Syongari ET_UNLOCK(sc); 635228331Syongari return; 636228331Syongari } 637228331Syongari 638228331Syongari mii = device_get_softc(sc->sc_miibus); 639179895Sdelphij mii_pollstat(mii); 640179895Sdelphij ifmr->ifm_active = mii->mii_media_active; 641179895Sdelphij ifmr->ifm_status = mii->mii_media_status; 642226480Syongari ET_UNLOCK(sc); 643179895Sdelphij} 644179895Sdelphij 645179895Sdelphijstatic void 646179895Sdelphijet_stop(struct et_softc *sc) 647179895Sdelphij{ 648229940Syongari struct ifnet *ifp; 649179895Sdelphij 650179895Sdelphij ET_LOCK_ASSERT(sc); 651179895Sdelphij 652229940Syongari ifp = sc->ifp; 653179895Sdelphij callout_stop(&sc->sc_tick); 654228327Syongari /* Disable interrupts. */ 655228327Syongari CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 656179895Sdelphij 657228331Syongari CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~( 658228331Syongari ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN)); 659228331Syongari DELAY(100); 660228331Syongari 661179895Sdelphij et_stop_rxdma(sc); 662179895Sdelphij et_stop_txdma(sc); 663228332Syongari et_stats_update(sc); 664179895Sdelphij 665179895Sdelphij et_free_tx_ring(sc); 666179895Sdelphij et_free_rx_ring(sc); 667179895Sdelphij 668179895Sdelphij sc->sc_tx = 0; 669179895Sdelphij sc->sc_tx_intr = 0; 670179895Sdelphij sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 671179895Sdelphij 672179895Sdelphij sc->watchdog_timer = 0; 673179895Sdelphij ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 674179895Sdelphij} 675179895Sdelphij 676179895Sdelphijstatic int 677199561Syongariet_bus_config(struct et_softc *sc) 678179895Sdelphij{ 679179895Sdelphij uint32_t val, max_plsz; 680179895Sdelphij uint16_t ack_latency, replay_timer; 681179895Sdelphij 682179895Sdelphij /* 683179895Sdelphij * Test whether EEPROM is valid 684179895Sdelphij * NOTE: Read twice to get the correct value 685179895Sdelphij */ 686199561Syongari pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 687199561Syongari val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 688179895Sdelphij if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 689199561Syongari device_printf(sc->dev, "EEPROM status error 0x%02x\n", val); 690199556Syongari return (ENXIO); 691179895Sdelphij } 692179895Sdelphij 693179895Sdelphij /* TODO: LED */ 694179895Sdelphij 695199561Syongari if ((sc->sc_flags & ET_FLAG_PCIE) == 0) 696199561Syongari return (0); 697199561Syongari 698179895Sdelphij /* 699179895Sdelphij * Configure ACK latency and replay timer according to 700179895Sdelphij * max playload size 701179895Sdelphij */ 702199561Syongari val = pci_read_config(sc->dev, 703240680Sgavin sc->sc_expcap + PCIER_DEVICE_CAP, 4); 704240680Sgavin max_plsz = val & PCIEM_CAP_MAX_PAYLOAD; 705179895Sdelphij 706179895Sdelphij switch (max_plsz) { 707179895Sdelphij case ET_PCIV_DEVICE_CAPS_PLSZ_128: 708179895Sdelphij ack_latency = ET_PCIV_ACK_LATENCY_128; 709179895Sdelphij replay_timer = ET_PCIV_REPLAY_TIMER_128; 710179895Sdelphij break; 711179895Sdelphij 712179895Sdelphij case ET_PCIV_DEVICE_CAPS_PLSZ_256: 713179895Sdelphij ack_latency = ET_PCIV_ACK_LATENCY_256; 714179895Sdelphij replay_timer = ET_PCIV_REPLAY_TIMER_256; 715179895Sdelphij break; 716179895Sdelphij 717179895Sdelphij default: 718199561Syongari ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2); 719199561Syongari replay_timer = pci_read_config(sc->dev, 720199561Syongari ET_PCIR_REPLAY_TIMER, 2); 721199561Syongari device_printf(sc->dev, "ack latency %u, replay timer %u\n", 722179895Sdelphij ack_latency, replay_timer); 723179895Sdelphij break; 724179895Sdelphij } 725179895Sdelphij if (ack_latency != 0) { 726199561Syongari pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 727199561Syongari pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer, 728199561Syongari 2); 729179895Sdelphij } 730179895Sdelphij 731179895Sdelphij /* 732179895Sdelphij * Set L0s and L1 latency timer to 2us 733179895Sdelphij */ 734199561Syongari val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); 735240680Sgavin val &= ~(PCIEM_LINK_CAP_L0S_EXIT | PCIEM_LINK_CAP_L1_EXIT); 736199548Syongari /* L0s exit latency : 2us */ 737199548Syongari val |= 0x00005000; 738199548Syongari /* L1 exit latency : 2us */ 739199548Syongari val |= 0x00028000; 740199561Syongari pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4); 741179895Sdelphij 742179895Sdelphij /* 743179895Sdelphij * Set max read request size to 2048 bytes 744179895Sdelphij */ 745228368Syongari pci_set_max_read_req(sc->dev, 2048); 746179895Sdelphij 747199556Syongari return (0); 748179895Sdelphij} 749179895Sdelphij 750179895Sdelphijstatic void 751179895Sdelphijet_get_eaddr(device_t dev, uint8_t eaddr[]) 752179895Sdelphij{ 753179895Sdelphij uint32_t val; 754179895Sdelphij int i; 755179895Sdelphij 756179895Sdelphij val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 757179895Sdelphij for (i = 0; i < 4; ++i) 758179895Sdelphij eaddr[i] = (val >> (8 * i)) & 0xff; 759179895Sdelphij 760179895Sdelphij val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 761179895Sdelphij for (; i < ETHER_ADDR_LEN; ++i) 762179895Sdelphij eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 763179895Sdelphij} 764179895Sdelphij 765179895Sdelphijstatic void 766179895Sdelphijet_reset(struct et_softc *sc) 767179895Sdelphij{ 768229940Syongari 769179895Sdelphij CSR_WRITE_4(sc, ET_MAC_CFG1, 770179895Sdelphij ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 771179895Sdelphij ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 772179895Sdelphij ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 773179895Sdelphij 774179895Sdelphij CSR_WRITE_4(sc, ET_SWRST, 775179895Sdelphij ET_SWRST_TXDMA | ET_SWRST_RXDMA | 776179895Sdelphij ET_SWRST_TXMAC | ET_SWRST_RXMAC | 777179895Sdelphij ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 778179895Sdelphij 779179895Sdelphij CSR_WRITE_4(sc, ET_MAC_CFG1, 780179895Sdelphij ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 781179895Sdelphij ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 782179895Sdelphij CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 783228327Syongari /* Disable interrupts. */ 784179895Sdelphij CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 785179895Sdelphij} 786179895Sdelphij 787228325Syongaristruct et_dmamap_arg { 788228325Syongari bus_addr_t et_busaddr; 789228325Syongari}; 790228325Syongari 791228325Syongaristatic void 792228325Syongariet_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 793228325Syongari{ 794228325Syongari struct et_dmamap_arg *ctx; 795228325Syongari 796228325Syongari if (error) 797228325Syongari return; 798228325Syongari 799228325Syongari KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 800228325Syongari 801228325Syongari ctx = arg; 802228325Syongari ctx->et_busaddr = segs->ds_addr; 803228325Syongari} 804228325Syongari 805179895Sdelphijstatic int 806228325Syongariet_dma_ring_alloc(struct et_softc *sc, bus_size_t alignment, bus_size_t maxsize, 807228325Syongari bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 808228325Syongari const char *msg) 809179895Sdelphij{ 810228325Syongari struct et_dmamap_arg ctx; 811228325Syongari int error; 812179895Sdelphij 813228325Syongari error = bus_dma_tag_create(sc->sc_dtag, alignment, 0, BUS_SPACE_MAXADDR, 814228325Syongari BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, maxsize, 0, NULL, NULL, 815228325Syongari tag); 816228325Syongari if (error != 0) { 817228325Syongari device_printf(sc->dev, "could not create %s dma tag\n", msg); 818199556Syongari return (error); 819179895Sdelphij } 820228325Syongari /* Allocate DMA'able memory for ring. */ 821228325Syongari error = bus_dmamem_alloc(*tag, (void **)ring, 822228325Syongari BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 823228325Syongari if (error != 0) { 824228325Syongari device_printf(sc->dev, 825228325Syongari "could not allocate DMA'able memory for %s\n", msg); 826199556Syongari return (error); 827179895Sdelphij } 828228325Syongari /* Load the address of the ring. */ 829228325Syongari ctx.et_busaddr = 0; 830228325Syongari error = bus_dmamap_load(*tag, *map, *ring, maxsize, et_dma_map_addr, 831228325Syongari &ctx, BUS_DMA_NOWAIT); 832228325Syongari if (error != 0) { 833228325Syongari device_printf(sc->dev, 834228325Syongari "could not load DMA'able memory for %s\n", msg); 835199556Syongari return (error); 836179895Sdelphij } 837228325Syongari *paddr = ctx.et_busaddr; 838228325Syongari return (0); 839228325Syongari} 840179895Sdelphij 841228325Syongaristatic void 842228325Syongariet_dma_ring_free(struct et_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 843228325Syongari bus_dmamap_t *map) 844228325Syongari{ 845179895Sdelphij 846228325Syongari if (*map != NULL) 847228325Syongari bus_dmamap_unload(*tag, *map); 848228325Syongari if (*map != NULL && *ring != NULL) { 849228325Syongari bus_dmamem_free(*tag, *ring, *map); 850228325Syongari *ring = NULL; 851228325Syongari *map = NULL; 852179895Sdelphij } 853228325Syongari if (*tag) { 854228325Syongari bus_dma_tag_destroy(*tag); 855228325Syongari *tag = NULL; 856228325Syongari } 857228325Syongari} 858179895Sdelphij 859228325Syongaristatic int 860228325Syongariet_dma_alloc(struct et_softc *sc) 861228325Syongari{ 862228325Syongari struct et_txdesc_ring *tx_ring; 863228325Syongari struct et_rxdesc_ring *rx_ring; 864228325Syongari struct et_rxstat_ring *rxst_ring; 865228325Syongari struct et_rxstatus_data *rxsd; 866228325Syongari struct et_rxbuf_data *rbd; 867228325Syongari struct et_txbuf_data *tbd; 868228325Syongari struct et_txstatus_data *txsd; 869228325Syongari int i, error; 870228325Syongari 871228325Syongari error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 872228325Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 873228325Syongari BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 874228325Syongari &sc->sc_dtag); 875228325Syongari if (error != 0) { 876228325Syongari device_printf(sc->dev, "could not allocate parent dma tag\n"); 877199556Syongari return (error); 878179895Sdelphij } 879179895Sdelphij 880228325Syongari /* TX ring. */ 881228325Syongari tx_ring = &sc->sc_tx_ring; 882228325Syongari error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_TX_RING_SIZE, 883228325Syongari &tx_ring->tr_dtag, (uint8_t **)&tx_ring->tr_desc, &tx_ring->tr_dmap, 884228325Syongari &tx_ring->tr_paddr, "TX ring"); 885228325Syongari if (error) 886199556Syongari return (error); 887179895Sdelphij 888228325Syongari /* TX status block. */ 889228325Syongari txsd = &sc->sc_tx_status; 890228325Syongari error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, sizeof(uint32_t), 891228325Syongari &txsd->txsd_dtag, (uint8_t **)&txsd->txsd_status, &txsd->txsd_dmap, 892228325Syongari &txsd->txsd_paddr, "TX status block"); 893179895Sdelphij if (error) 894199556Syongari return (error); 895179895Sdelphij 896228325Syongari /* RX ring 0, used as to recive small sized frames. */ 897228325Syongari rx_ring = &sc->sc_rx_ring[0]; 898228325Syongari error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 899228325Syongari &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 900228325Syongari &rx_ring->rr_paddr, "RX ring 0"); 901228325Syongari rx_ring->rr_posreg = ET_RX_RING0_POS; 902228325Syongari if (error) 903228325Syongari return (error); 904179895Sdelphij 905228325Syongari /* RX ring 1, used as to store normal sized frames. */ 906228325Syongari rx_ring = &sc->sc_rx_ring[1]; 907228325Syongari error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 908228325Syongari &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 909228325Syongari &rx_ring->rr_paddr, "RX ring 1"); 910228325Syongari rx_ring->rr_posreg = ET_RX_RING1_POS; 911228325Syongari if (error) 912228325Syongari return (error); 913179895Sdelphij 914228325Syongari /* RX stat ring. */ 915228325Syongari rxst_ring = &sc->sc_rxstat_ring; 916228325Syongari error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RXSTAT_RING_SIZE, 917228325Syongari &rxst_ring->rsr_dtag, (uint8_t **)&rxst_ring->rsr_stat, 918228325Syongari &rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr, "RX stat ring"); 919228325Syongari if (error) 920228325Syongari return (error); 921179895Sdelphij 922228325Syongari /* RX status block. */ 923228325Syongari rxsd = &sc->sc_rx_status; 924228325Syongari error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, 925228325Syongari sizeof(struct et_rxstatus), &rxsd->rxsd_dtag, 926228325Syongari (uint8_t **)&rxsd->rxsd_status, &rxsd->rxsd_dmap, 927228325Syongari &rxsd->rxsd_paddr, "RX status block"); 928228325Syongari if (error) 929228325Syongari return (error); 930179895Sdelphij 931228325Syongari /* Create parent DMA tag for mbufs. */ 932228325Syongari error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 933228325Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 934228325Syongari BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 935228325Syongari &sc->sc_mbuf_dtag); 936228325Syongari if (error != 0) { 937228325Syongari device_printf(sc->dev, 938228325Syongari "could not allocate parent dma tag for mbuf\n"); 939228325Syongari return (error); 940228325Syongari } 941179895Sdelphij 942228325Syongari /* Create DMA tag for mini RX mbufs to use RX ring 0. */ 943228325Syongari error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 944228325Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 945228325Syongari MHLEN, 0, NULL, NULL, &sc->sc_rx_mini_tag); 946228325Syongari if (error) { 947228325Syongari device_printf(sc->dev, "could not create mini RX dma tag\n"); 948228325Syongari return (error); 949179895Sdelphij } 950179895Sdelphij 951228325Syongari /* Create DMA tag for standard RX mbufs to use RX ring 1. */ 952228325Syongari error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 953228325Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 954228325Syongari MCLBYTES, 0, NULL, NULL, &sc->sc_rx_tag); 955228325Syongari if (error) { 956228325Syongari device_printf(sc->dev, "could not create RX dma tag\n"); 957228325Syongari return (error); 958228325Syongari } 959179895Sdelphij 960228325Syongari /* Create DMA tag for TX mbufs. */ 961228325Syongari error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 962228325Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 963228325Syongari MCLBYTES * ET_NSEG_MAX, ET_NSEG_MAX, MCLBYTES, 0, NULL, NULL, 964228325Syongari &sc->sc_tx_tag); 965179895Sdelphij if (error) { 966228325Syongari device_printf(sc->dev, "could not create TX dma tag\n"); 967199556Syongari return (error); 968179895Sdelphij } 969179895Sdelphij 970228325Syongari /* Initialize RX ring 0. */ 971228325Syongari rbd = &sc->sc_rx_data[0]; 972228325Syongari rbd->rbd_bufsize = ET_RXDMA_CTRL_RING0_128; 973228325Syongari rbd->rbd_newbuf = et_newbuf_hdr; 974228325Syongari rbd->rbd_discard = et_rxbuf_discard; 975228325Syongari rbd->rbd_softc = sc; 976228325Syongari rbd->rbd_ring = &sc->sc_rx_ring[0]; 977228325Syongari /* Create DMA maps for mini RX buffers, ring 0. */ 978228325Syongari for (i = 0; i < ET_RX_NDESC; i++) { 979228325Syongari error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 980228325Syongari &rbd->rbd_buf[i].rb_dmap); 981228325Syongari if (error) { 982228325Syongari device_printf(sc->dev, 983228325Syongari "could not create DMA map for mini RX mbufs\n"); 984228325Syongari return (error); 985228325Syongari } 986228325Syongari } 987228325Syongari 988228325Syongari /* Create a spare DMA map for mini RX buffers, ring 0. */ 989228325Syongari error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 990228325Syongari &sc->sc_rx_mini_sparemap); 991179895Sdelphij if (error) { 992228325Syongari device_printf(sc->dev, 993228325Syongari "could not create spare DMA map for mini RX mbuf\n"); 994199556Syongari return (error); 995179895Sdelphij } 996179895Sdelphij 997228325Syongari /* Initialize RX ring 1. */ 998228325Syongari rbd = &sc->sc_rx_data[1]; 999228325Syongari rbd->rbd_bufsize = ET_RXDMA_CTRL_RING1_2048; 1000228325Syongari rbd->rbd_newbuf = et_newbuf_cluster; 1001228325Syongari rbd->rbd_discard = et_rxbuf_discard; 1002228325Syongari rbd->rbd_softc = sc; 1003228325Syongari rbd->rbd_ring = &sc->sc_rx_ring[1]; 1004228325Syongari /* Create DMA maps for standard RX buffers, ring 1. */ 1005228325Syongari for (i = 0; i < ET_RX_NDESC; i++) { 1006228325Syongari error = bus_dmamap_create(sc->sc_rx_tag, 0, 1007228325Syongari &rbd->rbd_buf[i].rb_dmap); 1008228325Syongari if (error) { 1009228325Syongari device_printf(sc->dev, 1010228325Syongari "could not create DMA map for mini RX mbufs\n"); 1011228325Syongari return (error); 1012179895Sdelphij } 1013228325Syongari } 1014179895Sdelphij 1015228325Syongari /* Create a spare DMA map for standard RX buffers, ring 1. */ 1016228325Syongari error = bus_dmamap_create(sc->sc_rx_tag, 0, &sc->sc_rx_sparemap); 1017228325Syongari if (error) { 1018228325Syongari device_printf(sc->dev, 1019228325Syongari "could not create spare DMA map for RX mbuf\n"); 1020228325Syongari return (error); 1021179895Sdelphij } 1022179895Sdelphij 1023228325Syongari /* Create DMA maps for TX buffers. */ 1024228325Syongari tbd = &sc->sc_tx_data; 1025228325Syongari for (i = 0; i < ET_TX_NDESC; i++) { 1026228325Syongari error = bus_dmamap_create(sc->sc_tx_tag, 0, 1027228325Syongari &tbd->tbd_buf[i].tb_dmap); 1028179895Sdelphij if (error) { 1029228325Syongari device_printf(sc->dev, 1030228325Syongari "could not create DMA map for TX mbufs\n"); 1031199556Syongari return (error); 1032179895Sdelphij } 1033179895Sdelphij } 1034179895Sdelphij 1035199556Syongari return (0); 1036179895Sdelphij} 1037179895Sdelphij 1038179895Sdelphijstatic void 1039228325Syongariet_dma_free(struct et_softc *sc) 1040179895Sdelphij{ 1041228325Syongari struct et_txdesc_ring *tx_ring; 1042228325Syongari struct et_rxdesc_ring *rx_ring; 1043228325Syongari struct et_txstatus_data *txsd; 1044228325Syongari struct et_rxstat_ring *rxst_ring; 1045228325Syongari struct et_rxstatus_data *rxsd; 1046228325Syongari struct et_rxbuf_data *rbd; 1047228325Syongari struct et_txbuf_data *tbd; 1048179895Sdelphij int i; 1049179895Sdelphij 1050228325Syongari /* Destroy DMA maps for mini RX buffers, ring 0. */ 1051228325Syongari rbd = &sc->sc_rx_data[0]; 1052228325Syongari for (i = 0; i < ET_RX_NDESC; i++) { 1053228325Syongari if (rbd->rbd_buf[i].rb_dmap) { 1054228325Syongari bus_dmamap_destroy(sc->sc_rx_mini_tag, 1055228325Syongari rbd->rbd_buf[i].rb_dmap); 1056228325Syongari rbd->rbd_buf[i].rb_dmap = NULL; 1057179895Sdelphij } 1058179895Sdelphij } 1059228325Syongari if (sc->sc_rx_mini_sparemap) { 1060228325Syongari bus_dmamap_destroy(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap); 1061228325Syongari sc->sc_rx_mini_sparemap = NULL; 1062179895Sdelphij } 1063228325Syongari if (sc->sc_rx_mini_tag) { 1064228325Syongari bus_dma_tag_destroy(sc->sc_rx_mini_tag); 1065228325Syongari sc->sc_rx_mini_tag = NULL; 1066179895Sdelphij } 1067179895Sdelphij 1068228325Syongari /* Destroy DMA maps for standard RX buffers, ring 1. */ 1069228325Syongari rbd = &sc->sc_rx_data[1]; 1070228325Syongari for (i = 0; i < ET_RX_NDESC; i++) { 1071228325Syongari if (rbd->rbd_buf[i].rb_dmap) { 1072228325Syongari bus_dmamap_destroy(sc->sc_rx_tag, 1073228325Syongari rbd->rbd_buf[i].rb_dmap); 1074228325Syongari rbd->rbd_buf[i].rb_dmap = NULL; 1075228325Syongari } 1076179895Sdelphij } 1077228325Syongari if (sc->sc_rx_sparemap) { 1078228325Syongari bus_dmamap_destroy(sc->sc_rx_tag, sc->sc_rx_sparemap); 1079228325Syongari sc->sc_rx_sparemap = NULL; 1080228325Syongari } 1081228325Syongari if (sc->sc_rx_tag) { 1082228325Syongari bus_dma_tag_destroy(sc->sc_rx_tag); 1083228325Syongari sc->sc_rx_tag = NULL; 1084228325Syongari } 1085179895Sdelphij 1086228325Syongari /* Destroy DMA maps for TX buffers. */ 1087228325Syongari tbd = &sc->sc_tx_data; 1088228325Syongari for (i = 0; i < ET_TX_NDESC; i++) { 1089228325Syongari if (tbd->tbd_buf[i].tb_dmap) { 1090228325Syongari bus_dmamap_destroy(sc->sc_tx_tag, 1091228325Syongari tbd->tbd_buf[i].tb_dmap); 1092228325Syongari tbd->tbd_buf[i].tb_dmap = NULL; 1093228325Syongari } 1094179895Sdelphij } 1095228325Syongari if (sc->sc_tx_tag) { 1096228325Syongari bus_dma_tag_destroy(sc->sc_tx_tag); 1097228325Syongari sc->sc_tx_tag = NULL; 1098228325Syongari } 1099179895Sdelphij 1100228325Syongari /* Destroy mini RX ring, ring 0. */ 1101228325Syongari rx_ring = &sc->sc_rx_ring[0]; 1102228325Syongari et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1103228325Syongari &rx_ring->rr_dmap); 1104228325Syongari /* Destroy standard RX ring, ring 1. */ 1105228325Syongari rx_ring = &sc->sc_rx_ring[1]; 1106228325Syongari et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1107228325Syongari &rx_ring->rr_dmap); 1108228325Syongari /* Destroy RX stat ring. */ 1109228325Syongari rxst_ring = &sc->sc_rxstat_ring; 1110228325Syongari et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1111228325Syongari &rxst_ring->rsr_dmap); 1112228325Syongari /* Destroy RX status block. */ 1113228325Syongari rxsd = &sc->sc_rx_status; 1114228325Syongari et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1115228325Syongari &rxst_ring->rsr_dmap); 1116228325Syongari /* Destroy TX ring. */ 1117228325Syongari tx_ring = &sc->sc_tx_ring; 1118228325Syongari et_dma_ring_free(sc, &tx_ring->tr_dtag, (void *)&tx_ring->tr_desc, 1119228325Syongari &tx_ring->tr_dmap); 1120228325Syongari /* Destroy TX status block. */ 1121228325Syongari txsd = &sc->sc_tx_status; 1122228325Syongari et_dma_ring_free(sc, &txsd->txsd_dtag, (void *)&txsd->txsd_status, 1123228325Syongari &txsd->txsd_dmap); 1124228325Syongari 1125228325Syongari /* Destroy the parent tag. */ 1126228325Syongari if (sc->sc_dtag) { 1127228325Syongari bus_dma_tag_destroy(sc->sc_dtag); 1128228325Syongari sc->sc_dtag = NULL; 1129179895Sdelphij } 1130179895Sdelphij} 1131179895Sdelphij 1132179895Sdelphijstatic void 1133179895Sdelphijet_chip_attach(struct et_softc *sc) 1134179895Sdelphij{ 1135179895Sdelphij uint32_t val; 1136179895Sdelphij 1137179895Sdelphij /* 1138179895Sdelphij * Perform minimal initialization 1139179895Sdelphij */ 1140179895Sdelphij 1141179895Sdelphij /* Disable loopback */ 1142179895Sdelphij CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1143179895Sdelphij 1144179895Sdelphij /* Reset MAC */ 1145179895Sdelphij CSR_WRITE_4(sc, ET_MAC_CFG1, 1146179895Sdelphij ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1147179895Sdelphij ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1148179895Sdelphij ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1149179895Sdelphij 1150179895Sdelphij /* 1151179895Sdelphij * Setup half duplex mode 1152179895Sdelphij */ 1153199548Syongari val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1154199548Syongari (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1155199548Syongari (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1156199548Syongari ET_MAC_HDX_EXC_DEFER; 1157179895Sdelphij CSR_WRITE_4(sc, ET_MAC_HDX, val); 1158179895Sdelphij 1159179895Sdelphij /* Clear MAC control */ 1160179895Sdelphij CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1161179895Sdelphij 1162179895Sdelphij /* Reset MII */ 1163179895Sdelphij CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1164179895Sdelphij 1165179895Sdelphij /* Bring MAC out of reset state */ 1166179895Sdelphij CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1167179895Sdelphij 1168179895Sdelphij /* Enable memory controllers */ 1169179895Sdelphij CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1170179895Sdelphij} 1171179895Sdelphij 1172179895Sdelphijstatic void 1173179895Sdelphijet_intr(void *xsc) 1174179895Sdelphij{ 1175229940Syongari struct et_softc *sc; 1176179895Sdelphij struct ifnet *ifp; 1177228362Syongari uint32_t status; 1178179895Sdelphij 1179229940Syongari sc = xsc; 1180179895Sdelphij ET_LOCK(sc); 1181179895Sdelphij ifp = sc->ifp; 1182228362Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1183228362Syongari goto done; 1184179895Sdelphij 1185228362Syongari status = CSR_READ_4(sc, ET_INTR_STATUS); 1186228362Syongari if ((status & ET_INTRS) == 0) 1187228362Syongari goto done; 1188228362Syongari 1189228327Syongari /* Disable further interrupts. */ 1190228327Syongari CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 1191179895Sdelphij 1192228362Syongari if (status & (ET_INTR_RXDMA_ERROR | ET_INTR_TXDMA_ERROR)) { 1193228362Syongari device_printf(sc->dev, "DMA error(0x%08x) -- resetting\n", 1194228362Syongari status); 1195228362Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1196228362Syongari et_init_locked(sc); 1197228362Syongari ET_UNLOCK(sc); 1198228362Syongari return; 1199228362Syongari } 1200228362Syongari if (status & ET_INTR_RXDMA) 1201179895Sdelphij et_rxeof(sc); 1202228362Syongari if (status & (ET_INTR_TXDMA | ET_INTR_TIMER)) 1203179895Sdelphij et_txeof(sc); 1204228362Syongari if (status & ET_INTR_TIMER) 1205179895Sdelphij CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1206228326Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1207228327Syongari CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1208228326Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1209228326Syongari et_start_locked(ifp); 1210228326Syongari } 1211228362Syongaridone: 1212179895Sdelphij ET_UNLOCK(sc); 1213179895Sdelphij} 1214179895Sdelphij 1215179895Sdelphijstatic void 1216179895Sdelphijet_init_locked(struct et_softc *sc) 1217179895Sdelphij{ 1218228325Syongari struct ifnet *ifp; 1219228325Syongari int error; 1220179895Sdelphij 1221179895Sdelphij ET_LOCK_ASSERT(sc); 1222179895Sdelphij 1223228325Syongari ifp = sc->ifp; 1224179895Sdelphij if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1225179895Sdelphij return; 1226179895Sdelphij 1227179895Sdelphij et_stop(sc); 1228228331Syongari et_reset(sc); 1229179895Sdelphij 1230228325Syongari et_init_tx_ring(sc); 1231179895Sdelphij error = et_init_rx_ring(sc); 1232179895Sdelphij if (error) 1233228325Syongari return; 1234179895Sdelphij 1235179895Sdelphij error = et_chip_init(sc); 1236179895Sdelphij if (error) 1237228331Syongari goto fail; 1238179895Sdelphij 1239228331Syongari /* 1240228331Syongari * Start TX/RX DMA engine 1241228331Syongari */ 1242228331Syongari error = et_start_rxdma(sc); 1243179895Sdelphij if (error) 1244228331Syongari return; 1245179895Sdelphij 1246228331Syongari error = et_start_txdma(sc); 1247228331Syongari if (error) 1248228331Syongari return; 1249228331Syongari 1250228327Syongari /* Enable interrupts. */ 1251228327Syongari CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1252179895Sdelphij 1253179895Sdelphij CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1254179895Sdelphij 1255179895Sdelphij ifp->if_drv_flags |= IFF_DRV_RUNNING; 1256179895Sdelphij ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1257228331Syongari 1258228331Syongari sc->sc_flags &= ~ET_FLAG_LINK; 1259228331Syongari et_ifmedia_upd_locked(ifp); 1260228331Syongari 1261228331Syongari callout_reset(&sc->sc_tick, hz, et_tick, sc); 1262228331Syongari 1263228331Syongarifail: 1264179895Sdelphij if (error) 1265179895Sdelphij et_stop(sc); 1266179895Sdelphij} 1267179895Sdelphij 1268179895Sdelphijstatic void 1269179895Sdelphijet_init(void *xsc) 1270179895Sdelphij{ 1271179895Sdelphij struct et_softc *sc = xsc; 1272179895Sdelphij 1273179895Sdelphij ET_LOCK(sc); 1274179895Sdelphij et_init_locked(sc); 1275179895Sdelphij ET_UNLOCK(sc); 1276179895Sdelphij} 1277179895Sdelphij 1278179895Sdelphijstatic int 1279179895Sdelphijet_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1280179895Sdelphij{ 1281229940Syongari struct et_softc *sc; 1282229940Syongari struct mii_data *mii; 1283229940Syongari struct ifreq *ifr; 1284229940Syongari int error, mask, max_framelen; 1285179895Sdelphij 1286229940Syongari sc = ifp->if_softc; 1287229940Syongari ifr = (struct ifreq *)data; 1288229940Syongari error = 0; 1289229940Syongari 1290179895Sdelphij/* XXX LOCKSUSED */ 1291179895Sdelphij switch (cmd) { 1292179895Sdelphij case SIOCSIFFLAGS: 1293179895Sdelphij ET_LOCK(sc); 1294179895Sdelphij if (ifp->if_flags & IFF_UP) { 1295179895Sdelphij if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1296179895Sdelphij if ((ifp->if_flags ^ sc->sc_if_flags) & 1297179895Sdelphij (IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST)) 1298179895Sdelphij et_setmulti(sc); 1299179895Sdelphij } else { 1300179895Sdelphij et_init_locked(sc); 1301179895Sdelphij } 1302179895Sdelphij } else { 1303179895Sdelphij if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1304179895Sdelphij et_stop(sc); 1305179895Sdelphij } 1306179895Sdelphij sc->sc_if_flags = ifp->if_flags; 1307179895Sdelphij ET_UNLOCK(sc); 1308179895Sdelphij break; 1309179895Sdelphij 1310179895Sdelphij case SIOCSIFMEDIA: 1311179895Sdelphij case SIOCGIFMEDIA: 1312229940Syongari mii = device_get_softc(sc->sc_miibus); 1313179895Sdelphij error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1314179895Sdelphij break; 1315179895Sdelphij 1316179895Sdelphij case SIOCADDMULTI: 1317179895Sdelphij case SIOCDELMULTI: 1318179895Sdelphij if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1319179895Sdelphij ET_LOCK(sc); 1320179895Sdelphij et_setmulti(sc); 1321179895Sdelphij ET_UNLOCK(sc); 1322179895Sdelphij } 1323179895Sdelphij break; 1324179895Sdelphij 1325179895Sdelphij case SIOCSIFMTU: 1326228333Syongari ET_LOCK(sc); 1327179895Sdelphij#if 0 1328179895Sdelphij if (sc->sc_flags & ET_FLAG_JUMBO) 1329179895Sdelphij max_framelen = ET_JUMBO_FRAMELEN; 1330179895Sdelphij else 1331179895Sdelphij#endif 1332179895Sdelphij max_framelen = MCLBYTES - 1; 1333179895Sdelphij 1334179895Sdelphij if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 1335179895Sdelphij error = EOPNOTSUPP; 1336228333Syongari ET_UNLOCK(sc); 1337179895Sdelphij break; 1338179895Sdelphij } 1339179895Sdelphij 1340179895Sdelphij if (ifp->if_mtu != ifr->ifr_mtu) { 1341179895Sdelphij ifp->if_mtu = ifr->ifr_mtu; 1342228333Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1343228333Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1344228333Syongari et_init_locked(sc); 1345228333Syongari } 1346179895Sdelphij } 1347228333Syongari ET_UNLOCK(sc); 1348179895Sdelphij break; 1349179895Sdelphij 1350199611Syongari case SIOCSIFCAP: 1351199611Syongari ET_LOCK(sc); 1352199611Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1353199611Syongari if ((mask & IFCAP_TXCSUM) != 0 && 1354199611Syongari (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1355199611Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 1356199611Syongari if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1357199611Syongari ifp->if_hwassist |= ET_CSUM_FEATURES; 1358199611Syongari else 1359199611Syongari ifp->if_hwassist &= ~ET_CSUM_FEATURES; 1360199611Syongari } 1361199611Syongari ET_UNLOCK(sc); 1362199611Syongari break; 1363199611Syongari 1364179895Sdelphij default: 1365179895Sdelphij error = ether_ioctl(ifp, cmd, data); 1366179895Sdelphij break; 1367179895Sdelphij } 1368199556Syongari return (error); 1369179895Sdelphij} 1370179895Sdelphij 1371179895Sdelphijstatic void 1372179895Sdelphijet_start_locked(struct ifnet *ifp) 1373179895Sdelphij{ 1374228293Syongari struct et_softc *sc; 1375228293Syongari struct mbuf *m_head = NULL; 1376228326Syongari struct et_txdesc_ring *tx_ring; 1377179895Sdelphij struct et_txbuf_data *tbd; 1378228326Syongari uint32_t tx_ready_pos; 1379228293Syongari int enq; 1380179895Sdelphij 1381228293Syongari sc = ifp->if_softc; 1382179895Sdelphij ET_LOCK_ASSERT(sc); 1383179895Sdelphij 1384228331Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1385228331Syongari IFF_DRV_RUNNING || 1386228331Syongari (sc->sc_flags & (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) != 1387228331Syongari (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) 1388179895Sdelphij return; 1389179895Sdelphij 1390228326Syongari /* 1391228326Syongari * Driver does not request TX completion interrupt for every 1392228326Syongari * queued frames to prevent generating excessive interrupts. 1393228326Syongari * This means driver may wait for TX completion interrupt even 1394228326Syongari * though some frames were sucessfully transmitted. Reclaiming 1395228326Syongari * transmitted frames will ensure driver see all available 1396228326Syongari * descriptors. 1397228326Syongari */ 1398228293Syongari tbd = &sc->sc_tx_data; 1399228326Syongari if (tbd->tbd_used > (ET_TX_NDESC * 2) / 3) 1400228326Syongari et_txeof(sc); 1401228326Syongari 1402228293Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1403228293Syongari if (tbd->tbd_used + ET_NSEG_SPARE >= ET_TX_NDESC) { 1404179895Sdelphij ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1405179895Sdelphij break; 1406179895Sdelphij } 1407179895Sdelphij 1408228293Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1409228293Syongari if (m_head == NULL) 1410179895Sdelphij break; 1411179895Sdelphij 1412228293Syongari if (et_encap(sc, &m_head)) { 1413228293Syongari if (m_head == NULL) { 1414228293Syongari ifp->if_oerrors++; 1415228293Syongari break; 1416228293Syongari } 1417228293Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1418228293Syongari if (tbd->tbd_used > 0) 1419228293Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1420179895Sdelphij break; 1421179895Sdelphij } 1422228293Syongari enq++; 1423228293Syongari ETHER_BPF_MTAP(ifp, m_head); 1424179895Sdelphij } 1425179895Sdelphij 1426228326Syongari if (enq > 0) { 1427228326Syongari tx_ring = &sc->sc_tx_ring; 1428228326Syongari bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1429228326Syongari BUS_DMASYNC_PREWRITE); 1430228326Syongari tx_ready_pos = tx_ring->tr_ready_index & 1431228326Syongari ET_TX_READY_POS_INDEX_MASK; 1432228326Syongari if (tx_ring->tr_ready_wrap) 1433228326Syongari tx_ready_pos |= ET_TX_READY_POS_WRAP; 1434228326Syongari CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1435179895Sdelphij sc->watchdog_timer = 5; 1436228326Syongari } 1437179895Sdelphij} 1438179895Sdelphij 1439179895Sdelphijstatic void 1440179895Sdelphijet_start(struct ifnet *ifp) 1441179895Sdelphij{ 1442229940Syongari struct et_softc *sc; 1443179895Sdelphij 1444229940Syongari sc = ifp->if_softc; 1445179895Sdelphij ET_LOCK(sc); 1446179895Sdelphij et_start_locked(ifp); 1447179895Sdelphij ET_UNLOCK(sc); 1448179895Sdelphij} 1449179895Sdelphij 1450228325Syongaristatic int 1451179895Sdelphijet_watchdog(struct et_softc *sc) 1452179895Sdelphij{ 1453228325Syongari uint32_t status; 1454228325Syongari 1455179895Sdelphij ET_LOCK_ASSERT(sc); 1456179895Sdelphij 1457179895Sdelphij if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1458228325Syongari return (0); 1459179895Sdelphij 1460228325Syongari bus_dmamap_sync(sc->sc_tx_status.txsd_dtag, sc->sc_tx_status.txsd_dmap, 1461228325Syongari BUS_DMASYNC_POSTREAD); 1462228325Syongari status = le32toh(*(sc->sc_tx_status.txsd_status)); 1463228325Syongari if_printf(sc->ifp, "watchdog timed out (0x%08x) -- resetting\n", 1464228325Syongari status); 1465179895Sdelphij 1466212969Syongari sc->ifp->if_oerrors++; 1467212969Syongari sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1468179895Sdelphij et_init_locked(sc); 1469228325Syongari return (EJUSTRETURN); 1470179895Sdelphij} 1471179895Sdelphij 1472179895Sdelphijstatic int 1473179895Sdelphijet_stop_rxdma(struct et_softc *sc) 1474179895Sdelphij{ 1475229940Syongari 1476179895Sdelphij CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1477179895Sdelphij ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1478179895Sdelphij 1479179895Sdelphij DELAY(5); 1480179895Sdelphij if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1481179895Sdelphij if_printf(sc->ifp, "can't stop RX DMA engine\n"); 1482199556Syongari return (ETIMEDOUT); 1483179895Sdelphij } 1484199556Syongari return (0); 1485179895Sdelphij} 1486179895Sdelphij 1487179895Sdelphijstatic int 1488179895Sdelphijet_stop_txdma(struct et_softc *sc) 1489179895Sdelphij{ 1490229940Syongari 1491179895Sdelphij CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1492179895Sdelphij ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1493199556Syongari return (0); 1494179895Sdelphij} 1495179895Sdelphij 1496179895Sdelphijstatic void 1497179895Sdelphijet_free_tx_ring(struct et_softc *sc) 1498179895Sdelphij{ 1499228325Syongari struct et_txdesc_ring *tx_ring; 1500228325Syongari struct et_txbuf_data *tbd; 1501228325Syongari struct et_txbuf *tb; 1502179895Sdelphij int i; 1503179895Sdelphij 1504228325Syongari tbd = &sc->sc_tx_data; 1505228325Syongari tx_ring = &sc->sc_tx_ring; 1506179895Sdelphij for (i = 0; i < ET_TX_NDESC; ++i) { 1507228325Syongari tb = &tbd->tbd_buf[i]; 1508179895Sdelphij if (tb->tb_mbuf != NULL) { 1509228325Syongari bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 1510228325Syongari BUS_DMASYNC_POSTWRITE); 1511179895Sdelphij bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 1512179895Sdelphij m_freem(tb->tb_mbuf); 1513179895Sdelphij tb->tb_mbuf = NULL; 1514179895Sdelphij } 1515179895Sdelphij } 1516179895Sdelphij} 1517179895Sdelphij 1518179895Sdelphijstatic void 1519179895Sdelphijet_free_rx_ring(struct et_softc *sc) 1520179895Sdelphij{ 1521228325Syongari struct et_rxbuf_data *rbd; 1522228325Syongari struct et_rxdesc_ring *rx_ring; 1523228325Syongari struct et_rxbuf *rb; 1524228325Syongari int i; 1525179895Sdelphij 1526228325Syongari /* Ring 0 */ 1527228325Syongari rx_ring = &sc->sc_rx_ring[0]; 1528228325Syongari rbd = &sc->sc_rx_data[0]; 1529228325Syongari for (i = 0; i < ET_RX_NDESC; ++i) { 1530228325Syongari rb = &rbd->rbd_buf[i]; 1531228325Syongari if (rb->rb_mbuf != NULL) { 1532228325Syongari bus_dmamap_sync(sc->sc_rx_mini_tag, rx_ring->rr_dmap, 1533228325Syongari BUS_DMASYNC_POSTREAD); 1534228325Syongari bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 1535228325Syongari m_freem(rb->rb_mbuf); 1536228325Syongari rb->rb_mbuf = NULL; 1537228325Syongari } 1538228325Syongari } 1539179895Sdelphij 1540228325Syongari /* Ring 1 */ 1541228325Syongari rx_ring = &sc->sc_rx_ring[1]; 1542228325Syongari rbd = &sc->sc_rx_data[1]; 1543228325Syongari for (i = 0; i < ET_RX_NDESC; ++i) { 1544228325Syongari rb = &rbd->rbd_buf[i]; 1545228325Syongari if (rb->rb_mbuf != NULL) { 1546228325Syongari bus_dmamap_sync(sc->sc_rx_tag, rx_ring->rr_dmap, 1547228325Syongari BUS_DMASYNC_POSTREAD); 1548228325Syongari bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 1549228325Syongari m_freem(rb->rb_mbuf); 1550228325Syongari rb->rb_mbuf = NULL; 1551179895Sdelphij } 1552179895Sdelphij } 1553179895Sdelphij} 1554179895Sdelphij 1555179895Sdelphijstatic void 1556179895Sdelphijet_setmulti(struct et_softc *sc) 1557179895Sdelphij{ 1558179895Sdelphij struct ifnet *ifp; 1559179895Sdelphij uint32_t hash[4] = { 0, 0, 0, 0 }; 1560179895Sdelphij uint32_t rxmac_ctrl, pktfilt; 1561179895Sdelphij struct ifmultiaddr *ifma; 1562179895Sdelphij int i, count; 1563179895Sdelphij 1564179895Sdelphij ET_LOCK_ASSERT(sc); 1565179895Sdelphij ifp = sc->ifp; 1566179895Sdelphij 1567179895Sdelphij pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1568179895Sdelphij rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1569179895Sdelphij 1570179895Sdelphij pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1571179895Sdelphij if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1572179895Sdelphij rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1573179895Sdelphij goto back; 1574179895Sdelphij } 1575179895Sdelphij 1576179895Sdelphij count = 0; 1577195049Srwatson if_maddr_rlock(ifp); 1578179895Sdelphij TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1579179895Sdelphij uint32_t *hp, h; 1580179895Sdelphij 1581179895Sdelphij if (ifma->ifma_addr->sa_family != AF_LINK) 1582179895Sdelphij continue; 1583179895Sdelphij 1584179895Sdelphij h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1585179895Sdelphij ifma->ifma_addr), ETHER_ADDR_LEN); 1586179895Sdelphij h = (h & 0x3f800000) >> 23; 1587179895Sdelphij 1588179895Sdelphij hp = &hash[0]; 1589179895Sdelphij if (h >= 32 && h < 64) { 1590179895Sdelphij h -= 32; 1591179895Sdelphij hp = &hash[1]; 1592179895Sdelphij } else if (h >= 64 && h < 96) { 1593179895Sdelphij h -= 64; 1594179895Sdelphij hp = &hash[2]; 1595179895Sdelphij } else if (h >= 96) { 1596179895Sdelphij h -= 96; 1597179895Sdelphij hp = &hash[3]; 1598179895Sdelphij } 1599179895Sdelphij *hp |= (1 << h); 1600179895Sdelphij 1601179895Sdelphij ++count; 1602179895Sdelphij } 1603195049Srwatson if_maddr_runlock(ifp); 1604179895Sdelphij 1605179895Sdelphij for (i = 0; i < 4; ++i) 1606179895Sdelphij CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1607179895Sdelphij 1608179895Sdelphij if (count > 0) 1609179895Sdelphij pktfilt |= ET_PKTFILT_MCAST; 1610179895Sdelphij rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1611179895Sdelphijback: 1612179895Sdelphij CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1613179895Sdelphij CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1614179895Sdelphij} 1615179895Sdelphij 1616179895Sdelphijstatic int 1617179895Sdelphijet_chip_init(struct et_softc *sc) 1618179895Sdelphij{ 1619229940Syongari struct ifnet *ifp; 1620179895Sdelphij uint32_t rxq_end; 1621179895Sdelphij int error, frame_len, rxmem_size; 1622179895Sdelphij 1623229940Syongari ifp = sc->ifp; 1624179895Sdelphij /* 1625179895Sdelphij * Split 16Kbytes internal memory between TX and RX 1626179895Sdelphij * according to frame length. 1627179895Sdelphij */ 1628179895Sdelphij frame_len = ET_FRAMELEN(ifp->if_mtu); 1629179895Sdelphij if (frame_len < 2048) { 1630179895Sdelphij rxmem_size = ET_MEM_RXSIZE_DEFAULT; 1631179895Sdelphij } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 1632179895Sdelphij rxmem_size = ET_MEM_SIZE / 2; 1633179895Sdelphij } else { 1634179895Sdelphij rxmem_size = ET_MEM_SIZE - 1635179895Sdelphij roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 1636179895Sdelphij } 1637179895Sdelphij rxq_end = ET_QUEUE_ADDR(rxmem_size); 1638179895Sdelphij 1639179895Sdelphij CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 1640179895Sdelphij CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 1641179895Sdelphij CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 1642179895Sdelphij CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 1643179895Sdelphij 1644179895Sdelphij /* No loopback */ 1645179895Sdelphij CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1646179895Sdelphij 1647179895Sdelphij /* Clear MSI configure */ 1648199552Syongari if ((sc->sc_flags & ET_FLAG_MSI) == 0) 1649199552Syongari CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1650179895Sdelphij 1651179895Sdelphij /* Disable timer */ 1652179895Sdelphij CSR_WRITE_4(sc, ET_TIMER, 0); 1653179895Sdelphij 1654179895Sdelphij /* Initialize MAC */ 1655179895Sdelphij et_init_mac(sc); 1656179895Sdelphij 1657179895Sdelphij /* Enable memory controllers */ 1658179895Sdelphij CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1659179895Sdelphij 1660179895Sdelphij /* Initialize RX MAC */ 1661179895Sdelphij et_init_rxmac(sc); 1662179895Sdelphij 1663179895Sdelphij /* Initialize TX MAC */ 1664179895Sdelphij et_init_txmac(sc); 1665179895Sdelphij 1666179895Sdelphij /* Initialize RX DMA engine */ 1667179895Sdelphij error = et_init_rxdma(sc); 1668179895Sdelphij if (error) 1669199556Syongari return (error); 1670179895Sdelphij 1671179895Sdelphij /* Initialize TX DMA engine */ 1672179895Sdelphij error = et_init_txdma(sc); 1673179895Sdelphij if (error) 1674199556Syongari return (error); 1675179895Sdelphij 1676199556Syongari return (0); 1677179895Sdelphij} 1678179895Sdelphij 1679228325Syongaristatic void 1680179895Sdelphijet_init_tx_ring(struct et_softc *sc) 1681179895Sdelphij{ 1682228325Syongari struct et_txdesc_ring *tx_ring; 1683228325Syongari struct et_txbuf_data *tbd; 1684228325Syongari struct et_txstatus_data *txsd; 1685179895Sdelphij 1686228325Syongari tx_ring = &sc->sc_tx_ring; 1687179895Sdelphij bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1688179895Sdelphij bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1689228325Syongari BUS_DMASYNC_PREWRITE); 1690179895Sdelphij 1691228325Syongari tbd = &sc->sc_tx_data; 1692179895Sdelphij tbd->tbd_start_index = 0; 1693179895Sdelphij tbd->tbd_start_wrap = 0; 1694179895Sdelphij tbd->tbd_used = 0; 1695179895Sdelphij 1696228325Syongari txsd = &sc->sc_tx_status; 1697179895Sdelphij bzero(txsd->txsd_status, sizeof(uint32_t)); 1698179895Sdelphij bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap, 1699228325Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1700179895Sdelphij} 1701179895Sdelphij 1702179895Sdelphijstatic int 1703179895Sdelphijet_init_rx_ring(struct et_softc *sc) 1704179895Sdelphij{ 1705228325Syongari struct et_rxstatus_data *rxsd; 1706228325Syongari struct et_rxstat_ring *rxst_ring; 1707228325Syongari struct et_rxbuf_data *rbd; 1708228325Syongari int i, error, n; 1709179895Sdelphij 1710179895Sdelphij for (n = 0; n < ET_RX_NRING; ++n) { 1711228325Syongari rbd = &sc->sc_rx_data[n]; 1712179895Sdelphij for (i = 0; i < ET_RX_NDESC; ++i) { 1713228325Syongari error = rbd->rbd_newbuf(rbd, i); 1714179895Sdelphij if (error) { 1715179895Sdelphij if_printf(sc->ifp, "%d ring %d buf, " 1716179895Sdelphij "newbuf failed: %d\n", n, i, error); 1717199556Syongari return (error); 1718179895Sdelphij } 1719179895Sdelphij } 1720179895Sdelphij } 1721179895Sdelphij 1722228325Syongari rxsd = &sc->sc_rx_status; 1723179895Sdelphij bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1724179895Sdelphij bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1725228325Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1726179895Sdelphij 1727228325Syongari rxst_ring = &sc->sc_rxstat_ring; 1728179895Sdelphij bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1729179895Sdelphij bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1730228325Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1731179895Sdelphij 1732199556Syongari return (0); 1733179895Sdelphij} 1734179895Sdelphij 1735179895Sdelphijstatic int 1736179895Sdelphijet_init_rxdma(struct et_softc *sc) 1737179895Sdelphij{ 1738229940Syongari struct et_rxstatus_data *rxsd; 1739229940Syongari struct et_rxstat_ring *rxst_ring; 1740179895Sdelphij struct et_rxdesc_ring *rx_ring; 1741179895Sdelphij int error; 1742179895Sdelphij 1743179895Sdelphij error = et_stop_rxdma(sc); 1744179895Sdelphij if (error) { 1745179895Sdelphij if_printf(sc->ifp, "can't init RX DMA engine\n"); 1746199556Syongari return (error); 1747179895Sdelphij } 1748179895Sdelphij 1749179895Sdelphij /* 1750179895Sdelphij * Install RX status 1751179895Sdelphij */ 1752229940Syongari rxsd = &sc->sc_rx_status; 1753179895Sdelphij CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1754179895Sdelphij CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1755179895Sdelphij 1756179895Sdelphij /* 1757179895Sdelphij * Install RX stat ring 1758179895Sdelphij */ 1759229940Syongari rxst_ring = &sc->sc_rxstat_ring; 1760179895Sdelphij CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1761179895Sdelphij CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1762179895Sdelphij CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1763179895Sdelphij CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1764179895Sdelphij CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1765179895Sdelphij 1766179895Sdelphij /* Match ET_RXSTAT_POS */ 1767179895Sdelphij rxst_ring->rsr_index = 0; 1768179895Sdelphij rxst_ring->rsr_wrap = 0; 1769179895Sdelphij 1770179895Sdelphij /* 1771179895Sdelphij * Install the 2nd RX descriptor ring 1772179895Sdelphij */ 1773179895Sdelphij rx_ring = &sc->sc_rx_ring[1]; 1774179895Sdelphij CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1775179895Sdelphij CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1776179895Sdelphij CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1777179895Sdelphij CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1778179895Sdelphij CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1779179895Sdelphij 1780179895Sdelphij /* Match ET_RX_RING1_POS */ 1781179895Sdelphij rx_ring->rr_index = 0; 1782179895Sdelphij rx_ring->rr_wrap = 1; 1783179895Sdelphij 1784179895Sdelphij /* 1785179895Sdelphij * Install the 1st RX descriptor ring 1786179895Sdelphij */ 1787179895Sdelphij rx_ring = &sc->sc_rx_ring[0]; 1788179895Sdelphij CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1789179895Sdelphij CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1790179895Sdelphij CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1791179895Sdelphij CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1792179895Sdelphij CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1793179895Sdelphij 1794179895Sdelphij /* Match ET_RX_RING0_POS */ 1795179895Sdelphij rx_ring->rr_index = 0; 1796179895Sdelphij rx_ring->rr_wrap = 1; 1797179895Sdelphij 1798179895Sdelphij /* 1799179895Sdelphij * RX intr moderation 1800179895Sdelphij */ 1801179895Sdelphij CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1802179895Sdelphij CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1803179895Sdelphij 1804199556Syongari return (0); 1805179895Sdelphij} 1806179895Sdelphij 1807179895Sdelphijstatic int 1808179895Sdelphijet_init_txdma(struct et_softc *sc) 1809179895Sdelphij{ 1810229940Syongari struct et_txdesc_ring *tx_ring; 1811229940Syongari struct et_txstatus_data *txsd; 1812179895Sdelphij int error; 1813179895Sdelphij 1814179895Sdelphij error = et_stop_txdma(sc); 1815179895Sdelphij if (error) { 1816179895Sdelphij if_printf(sc->ifp, "can't init TX DMA engine\n"); 1817199556Syongari return (error); 1818179895Sdelphij } 1819179895Sdelphij 1820179895Sdelphij /* 1821179895Sdelphij * Install TX descriptor ring 1822179895Sdelphij */ 1823229940Syongari tx_ring = &sc->sc_tx_ring; 1824179895Sdelphij CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1825179895Sdelphij CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1826179895Sdelphij CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1827179895Sdelphij 1828179895Sdelphij /* 1829179895Sdelphij * Install TX status 1830179895Sdelphij */ 1831229940Syongari txsd = &sc->sc_tx_status; 1832179895Sdelphij CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1833179895Sdelphij CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1834179895Sdelphij 1835179895Sdelphij CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1836179895Sdelphij 1837179895Sdelphij /* Match ET_TX_READY_POS */ 1838179895Sdelphij tx_ring->tr_ready_index = 0; 1839179895Sdelphij tx_ring->tr_ready_wrap = 0; 1840179895Sdelphij 1841199556Syongari return (0); 1842179895Sdelphij} 1843179895Sdelphij 1844179895Sdelphijstatic void 1845179895Sdelphijet_init_mac(struct et_softc *sc) 1846179895Sdelphij{ 1847229940Syongari struct ifnet *ifp; 1848229940Syongari const uint8_t *eaddr; 1849179895Sdelphij uint32_t val; 1850179895Sdelphij 1851179895Sdelphij /* Reset MAC */ 1852179895Sdelphij CSR_WRITE_4(sc, ET_MAC_CFG1, 1853179895Sdelphij ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1854179895Sdelphij ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1855179895Sdelphij ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1856179895Sdelphij 1857179895Sdelphij /* 1858179895Sdelphij * Setup inter packet gap 1859179895Sdelphij */ 1860199548Syongari val = (56 << ET_IPG_NONB2B_1_SHIFT) | 1861199548Syongari (88 << ET_IPG_NONB2B_2_SHIFT) | 1862199548Syongari (80 << ET_IPG_MINIFG_SHIFT) | 1863199548Syongari (96 << ET_IPG_B2B_SHIFT); 1864179895Sdelphij CSR_WRITE_4(sc, ET_IPG, val); 1865179895Sdelphij 1866179895Sdelphij /* 1867179895Sdelphij * Setup half duplex mode 1868179895Sdelphij */ 1869199548Syongari val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1870199548Syongari (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1871199548Syongari (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1872199548Syongari ET_MAC_HDX_EXC_DEFER; 1873179895Sdelphij CSR_WRITE_4(sc, ET_MAC_HDX, val); 1874179895Sdelphij 1875179895Sdelphij /* Clear MAC control */ 1876179895Sdelphij CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1877179895Sdelphij 1878179895Sdelphij /* Reset MII */ 1879179895Sdelphij CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1880179895Sdelphij 1881179895Sdelphij /* 1882179895Sdelphij * Set MAC address 1883179895Sdelphij */ 1884229940Syongari ifp = sc->ifp; 1885229940Syongari eaddr = IF_LLADDR(ifp); 1886179895Sdelphij val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1887179895Sdelphij CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1888179895Sdelphij val = (eaddr[0] << 16) | (eaddr[1] << 24); 1889179895Sdelphij CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1890179895Sdelphij 1891179895Sdelphij /* Set max frame length */ 1892179895Sdelphij CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu)); 1893179895Sdelphij 1894179895Sdelphij /* Bring MAC out of reset state */ 1895179895Sdelphij CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1896179895Sdelphij} 1897179895Sdelphij 1898179895Sdelphijstatic void 1899179895Sdelphijet_init_rxmac(struct et_softc *sc) 1900179895Sdelphij{ 1901229940Syongari struct ifnet *ifp; 1902229940Syongari const uint8_t *eaddr; 1903179895Sdelphij uint32_t val; 1904179895Sdelphij int i; 1905179895Sdelphij 1906179895Sdelphij /* Disable RX MAC and WOL */ 1907179895Sdelphij CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1908179895Sdelphij 1909179895Sdelphij /* 1910179895Sdelphij * Clear all WOL related registers 1911179895Sdelphij */ 1912179895Sdelphij for (i = 0; i < 3; ++i) 1913179895Sdelphij CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1914179895Sdelphij for (i = 0; i < 20; ++i) 1915179895Sdelphij CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1916179895Sdelphij 1917179895Sdelphij /* 1918179895Sdelphij * Set WOL source address. XXX is this necessary? 1919179895Sdelphij */ 1920229940Syongari ifp = sc->ifp; 1921229940Syongari eaddr = IF_LLADDR(ifp); 1922179895Sdelphij val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1923179895Sdelphij CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1924179895Sdelphij val = (eaddr[0] << 8) | eaddr[1]; 1925179895Sdelphij CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1926179895Sdelphij 1927179895Sdelphij /* Clear packet filters */ 1928179895Sdelphij CSR_WRITE_4(sc, ET_PKTFILT, 0); 1929179895Sdelphij 1930179895Sdelphij /* No ucast filtering */ 1931179895Sdelphij CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1932179895Sdelphij CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1933179895Sdelphij CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1934179895Sdelphij 1935179895Sdelphij if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) { 1936179895Sdelphij /* 1937179895Sdelphij * In order to transmit jumbo packets greater than 1938179895Sdelphij * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 1939179895Sdelphij * RX MAC and RX DMA needs to be reduced in size to 1940179895Sdelphij * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 1941179895Sdelphij * order to implement this, we must use "cut through" 1942179895Sdelphij * mode in the RX MAC, which chops packets down into 1943179895Sdelphij * segments. In this case we selected 256 bytes, 1944179895Sdelphij * since this is the size of the PCI-Express TLP's 1945179895Sdelphij * that the ET1310 uses. 1946179895Sdelphij */ 1947199548Syongari val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) | 1948179895Sdelphij ET_RXMAC_MC_SEGSZ_ENABLE; 1949179895Sdelphij } else { 1950179895Sdelphij val = 0; 1951179895Sdelphij } 1952179895Sdelphij CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1953179895Sdelphij 1954179895Sdelphij CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1955179895Sdelphij 1956179895Sdelphij /* Initialize RX MAC management register */ 1957179895Sdelphij CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1958179895Sdelphij 1959179895Sdelphij CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1960179895Sdelphij 1961179895Sdelphij CSR_WRITE_4(sc, ET_RXMAC_MGT, 1962179895Sdelphij ET_RXMAC_MGT_PASS_ECRC | 1963179895Sdelphij ET_RXMAC_MGT_PASS_ELEN | 1964179895Sdelphij ET_RXMAC_MGT_PASS_ETRUNC | 1965179895Sdelphij ET_RXMAC_MGT_CHECK_PKT); 1966179895Sdelphij 1967179895Sdelphij /* 1968179895Sdelphij * Configure runt filtering (may not work on certain chip generation) 1969179895Sdelphij */ 1970199548Syongari val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) & 1971199548Syongari ET_PKTFILT_MINLEN_MASK; 1972199548Syongari val |= ET_PKTFILT_FRAG; 1973179895Sdelphij CSR_WRITE_4(sc, ET_PKTFILT, val); 1974179895Sdelphij 1975179895Sdelphij /* Enable RX MAC but leave WOL disabled */ 1976179895Sdelphij CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1977179895Sdelphij ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1978179895Sdelphij 1979179895Sdelphij /* 1980179895Sdelphij * Setup multicast hash and allmulti/promisc mode 1981179895Sdelphij */ 1982179895Sdelphij et_setmulti(sc); 1983179895Sdelphij} 1984179895Sdelphij 1985179895Sdelphijstatic void 1986179895Sdelphijet_init_txmac(struct et_softc *sc) 1987179895Sdelphij{ 1988229940Syongari 1989179895Sdelphij /* Disable TX MAC and FC(?) */ 1990179895Sdelphij CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1991179895Sdelphij 1992228369Syongari /* 1993228369Syongari * Initialize pause time. 1994228369Syongari * This register should be set before XON/XOFF frame is 1995228369Syongari * sent by driver. 1996228369Syongari */ 1997228369Syongari CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0 << ET_TXMAC_FLOWCTRL_CFPT_SHIFT); 1998179895Sdelphij 1999179895Sdelphij /* Enable TX MAC but leave FC(?) diabled */ 2000179895Sdelphij CSR_WRITE_4(sc, ET_TXMAC_CTRL, 2001179895Sdelphij ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 2002179895Sdelphij} 2003179895Sdelphij 2004179895Sdelphijstatic int 2005179895Sdelphijet_start_rxdma(struct et_softc *sc) 2006179895Sdelphij{ 2007229940Syongari uint32_t val; 2008179895Sdelphij 2009229940Syongari val = (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) | 2010229940Syongari ET_RXDMA_CTRL_RING0_ENABLE; 2011199548Syongari val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) | 2012229940Syongari ET_RXDMA_CTRL_RING1_ENABLE; 2013179895Sdelphij 2014179895Sdelphij CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 2015179895Sdelphij 2016179895Sdelphij DELAY(5); 2017179895Sdelphij 2018179895Sdelphij if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 2019179895Sdelphij if_printf(sc->ifp, "can't start RX DMA engine\n"); 2020199556Syongari return (ETIMEDOUT); 2021179895Sdelphij } 2022199556Syongari return (0); 2023179895Sdelphij} 2024179895Sdelphij 2025179895Sdelphijstatic int 2026179895Sdelphijet_start_txdma(struct et_softc *sc) 2027179895Sdelphij{ 2028229940Syongari 2029179895Sdelphij CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 2030199556Syongari return (0); 2031179895Sdelphij} 2032179895Sdelphij 2033179895Sdelphijstatic void 2034179895Sdelphijet_rxeof(struct et_softc *sc) 2035179895Sdelphij{ 2036179895Sdelphij struct et_rxstatus_data *rxsd; 2037179895Sdelphij struct et_rxstat_ring *rxst_ring; 2038228325Syongari struct et_rxbuf_data *rbd; 2039228325Syongari struct et_rxdesc_ring *rx_ring; 2040228325Syongari struct et_rxstat *st; 2041228325Syongari struct ifnet *ifp; 2042228325Syongari struct mbuf *m; 2043228325Syongari uint32_t rxstat_pos, rxring_pos; 2044228325Syongari uint32_t rxst_info1, rxst_info2, rxs_stat_ring; 2045228325Syongari int buflen, buf_idx, npost[2], ring_idx; 2046228325Syongari int rxst_index, rxst_wrap; 2047179895Sdelphij 2048179895Sdelphij ET_LOCK_ASSERT(sc); 2049228325Syongari 2050179895Sdelphij ifp = sc->ifp; 2051179895Sdelphij rxsd = &sc->sc_rx_status; 2052179895Sdelphij rxst_ring = &sc->sc_rxstat_ring; 2053179895Sdelphij 2054179895Sdelphij if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2055179895Sdelphij return; 2056179895Sdelphij 2057179895Sdelphij bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2058228325Syongari BUS_DMASYNC_POSTREAD); 2059179895Sdelphij bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2060228325Syongari BUS_DMASYNC_POSTREAD); 2061179895Sdelphij 2062228325Syongari npost[0] = npost[1] = 0; 2063199609Syongari rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring); 2064179895Sdelphij rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 2065199548Syongari rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >> 2066199548Syongari ET_RXS_STATRING_INDEX_SHIFT; 2067179895Sdelphij 2068179895Sdelphij while (rxst_index != rxst_ring->rsr_index || 2069228325Syongari rxst_wrap != rxst_ring->rsr_wrap) { 2070228325Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2071228325Syongari break; 2072179895Sdelphij 2073179895Sdelphij MPASS(rxst_ring->rsr_index < ET_RX_NSTAT); 2074179895Sdelphij st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 2075228325Syongari rxst_info1 = le32toh(st->rxst_info1); 2076199609Syongari rxst_info2 = le32toh(st->rxst_info2); 2077199609Syongari buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >> 2078199548Syongari ET_RXST_INFO2_LEN_SHIFT; 2079199609Syongari buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >> 2080199548Syongari ET_RXST_INFO2_BUFIDX_SHIFT; 2081199609Syongari ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >> 2082199548Syongari ET_RXST_INFO2_RINGIDX_SHIFT; 2083179895Sdelphij 2084179895Sdelphij if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 2085179895Sdelphij rxst_ring->rsr_index = 0; 2086179895Sdelphij rxst_ring->rsr_wrap ^= 1; 2087179895Sdelphij } 2088199548Syongari rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK; 2089179895Sdelphij if (rxst_ring->rsr_wrap) 2090179895Sdelphij rxstat_pos |= ET_RXSTAT_POS_WRAP; 2091179895Sdelphij CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 2092179895Sdelphij 2093179895Sdelphij if (ring_idx >= ET_RX_NRING) { 2094179895Sdelphij ifp->if_ierrors++; 2095179895Sdelphij if_printf(ifp, "invalid ring index %d\n", ring_idx); 2096179895Sdelphij continue; 2097179895Sdelphij } 2098179895Sdelphij if (buf_idx >= ET_RX_NDESC) { 2099179895Sdelphij ifp->if_ierrors++; 2100179895Sdelphij if_printf(ifp, "invalid buf index %d\n", buf_idx); 2101179895Sdelphij continue; 2102179895Sdelphij } 2103179895Sdelphij 2104179895Sdelphij rbd = &sc->sc_rx_data[ring_idx]; 2105179895Sdelphij m = rbd->rbd_buf[buf_idx].rb_mbuf; 2106228325Syongari if ((rxst_info1 & ET_RXST_INFO1_OK) == 0){ 2107228325Syongari /* Discard errored frame. */ 2108228325Syongari rbd->rbd_discard(rbd, buf_idx); 2109228325Syongari } else if (rbd->rbd_newbuf(rbd, buf_idx) != 0) { 2110228325Syongari /* No available mbufs, discard it. */ 2111228325Syongari ifp->if_iqdrops++; 2112228325Syongari rbd->rbd_discard(rbd, buf_idx); 2113228325Syongari } else { 2114228325Syongari buflen -= ETHER_CRC_LEN; 2115228325Syongari if (buflen < ETHER_HDR_LEN) { 2116179895Sdelphij m_freem(m); 2117179895Sdelphij ifp->if_ierrors++; 2118179895Sdelphij } else { 2119228325Syongari m->m_pkthdr.len = m->m_len = buflen; 2120179895Sdelphij m->m_pkthdr.rcvif = ifp; 2121179895Sdelphij ET_UNLOCK(sc); 2122179895Sdelphij ifp->if_input(ifp, m); 2123179895Sdelphij ET_LOCK(sc); 2124179895Sdelphij } 2125179895Sdelphij } 2126179895Sdelphij 2127179895Sdelphij rx_ring = &sc->sc_rx_ring[ring_idx]; 2128179895Sdelphij if (buf_idx != rx_ring->rr_index) { 2129228325Syongari if_printf(ifp, 2130228325Syongari "WARNING!! ring %d, buf_idx %d, rr_idx %d\n", 2131228325Syongari ring_idx, buf_idx, rx_ring->rr_index); 2132179895Sdelphij } 2133179895Sdelphij 2134179895Sdelphij MPASS(rx_ring->rr_index < ET_RX_NDESC); 2135179895Sdelphij if (++rx_ring->rr_index == ET_RX_NDESC) { 2136179895Sdelphij rx_ring->rr_index = 0; 2137179895Sdelphij rx_ring->rr_wrap ^= 1; 2138179895Sdelphij } 2139199548Syongari rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK; 2140179895Sdelphij if (rx_ring->rr_wrap) 2141179895Sdelphij rxring_pos |= ET_RX_RING_POS_WRAP; 2142179895Sdelphij CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 2143179895Sdelphij } 2144228325Syongari 2145228325Syongari bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2146228325Syongari BUS_DMASYNC_PREREAD); 2147228325Syongari bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2148228325Syongari BUS_DMASYNC_PREREAD); 2149179895Sdelphij} 2150179895Sdelphij 2151179895Sdelphijstatic int 2152179895Sdelphijet_encap(struct et_softc *sc, struct mbuf **m0) 2153179895Sdelphij{ 2154228325Syongari struct et_txdesc_ring *tx_ring; 2155228325Syongari struct et_txbuf_data *tbd; 2156228325Syongari struct et_txdesc *td; 2157228325Syongari struct mbuf *m; 2158179895Sdelphij bus_dma_segment_t segs[ET_NSEG_MAX]; 2159179895Sdelphij bus_dmamap_t map; 2160228326Syongari uint32_t csum_flags, last_td_ctrl2; 2161228325Syongari int error, i, idx, first_idx, last_idx, nsegs; 2162179895Sdelphij 2163228325Syongari tx_ring = &sc->sc_tx_ring; 2164179895Sdelphij MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2165228325Syongari tbd = &sc->sc_tx_data; 2166179895Sdelphij first_idx = tx_ring->tr_ready_index; 2167179895Sdelphij map = tbd->tbd_buf[first_idx].tb_dmap; 2168179895Sdelphij 2169228325Syongari error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, &nsegs, 2170228325Syongari 0); 2171228325Syongari if (error == EFBIG) { 2172243857Sglebius m = m_collapse(*m0, M_NOWAIT, ET_NSEG_MAX); 2173228325Syongari if (m == NULL) { 2174228325Syongari m_freem(*m0); 2175228325Syongari *m0 = NULL; 2176228325Syongari return (ENOMEM); 2177179895Sdelphij } 2178228325Syongari *m0 = m; 2179228325Syongari error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, 2180228325Syongari &nsegs, 0); 2181228325Syongari if (error != 0) { 2182228325Syongari m_freem(*m0); 2183228325Syongari *m0 = NULL; 2184228325Syongari return (error); 2185228325Syongari } 2186228325Syongari } else if (error != 0) 2187228325Syongari return (error); 2188179895Sdelphij 2189228325Syongari /* Check for descriptor overruns. */ 2190228325Syongari if (tbd->tbd_used + nsegs > ET_TX_NDESC - 1) { 2191228325Syongari bus_dmamap_unload(sc->sc_tx_tag, map); 2192228325Syongari return (ENOBUFS); 2193179895Sdelphij } 2194228325Syongari bus_dmamap_sync(sc->sc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2195179895Sdelphij 2196179895Sdelphij last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 2197228325Syongari sc->sc_tx += nsegs; 2198179895Sdelphij if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 2199179895Sdelphij sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 2200179895Sdelphij last_td_ctrl2 |= ET_TDCTRL2_INTR; 2201179895Sdelphij } 2202179895Sdelphij 2203228325Syongari m = *m0; 2204199611Syongari csum_flags = 0; 2205199611Syongari if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) { 2206199611Syongari if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2207199611Syongari csum_flags |= ET_TDCTRL2_CSUM_IP; 2208199611Syongari if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2209199611Syongari csum_flags |= ET_TDCTRL2_CSUM_UDP; 2210199611Syongari else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2211199611Syongari csum_flags |= ET_TDCTRL2_CSUM_TCP; 2212199611Syongari } 2213179895Sdelphij last_idx = -1; 2214228325Syongari for (i = 0; i < nsegs; ++i) { 2215179895Sdelphij idx = (first_idx + i) % ET_TX_NDESC; 2216179895Sdelphij td = &tx_ring->tr_desc[idx]; 2217199609Syongari td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr)); 2218199609Syongari td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr)); 2219199609Syongari td->td_ctrl1 = htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK); 2220228325Syongari if (i == nsegs - 1) { 2221228325Syongari /* Last frag */ 2222199611Syongari td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags); 2223179895Sdelphij last_idx = idx; 2224199611Syongari } else 2225199611Syongari td->td_ctrl2 = htole32(csum_flags); 2226179895Sdelphij 2227179895Sdelphij MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2228179895Sdelphij if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 2229179895Sdelphij tx_ring->tr_ready_index = 0; 2230179895Sdelphij tx_ring->tr_ready_wrap ^= 1; 2231179895Sdelphij } 2232179895Sdelphij } 2233179895Sdelphij td = &tx_ring->tr_desc[first_idx]; 2234228325Syongari /* First frag */ 2235228325Syongari td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG); 2236179895Sdelphij 2237179895Sdelphij MPASS(last_idx >= 0); 2238179895Sdelphij tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 2239179895Sdelphij tbd->tbd_buf[last_idx].tb_dmap = map; 2240179895Sdelphij tbd->tbd_buf[last_idx].tb_mbuf = m; 2241179895Sdelphij 2242228325Syongari tbd->tbd_used += nsegs; 2243179895Sdelphij MPASS(tbd->tbd_used <= ET_TX_NDESC); 2244179895Sdelphij 2245228325Syongari return (0); 2246179895Sdelphij} 2247179895Sdelphij 2248179895Sdelphijstatic void 2249179895Sdelphijet_txeof(struct et_softc *sc) 2250179895Sdelphij{ 2251179895Sdelphij struct et_txdesc_ring *tx_ring; 2252179895Sdelphij struct et_txbuf_data *tbd; 2253228325Syongari struct et_txbuf *tb; 2254228325Syongari struct ifnet *ifp; 2255179895Sdelphij uint32_t tx_done; 2256179895Sdelphij int end, wrap; 2257179895Sdelphij 2258179895Sdelphij ET_LOCK_ASSERT(sc); 2259228325Syongari 2260179895Sdelphij ifp = sc->ifp; 2261179895Sdelphij tx_ring = &sc->sc_tx_ring; 2262179895Sdelphij tbd = &sc->sc_tx_data; 2263179895Sdelphij 2264179895Sdelphij if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2265179895Sdelphij return; 2266179895Sdelphij 2267179895Sdelphij if (tbd->tbd_used == 0) 2268179895Sdelphij return; 2269179895Sdelphij 2270228325Syongari bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2271228325Syongari BUS_DMASYNC_POSTWRITE); 2272228325Syongari 2273179895Sdelphij tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 2274199548Syongari end = tx_done & ET_TX_DONE_POS_INDEX_MASK; 2275179895Sdelphij wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 2276179895Sdelphij 2277179895Sdelphij while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 2278179895Sdelphij MPASS(tbd->tbd_start_index < ET_TX_NDESC); 2279179895Sdelphij tb = &tbd->tbd_buf[tbd->tbd_start_index]; 2280179895Sdelphij if (tb->tb_mbuf != NULL) { 2281228325Syongari bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 2282228325Syongari BUS_DMASYNC_POSTWRITE); 2283228325Syongari bus_dmamap_unload(sc->sc_tx_tag, tb->tb_dmap); 2284179895Sdelphij m_freem(tb->tb_mbuf); 2285179895Sdelphij tb->tb_mbuf = NULL; 2286179895Sdelphij } 2287179895Sdelphij 2288179895Sdelphij if (++tbd->tbd_start_index == ET_TX_NDESC) { 2289179895Sdelphij tbd->tbd_start_index = 0; 2290179895Sdelphij tbd->tbd_start_wrap ^= 1; 2291179895Sdelphij } 2292179895Sdelphij 2293179895Sdelphij MPASS(tbd->tbd_used > 0); 2294179895Sdelphij tbd->tbd_used--; 2295179895Sdelphij } 2296179895Sdelphij 2297179895Sdelphij if (tbd->tbd_used == 0) 2298179895Sdelphij sc->watchdog_timer = 0; 2299228325Syongari if (tbd->tbd_used + ET_NSEG_SPARE < ET_TX_NDESC) 2300179895Sdelphij ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2301179895Sdelphij} 2302228331Syongari 2303179895Sdelphijstatic void 2304179895Sdelphijet_tick(void *xsc) 2305179895Sdelphij{ 2306229940Syongari struct et_softc *sc; 2307179895Sdelphij struct ifnet *ifp; 2308179895Sdelphij struct mii_data *mii; 2309179895Sdelphij 2310229940Syongari sc = xsc; 2311179895Sdelphij ET_LOCK_ASSERT(sc); 2312179895Sdelphij ifp = sc->ifp; 2313179895Sdelphij mii = device_get_softc(sc->sc_miibus); 2314179895Sdelphij 2315179895Sdelphij mii_tick(mii); 2316228332Syongari et_stats_update(sc); 2317228325Syongari if (et_watchdog(sc) == EJUSTRETURN) 2318228325Syongari return; 2319179895Sdelphij callout_reset(&sc->sc_tick, hz, et_tick, sc); 2320179895Sdelphij} 2321179895Sdelphij 2322179895Sdelphijstatic int 2323228325Syongariet_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx) 2324179895Sdelphij{ 2325228325Syongari struct et_softc *sc; 2326228325Syongari struct et_rxdesc *desc; 2327228325Syongari struct et_rxbuf *rb; 2328228325Syongari struct mbuf *m; 2329228325Syongari bus_dma_segment_t segs[1]; 2330228325Syongari bus_dmamap_t dmap; 2331228325Syongari int nsegs; 2332228325Syongari 2333228325Syongari MPASS(buf_idx < ET_RX_NDESC); 2334243857Sglebius m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2335228325Syongari if (m == NULL) 2336228325Syongari return (ENOBUFS); 2337228325Syongari m->m_len = m->m_pkthdr.len = MCLBYTES; 2338228325Syongari m_adj(m, ETHER_ALIGN); 2339228325Syongari 2340228325Syongari sc = rbd->rbd_softc; 2341228325Syongari rb = &rbd->rbd_buf[buf_idx]; 2342228325Syongari 2343228325Syongari if (bus_dmamap_load_mbuf_sg(sc->sc_rx_tag, sc->sc_rx_sparemap, m, 2344228325Syongari segs, &nsegs, 0) != 0) { 2345228325Syongari m_freem(m); 2346228325Syongari return (ENOBUFS); 2347228325Syongari } 2348228325Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2349228325Syongari 2350228325Syongari if (rb->rb_mbuf != NULL) { 2351228325Syongari bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, 2352228325Syongari BUS_DMASYNC_POSTREAD); 2353228325Syongari bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 2354228325Syongari } 2355228325Syongari dmap = rb->rb_dmap; 2356228325Syongari rb->rb_dmap = sc->sc_rx_sparemap; 2357228325Syongari sc->sc_rx_sparemap = dmap; 2358228325Syongari bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2359228325Syongari 2360228325Syongari rb->rb_mbuf = m; 2361228325Syongari desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2362228325Syongari desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2363228325Syongari desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2364228325Syongari desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2365228325Syongari bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2366228325Syongari BUS_DMASYNC_PREWRITE); 2367228325Syongari return (0); 2368179895Sdelphij} 2369179895Sdelphij 2370228325Syongaristatic void 2371228325Syongariet_rxbuf_discard(struct et_rxbuf_data *rbd, int buf_idx) 2372179895Sdelphij{ 2373228325Syongari struct et_rxdesc *desc; 2374228325Syongari 2375228325Syongari desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2376228325Syongari desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2377228325Syongari bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2378228325Syongari BUS_DMASYNC_PREWRITE); 2379179895Sdelphij} 2380179895Sdelphij 2381179895Sdelphijstatic int 2382228325Syongariet_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx) 2383179895Sdelphij{ 2384228325Syongari struct et_softc *sc; 2385228325Syongari struct et_rxdesc *desc; 2386179895Sdelphij struct et_rxbuf *rb; 2387179895Sdelphij struct mbuf *m; 2388228325Syongari bus_dma_segment_t segs[1]; 2389179895Sdelphij bus_dmamap_t dmap; 2390228325Syongari int nsegs; 2391179895Sdelphij 2392179895Sdelphij MPASS(buf_idx < ET_RX_NDESC); 2393243857Sglebius MGETHDR(m, M_NOWAIT, MT_DATA); 2394228325Syongari if (m == NULL) 2395228325Syongari return (ENOBUFS); 2396228325Syongari m->m_len = m->m_pkthdr.len = MHLEN; 2397228325Syongari m_adj(m, ETHER_ALIGN); 2398228325Syongari 2399228325Syongari sc = rbd->rbd_softc; 2400179895Sdelphij rb = &rbd->rbd_buf[buf_idx]; 2401179895Sdelphij 2402228325Syongari if (bus_dmamap_load_mbuf_sg(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap, 2403228325Syongari m, segs, &nsegs, 0) != 0) { 2404179895Sdelphij m_freem(m); 2405228325Syongari return (ENOBUFS); 2406179895Sdelphij } 2407228325Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2408179895Sdelphij 2409228325Syongari if (rb->rb_mbuf != NULL) { 2410228325Syongari bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, 2411228325Syongari BUS_DMASYNC_POSTREAD); 2412228325Syongari bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 2413179895Sdelphij } 2414179895Sdelphij dmap = rb->rb_dmap; 2415228325Syongari rb->rb_dmap = sc->sc_rx_mini_sparemap; 2416228325Syongari sc->sc_rx_mini_sparemap = dmap; 2417228325Syongari bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2418179895Sdelphij 2419228325Syongari rb->rb_mbuf = m; 2420228325Syongari desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2421228325Syongari desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2422228325Syongari desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2423228325Syongari desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2424228325Syongari bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2425228325Syongari BUS_DMASYNC_PREWRITE); 2426228325Syongari return (0); 2427179895Sdelphij} 2428179895Sdelphij 2429228332Syongari#define ET_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2430228332Syongari SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2431228332Syongari#define ET_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2432228332Syongari SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2433228332Syongari 2434179895Sdelphij/* 2435179895Sdelphij * Create sysctl tree 2436179895Sdelphij */ 2437179895Sdelphijstatic void 2438179895Sdelphijet_add_sysctls(struct et_softc * sc) 2439179895Sdelphij{ 2440179895Sdelphij struct sysctl_ctx_list *ctx; 2441228332Syongari struct sysctl_oid_list *children, *parent; 2442228332Syongari struct sysctl_oid *tree; 2443228332Syongari struct et_hw_stats *stats; 2444179895Sdelphij 2445179895Sdelphij ctx = device_get_sysctl_ctx(sc->dev); 2446179895Sdelphij children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2447179895Sdelphij 2448179895Sdelphij SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts", 2449179895Sdelphij CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_npkts, "I", 2450179895Sdelphij "RX IM, # packets per RX interrupt"); 2451179895Sdelphij SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay", 2452179895Sdelphij CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_delay, "I", 2453179895Sdelphij "RX IM, RX interrupt delay (x10 usec)"); 2454179895Sdelphij SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs", 2455179895Sdelphij CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 2456179895Sdelphij "TX IM, # segments per TX interrupt"); 2457179895Sdelphij SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer", 2458179895Sdelphij CTLFLAG_RW, &sc->sc_timer, 0, "TX timer"); 2459228332Syongari 2460228332Syongari tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 2461228332Syongari NULL, "ET statistics"); 2462228332Syongari parent = SYSCTL_CHILDREN(tree); 2463228332Syongari 2464228332Syongari /* TX/RX statistics. */ 2465228332Syongari stats = &sc->sc_stats; 2466228332Syongari ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_64", &stats->pkts_64, 2467228332Syongari "0 to 64 bytes frames"); 2468228332Syongari ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_65_127", &stats->pkts_65, 2469228332Syongari "65 to 127 bytes frames"); 2470228332Syongari ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_128_255", &stats->pkts_128, 2471228332Syongari "128 to 255 bytes frames"); 2472228332Syongari ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_256_511", &stats->pkts_256, 2473228332Syongari "256 to 511 bytes frames"); 2474228332Syongari ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_512_1023", &stats->pkts_512, 2475228332Syongari "512 to 1023 bytes frames"); 2476228332Syongari ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1024_1518", &stats->pkts_1024, 2477228332Syongari "1024 to 1518 bytes frames"); 2478228332Syongari ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1519_1522", &stats->pkts_1519, 2479228332Syongari "1519 to 1522 bytes frames"); 2480228332Syongari 2481228332Syongari /* RX statistics. */ 2482228332Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 2483228332Syongari NULL, "RX MAC statistics"); 2484228332Syongari children = SYSCTL_CHILDREN(tree); 2485228332Syongari ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2486228332Syongari &stats->rx_bytes, "Good bytes"); 2487228332Syongari ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2488228332Syongari &stats->rx_frames, "Good frames"); 2489228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2490228332Syongari &stats->rx_crcerrs, "CRC errors"); 2491228332Syongari ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2492228332Syongari &stats->rx_mcast, "Multicast frames"); 2493228332Syongari ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2494228332Syongari &stats->rx_bcast, "Broadcast frames"); 2495228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2496228332Syongari &stats->rx_control, "Control frames"); 2497228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2498228332Syongari &stats->rx_pause, "Pause frames"); 2499228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "unknown_control", 2500228332Syongari &stats->rx_unknown_control, "Unknown control frames"); 2501228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "align_errs", 2502228332Syongari &stats->rx_alignerrs, "Alignment errors"); 2503228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "len_errs", 2504228332Syongari &stats->rx_lenerrs, "Frames with length mismatched"); 2505228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "code_errs", 2506228332Syongari &stats->rx_codeerrs, "Frames with code error"); 2507228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "cs_errs", 2508228332Syongari &stats->rx_cserrs, "Frames with carrier sense error"); 2509228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "runts", 2510228332Syongari &stats->rx_runts, "Too short frames"); 2511228332Syongari ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2512228332Syongari &stats->rx_oversize, "Oversized frames"); 2513228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2514228332Syongari &stats->rx_fragments, "Fragmented frames"); 2515228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2516228332Syongari &stats->rx_jabbers, "Frames with jabber error"); 2517228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2518228332Syongari &stats->rx_drop, "Dropped frames"); 2519228332Syongari 2520228332Syongari /* TX statistics. */ 2521228332Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 2522228332Syongari NULL, "TX MAC statistics"); 2523228332Syongari children = SYSCTL_CHILDREN(tree); 2524228332Syongari ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2525228332Syongari &stats->tx_bytes, "Good bytes"); 2526228332Syongari ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2527228332Syongari &stats->tx_frames, "Good frames"); 2528228332Syongari ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2529228332Syongari &stats->tx_mcast, "Multicast frames"); 2530228332Syongari ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2531228332Syongari &stats->tx_bcast, "Broadcast frames"); 2532228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2533228332Syongari &stats->tx_pause, "Pause frames"); 2534228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "deferred", 2535228332Syongari &stats->tx_deferred, "Deferred frames"); 2536228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "excess_deferred", 2537228332Syongari &stats->tx_excess_deferred, "Excessively deferred frames"); 2538228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "single_colls", 2539228332Syongari &stats->tx_single_colls, "Single collisions"); 2540228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "multi_colls", 2541228332Syongari &stats->tx_multi_colls, "Multiple collisions"); 2542228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "late_colls", 2543228332Syongari &stats->tx_late_colls, "Late collisions"); 2544228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "excess_colls", 2545228332Syongari &stats->tx_excess_colls, "Excess collisions"); 2546228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "total_colls", 2547228332Syongari &stats->tx_total_colls, "Total collisions"); 2548228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "pause_honored", 2549228332Syongari &stats->tx_pause_honored, "Honored pause frames"); 2550228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2551228332Syongari &stats->tx_drop, "Dropped frames"); 2552228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2553228332Syongari &stats->tx_jabbers, "Frames with jabber errors"); 2554228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2555228332Syongari &stats->tx_crcerrs, "Frames with CRC errors"); 2556228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2557228332Syongari &stats->tx_control, "Control frames"); 2558228332Syongari ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2559228332Syongari &stats->tx_oversize, "Oversized frames"); 2560228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "undersize", 2561228332Syongari &stats->tx_undersize, "Undersized frames"); 2562228332Syongari ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2563228332Syongari &stats->tx_fragments, "Fragmented frames"); 2564179895Sdelphij} 2565179895Sdelphij 2566228332Syongari#undef ET_SYSCTL_STAT_ADD32 2567228332Syongari#undef ET_SYSCTL_STAT_ADD64 2568228332Syongari 2569179895Sdelphijstatic int 2570179895Sdelphijet_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 2571179895Sdelphij{ 2572229940Syongari struct et_softc *sc; 2573229940Syongari struct ifnet *ifp; 2574229940Syongari int error, v; 2575179895Sdelphij 2576229940Syongari sc = arg1; 2577229940Syongari ifp = sc->ifp; 2578179895Sdelphij v = sc->sc_rx_intr_npkts; 2579179895Sdelphij error = sysctl_handle_int(oidp, &v, 0, req); 2580179895Sdelphij if (error || req->newptr == NULL) 2581179895Sdelphij goto back; 2582179895Sdelphij if (v <= 0) { 2583179895Sdelphij error = EINVAL; 2584179895Sdelphij goto back; 2585179895Sdelphij } 2586179895Sdelphij 2587179895Sdelphij if (sc->sc_rx_intr_npkts != v) { 2588179895Sdelphij if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2589179895Sdelphij CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 2590179895Sdelphij sc->sc_rx_intr_npkts = v; 2591179895Sdelphij } 2592179895Sdelphijback: 2593199556Syongari return (error); 2594179895Sdelphij} 2595179895Sdelphij 2596179895Sdelphijstatic int 2597179895Sdelphijet_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 2598179895Sdelphij{ 2599229940Syongari struct et_softc *sc; 2600229940Syongari struct ifnet *ifp; 2601229940Syongari int error, v; 2602179895Sdelphij 2603229940Syongari sc = arg1; 2604229940Syongari ifp = sc->ifp; 2605179895Sdelphij v = sc->sc_rx_intr_delay; 2606179895Sdelphij error = sysctl_handle_int(oidp, &v, 0, req); 2607179895Sdelphij if (error || req->newptr == NULL) 2608179895Sdelphij goto back; 2609179895Sdelphij if (v <= 0) { 2610179895Sdelphij error = EINVAL; 2611179895Sdelphij goto back; 2612179895Sdelphij } 2613179895Sdelphij 2614179895Sdelphij if (sc->sc_rx_intr_delay != v) { 2615179895Sdelphij if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2616179895Sdelphij CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 2617179895Sdelphij sc->sc_rx_intr_delay = v; 2618179895Sdelphij } 2619179895Sdelphijback: 2620199556Syongari return (error); 2621179895Sdelphij} 2622179895Sdelphij 2623228332Syongaristatic void 2624228332Syongariet_stats_update(struct et_softc *sc) 2625228332Syongari{ 2626228332Syongari struct ifnet *ifp; 2627228332Syongari struct et_hw_stats *stats; 2628228332Syongari 2629228332Syongari stats = &sc->sc_stats; 2630228332Syongari stats->pkts_64 += CSR_READ_4(sc, ET_STAT_PKTS_64); 2631228332Syongari stats->pkts_65 += CSR_READ_4(sc, ET_STAT_PKTS_65_127); 2632228332Syongari stats->pkts_128 += CSR_READ_4(sc, ET_STAT_PKTS_128_255); 2633228332Syongari stats->pkts_256 += CSR_READ_4(sc, ET_STAT_PKTS_256_511); 2634228332Syongari stats->pkts_512 += CSR_READ_4(sc, ET_STAT_PKTS_512_1023); 2635228332Syongari stats->pkts_1024 += CSR_READ_4(sc, ET_STAT_PKTS_1024_1518); 2636228332Syongari stats->pkts_1519 += CSR_READ_4(sc, ET_STAT_PKTS_1519_1522); 2637228332Syongari 2638228332Syongari stats->rx_bytes += CSR_READ_4(sc, ET_STAT_RX_BYTES); 2639228332Syongari stats->rx_frames += CSR_READ_4(sc, ET_STAT_RX_FRAMES); 2640228332Syongari stats->rx_crcerrs += CSR_READ_4(sc, ET_STAT_RX_CRC_ERR); 2641228332Syongari stats->rx_mcast += CSR_READ_4(sc, ET_STAT_RX_MCAST); 2642228332Syongari stats->rx_bcast += CSR_READ_4(sc, ET_STAT_RX_BCAST); 2643228332Syongari stats->rx_control += CSR_READ_4(sc, ET_STAT_RX_CTL); 2644228332Syongari stats->rx_pause += CSR_READ_4(sc, ET_STAT_RX_PAUSE); 2645228332Syongari stats->rx_unknown_control += CSR_READ_4(sc, ET_STAT_RX_UNKNOWN_CTL); 2646228332Syongari stats->rx_alignerrs += CSR_READ_4(sc, ET_STAT_RX_ALIGN_ERR); 2647228332Syongari stats->rx_lenerrs += CSR_READ_4(sc, ET_STAT_RX_LEN_ERR); 2648228332Syongari stats->rx_codeerrs += CSR_READ_4(sc, ET_STAT_RX_CODE_ERR); 2649228332Syongari stats->rx_cserrs += CSR_READ_4(sc, ET_STAT_RX_CS_ERR); 2650228332Syongari stats->rx_runts += CSR_READ_4(sc, ET_STAT_RX_RUNT); 2651228332Syongari stats->rx_oversize += CSR_READ_4(sc, ET_STAT_RX_OVERSIZE); 2652228332Syongari stats->rx_fragments += CSR_READ_4(sc, ET_STAT_RX_FRAG); 2653228332Syongari stats->rx_jabbers += CSR_READ_4(sc, ET_STAT_RX_JABBER); 2654228332Syongari stats->rx_drop += CSR_READ_4(sc, ET_STAT_RX_DROP); 2655228332Syongari 2656228332Syongari stats->tx_bytes += CSR_READ_4(sc, ET_STAT_TX_BYTES); 2657228332Syongari stats->tx_frames += CSR_READ_4(sc, ET_STAT_TX_FRAMES); 2658228332Syongari stats->tx_mcast += CSR_READ_4(sc, ET_STAT_TX_MCAST); 2659228332Syongari stats->tx_bcast += CSR_READ_4(sc, ET_STAT_TX_BCAST); 2660228332Syongari stats->tx_pause += CSR_READ_4(sc, ET_STAT_TX_PAUSE); 2661228332Syongari stats->tx_deferred += CSR_READ_4(sc, ET_STAT_TX_DEFER); 2662228332Syongari stats->tx_excess_deferred += CSR_READ_4(sc, ET_STAT_TX_EXCESS_DEFER); 2663228332Syongari stats->tx_single_colls += CSR_READ_4(sc, ET_STAT_TX_SINGLE_COL); 2664228332Syongari stats->tx_multi_colls += CSR_READ_4(sc, ET_STAT_TX_MULTI_COL); 2665228332Syongari stats->tx_late_colls += CSR_READ_4(sc, ET_STAT_TX_LATE_COL); 2666228332Syongari stats->tx_excess_colls += CSR_READ_4(sc, ET_STAT_TX_EXCESS_COL); 2667228332Syongari stats->tx_total_colls += CSR_READ_4(sc, ET_STAT_TX_TOTAL_COL); 2668228332Syongari stats->tx_pause_honored += CSR_READ_4(sc, ET_STAT_TX_PAUSE_HONOR); 2669228332Syongari stats->tx_drop += CSR_READ_4(sc, ET_STAT_TX_DROP); 2670228332Syongari stats->tx_jabbers += CSR_READ_4(sc, ET_STAT_TX_JABBER); 2671228332Syongari stats->tx_crcerrs += CSR_READ_4(sc, ET_STAT_TX_CRC_ERR); 2672228332Syongari stats->tx_control += CSR_READ_4(sc, ET_STAT_TX_CTL); 2673228332Syongari stats->tx_oversize += CSR_READ_4(sc, ET_STAT_TX_OVERSIZE); 2674228332Syongari stats->tx_undersize += CSR_READ_4(sc, ET_STAT_TX_UNDERSIZE); 2675228332Syongari stats->tx_fragments += CSR_READ_4(sc, ET_STAT_TX_FRAG); 2676228332Syongari 2677228332Syongari /* Update ifnet counters. */ 2678228332Syongari ifp = sc->ifp; 2679228332Syongari ifp->if_opackets = (u_long)stats->tx_frames; 2680228332Syongari ifp->if_collisions = stats->tx_total_colls; 2681228332Syongari ifp->if_oerrors = stats->tx_drop + stats->tx_jabbers + 2682228332Syongari stats->tx_crcerrs + stats->tx_excess_deferred + 2683228332Syongari stats->tx_late_colls; 2684228332Syongari ifp->if_ipackets = (u_long)stats->rx_frames; 2685228332Syongari ifp->if_ierrors = stats->rx_crcerrs + stats->rx_alignerrs + 2686228332Syongari stats->rx_lenerrs + stats->rx_codeerrs + stats->rx_cserrs + 2687228332Syongari stats->rx_runts + stats->rx_jabbers + stats->rx_drop; 2688228332Syongari} 2689228332Syongari 2690228292Syongaristatic int 2691228292Syongariet_suspend(device_t dev) 2692228292Syongari{ 2693228292Syongari struct et_softc *sc; 2694228336Syongari uint32_t pmcfg; 2695228292Syongari 2696228292Syongari sc = device_get_softc(dev); 2697228292Syongari ET_LOCK(sc); 2698228292Syongari if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2699228292Syongari et_stop(sc); 2700228336Syongari /* Diable all clocks and put PHY into COMA. */ 2701228336Syongari pmcfg = CSR_READ_4(sc, ET_PM); 2702228336Syongari pmcfg &= ~(EM_PM_GIGEPHY_ENB | ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | 2703228336Syongari ET_PM_RXCLK_GATE); 2704228336Syongari pmcfg |= ET_PM_PHY_SW_COMA; 2705228336Syongari CSR_WRITE_4(sc, ET_PM, pmcfg); 2706228292Syongari ET_UNLOCK(sc); 2707228292Syongari return (0); 2708228292Syongari} 2709228292Syongari 2710228292Syongaristatic int 2711228292Syongariet_resume(device_t dev) 2712228292Syongari{ 2713228292Syongari struct et_softc *sc; 2714228336Syongari uint32_t pmcfg; 2715228292Syongari 2716228292Syongari sc = device_get_softc(dev); 2717228292Syongari ET_LOCK(sc); 2718228336Syongari /* Take PHY out of COMA and enable clocks. */ 2719228336Syongari pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 2720228336Syongari if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 2721228336Syongari pmcfg |= EM_PM_GIGEPHY_ENB; 2722228336Syongari CSR_WRITE_4(sc, ET_PM, pmcfg); 2723228292Syongari if ((sc->ifp->if_flags & IFF_UP) != 0) 2724228292Syongari et_init_locked(sc); 2725228292Syongari ET_UNLOCK(sc); 2726228292Syongari return (0); 2727228292Syongari} 2728