if_edreg.h revision 8876
1/* 2 * Copyright (C) 1993, David Greenman. This software may be used, modified, 3 * copied, distributed, and sold, in both source and binary form provided 4 * that the above copyright and these terms are retained. Under no 5 * circumstances is the author responsible for the proper functioning 6 * of this software, nor does the author assume any responsibility 7 * for damages incurred with its use. 8 * 9 * $Id: if_edreg.h,v 1.17 1995/01/23 19:06:08 davidg Exp $ 10 */ 11/* 12 * National Semiconductor DS8390 NIC register definitions 13 * 14 * 15 * Modification history 16 * 17 * Revision 2.2 1993/11/29 16:33:39 davidg 18 * From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk> 19 * Add support for the 8013W board type 20 * 21 * Revision 2.1 1993/11/22 10:52:33 davidg 22 * patch to add support for SMC8216 (Elite-Ultra) boards 23 * from Glen H. Lowe 24 * 25 * Revision 2.0 93/09/29 00:37:15 davidg 26 * changed double buffering flag to multi buffering 27 * made changes/additions for 3c503 multi-buffering 28 * ...companion to Rev. 2.0 of 'ed' driver. 29 * 30 * Revision 1.1 93/06/23 03:01:07 davidg 31 * Initial revision 32 * 33 */ 34 35/* 36 * Page 0 register offsets 37 */ 38#define ED_P0_CR 0x00 /* Command Register */ 39 40#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 41#define ED_P0_PSTART 0x01 /* Page Start register (write) */ 42 43#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 44#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ 45 46#define ED_P0_BNRY 0x03 /* Boundary Pointer */ 47 48#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ 49#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ 50 51#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 52#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 53 54#define ED_P0_FIFO 0x06 /* FIFO register (read) */ 55#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 56 57#define ED_P0_ISR 0x07 /* Interrupt Status Register */ 58 59#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 60#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 61 62#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 63#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 64 65#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 66 67#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 68 69#define ED_P0_RSR 0x0c /* Receive Status (read) */ 70#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 71 72#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 73#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 74 75#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ 76#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ 77 78#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ 79#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 80 81/* 82 * Page 1 register offsets 83 */ 84#define ED_P1_CR 0x00 /* Command Register */ 85#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ 86#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ 87#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ 88#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ 89#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ 90#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ 91#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ 92#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ 93#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ 94#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ 95#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ 96#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ 97#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ 98#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ 99#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ 100 101/* 102 * Page 2 register offsets 103 */ 104#define ED_P2_CR 0x00 /* Command Register */ 105#define ED_P2_PSTART 0x01 /* Page Start (read) */ 106#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 107#define ED_P2_PSTOP 0x02 /* Page Stop (read) */ 108#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 109#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 110#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ 111#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ 112#define ED_P2_ACU 0x06 /* Address Counter Upper */ 113#define ED_P2_ACL 0x07 /* Address Counter Lower */ 114#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ 115#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 116#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ 117#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 118 119/* 120 * Command Register (CR) definitions 121 */ 122 123/* 124 * STP: SToP. Software reset command. Takes the controller offline. No 125 * packets will be received or transmitted. Any reception or 126 * transmission in progress will continue to completion before 127 * entering reset state. To exit this state, the STP bit must 128 * reset and the STA bit must be set. The software reset has 129 * executed only when indicated by the RST bit in the ISR being 130 * set. 131 */ 132#define ED_CR_STP 0x01 133 134/* 135 * STA: STArt. This bit is used to activate the NIC after either power-up, 136 * or when the NIC has been put in reset mode by software command 137 * or error. 138 */ 139#define ED_CR_STA 0x02 140 141/* 142 * TXP: Transmit Packet. This bit must be set to indicate transmission of 143 * a packet. TXP is internally reset either after the transmission is 144 * completed or aborted. This bit should be set only after the Transmit 145 * Byte Count and Transmit Page Start register have been programmed. 146 */ 147#define ED_CR_TXP 0x04 148 149/* 150 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 151 * of the remote DMA channel. RD2 can be set to abort any remote DMA 152 * command in progress. The Remote Byte Count registers should be cleared 153 * when a remote DMA has been aborted. The Remote Start Addresses are not 154 * restored to the starting address if the remote DMA is aborted. 155 * 156 * RD2 RD1 RD0 function 157 * 0 0 0 not allowed 158 * 0 0 1 remote read 159 * 0 1 0 remote write 160 * 0 1 1 send packet 161 * 1 X X abort 162 */ 163#define ED_CR_RD0 0x08 164#define ED_CR_RD1 0x10 165#define ED_CR_RD2 0x20 166 167/* 168 * PS0, PS1: Page Select. The two bits select which register set or 'page' to 169 * access. 170 * 171 * PS1 PS0 page 172 * 0 0 0 173 * 0 1 1 174 * 1 0 2 175 * 1 1 reserved 176 */ 177#define ED_CR_PS0 0x40 178#define ED_CR_PS1 0x80 179/* bit encoded aliases */ 180#define ED_CR_PAGE_0 0x00 /* (for consistency) */ 181#define ED_CR_PAGE_1 0x40 182#define ED_CR_PAGE_2 0x80 183 184/* 185 * Interrupt Status Register (ISR) definitions 186 */ 187 188/* 189 * PRX: Packet Received. Indicates packet received with no errors. 190 */ 191#define ED_ISR_PRX 0x01 192 193/* 194 * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 195 */ 196#define ED_ISR_PTX 0x02 197 198/* 199 * RXE: Receive Error. Indicates that a packet was received with one or more 200 * the following errors: CRC error, frame alignment error, FIFO overrun, 201 * missed packet. 202 */ 203#define ED_ISR_RXE 0x04 204 205/* 206 * TXE: Transmission Error. Indicates that an attempt to transmit a packet 207 * resulted in one or more of the following errors: excessive 208 * collisions, FIFO underrun. 209 */ 210#define ED_ISR_TXE 0x08 211 212/* 213 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 214 * would exceed (has exceeded?) the boundry pointer, resulting in data 215 * that was previously received and not yet read from the buffer to be 216 * overwritten. 217 */ 218#define ED_ISR_OVW 0x10 219 220/* 221 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley 222 * Counters has been set. 223 */ 224#define ED_ISR_CNT 0x20 225 226/* 227 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed. 228 */ 229#define ED_ISR_RDC 0x40 230 231/* 232 * RST: Reset status. Set when the NIC enters the reset state and cleared when a 233 * Start Command is issued to the CR. This bit is also set when a receive 234 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 235 * packets have been removed from the ring. This is a read-only bit. 236 */ 237#define ED_ISR_RST 0x80 238 239/* 240 * Interrupt Mask Register (IMR) definitions 241 */ 242 243/* 244 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause 245 * an interrupt. 246 */ 247#define ED_IMR_PRXE 0x01 248 249/* 250 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when 251 * a packet transmission completes. 252 */ 253#define ED_IMR_PTXE 0x02 254 255/* 256 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a 257 * packet is received with an error. 258 */ 259#define ED_IMR_RXEE 0x04 260 261/* 262 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever 263 * a transmission results in an error. 264 */ 265#define ED_IMR_TXEE 0x08 266 267/* 268 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever 269 * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded. 270 */ 271#define ED_IMR_OVWE 0x10 272 273/* 274 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever 275 * the MSB of one or more of the Network Statistics counters has been set. 276 */ 277#define ED_IMR_CNTE 0x20 278 279/* 280 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated 281 * when a remote DMA transfer has completed. 282 */ 283#define ED_IMR_RDCE 0x40 284 285/* 286 * bit 7 is unused/reserved 287 */ 288 289/* 290 * Data Configuration Register (DCR) definitions 291 */ 292 293/* 294 * WTS: Word Transfer Select. WTS establishes byte or word transfers for 295 * both remote and local DMA transfers 296 */ 297#define ED_DCR_WTS 0x01 298 299/* 300 * BOS: Byte Order Select. BOS sets the byte order for the host. 301 * Should be 0 for 80x86, and 1 for 68000 series processors 302 */ 303#define ED_DCR_BOS 0x02 304 305/* 306 * LAS: Long Address Select. When LAS is 1, the contents of the remote 307 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31 308 */ 309#define ED_DCR_LAS 0x04 310 311/* 312 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 313 * of the TCR must also be programmed for loopback operation. 314 * When 1, normal operation is selected. 315 */ 316#define ED_DCR_LS 0x08 317 318/* 319 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 320 * under program control. When 1, remote DMA is automatically initiated 321 * and the boundry pointer is automatically updated 322 */ 323#define ED_DCR_AR 0x10 324 325/* 326 * FT0, FT1: Fifo Threshold select. 327 * FT1 FT0 Word-width Byte-width 328 * 0 0 1 word 2 bytes 329 * 0 1 2 words 4 bytes 330 * 1 0 4 words 8 bytes 331 * 1 1 8 words 12 bytes 332 * 333 * During transmission, the FIFO threshold indicates the number of bytes 334 * or words that the FIFO has filled from the local DMA before BREQ is 335 * asserted. The transmission threshold is 16 bytes minus the receiver 336 * threshold. 337 */ 338#define ED_DCR_FT0 0x20 339#define ED_DCR_FT1 0x40 340 341/* 342 * bit 7 (0x80) is unused/reserved 343 */ 344 345/* 346 * Transmit Configuration Register (TCR) definitions 347 */ 348 349/* 350 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 351 * is not appended by the transmitter. 352 */ 353#define ED_TCR_CRC 0x01 354 355/* 356 * LB0, LB1: Loopback control. These two bits set the type of loopback that is 357 * to be performed. 358 * 359 * LB1 LB0 mode 360 * 0 0 0 - normal operation (DCR_LS = 0) 361 * 0 1 1 - internal loopback (DCR_LS = 0) 362 * 1 0 2 - external loopback (DCR_LS = 1) 363 * 1 1 3 - external loopback (DCR_LS = 0) 364 */ 365#define ED_TCR_LB0 0x02 366#define ED_TCR_LB1 0x04 367 368/* 369 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 370 * another station to disable the NIC's transmitter by transmitting to 371 * a multicast address hashing to bit 62. Reception of a multicast address 372 * hashing to bit 63 enables the transmitter. 373 */ 374#define ED_TCR_ATD 0x08 375 376/* 377 * OFST: Collision Offset enable. This bit when set modifies the backoff 378 * algorithm to allow prioritization of nodes. 379 */ 380#define ED_TCR_OFST 0x10 381 382/* 383 * bits 5, 6, and 7 are unused/reserved 384 */ 385 386/* 387 * Transmit Status Register (TSR) definitions 388 */ 389 390/* 391 * PTX: Packet Transmitted. Indicates successful transmission of packet. 392 */ 393#define ED_TSR_PTX 0x01 394 395/* 396 * bit 1 (0x02) is unused/reserved 397 */ 398 399/* 400 * COL: Transmit Collided. Indicates that the transmission collided at least 401 * once with another station on the network. 402 */ 403#define ED_TSR_COL 0x04 404 405/* 406 * ABT: Transmit aborted. Indicates that the transmission was aborted due to 407 * excessive collisions. 408 */ 409#define ED_TSR_ABT 0x08 410 411/* 412 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 413 * transmission of the packet. (Transmission is not aborted because 414 * of a loss of carrier) 415 */ 416#define ED_TSR_CRS 0x10 417 418/* 419 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 420 * transmission memory before the FIFO emptied. Transmission of the 421 * packet was aborted. 422 */ 423#define ED_TSR_FU 0x20 424 425/* 426 * CDH: CD Heartbeat. Indicates that the collision detection circuitry 427 * isn't working correctly during a collision heartbeat test. 428 */ 429#define ED_TSR_CDH 0x40 430 431/* 432 * OWC: Out of Window Collision: Indicates that a collision occurred after 433 * a slot time (51.2us). The transmission is rescheduled just as in 434 * normal collisions. 435 */ 436#define ED_TSR_OWC 0x80 437 438/* 439 * Receiver Configuration Register (RCR) definitions 440 */ 441 442/* 443 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 444 * packets with CRC and frame errors are not discarded. 445 */ 446#define ED_RCR_SEP 0x01 447 448/* 449 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 450 * If set to 1, packets with less than 64 byte are not discarded. 451 */ 452#define ED_RCR_AR 0x02 453 454/* 455 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 456 * accepted. 457 */ 458#define ED_RCR_AB 0x04 459 460/* 461 * AM: Accept Multicast. If set, packets sent to a multicast address are checked 462 * for a match in the hashing array. If clear, multicast packets are ignored. 463 */ 464#define ED_RCR_AM 0x08 465 466/* 467 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are 468 * accepted. If clear, a physical destination address must match this 469 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM 470 * must also be set. In addition, the multicast hashing array must be set 471 * to all 1's so that all multicast addresses are accepted. 472 */ 473#define ED_RCR_PRO 0x10 474 475/* 476 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing, 477 * but are not stored in the ring-buffer. If clear, packets are stored (normal 478 * operation). 479 */ 480#define ED_RCR_MON 0x20 481 482/* 483 * bits 6 and 7 are unused/reserved. 484 */ 485 486/* 487 * Receiver Status Register (RSR) definitions 488 */ 489 490/* 491 * PRX: Packet Received without error. 492 */ 493#define ED_RSR_PRX 0x01 494 495/* 496 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame 497 * alignment errors. 498 */ 499#define ED_RSR_CRC 0x02 500 501/* 502 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on 503 * a byte boundry and the CRC did not match at the last byte boundry. 504 */ 505#define ED_RSR_FAE 0x04 506 507/* 508 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA) 509 * causing it to overrun. Reception of the packet is aborted. 510 */ 511#define ED_RSR_FO 0x08 512 513/* 514 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in 515 * the ring-buffer because of insufficient buffer space (exceeding the 516 * boundry pointer), or because the transfer to the ring-buffer was inhibited 517 * by RCR_MON - monitor mode. 518 */ 519#define ED_RSR_MPA 0x10 520 521/* 522 * PHY: Physical address. If 0, the packet received was sent to a physical address. 523 * If 1, the packet was accepted because of a multicast/broadcast address 524 * match. 525 */ 526#define ED_RSR_PHY 0x20 527 528/* 529 * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor 530 * mode. Cleared when the receiver exits monitor mode. 531 */ 532#define ED_RSR_DIS 0x40 533 534/* 535 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs 536 * are active, and the transceiver has set the CD line as a result of the 537 * jabber. 538 */ 539#define ED_RSR_DFR 0x80 540 541/* 542 * receive ring discriptor 543 * 544 * The National Semiconductor DS8390 Network interface controller uses 545 * the following receive ring headers. The way this works is that the 546 * memory on the interface card is chopped up into 256 bytes blocks. 547 * A contiguous portion of those blocks are marked for receive packets 548 * by setting start and end block #'s in the NIC. For each packet that 549 * is put into the receive ring, one of these headers (4 bytes each) is 550 * tacked onto the front. The first byte is a copy of the receiver status 551 * register at the time the packet was received. 552 */ 553struct ed_ring { 554 u_char rsr; /* receiver status */ 555 u_char next_packet; /* pointer to next packet */ 556 u_short count; /* bytes in packet (length + 4) */ 557}; 558 559/* 560 * Common constants 561 */ 562#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 563#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 564 565/* 566 * Vendor types 567 */ 568#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ 569#define ED_VENDOR_3COM 0x01 /* 3Com */ 570#define ED_VENDOR_NOVELL 0x02 /* Novell */ 571 572/* 573 * Compile-time config flags 574 */ 575/* 576 * this sets the default for enabling/disablng the tranceiver 577 */ 578#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001 579 580/* 581 * This forces the board to be used in 8/16bit mode even if it 582 * autoconfigs differently 583 */ 584#define ED_FLAGS_FORCE_8BIT_MODE 0x0002 585#define ED_FLAGS_FORCE_16BIT_MODE 0x0004 586 587/* 588 * This disables the use of double transmit buffers. 589 */ 590#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008 591 592/* 593 * This forces all operations with the NIC memory to use Programmed 594 * I/O (i.e. not via shared memory) 595 */ 596#define ED_FLAGS_FORCE_PIO 0x0010 597 598/* 599 * Definitions for Western digital/SMC WD80x3 series ASIC 600 */ 601/* 602 * Memory Select Register (MSR) 603 */ 604#define ED_WD_MSR 0 605 606/* next three definitions for Toshiba */ 607#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */ 608#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */ 609#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits, 610 1 = 8 bits (R/W) */ 611#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ 612#define ED_WD_MSR_MENB 0x40 /* Memory enable */ 613#define ED_WD_MSR_RST 0x80 /* Reset board */ 614 615/* 616 * Interface Configuration Register (ICR) 617 */ 618#define ED_WD_ICR 1 619 620#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */ 621#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */ 622#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */ 623#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ 624#define ED_WD_ICR_RLA 0x10 /* recall LAN address */ 625#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */ 626#define ED_WD_ICR_RIO 0x40 /* recall i/o address */ 627#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */ 628#ifdef TOSH_ETHER 629#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */ 630#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K, 631 0x02 = 16K, 0x01 = 8K */ 632 /* 64K can only be used if mem address 633 above 1Mb */ 634 /* IAR holds address A23-A16 (R/W) */ 635#endif 636 637/* 638 * IO Address Register (IAR) 639 */ 640#define ED_WD_IAR 2 641 642/* 643 * EEROM Address Register 644 */ 645#define ED_WD_EAR 3 646 647/* 648 * Interrupt Request Register (IRR) 649 */ 650#define ED_WD_IRR 4 651 652#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ 653#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ 654#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ 655#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ 656#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ 657 658/* 659 * The three bits of the encoded IRQ are decoded as follows: 660 * 661 * IR2 IR1 IR0 IRQ 662 * 0 0 0 2/9 663 * 0 0 1 3 664 * 0 1 0 5 665 * 0 1 1 7 666 * 1 0 0 10 667 * 1 0 1 11 668 * 1 1 0 15 669 * 1 1 1 4 670 */ 671#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 672#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 673#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */ 674 675/* 676 * LA Address Register (LAAR) 677 */ 678#define ED_WD_LAAR 5 679 680#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ 681#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ 682#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */ 683#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */ 684 685/* i/o base offset to station address/card-ID PROM */ 686#define ED_WD_PROM 8 687 688/* 689 * 83C790 specific registers 690 */ 691/* 692 * Hardware Support Register (HWR) ('790) 693 */ 694#define ED_WD790_HWR 4 695 696#define WD_WD790_HWR_NUKE 0x10 /* hardware reset */ 697#define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */ 698#define ED_WD790_HWR_SWH 0x80 /* switch register set */ 699 700/* 701 * ICR790 Interrupt Control Register for the 83C790 702 */ 703#define ED_WD790_ICR 6 704 705#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */ 706 707/* 708 * REV/IOPA Revision / I/O Pipe register for the 83C79X 709 */ 710#define ED_WD790_REV 7 711 712#define ED_WD790 0x20 713#define ED_WD795 0x40 714 715/* 716 * 79X RAM Address Register (RAR) 717 * Enabled with SWH bit=1 in HWR register 718 */ 719#define ED_WD790_RAR 0x0b 720 721#define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */ 722#define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */ 723#define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */ 724#define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */ 725 726/* 727 * General Control Register (GCR) 728 * Enabled with SWH bit=1 in HWR register 729 */ 730#define ED_WD790_GCR 0x0d 731 732#define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */ 733#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */ 734#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */ 735#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */ 736#define ED_WD790_GCR_LIT 0x01 /* Link Integrity Test Enable */ 737/* 738 * The three bits of the encoded IRQ are decoded as follows: 739 * 740 * IR2 IR1 IR0 IRQ 741 * 0 0 0 none 742 * 0 0 1 9 743 * 0 1 0 3 744 * 0 1 1 5 745 * 1 0 0 7 746 * 1 0 1 10 747 * 1 1 0 11 748 * 1 1 1 15 749 */ 750 751/* i/o base offset to CARD ID */ 752#define ED_WD_CARD_ID ED_WD_PROM+6 753 754/* Board type codes in card ID */ 755#define ED_TYPE_WD8003S 0x02 756#define ED_TYPE_WD8003E 0x03 757#define ED_TYPE_WD8013EBT 0x05 758#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */ 759#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */ 760#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */ 761#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */ 762#define ED_TYPE_WD8003W 0x24 763#define ED_TYPE_WD8003EB 0x25 764#define ED_TYPE_WD8013W 0x26 765#define ED_TYPE_WD8013EP 0x27 766#define ED_TYPE_WD8013WC 0x28 767#define ED_TYPE_WD8013EPC 0x29 768#define ED_TYPE_SMC8216T 0x2a 769#define ED_TYPE_SMC8216C 0x2b 770#define ED_TYPE_WD8013EBP 0x2c 771 772/* Bit definitions in card ID */ 773#define ED_WD_REV_MASK 0x1f /* Revision mask */ 774#define ED_WD_SOFTCONFIG 0x20 /* Soft config */ 775#define ED_WD_LARGERAM 0x40 /* Large RAM */ 776#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ 777 778/* 779 * Checksum total. All 8 bytes in station address PROM will add up to this 780 */ 781#ifdef TOSH_ETHER 782#define ED_WD_ROM_CHECKSUM_TOTAL 0xA5 783#else 784#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF 785#endif 786 787#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */ 788#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */ 789#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */ 790 791#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */ 792 793/* 794 * Definitions for 3Com 3c503 795 */ 796#define ED_3COM_NIC_OFFSET 0 797#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ 798 799/* 800 * XXX - The I/O address range is fragmented in the 3c503; this is the 801 * number of regs at iobase. 802 */ 803#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */ 804 805/* tx memory starts in second bank on 8bit cards */ 806#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20 807 808/* tx memory starts in first bank on 16bit cards */ 809#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0 810 811/* ...and rx memory starts in second bank */ 812#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20 813 814 815/* 816 * Page Start Register. Must match PSTART in NIC 817 */ 818#define ED_3COM_PSTR 0 819 820/* 821 * Page Stop Register. Must match PSTOP in NIC 822 */ 823#define ED_3COM_PSPR 1 824 825/* 826 * Drq Timer Register. Determines number of bytes to be transfered during 827 * a DMA burst. 828 */ 829#define ED_3COM_DQTR 2 830 831/* 832 * Base Configuration Register. Read-only register which contains the 833 * board-configured I/O base address of the adapter. Bit encoded. 834 */ 835#define ED_3COM_BCFR 3 836 837#define ED_3COM_BCFR_2E0 0x01 838#define ED_3COM_BCFR_2A0 0x02 839#define ED_3COM_BCFR_280 0x04 840#define ED_3COM_BCFR_250 0x08 841#define ED_3COM_BCFR_350 0x10 842#define ED_3COM_BCFR_330 0x20 843#define ED_3COM_BCFR_310 0x40 844#define ED_3COM_BCFR_300 0x80 845 846/* 847 * EPROM Configuration Register. Read-only register which contains the 848 * board-configured memory base address. Bit encoded. 849 */ 850#define ED_3COM_PCFR 4 851 852#define ED_3COM_PCFR_C8000 0x10 853#define ED_3COM_PCFR_CC000 0x20 854#define ED_3COM_PCFR_D8000 0x40 855#define ED_3COM_PCFR_DC000 0x80 856 857/* 858 * GA Configuration Register. Gate-Array Configuration Register. 859 */ 860#define ED_3COM_GACFR 5 861 862/* 863 * mbs2 mbs1 mbs0 start address 864 * 0 0 0 0x0000 865 * 0 0 1 0x2000 866 * 0 1 0 0x4000 867 * 0 1 1 0x6000 868 * 869 * Note that with adapters with only 8K, the setting for 0x2000 must 870 * always be used. 871 */ 872#define ED_3COM_GACFR_MBS0 0x01 873#define ED_3COM_GACFR_MBS1 0x02 874#define ED_3COM_GACFR_MBS2 0x04 875 876#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */ 877#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */ 878#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ 879#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ 880#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ 881 882/* 883 * Control Register. Miscellaneous control functions. 884 */ 885#define ED_3COM_CR 6 886 887#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */ 888#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 889#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 890#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 891#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */ 892#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */ 893#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */ 894#define ED_3COM_CR_START 0x80 /* Start DMA controller */ 895 896/* 897 * Status Register. Miscellaneous status information. 898 */ 899#define ED_3COM_STREG 7 900 901#define ED_3COM_STREG_REV 0x07 /* GA revision */ 902#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */ 903#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */ 904#define ED_3COM_STREG_OFLW 0x20 /* Overflow */ 905#define ED_3COM_STREG_UFLW 0x40 /* Underflow */ 906#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */ 907 908/* 909 * Interrupt/DMA Configuration Register 910 */ 911#define ED_3COM_IDCFR 8 912 913#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ 914#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ 915#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ 916#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */ 917#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 918#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 919#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 920#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 921 922/* 923 * DMA Address Register MSB 924 */ 925#define ED_3COM_DAMSB 9 926 927/* 928 * DMA Address Register LSB 929 */ 930#define ED_3COM_DALSB 0x0a 931 932/* 933 * Vector Pointer Register 2 934 */ 935#define ED_3COM_VPTR2 0x0b 936 937/* 938 * Vector Pointer Register 1 939 */ 940#define ED_3COM_VPTR1 0x0c 941 942/* 943 * Vector Pointer Register 0 944 */ 945#define ED_3COM_VPTR0 0x0d 946 947/* 948 * Register File Access MSB 949 */ 950#define ED_3COM_RFMSB 0x0e 951 952/* 953 * Register File Access LSB 954 */ 955#define ED_3COM_RFLSB 0x0f 956 957/* 958 * Definitions for Novell NE1000/2000 boards 959 */ 960 961/* 962 * Board type codes 963 */ 964#define ED_TYPE_NE1000 0x01 965#define ED_TYPE_NE2000 0x02 966 967/* 968 * Register offsets/total 969 */ 970#define ED_NOVELL_NIC_OFFSET 0x00 971#define ED_NOVELL_ASIC_OFFSET 0x10 972#define ED_NOVELL_IO_PORTS 32 973 974/* 975 * Remote DMA data register; for reading or writing to the NIC mem 976 * via programmed I/O (offset from ASIC base) 977 */ 978#define ED_NOVELL_DATA 0x00 979 980/* 981 * Reset register; reading from this register causes a board reset 982 */ 983#define ED_NOVELL_RESET 0x0f 984