if_edreg.h revision 40072
1184610Salfred/* 2184610Salfred * Copyright (C) 1993, David Greenman. This software may be used, modified, 3184610Salfred * copied, distributed, and sold, in both source and binary form provided 4184610Salfred * that the above copyright and these terms are retained. Under no 5184610Salfred * circumstances is the author responsible for the proper functioning 6184610Salfred * of this software, nor does the author assume any responsibility 7184610Salfred * for damages incurred with its use. 8184610Salfred * 9184610Salfred * $Id: if_edreg.h,v 1.24 1998/10/08 17:04:47 kato Exp $ 10184610Salfred */ 11184610Salfred/* 12184610Salfred * National Semiconductor DS8390 NIC register definitions 13184610Salfred * 14184610Salfred * 15184610Salfred * Modification history 16184610Salfred * 17184610Salfred * Revision 2.2 1993/11/29 16:33:39 davidg 18184610Salfred * From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk> 19184610Salfred * Add support for the 8013W board type 20184610Salfred * 21184610Salfred * Revision 2.1 1993/11/22 10:52:33 davidg 22184610Salfred * patch to add support for SMC8216 (Elite-Ultra) boards 23184610Salfred * from Glen H. Lowe 24184610Salfred * 25184610Salfred * Revision 2.0 93/09/29 00:37:15 davidg 26184610Salfred * changed double buffering flag to multi buffering 27194677Sthompsa * made changes/additions for 3c503 multi-buffering 28194677Sthompsa * ...companion to Rev. 2.0 of 'ed' driver. 29194677Sthompsa * 30194677Sthompsa * Revision 1.1 93/06/23 03:01:07 davidg 31194677Sthompsa * Initial revision 32194677Sthompsa * 33194677Sthompsa */ 34194677Sthompsa 35194677Sthompsa/* 36194677Sthompsa * Page 0 register offsets 37194677Sthompsa */ 38194677Sthompsa#define ED_P0_CR 0x00 /* Command Register */ 39194677Sthompsa 40194677Sthompsa#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 41194677Sthompsa#define ED_P0_PSTART 0x01 /* Page Start register (write) */ 42194677Sthompsa 43194677Sthompsa#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 44194677Sthompsa#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ 45194677Sthompsa 46194677Sthompsa#define ED_P0_BNRY 0x03 /* Boundary Pointer */ 47188942Sthompsa 48194677Sthompsa#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ 49195963Salfred#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ 50194677Sthompsa 51184610Salfred#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 52194228Sthompsa#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 53184610Salfred 54188942Sthompsa#define ED_P0_FIFO 0x06 /* FIFO register (read) */ 55188942Sthompsa#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 56188942Sthompsa 57188942Sthompsa#define ED_P0_ISR 0x07 /* Interrupt Status Register */ 58188942Sthompsa 59188942Sthompsa#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 60188942Sthompsa#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 61188942Sthompsa 62184610Salfred#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 63188942Sthompsa#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 64188942Sthompsa 65184610Salfred#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 66184610Salfred 67184610Salfred#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 68194228Sthompsa 69194228Sthompsa#define ED_P0_RSR 0x0c /* Receive Status (read) */ 70194228Sthompsa#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 71194228Sthompsa 72194228Sthompsa#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 73185948Sthompsa#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 74194228Sthompsa 75192984Sthompsa#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ 76185948Sthompsa#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ 77184610Salfred 78184610Salfred#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ 79194228Sthompsa#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 80184610Salfred 81184610Salfred/* 82184610Salfred * Page 1 register offsets 83184610Salfred */ 84184610Salfred#define ED_P1_CR 0x00 /* Command Register */ 85194677Sthompsa#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ 86184610Salfred#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ 87193045Sthompsa#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ 88184610Salfred#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ 89184610Salfred#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ 90184610Salfred#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ 91184610Salfred#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ 92184610Salfred#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ 93184610Salfred#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ 94184610Salfred#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ 95184610Salfred#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ 96194228Sthompsa#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ 97184610Salfred#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ 98184610Salfred#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ 99184610Salfred#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ 100184610Salfred 101184610Salfred/* 102194228Sthompsa * Page 2 register offsets 103184610Salfred */ 104184610Salfred#define ED_P2_CR 0x00 /* Command Register */ 105184610Salfred#define ED_P2_PSTART 0x01 /* Page Start (read) */ 106184610Salfred#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 107194228Sthompsa#define ED_P2_PSTOP 0x02 /* Page Stop (read) */ 108184610Salfred#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 109184610Salfred#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 110184610Salfred#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ 111194064Sthompsa#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ 112194064Sthompsa#define ED_P2_ACU 0x06 /* Address Counter Upper */ 113194064Sthompsa#define ED_P2_ACL 0x07 /* Address Counter Lower */ 114194228Sthompsa#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ 115194064Sthompsa#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 116184610Salfred#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ 117184610Salfred#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 118184610Salfred 119184610Salfred/* 120184610Salfred * Command Register (CR) definitions 121184610Salfred */ 122184610Salfred 123184610Salfred/* 124184610Salfred * STP: SToP. Software reset command. Takes the controller offline. No 125194064Sthompsa * packets will be received or transmitted. Any reception or 126194064Sthompsa * transmission in progress will continue to completion before 127194064Sthompsa * entering reset state. To exit this state, the STP bit must 128194064Sthompsa * reset and the STA bit must be set. The software reset has 129194677Sthompsa * executed only when indicated by the RST bit in the ISR being 130184610Salfred * set. 131184610Salfred */ 132184610Salfred#define ED_CR_STP 0x01 133194677Sthompsa 134194228Sthompsa/* 135184610Salfred * STA: STArt. This bit is used to activate the NIC after either power-up, 136184610Salfred * or when the NIC has been put in reset mode by software command 137184610Salfred * or error. 138194228Sthompsa */ 139184610Salfred#define ED_CR_STA 0x02 140184610Salfred 141184610Salfred/* 142184610Salfred * TXP: Transmit Packet. This bit must be set to indicate transmission of 143184610Salfred * a packet. TXP is internally reset either after the transmission is 144193045Sthompsa * completed or aborted. This bit should be set only after the Transmit 145194228Sthompsa * Byte Count and Transmit Page Start register have been programmed. 146184610Salfred */ 147192984Sthompsa#define ED_CR_TXP 0x04 148193045Sthompsa 149184610Salfred/* 150184610Salfred * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 151184610Salfred * of the remote DMA channel. RD2 can be set to abort any remote DMA 152184610Salfred * command in progress. The Remote Byte Count registers should be cleared 153184610Salfred * when a remote DMA has been aborted. The Remote Start Addresses are not 154184824Sthompsa * restored to the starting address if the remote DMA is aborted. 155184610Salfred * 156196498Salfred * RD2 RD1 RD0 function 157196498Salfred * 0 0 0 not allowed 158184610Salfred * 0 0 1 remote read 159184610Salfred * 0 1 0 remote write 160184610Salfred * 0 1 1 send packet 161184610Salfred * 1 X X abort 162184610Salfred */ 163184610Salfred#define ED_CR_RD0 0x08 164184610Salfred#define ED_CR_RD1 0x10 165184610Salfred#define ED_CR_RD2 0x20 166184610Salfred 167184610Salfred/* 168194228Sthompsa * PS0, PS1: Page Select. The two bits select which register set or 'page' to 169184610Salfred * access. 170184610Salfred * 171184610Salfred * PS1 PS0 page 172184610Salfred * 0 0 0 173194228Sthompsa * 0 1 1 174184610Salfred * 1 0 2 175184610Salfred * 1 1 reserved 176184610Salfred */ 177184610Salfred#define ED_CR_PS0 0x40 178184610Salfred#define ED_CR_PS1 0x80 179196498Salfred/* bit encoded aliases */ 180184824Sthompsa#define ED_CR_PAGE_0 0x00 /* (for consistency) */ 181184610Salfred#define ED_CR_PAGE_1 0x40 182184610Salfred#define ED_CR_PAGE_2 0x80 183184610Salfred 184195963Salfred/* 185195963Salfred * Interrupt Status Register (ISR) definitions 186195963Salfred */ 187195963Salfred 188195963Salfred/* 189195963Salfred * PRX: Packet Received. Indicates packet received with no errors. 190195963Salfred */ 191195963Salfred#define ED_ISR_PRX 0x01 192196498Salfred 193195963Salfred/* 194195963Salfred * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 195195963Salfred */ 196196498Salfred#define ED_ISR_PTX 0x02 197195963Salfred 198195963Salfred/* 199195963Salfred * RXE: Receive Error. Indicates that a packet was received with one or more 200195963Salfred * the following errors: CRC error, frame alignment error, FIFO overrun, 201195963Salfred * missed packet. 202196498Salfred */ 203196498Salfred#define ED_ISR_RXE 0x04 204196498Salfred 205195963Salfred/* 206195963Salfred * TXE: Transmission Error. Indicates that an attempt to transmit a packet 207195963Salfred * resulted in one or more of the following errors: excessive 208184610Salfred * collisions, FIFO underrun. 209194228Sthompsa */ 210184610Salfred#define ED_ISR_TXE 0x08 211184610Salfred 212184610Salfred/* 213184610Salfred * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 214184610Salfred * would exceed (has exceeded?) the boundary pointer, resulting in data 215193045Sthompsa * that was previously received and not yet read from the buffer to be 216194228Sthompsa * overwritten. 217184610Salfred */ 218192984Sthompsa#define ED_ISR_OVW 0x10 219184610Salfred 220192984Sthompsa/* 221192984Sthompsa * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley 222192984Sthompsa * Counters has been set. 223184610Salfred */ 224184610Salfred#define ED_ISR_CNT 0x20 225195121Sthompsa 226184610Salfred/* 227184610Salfred * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed. 228184610Salfred */ 229184610Salfred#define ED_ISR_RDC 0x40 230184610Salfred 231184610Salfred/* 232184610Salfred * RST: Reset status. Set when the NIC enters the reset state and cleared when a 233184610Salfred * Start Command is issued to the CR. This bit is also set when a receive 234184610Salfred * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 235184610Salfred * packets have been removed from the ring. This is a read-only bit. 236184610Salfred */ 237184824Sthompsa#define ED_ISR_RST 0x80 238184610Salfred 239196498Salfred/* 240196498Salfred * Interrupt Mask Register (IMR) definitions 241184610Salfred */ 242184610Salfred 243184610Salfred/* 244194228Sthompsa * PRXE: Packet Received interrupt Enable. If set, a received packet will cause 245184610Salfred * an interrupt. 246184610Salfred */ 247184610Salfred#define ED_IMR_PRXE 0x01 248184610Salfred 249184610Salfred/* 250195121Sthompsa * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when 251195121Sthompsa * a packet transmission completes. 252195121Sthompsa */ 253195121Sthompsa#define ED_IMR_PTXE 0x02 254184610Salfred 255184610Salfred/* 256184610Salfred * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a 257184610Salfred * packet is received with an error. 258184610Salfred */ 259184610Salfred#define ED_IMR_RXEE 0x04 260184610Salfred 261190186Sthompsa/* 262184610Salfred * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever 263188942Sthompsa * a transmission results in an error. 264184610Salfred */ 265195121Sthompsa#define ED_IMR_TXEE 0x08 266184610Salfred 267194228Sthompsa/* 268184610Salfred * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever 269184610Salfred * the receive ring-buffer is overrun. i.e. when the boundary pointer is exceeded. 270184610Salfred */ 271184610Salfred#define ED_IMR_OVWE 0x10 272184610Salfred 273184610Salfred/* 274184610Salfred * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever 275184610Salfred * the MSB of one or more of the Network Statistics counters has been set. 276184610Salfred */ 277184610Salfred#define ED_IMR_CNTE 0x20 278184610Salfred 279184610Salfred/* 280184610Salfred * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated 281184610Salfred * when a remote DMA transfer has completed. 282184610Salfred */ 283188942Sthompsa#define ED_IMR_RDCE 0x40 284195121Sthompsa 285184610Salfred/* 286184610Salfred * bit 7 is unused/reserved 287184610Salfred */ 288184610Salfred 289184610Salfred/* 290195121Sthompsa * Data Configuration Register (DCR) definitions 291195121Sthompsa */ 292195121Sthompsa 293195121Sthompsa/* 294195121Sthompsa * WTS: Word Transfer Select. WTS establishes byte or word transfers for 295195121Sthompsa * both remote and local DMA transfers 296184610Salfred */ 297184610Salfred#define ED_DCR_WTS 0x01 298184610Salfred 299184610Salfred/* 300184610Salfred * BOS: Byte Order Select. BOS sets the byte order for the host. 301184610Salfred * Should be 0 for 80x86, and 1 for 68000 series processors 302184610Salfred */ 303194064Sthompsa#define ED_DCR_BOS 0x02 304184610Salfred 305184610Salfred/* 306184610Salfred * LAS: Long Address Select. When LAS is 1, the contents of the remote 307184610Salfred * DMA registers RSAR0 and RSAR1 are used to provide A16-A31 308184610Salfred */ 309184610Salfred#define ED_DCR_LAS 0x04 310184610Salfred 311184610Salfred/* 312195963Salfred * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 313195963Salfred * of the TCR must also be programmed for loopback operation. 314195963Salfred * When 1, normal operation is selected. 315195963Salfred */ 316195963Salfred#define ED_DCR_LS 0x08 317184610Salfred 318195963Salfred/* 319195963Salfred * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 320184610Salfred * under program control. When 1, remote DMA is automatically initiated 321195963Salfred * and the boundary pointer is automatically updated 322194228Sthompsa */ 323184610Salfred#define ED_DCR_AR 0x10 324184610Salfred 325195963Salfred/* 326184610Salfred * FT0, FT1: Fifo Threshold select. 327195963Salfred * FT1 FT0 Word-width Byte-width 328195963Salfred * 0 0 1 word 2 bytes 329184610Salfred * 0 1 2 words 4 bytes 330184610Salfred * 1 0 4 words 8 bytes 331195963Salfred * 1 1 8 words 12 bytes 332195963Salfred * 333184610Salfred * During transmission, the FIFO threshold indicates the number of bytes 334195963Salfred * or words that the FIFO has filled from the local DMA before BREQ is 335184610Salfred * asserted. The transmission threshold is 16 bytes minus the receiver 336184610Salfred * threshold. 337184610Salfred */ 338184610Salfred#define ED_DCR_FT0 0x20 339184610Salfred#define ED_DCR_FT1 0x40 340184610Salfred 341184610Salfred/* 342184610Salfred * bit 7 (0x80) is unused/reserved 343184610Salfred */ 344184610Salfred 345184610Salfred/* 346184610Salfred * Transmit Configuration Register (TCR) definitions 347184610Salfred */ 348184610Salfred 349184610Salfred/* 350184610Salfred * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 351184610Salfred * is not appended by the transmitter. 352184610Salfred */ 353184610Salfred#define ED_TCR_CRC 0x01 354184610Salfred 355196498Salfred/* 356184824Sthompsa * LB0, LB1: Loopback control. These two bits set the type of loopback that is 357184610Salfred * to be performed. 358184610Salfred * 359195121Sthompsa * LB1 LB0 mode 360196498Salfred * 0 0 0 - normal operation (DCR_LS = 0) 361195121Sthompsa * 0 1 1 - internal loopback (DCR_LS = 0) 362195121Sthompsa * 1 0 2 - external loopback (DCR_LS = 1) 363195121Sthompsa * 1 1 3 - external loopback (DCR_LS = 0) 364184610Salfred */ 365196498Salfred#define ED_TCR_LB0 0x02 366184824Sthompsa#define ED_TCR_LB1 0x04 367184610Salfred 368184610Salfred/* 369184610Salfred * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 370184610Salfred * another station to disable the NIC's transmitter by transmitting to 371194228Sthompsa * a multicast address hashing to bit 62. Reception of a multicast address 372184610Salfred * hashing to bit 63 enables the transmitter. 373184610Salfred */ 374184610Salfred#define ED_TCR_ATD 0x08 375184610Salfred 376184610Salfred/* 377193045Sthompsa * OFST: Collision Offset enable. This bit when set modifies the backoff 378194228Sthompsa * algorithm to allow prioritization of nodes. 379184610Salfred */ 380192984Sthompsa#define ED_TCR_OFST 0x10 381193045Sthompsa 382184610Salfred/* 383184824Sthompsa * bits 5, 6, and 7 are unused/reserved 384194228Sthompsa */ 385194228Sthompsa 386184824Sthompsa/* 387184610Salfred * Transmit Status Register (TSR) definitions 388184610Salfred */ 389184610Salfred 390184610Salfred/* 391194228Sthompsa * PTX: Packet Transmitted. Indicates successful transmission of packet. 392184610Salfred */ 393184610Salfred#define ED_TSR_PTX 0x01 394184610Salfred 395184610Salfred/* 396184610Salfred * bit 1 (0x02) is unused/reserved 397184610Salfred */ 398194228Sthompsa 399184610Salfred/* 400193644Sthompsa * COL: Transmit Collided. Indicates that the transmission collided at least 401184610Salfred * once with another station on the network. 402184610Salfred */ 403194228Sthompsa#define ED_TSR_COL 0x04 404193644Sthompsa 405184610Salfred/* 406184610Salfred * ABT: Transmit aborted. Indicates that the transmission was aborted due to 407184610Salfred * excessive collisions. 408184824Sthompsa */ 409193644Sthompsa#define ED_TSR_ABT 0x08 410184824Sthompsa 411184610Salfred/* 412184610Salfred * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 413184610Salfred * transmission of the packet. (Transmission is not aborted because 414184610Salfred * of a loss of carrier) 415184610Salfred */ 416194228Sthompsa#define ED_TSR_CRS 0x10 417184610Salfred 418184610Salfred/* 419184610Salfred * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 420184610Salfred * transmission memory before the FIFO emptied. Transmission of the 421184610Salfred * packet was aborted. 422193045Sthompsa */ 423194228Sthompsa#define ED_TSR_FU 0x20 424184610Salfred 425192984Sthompsa/* 426192984Sthompsa * CDH: CD Heartbeat. Indicates that the collision detection circuitry 427184610Salfred * isn't working correctly during a collision heartbeat test. 428187173Sthompsa */ 429184610Salfred#define ED_TSR_CDH 0x40 430184610Salfred 431184824Sthompsa/* 432184610Salfred * OWC: Out of Window Collision: Indicates that a collision occurred after 433184610Salfred * a slot time (51.2us). The transmission is rescheduled just as in 434184610Salfred * normal collisions. 435184610Salfred */ 436184610Salfred#define ED_TSR_OWC 0x80 437184610Salfred 438184610Salfred/* 439184824Sthompsa * Receiver Configuration Register (RCR) definitions 440184610Salfred */ 441213434Shselasky 442186730Salfred/* 443194228Sthompsa * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 444213434Shselasky * packets with CRC and frame errors are not discarded. 445184610Salfred */ 446184610Salfred#define ED_RCR_SEP 0x01 447184610Salfred 448184610Salfred/* 449194228Sthompsa * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 450184610Salfred * If set to 1, packets with less than 64 byte are not discarded. 451184610Salfred */ 452184610Salfred#define ED_RCR_AR 0x02 453194064Sthompsa 454184610Salfred/* 455184610Salfred * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 456184610Salfred * accepted. 457184610Salfred */ 458184610Salfred#define ED_RCR_AB 0x04 459193045Sthompsa 460194228Sthompsa/* 461184610Salfred * AM: Accept Multicast. If set, packets sent to a multicast address are checked 462192984Sthompsa * for a match in the hashing array. If clear, multicast packets are ignored. 463192984Sthompsa */ 464184610Salfred#define ED_RCR_AM 0x08 465184610Salfred 466184610Salfred/* 467184610Salfred * PRO: Promiscuous Physical. If set, all packets with a physical addresses are 468184610Salfred * accepted. If clear, a physical destination address must match this 469184610Salfred * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM 470184610Salfred * must also be set. In addition, the multicast hashing array must be set 471184610Salfred * to all 1's so that all multicast addresses are accepted. 472195121Sthompsa */ 473193045Sthompsa#define ED_RCR_PRO 0x10 474184610Salfred 475184610Salfred/* 476184610Salfred * MON: Monitor Mode. If set, packets will be checked for good CRC and framing, 477184610Salfred * but are not stored in the ring-buffer. If clear, packets are stored (normal 478184610Salfred * operation). 479184610Salfred */ 480184610Salfred#define ED_RCR_MON 0x20 481184610Salfred 482184610Salfred/* 483184610Salfred * bits 6 and 7 are unused/reserved. 484184610Salfred */ 485184610Salfred 486194064Sthompsa/* 487184610Salfred * Receiver Status Register (RSR) definitions 488184610Salfred */ 489184610Salfred 490184610Salfred/* 491184610Salfred * PRX: Packet Received without error. 492184610Salfred */ 493194064Sthompsa#define ED_RSR_PRX 0x01 494184610Salfred 495194064Sthompsa/* 496184610Salfred * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame 497194064Sthompsa * alignment errors. 498184610Salfred */ 499184610Salfred#define ED_RSR_CRC 0x02 500194064Sthompsa 501194064Sthompsa/* 502194064Sthompsa * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on 503184610Salfred * a byte boundary and the CRC did not match at the last byte boundary. 504184610Salfred */ 505184610Salfred#define ED_RSR_FAE 0x04 506184610Salfred 507194677Sthompsa/* 508184610Salfred * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA) 509194677Sthompsa * causing it to overrun. Reception of the packet is aborted. 510194677Sthompsa */ 511184610Salfred#define ED_RSR_FO 0x08 512184610Salfred 513184610Salfred/* 514194228Sthompsa * MPA: Missed Packet. Indicates that the received packet couldn't be stored in 515184610Salfred * the ring-buffer because of insufficient buffer space (exceeding the 516184610Salfred * boundary pointer), or because the transfer to the ring-buffer was inhibited 517184610Salfred * by RCR_MON - monitor mode. 518184610Salfred */ 519184610Salfred#define ED_RSR_MPA 0x10 520184610Salfred 521184610Salfred/* 522184610Salfred * PHY: Physical address. If 0, the packet received was sent to a physical address. 523184610Salfred * If 1, the packet was accepted because of a multicast/broadcast address 524184610Salfred * match. 525184610Salfred */ 526184610Salfred#define ED_RSR_PHY 0x20 527184610Salfred 528184610Salfred/* 529184610Salfred * DIS: Receiver Disabled. Set to indicate that the receiver has entered monitor 530184610Salfred * mode. Cleared when the receiver exits monitor mode. 531187173Sthompsa */ 532184610Salfred#define ED_RSR_DIS 0x40 533184610Salfred 534184610Salfred/* 535184610Salfred * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs 536184610Salfred * are active, and the transceiver has set the CD line as a result of the 537184610Salfred * jabber. 538184610Salfred */ 539184610Salfred#define ED_RSR_DFR 0x80 540184610Salfred 541184610Salfred/* 542184610Salfred * receive ring descriptor 543184610Salfred * 544184610Salfred * The National Semiconductor DS8390 Network interface controller uses 545184610Salfred * the following receive ring headers. The way this works is that the 546194064Sthompsa * memory on the interface card is chopped up into 256 bytes blocks. 547184610Salfred * A contiguous portion of those blocks are marked for receive packets 548184610Salfred * by setting start and end block #'s in the NIC. For each packet that 549184610Salfred * is put into the receive ring, one of these headers (4 bytes each) is 550184610Salfred * tacked onto the front. The first byte is a copy of the receiver status 551184610Salfred * register at the time the packet was received. 552184610Salfred */ 553184610Salfredstruct ed_ring { 554184610Salfred u_char rsr; /* receiver status */ 555184610Salfred u_char next_packet; /* pointer to next packet */ 556184610Salfred u_short count; /* bytes in packet (length + 4) */ 557184610Salfred}; 558184610Salfred 559184610Salfred/* 560184610Salfred * Common constants 561184610Salfred */ 562184610Salfred#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 563184610Salfred#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 564184610Salfred 565184610Salfred/* 566184610Salfred * Vendor types 567184610Salfred */ 568184610Salfred#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ 569184610Salfred#define ED_VENDOR_3COM 0x01 /* 3Com */ 570184610Salfred#define ED_VENDOR_NOVELL 0x02 /* Novell */ 571184610Salfred#define ED_VENDOR_PCCARD 0x03 /* PCMCIA/PCCARD */ 572184610Salfred#define ED_VENDOR_HP 0x04 /* Hewlett Packard */ 573184610Salfred 574184610Salfred/* 575184610Salfred * Compile-time config flags 576184610Salfred */ 577184610Salfred/* 578184610Salfred * this sets the default for enabling/disabling the transceiver 579184610Salfred */ 580184610Salfred#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001 581184610Salfred 582184610Salfred/* 583184610Salfred * This forces the board to be used in 8/16bit mode even if it 584184610Salfred * autoconfigs differently 585184610Salfred */ 586184610Salfred#define ED_FLAGS_FORCE_8BIT_MODE 0x0002 587184610Salfred#define ED_FLAGS_FORCE_16BIT_MODE 0x0004 588184610Salfred 589184610Salfred/* 590184610Salfred * This disables the use of double transmit buffers. 591184610Salfred */ 592184610Salfred#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008 593184610Salfred 594184610Salfred/* 595184610Salfred * This forces all operations with the NIC memory to use Programmed 596184610Salfred * I/O (i.e. not via shared memory) 597184610Salfred */ 598184610Salfred#define ED_FLAGS_FORCE_PIO 0x0010 599184610Salfred 600184610Salfred/* 601184610Salfred * Definitions for Western digital/SMC WD80x3 series ASIC 602184610Salfred */ 603184610Salfred/* 604184610Salfred * Memory Select Register (MSR) 605184610Salfred */ 606184610Salfred#define ED_WD_MSR 0 607184610Salfred 608184610Salfred/* next three definitions for Toshiba */ 609184610Salfred#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */ 610184610Salfred#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */ 611184610Salfred#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits, 612184610Salfred 1 = 8 bits (R/W) */ 613184610Salfred#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ 614184610Salfred#define ED_WD_MSR_MENB 0x40 /* Memory enable */ 615184610Salfred#define ED_WD_MSR_RST 0x80 /* Reset board */ 616184610Salfred 617184610Salfred/* 618184610Salfred * Interface Configuration Register (ICR) 619184610Salfred */ 620184610Salfred#define ED_WD_ICR 1 621194228Sthompsa 622184610Salfred#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */ 623184610Salfred#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */ 624184610Salfred#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */ 625195121Sthompsa#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ 626184610Salfred#define ED_WD_ICR_RLA 0x10 /* recall LAN address */ 627195121Sthompsa#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */ 628195121Sthompsa#define ED_WD_ICR_RIO 0x40 /* recall i/o address */ 629184610Salfred#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */ 630184610Salfred#ifdef TOSH_ETHER 631184610Salfred#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */ 632184610Salfred#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K, 633184610Salfred 0x02 = 16K, 0x01 = 8K */ 634184610Salfred /* 64K can only be used if mem address 635184610Salfred above 1Mb */ 636184610Salfred /* IAR holds address A23-A16 (R/W) */ 637184610Salfred#endif 638184610Salfred 639184610Salfred/* 640184610Salfred * IO Address Register (IAR) 641184610Salfred */ 642184610Salfred#define ED_WD_IAR 2 643184610Salfred 644184610Salfred/* 645184610Salfred * EEROM Address Register 646184610Salfred */ 647194228Sthompsa#define ED_WD_EAR 3 648191402Sthompsa 649184610Salfred/* 650191402Sthompsa * Interrupt Request Register (IRR) 651191402Sthompsa */ 652184610Salfred#define ED_WD_IRR 4 653184610Salfred 654184610Salfred#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ 655184610Salfred#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ 656184610Salfred#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ 657184610Salfred#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ 658184610Salfred#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ 659184610Salfred 660184610Salfred/* 661184610Salfred * The three bits of the encoded IRQ are decoded as follows: 662184610Salfred * 663184610Salfred * IR2 IR1 IR0 IRQ 664184824Sthompsa * 0 0 0 2/9 665184610Salfred * 0 0 1 3 666184610Salfred * 0 1 0 5 667184610Salfred * 0 1 1 7 668184610Salfred * 1 0 0 10 669184610Salfred * 1 0 1 11 670184610Salfred * 1 1 0 15 671184824Sthompsa * 1 1 1 4 672184610Salfred */ 673184610Salfred#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 674184610Salfred#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 675184610Salfred#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */ 676184610Salfred 677184610Salfred/* 678184610Salfred * LA Address Register (LAAR) 679194064Sthompsa */ 680184610Salfred#define ED_WD_LAAR 5 681184610Salfred 682184610Salfred#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ 683184610Salfred#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ 684184610Salfred#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */ 685184610Salfred#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */ 686184610Salfred 687194064Sthompsa/* i/o base offset to station address/card-ID PROM */ 688184610Salfred#define ED_WD_PROM 8 689184610Salfred 690184610Salfred/* 691184610Salfred * 83C790 specific registers 692184610Salfred */ 693184610Salfred/* 694194064Sthompsa * Hardware Support Register (HWR) ('790) 695194228Sthompsa */ 696184610Salfred#define ED_WD790_HWR 4 697184610Salfred 698184610Salfred#define WD_WD790_HWR_NUKE 0x10 /* hardware reset */ 699184610Salfred#define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */ 700184610Salfred#define ED_WD790_HWR_SWH 0x80 /* switch register set */ 701184610Salfred 702194064Sthompsa/* 703194228Sthompsa * ICR790 Interrupt Control Register for the 83C790 704184610Salfred */ 705184610Salfred#define ED_WD790_ICR 6 706184610Salfred 707184610Salfred#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */ 708184610Salfred 709184610Salfred/* 710194064Sthompsa * REV/IOPA Revision / I/O Pipe register for the 83C79X 711194228Sthompsa */ 712184610Salfred#define ED_WD790_REV 7 713184610Salfred 714184610Salfred#define ED_WD790 0x20 715184610Salfred#define ED_WD795 0x40 716184610Salfred 717184610Salfred/* 718194064Sthompsa * 79X RAM Address Register (RAR) 719194228Sthompsa * Enabled with SWH bit=1 in HWR register 720184610Salfred */ 721184610Salfred#define ED_WD790_RAR 0x0b 722184610Salfred 723184610Salfred#define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */ 724184610Salfred#define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */ 725184610Salfred#define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */ 726194064Sthompsa#define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */ 727194228Sthompsa 728184610Salfred/* 729184610Salfred * General Control Register (GCR) 730184610Salfred * Enabled with SWH bit=1 in HWR register 731184610Salfred */ 732184610Salfred#define ED_WD790_GCR 0x0d 733184610Salfred 734194064Sthompsa#define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */ 735184610Salfred#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */ 736194228Sthompsa#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */ 737184610Salfred#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */ 738184610Salfred#define ED_WD790_GCR_LIT 0x01 /* Link Integrity Test Enable */ 739184610Salfred/* 740184610Salfred * The three bits of the encoded IRQ are decoded as follows: 741184610Salfred * 742184610Salfred * IR2 IR1 IR0 IRQ 743184610Salfred * 0 0 0 none 744194064Sthompsa * 0 0 1 9 745184610Salfred * 0 1 0 3 746184610Salfred * 0 1 1 5 747184610Salfred * 1 0 0 7 748184610Salfred * 1 0 1 10 749184610Salfred * 1 1 0 11 750184610Salfred * 1 1 1 15 751184610Salfred */ 752184610Salfred 753184610Salfred/* i/o base offset to CARD ID */ 754194677Sthompsa#define ED_WD_CARD_ID ED_WD_PROM+6 755184610Salfred 756184610Salfred/* Board type codes in card ID */ 757184610Salfred#define ED_TYPE_WD8003S 0x02 758184610Salfred#define ED_TYPE_WD8003E 0x03 759184610Salfred#define ED_TYPE_WD8013EBT 0x05 760184610Salfred#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */ 761184610Salfred#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */ 762184610Salfred#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */ 763184610Salfred#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */ 764184610Salfred#define ED_TYPE_WD8003W 0x24 765194677Sthompsa#define ED_TYPE_WD8003EB 0x25 766184610Salfred#define ED_TYPE_WD8013W 0x26 767195121Sthompsa#define ED_TYPE_WD8013EP 0x27 768184610Salfred#define ED_TYPE_WD8013WC 0x28 769184610Salfred#define ED_TYPE_WD8013EPC 0x29 770184610Salfred#define ED_TYPE_SMC8216T 0x2a 771184610Salfred#define ED_TYPE_SMC8216C 0x2b 772184610Salfred#define ED_TYPE_WD8013EBP 0x2c 773184610Salfred 774184610Salfred/* Bit definitions in card ID */ 775184610Salfred#define ED_WD_REV_MASK 0x1f /* Revision mask */ 776184610Salfred#define ED_WD_SOFTCONFIG 0x20 /* Soft config */ 777184610Salfred#define ED_WD_LARGERAM 0x40 /* Large RAM */ 778184610Salfred#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ 779184610Salfred 780184610Salfred/* 781184610Salfred * Checksum total. All 8 bytes in station address PROM will add up to this 782184610Salfred */ 783184610Salfred#ifdef TOSH_ETHER 784194228Sthompsa#define ED_WD_ROM_CHECKSUM_TOTAL 0xA5 785184610Salfred#else 786194677Sthompsa#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF 787184610Salfred#endif 788194677Sthompsa 789194677Sthompsa#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */ 790184610Salfred#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */ 791184610Salfred#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */ 792184610Salfred 793184610Salfred#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */ 794194677Sthompsa 795184610Salfred/* 796184610Salfred * Definitions for 3Com 3c503 797184610Salfred */ 798184610Salfred#define ED_3COM_NIC_OFFSET 0 799184610Salfred#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ 800194064Sthompsa 801184610Salfred/* 802184610Salfred * XXX - The I/O address range is fragmented in the 3c503; this is the 803184610Salfred * number of regs at iobase. 804184610Salfred */ 805184610Salfred#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */ 806184610Salfred 807184610Salfred/* tx memory starts in second bank on 8bit cards */ 808#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20 809 810/* tx memory starts in first bank on 16bit cards */ 811#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0 812 813/* ...and rx memory starts in second bank */ 814#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20 815 816 817/* 818 * Page Start Register. Must match PSTART in NIC 819 */ 820#define ED_3COM_PSTR 0 821 822/* 823 * Page Stop Register. Must match PSTOP in NIC 824 */ 825#define ED_3COM_PSPR 1 826 827/* 828 * Drq Timer Register. Determines number of bytes to be transfered during 829 * a DMA burst. 830 */ 831#define ED_3COM_DQTR 2 832 833/* 834 * Base Configuration Register. Read-only register which contains the 835 * board-configured I/O base address of the adapter. Bit encoded. 836 */ 837#define ED_3COM_BCFR 3 838 839#define ED_3COM_BCFR_2E0 0x01 840#define ED_3COM_BCFR_2A0 0x02 841#define ED_3COM_BCFR_280 0x04 842#define ED_3COM_BCFR_250 0x08 843#define ED_3COM_BCFR_350 0x10 844#define ED_3COM_BCFR_330 0x20 845#define ED_3COM_BCFR_310 0x40 846#define ED_3COM_BCFR_300 0x80 847 848/* 849 * EPROM Configuration Register. Read-only register which contains the 850 * board-configured memory base address. Bit encoded. 851 */ 852#define ED_3COM_PCFR 4 853 854#define ED_3COM_PCFR_C8000 0x10 855#define ED_3COM_PCFR_CC000 0x20 856#define ED_3COM_PCFR_D8000 0x40 857#define ED_3COM_PCFR_DC000 0x80 858 859/* 860 * GA Configuration Register. Gate-Array Configuration Register. 861 */ 862#define ED_3COM_GACFR 5 863 864/* 865 * mbs2 mbs1 mbs0 start address 866 * 0 0 0 0x0000 867 * 0 0 1 0x2000 868 * 0 1 0 0x4000 869 * 0 1 1 0x6000 870 * 871 * Note that with adapters with only 8K, the setting for 0x2000 must 872 * always be used. 873 */ 874#define ED_3COM_GACFR_MBS0 0x01 875#define ED_3COM_GACFR_MBS1 0x02 876#define ED_3COM_GACFR_MBS2 0x04 877 878#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */ 879#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */ 880#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ 881#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ 882#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ 883 884/* 885 * Control Register. Miscellaneous control functions. 886 */ 887#define ED_3COM_CR 6 888 889#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */ 890#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 891#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 892#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 893#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */ 894#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */ 895#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */ 896#define ED_3COM_CR_START 0x80 /* Start DMA controller */ 897 898/* 899 * Status Register. Miscellaneous status information. 900 */ 901#define ED_3COM_STREG 7 902 903#define ED_3COM_STREG_REV 0x07 /* GA revision */ 904#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */ 905#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */ 906#define ED_3COM_STREG_OFLW 0x20 /* Overflow */ 907#define ED_3COM_STREG_UFLW 0x40 /* Underflow */ 908#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */ 909 910/* 911 * Interrupt/DMA Configuration Register 912 */ 913#define ED_3COM_IDCFR 8 914 915#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ 916#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ 917#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ 918#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */ 919#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 920#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 921#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 922#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 923 924/* 925 * DMA Address Register MSB 926 */ 927#define ED_3COM_DAMSB 9 928 929/* 930 * DMA Address Register LSB 931 */ 932#define ED_3COM_DALSB 0x0a 933 934/* 935 * Vector Pointer Register 2 936 */ 937#define ED_3COM_VPTR2 0x0b 938 939/* 940 * Vector Pointer Register 1 941 */ 942#define ED_3COM_VPTR1 0x0c 943 944/* 945 * Vector Pointer Register 0 946 */ 947#define ED_3COM_VPTR0 0x0d 948 949/* 950 * Register File Access MSB 951 */ 952#define ED_3COM_RFMSB 0x0e 953 954/* 955 * Register File Access LSB 956 */ 957#define ED_3COM_RFLSB 0x0f 958 959/* 960 * Definitions for Novell NE1000/2000 boards 961 */ 962 963/* 964 * Board type codes 965 */ 966#define ED_TYPE_NE1000 0x01 967#define ED_TYPE_NE2000 0x02 968 969/* 970 * Register offsets/total 971 */ 972#define ED_NOVELL_NIC_OFFSET 0x00 973#define ED_NOVELL_ASIC_OFFSET 0x10 974#define ED_NOVELL_IO_PORTS 32 975 976/* 977 * Remote DMA data register; for reading or writing to the NIC mem 978 * via programmed I/O (offset from ASIC base) 979 */ 980#define ED_NOVELL_DATA 0x00 981 982/* 983 * Reset register; reading from this register causes a board reset 984 */ 985#define ED_NOVELL_RESET 0x0f 986 987/* 988 * Definitions for PCCARD 989 */ 990#define ED_PC_PAGE_OFFSET 0x40 /* page offset for NIC access to mem */ 991#define ED_PC_IO_PORTS 32 992#define ED_PC_RESET 0x1f 993#define ED_PC_MISC 0x18 994 995/* 996 * if_ze.h constants 997 */ 998 999#define ZE_PAGE_OFFSET 0x40 /* mem buffer starts at 0x4000 */ 1000 1001#define ZE_DATA_IO 0x10 1002#define ZE_MISC 0x18 1003#define ZE_RESET 0x1F 1004 1005/* 1006 * Definitions for HP PC LAN Adapter Plus; based on the CRYNWR packet 1007 * driver for the card. 1008 */ 1009 1010#define ED_HPP_ASIC_OFFSET 0x00 /* Offset to ASIC registers */ 1011#define ED_HPP_NIC_OFFSET 0x10 /* Offset to 8390 registers */ 1012 1013#define ED_HPP_ID 0x00 /* ID register, always 0x4850 */ 1014#define ED_HPP_PAGING 0x02 /* Page select register */ 1015#define ED_HPP_OPTION 0x04 /* Bitmask of supported options */ 1016#define ED_HPP_PAGE_0 0x08 /* Page 0 */ 1017#define ED_HPP_PAGE_2 0x0A /* Page 2 */ 1018#define ED_HPP_PAGE_4 0x0C /* Page 4 */ 1019#define ED_HPP_PAGE_6 0x0E /* Page 6 */ 1020 1021/* PERF PAGE */ 1022#define ED_HPP_OUT_ADDR ED_HPP_PAGE_0 /* I/O output location */ 1023#define ED_HPP_IN_ADDR ED_HPP_PAGE_2 /* I/O input location */ 1024#define ED_HPP_DATAPORT ED_HPP_PAGE_4 /* I/O data transfer */ 1025/* MAC PAGE */ 1026#define ED_HPP_MAC_ADDR 0x08 /* Offset of MAC address in MAC page */ 1027 1028#define ED_HPP_IO_PORTS 32 /* Number of IO ports */ 1029 1030#define ED_HPP_TX_PAGE_OFFSET 0x00 /* first page of TX buffer */ 1031#define ED_HPP_RX_PAGE_START 0x06 /* start at page 6 */ 1032#define ED_HPP_RX_PAGE_STOP 0x80 /* end at page 128 */ 1033 1034/* 1035 * Register pages supported. 1036 */ 1037 1038#define ED_HPP_PAGE_PERF 0 /* Normal operation */ 1039#define ED_HPP_PAGE_MAC 1 /* The ethernet address and checksum */ 1040#define ED_HPP_PAGE_HW 2 /* Hardware parameters in EEPROM */ 1041#define ED_HPP_PAGE_LAN 4 /* Transciever selection etc */ 1042#define ED_HPP_PAGE_ID 6 /* ID */ 1043 1044/* 1045 * Options supported. 1046 */ 1047 1048#define ED_HPP_OPTION_NIC_RESET 0x0001 /* active low */ 1049#define ED_HPP_OPTION_CHIP_RESET 0x0002 /* active low */ 1050#define ED_HPP_OPTION_ENABLE_IRQ 0x0004 1051#define ED_HPP_OPTION_FAKE_INTR 0x0008 1052#define ED_HPP_OPTION_BOOT_ROM_ENB 0x0010 1053#define ED_HPP_OPTION_IO_ENB 0x0020 1054#define ED_HPP_OPTION_MEM_ENABLE 0x0040 1055#define ED_HPP_OPTION_ZERO_WAIT 0x0080 1056#define ED_HPP_OPTION_MEM_DISABLE 0x1000 1057 1058/* 1059 * Page ID configuration. 1060 */ 1061 1062#define ED_HPP_ID_REVISION_MASK 0x0300 /* revision id */ 1063#define ED_HPP_ID_SOFT_MODEL_MASK 0xFC00 /* soft model number */ 1064#define ED_HPP_ID_16_BIT_ACCESS 0x0010 /* if set use 16 bit accesses */ 1065#define ED_HPP_ID_TWISTED_PAIR 0x0040 1066 1067/* 1068 * Hardware configuration. 1069 */ 1070 1071#define ED_HPP_HW_MEM_MAP 0x09 /* low mem map location in HW page */ 1072#define ED_HPP_HW_ID 0x0C /* revision number, capabilities */ 1073#define ED_HPP_HW_IRQ 0x0D /* IRQ channel register in HW page */ 1074#define ED_HPP_HW_WRAP 0x0E /* mem wrap page for rcv */ 1075 1076/* 1077 * Lan configuration 1078 */ 1079 1080#define ED_HPP_LAN_AUI 0x01 /* Use AUI */ 1081#define ED_HPP_LAN_TL 0x40 /* Don't use AUI */ 1082 1083/* 1084 * Card types. 1085 */ 1086 1087#define ED_TYPE_HP_PCLANPLUS 0x00 1088