if_edreg.h revision 190559
167754Smsmith/*- 267754Smsmith * Copyright (C) 1993, David Greenman. This software may be used, modified, 3218590Sjkim * copied, distributed, and sold, in both source and binary form provided 467754Smsmith * that the above copyright and these terms are retained. Under no 567754Smsmith * circumstances is the author responsible for the proper functioning 667754Smsmith * of this software, nor does the author assume any responsibility 7217365Sjkim * for damages incurred with its use. 8281075Sdim * 970243Smsmith * $FreeBSD: head/sys/dev/ed/if_edreg.h 190559 2009-03-30 16:15:06Z imp $ 1067754Smsmith */ 11217365Sjkim/* 12217365Sjkim * National Semiconductor DS8390 NIC register definitions 13217365Sjkim * 14217365Sjkim * 15217365Sjkim * Modification history 16217365Sjkim * 17217365Sjkim * Revision 2.2 1993/11/29 16:33:39 davidg 18217365Sjkim * From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk> 19217365Sjkim * Add support for the 8013W board type 20217365Sjkim * 21217365Sjkim * Revision 2.1 1993/11/22 10:52:33 davidg 22217365Sjkim * patch to add support for SMC8216 (Elite-Ultra) boards 23217365Sjkim * from Glen H. Lowe 24217365Sjkim * 2567754Smsmith * Revision 2.0 93/09/29 00:37:15 davidg 26217365Sjkim * changed double buffering flag to multi buffering 27217365Sjkim * made changes/additions for 3c503 multi-buffering 28217365Sjkim * ...companion to Rev. 2.0 of 'ed' driver. 2967754Smsmith * 30217365Sjkim * Revision 1.1 93/06/23 03:01:07 davidg 31217365Sjkim * Initial revision 32217365Sjkim * 33217365Sjkim */ 34217365Sjkim 35217365Sjkim/* 36217365Sjkim * Page 0 register offsets 37217365Sjkim */ 38217365Sjkim#define ED_P0_CR 0x00 /* Command Register */ 39217365Sjkim 40217365Sjkim#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 41217365Sjkim#define ED_P0_PSTART 0x01 /* Page Start register (write) */ 42217365Sjkim 4367754Smsmith#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 44193341Sjkim#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ 45193341Sjkim 46193341Sjkim#define ED_P0_BNRY 0x03 /* Boundary Pointer */ 47193341Sjkim 48228110Sjkim#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ 49193341Sjkim#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ 50193341Sjkim 51138287Smarks#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 52102550Siwasaki#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 5367754Smsmith 54102550Siwasaki#define ED_P0_FIFO 0x06 /* FIFO register (read) */ 5591116Smsmith#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 5667754Smsmith 57198237Sjkim#define ED_P0_ISR 0x07 /* Interrupt Status Register */ 58151937Sjkim 5967754Smsmith#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 60151937Sjkim#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 61151937Sjkim 62151937Sjkim#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 63151937Sjkim#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 64151937Sjkim 65151937Sjkim#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 66151937Sjkim 67151937Sjkim#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 68151937Sjkim 69151937Sjkim#define ED_P0_RSR 0x0c /* Receive Status (read) */ 70151937Sjkim#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 71151937Sjkim 72228110Sjkim#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 73228110Sjkim#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 74228110Sjkim 75228110Sjkim#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ 76151937Sjkim#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ 77228110Sjkim 78228110Sjkim#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ 79228110Sjkim#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 80228110Sjkim 81228110Sjkim/* 82228110Sjkim * Page 1 register offsets 83228110Sjkim */ 84245582Sjkim#define ED_P1_CR 0x00 /* Command Register */ 85245582Sjkim#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ 86245582Sjkim#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ 87228110Sjkim#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ 88245582Sjkim#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ 89138287Smarks#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ 90138287Smarks#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ 91151937Sjkim#define ED_P1_PAR(i) (ED_P1_PAR0 + i) 92151937Sjkim#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ 93245582Sjkim#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ 94151937Sjkim#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ 95151937Sjkim#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ 96151937Sjkim#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ 97241973Sjkim#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ 98245582Sjkim#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ 99151937Sjkim#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ 100151937Sjkim#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ 101151937Sjkim#define ED_P1_MAR(i) (ED_P1_MAR0 + i) 102218590Sjkim 103151937Sjkim/* 104151937Sjkim * Page 2 register offsets 105151937Sjkim */ 106151937Sjkim#define ED_P2_CR 0x00 /* Command Register */ 107252279Sjkim#define ED_P2_PSTART 0x01 /* Page Start (read) */ 108151937Sjkim#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 109151937Sjkim#define ED_P2_PSTOP 0x02 /* Page Stop (read) */ 110151937Sjkim#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 111151937Sjkim#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 112151937Sjkim#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ 113151937Sjkim#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ 114252279Sjkim#define ED_P2_ACU 0x06 /* Address Counter Upper */ 115252279Sjkim#define ED_P2_ACL 0x07 /* Address Counter Lower */ 116151937Sjkim#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ 117151937Sjkim#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 118281075Sdim#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ 119151937Sjkim#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 120151937Sjkim 121151937Sjkim/* 122151937Sjkim * Command Register (CR) definitions 123151937Sjkim */ 124151937Sjkim 125151937Sjkim/* 126151937Sjkim * STP: SToP. Software reset command. Takes the controller offline. No 127281075Sdim * packets will be received or transmitted. Any reception or 128151937Sjkim * transmission in progress will continue to completion before 129151937Sjkim * entering reset state. To exit this state, the STP bit must 130151937Sjkim * reset and the STA bit must be set. The software reset has 131151937Sjkim * executed only when indicated by the RST bit in the ISR being 132151937Sjkim * set. 133151937Sjkim */ 134245582Sjkim#define ED_CR_STP 0x01 135245582Sjkim 136245582Sjkim/* 137151937Sjkim * STA: STArt. This bit is used to activate the NIC after either power-up, 138151937Sjkim * or when the NIC has been put in reset mode by software command 139151937Sjkim * or error. 140151937Sjkim */ 141281075Sdim#define ED_CR_STA 0x02 142281075Sdim 143151937Sjkim/* 144151937Sjkim * TXP: Transmit Packet. This bit must be set to indicate transmission of 145151937Sjkim * a packet. TXP is internally reset either after the transmission is 146151937Sjkim * completed or aborted. This bit should be set only after the Transmit 147151937Sjkim * Byte Count and Transmit Page Start register have been programmed. 148151937Sjkim */ 149151937Sjkim#define ED_CR_TXP 0x04 150151937Sjkim 151151937Sjkim/* 152151937Sjkim * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 153138287Smarks * of the remote DMA channel. RD2 can be set to abort any remote DMA 154138287Smarks * command in progress. The Remote Byte Count registers should be cleared 155245582Sjkim * when a remote DMA has been aborted. The Remote Start Addresses are not 156245582Sjkim * restored to the starting address if the remote DMA is aborted. 157138287Smarks * 158138287Smarks * RD2 RD1 RD0 function 159138287Smarks * 0 0 0 not allowed 160245582Sjkim * 0 0 1 remote read 161138287Smarks * 0 1 0 remote write 162138287Smarks * 0 1 1 send packet 163138287Smarks * 1 X X abort 164129684Snjl */ 165129684Snjl#define ED_CR_RD0 0x08 166129684Snjl#define ED_CR_RD1 0x10 167129684Snjl#define ED_CR_RD2 0x20 168129684Snjl 169245582Sjkim/* 170129684Snjl * PS0, PS1: Page Select. The two bits select which register set or 'page' to 171129684Snjl * access. 172231844Sjkim * 173231844Sjkim * PS1 PS0 page 174231844Sjkim * 0 0 0 175245582Sjkim * 0 1 1 176245582Sjkim * 1 0 2 177245582Sjkim * 1 1 3 (some chips it is reserved) 178245582Sjkim */ 179245582Sjkim#define ED_CR_PS0 0x40 180245582Sjkim#define ED_CR_PS1 0x80 181245582Sjkim/* bit encoded aliases */ 182245582Sjkim#define ED_CR_PAGE_0 0x00 /* (for consistency) */ 183245582Sjkim#define ED_CR_PAGE_1 0x40 184245582Sjkim#define ED_CR_PAGE_2 0x80 185245582Sjkim#define ED_CR_PAGE_3 0xc0 186245582Sjkim 187245582Sjkim/* 188245582Sjkim * Interrupt Status Register (ISR) definitions 189245582Sjkim */ 190245582Sjkim 191245582Sjkim/* 192129684Snjl * PRX: Packet Received. Indicates packet received with no errors. 193245582Sjkim */ 194245582Sjkim#define ED_ISR_PRX 0x01 195245582Sjkim 196129684Snjl/* 197245582Sjkim * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 198245582Sjkim */ 199245582Sjkim#define ED_ISR_PTX 0x02 200245582Sjkim 201245582Sjkim/* 202245582Sjkim * RXE: Receive Error. Indicates that a packet was received with one or more 203245582Sjkim * the following errors: CRC error, frame alignment error, FIFO overrun, 204245582Sjkim * missed packet. 205245582Sjkim */ 206245582Sjkim#define ED_ISR_RXE 0x04 207245582Sjkim 208245582Sjkim/* 209245582Sjkim * TXE: Transmission Error. Indicates that an attempt to transmit a packet 210245582Sjkim * resulted in one or more of the following errors: excessive 211245582Sjkim * collisions, FIFO underrun. 212245582Sjkim */ 213245582Sjkim#define ED_ISR_TXE 0x08 214245582Sjkim 215245582Sjkim/* 216245582Sjkim * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 217245582Sjkim * would exceed (has exceeded?) the boundary pointer, resulting in data 218245582Sjkim * that was previously received and not yet read from the buffer to be 219245582Sjkim * overwritten. 220245582Sjkim */ 221245582Sjkim#define ED_ISR_OVW 0x10 222245582Sjkim 223245582Sjkim/* 224245582Sjkim * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley 225245582Sjkim * Counters has been set. 226245582Sjkim */ 227245582Sjkim#define ED_ISR_CNT 0x20 228245582Sjkim 229245582Sjkim/* 230245582Sjkim * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed. 231245582Sjkim */ 232245582Sjkim#define ED_ISR_RDC 0x40 233245582Sjkim 234245582Sjkim/* 235245582Sjkim * RST: Reset status. Set when the NIC enters the reset state and cleared when a 236245582Sjkim * Start Command is issued to the CR. This bit is also set when a receive 237245582Sjkim * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 238245582Sjkim * packets have been removed from the ring. This is a read-only bit. 239245582Sjkim */ 240245582Sjkim#define ED_ISR_RST 0x80 241245582Sjkim 242245582Sjkim/* 243245582Sjkim * Interrupt Mask Register (IMR) definitions 244245582Sjkim */ 245245582Sjkim 246245582Sjkim/* 247245582Sjkim * PRXE: Packet Received interrupt Enable. If set, a received packet will cause 248245582Sjkim * an interrupt. 249245582Sjkim */ 250129684Snjl#define ED_IMR_PRXE 0x01 251129684Snjl 252129684Snjl/* 253231844Sjkim * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when 254129684Snjl * a packet transmission completes. 255129684Snjl */ 256245582Sjkim#define ED_IMR_PTXE 0x02 257245582Sjkim 258239340Sjkim/* 259129684Snjl * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a 260129684Snjl * packet is received with an error. 261231844Sjkim */ 262129684Snjl#define ED_IMR_RXEE 0x04 263129684Snjl 264245582Sjkim/* 265245582Sjkim * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever 266239340Sjkim * a transmission results in an error. 267231844Sjkim */ 268231844Sjkim#define ED_IMR_TXEE 0x08 269231844Sjkim 270231844Sjkim/* 271231844Sjkim * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever 272245582Sjkim * the receive ring-buffer is overrun. i.e. when the boundary pointer is exceeded. 273245582Sjkim */ 274129684Snjl#define ED_IMR_OVWE 0x10 275231844Sjkim 276231844Sjkim/* 277231844Sjkim * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever 278231844Sjkim * the MSB of one or more of the Network Statistics counters has been set. 279129684Snjl */ 280245582Sjkim#define ED_IMR_CNTE 0x20 281231844Sjkim 282231844Sjkim/* 283231844Sjkim * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated 284245582Sjkim * when a remote DMA transfer has completed. 285245582Sjkim */ 286129684Snjl#define ED_IMR_RDCE 0x40 287129684Snjl 288231844Sjkim/* 28967754Smsmith * bit 7 is unused/reserved 29067754Smsmith */ 29177424Smsmith 29277424Smsmith/* 29377424Smsmith * Data Configuration Register (DCR) definitions 29477424Smsmith */ 29577424Smsmith 29677424Smsmith/* 29777424Smsmith * WTS: Word Transfer Select. WTS establishes byte or word transfers for 29877424Smsmith * both remote and local DMA transfers 29977424Smsmith */ 30077424Smsmith#define ED_DCR_WTS 0x01 30177424Smsmith 302151937Sjkim/* 303151937Sjkim * BOS: Byte Order Select. BOS sets the byte order for the host. 30477424Smsmith * Should be 0 for 80x86, and 1 for 68000 series processors 30577424Smsmith */ 30677424Smsmith#define ED_DCR_BOS 0x02 30777424Smsmith 308167802Sjkim/* 30977424Smsmith * LAS: Long Address Select. When LAS is 1, the contents of the remote 31077424Smsmith * DMA registers RSAR0 and RSAR1 are used to provide A16-A31 311167802Sjkim */ 312167802Sjkim#define ED_DCR_LAS 0x04 31377424Smsmith 31477424Smsmith/* 31577424Smsmith * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 31677424Smsmith * of the TCR must also be programmed for loopback operation. 31777424Smsmith * When 1, normal operation is selected. 31877424Smsmith */ 31967754Smsmith#define ED_DCR_LS 0x08 32067754Smsmith 321245582Sjkim/* 32267754Smsmith * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 32367754Smsmith * under program control. When 1, remote DMA is automatically initiated 32467754Smsmith * and the boundary pointer is automatically updated 325241973Sjkim */ 32667754Smsmith#define ED_DCR_AR 0x10 32767754Smsmith 32867754Smsmith/* 32967754Smsmith * FT0, FT1: Fifo Threshold select. 33067754Smsmith * FT1 FT0 Word-width Byte-width 33167754Smsmith * 0 0 1 word 2 bytes 332114237Snjl * 0 1 2 words 4 bytes 33367754Smsmith * 1 0 4 words 8 bytes 334193267Sjkim * 1 1 8 words 12 bytes 335117521Snjl * 336193267Sjkim * During transmission, the FIFO threshold indicates the number of bytes 33767754Smsmith * or words that the FIFO has filled from the local DMA before BREQ is 33867754Smsmith * asserted. The transmission threshold is 16 bytes minus the receiver 339238381Sjkim * threshold. 340238381Sjkim */ 341281075Sdim#define ED_DCR_FT0 0x20 342238381Sjkim#define ED_DCR_FT1 0x40 343193267Sjkim 344193267Sjkim/* 345207344Sjkim * bit 7 (0x80) is unused/reserved 34667754Smsmith */ 347167802Sjkim 348167802Sjkim/* 349238381Sjkim * Transmit Configuration Register (TCR) definitions 350238381Sjkim */ 351238381Sjkim 352238381Sjkim/* 353238381Sjkim * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 354238381Sjkim * is not appended by the transmitter. 355238381Sjkim */ 356238381Sjkim#define ED_TCR_CRC 0x01 357238381Sjkim 358238381Sjkim/* 359238381Sjkim * LB0, LB1: Loopback control. These two bits set the type of loopback that is 360238381Sjkim * to be performed. 361238381Sjkim * 362238381Sjkim * LB1 LB0 mode 363238381Sjkim * 0 0 0 - normal operation (DCR_LS = 0) 364238381Sjkim * 0 1 1 - internal loopback (DCR_LS = 0) 365238381Sjkim * 1 0 2 - external loopback (DCR_LS = 1) 366281075Sdim * 1 1 3 - external loopback (DCR_LS = 0) 367250838Sjkim */ 368281075Sdim#define ED_TCR_LB0 0x02 369238381Sjkim#define ED_TCR_LB1 0x04 370238381Sjkim 371281075Sdim/* 372250838Sjkim * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 373281075Sdim * another station to disable the NIC's transmitter by transmitting to 374238381Sjkim * a multicast address hashing to bit 62. Reception of a multicast address 375238381Sjkim * hashing to bit 63 enables the transmitter. 376281075Sdim */ 377250838Sjkim#define ED_TCR_ATD 0x08 378281075Sdim 379238381Sjkim/* 380238381Sjkim * OFST: Collision Offset enable. This bit when set modifies the backoff 381238381Sjkim * algorithm to allow prioritization of nodes. 382250838Sjkim */ 383281075Sdim#define ED_TCR_OFST 0x10 384238381Sjkim 385238381Sjkim/* 386238381Sjkim * bits 5, 6, and 7 are unused/reserved 387193267Sjkim */ 388193267Sjkim 389281075Sdim/* 390193267Sjkim * Transmit Status Register (TSR) definitions 39167754Smsmith */ 392193267Sjkim 39367754Smsmith/* 394193267Sjkim * PTX: Packet Transmitted. Indicates successful transmission of packet. 395193267Sjkim */ 396193267Sjkim#define ED_TSR_PTX 0x01 397193267Sjkim 398193267Sjkim/* 399193267Sjkim * bit 1 (0x02) is unused/reserved 400193267Sjkim */ 401193267Sjkim 402193267Sjkim/* 403193267Sjkim * COL: Transmit Collided. Indicates that the transmission collided at least 404193267Sjkim * once with another station on the network. 405193267Sjkim */ 406193267Sjkim#define ED_TSR_COL 0x04 407193267Sjkim 40867754Smsmith/* 40967754Smsmith * ABT: Transmit aborted. Indicates that the transmission was aborted due to 41067754Smsmith * excessive collisions. 41167754Smsmith */ 41267754Smsmith#define ED_TSR_ABT 0x08 41367754Smsmith 41467754Smsmith/* 41567754Smsmith * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 416238381Sjkim * transmission of the packet. (Transmission is not aborted because 417238381Sjkim * of a loss of carrier) 41867754Smsmith */ 419238381Sjkim#define ED_TSR_CRS 0x10 42067754Smsmith 421238381Sjkim/* 422238381Sjkim * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 42367754Smsmith * transmission memory before the FIFO emptied. Transmission of the 42467754Smsmith * packet was aborted. 42567754Smsmith */ 42667754Smsmith#define ED_TSR_FU 0x20 42767754Smsmith 428238381Sjkim/* 42967754Smsmith * CDH: CD Heartbeat. Indicates that the collision detection circuitry 430238381Sjkim * isn't working correctly during a collision heartbeat test. 43167754Smsmith */ 43267754Smsmith#define ED_TSR_CDH 0x40 43367754Smsmith 434238381Sjkim/* 43567754Smsmith * OWC: Out of Window Collision: Indicates that a collision occurred after 436238381Sjkim * a slot time (51.2us). The transmission is rescheduled just as in 437238381Sjkim * normal collisions. 43867754Smsmith */ 439238381Sjkim#define ED_TSR_OWC 0x80 440238381Sjkim 44167754Smsmith/* 442238381Sjkim * Receiver Configuration Register (RCR) definitions 443238381Sjkim */ 444238381Sjkim 445238381Sjkim/* 446238381Sjkim * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 44767754Smsmith * packets with CRC and frame errors are not discarded. 448238381Sjkim */ 449238381Sjkim#define ED_RCR_SEP 0x01 450238381Sjkim 451238381Sjkim/* 452238381Sjkim * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 45367754Smsmith * If set to 1, packets with less than 64 byte are not discarded. 45467754Smsmith */ 45567754Smsmith#define ED_RCR_AR 0x02 45667754Smsmith 45767754Smsmith/* 45867754Smsmith * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 45967754Smsmith * accepted. 460245582Sjkim */ 461245582Sjkim#define ED_RCR_AB 0x04 46267754Smsmith 46367754Smsmith/* 46467754Smsmith * AM: Accept Multicast. If set, packets sent to a multicast address are checked 465241973Sjkim * for a match in the hashing array. If clear, multicast packets are ignored. 46667754Smsmith */ 46767754Smsmith#define ED_RCR_AM 0x08 46867754Smsmith 46967754Smsmith/* 47067754Smsmith * PRO: Promiscuous Physical. If set, all packets with a physical addresses are 47167754Smsmith * accepted. If clear, a physical destination address must match this 472114237Snjl * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM 47367754Smsmith * must also be set. In addition, the multicast hashing array must be set 47467754Smsmith * to all 1's so that all multicast addresses are accepted. 47567754Smsmith */ 47699679Siwasaki#define ED_RCR_PRO 0x10 47767754Smsmith 47867754Smsmith/* 47967754Smsmith * MON: Monitor Mode. If set, packets will be checked for good CRC and framing, 48067754Smsmith * but are not stored in the ring-buffer. If clear, packets are stored (normal 481151937Sjkim * operation). 48267754Smsmith */ 48367754Smsmith#define ED_RCR_MON 0x20 48467754Smsmith 48567754Smsmith/* 48667754Smsmith * INTT: Interrupt Trigger Mode for AX88190. 487234623Sjkim */ 48867754Smsmith#define ED_RCR_INTT 0x40 489234623Sjkim 49067754Smsmith/* 49199679Siwasaki * bit 7 is unused/reserved. 49299679Siwasaki */ 49399679Siwasaki 49499679Siwasaki/* 49599679Siwasaki * Receiver Status Register (RSR) definitions 49667754Smsmith */ 497234623Sjkim 498234623Sjkim/* 499245582Sjkim * PRX: Packet Received without error. 500245582Sjkim */ 501234623Sjkim#define ED_RSR_PRX 0x01 502234623Sjkim 50367754Smsmith/* 50467754Smsmith * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame 50567754Smsmith * alignment errors. 50667754Smsmith */ 50767754Smsmith#define ED_RSR_CRC 0x02 508210976Sjkim 509210976Sjkim/* 510210976Sjkim * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on 511210976Sjkim * a byte boundary and the CRC did not match at the last byte boundary. 512210976Sjkim */ 513210976Sjkim#define ED_RSR_FAE 0x04 514210976Sjkim 515210976Sjkim/* 516210976Sjkim * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA) 517210976Sjkim * causing it to overrun. Reception of the packet is aborted. 518210976Sjkim */ 519210976Sjkim#define ED_RSR_FO 0x08 520210976Sjkim 521210976Sjkim/* 522210976Sjkim * MPA: Missed Packet. Indicates that the received packet couldn't be stored in 523210976Sjkim * the ring-buffer because of insufficient buffer space (exceeding the 524210976Sjkim * boundary pointer), or because the transfer to the ring-buffer was inhibited 525210976Sjkim * by RCR_MON - monitor mode. 526210976Sjkim */ 527210976Sjkim#define ED_RSR_MPA 0x10 528210976Sjkim 529210976Sjkim/* 530210976Sjkim * PHY: Physical address. If 0, the packet received was sent to a physical address. 531210976Sjkim * If 1, the packet was accepted because of a multicast/broadcast address 532210976Sjkim * match. 533210976Sjkim */ 534210976Sjkim#define ED_RSR_PHY 0x20 535210976Sjkim 536210976Sjkim/* 537210976Sjkim * DIS: Receiver Disabled. Set to indicate that the receiver has entered monitor 538210976Sjkim * mode. Cleared when the receiver exits monitor mode. 539210976Sjkim */ 540210976Sjkim#define ED_RSR_DIS 0x40 541210976Sjkim 542210976Sjkim/* 543210976Sjkim * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs 544210976Sjkim * are active, and the transceiver has set the CD line as a result of the 545210976Sjkim * jabber. 546210976Sjkim */ 547210976Sjkim#define ED_RSR_DFR 0x80 548210976Sjkim 549210976Sjkim/* 550210976Sjkim * receive ring descriptor 551210976Sjkim * 552210976Sjkim * The National Semiconductor DS8390 Network interface controller uses 553210976Sjkim * the following receive ring headers. The way this works is that the 554210976Sjkim * memory on the interface card is chopped up into 256 bytes blocks. 555210976Sjkim * A contiguous portion of those blocks are marked for receive packets 556210976Sjkim * by setting start and end block #'s in the NIC. For each packet that 557210976Sjkim * is put into the receive ring, one of these headers (4 bytes each) is 558210976Sjkim * tacked onto the front. The first byte is a copy of the receiver status 559210976Sjkim * register at the time the packet was received. 560210976Sjkim */ 561210976Sjkimstruct ed_ring { 562210976Sjkim u_char rsr; /* receiver status */ 563210976Sjkim u_char next_packet; /* pointer to next packet */ 564210976Sjkim u_short count; /* bytes in packet (length + 4) */ 565210976Sjkim}; 566210976Sjkim 567210976Sjkim/* 568210976Sjkim * Common constants 569210976Sjkim */ 570210976Sjkim#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 571210976Sjkim#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 572210976Sjkim 573210976Sjkim/* 574210976Sjkim * Definitions for Western digital/SMC WD80x3 series ASIC 575210976Sjkim */ 576210976Sjkim/* 577210976Sjkim * Memory Select Register (MSR) 578210976Sjkim */ 579210976Sjkim#define ED_WD_MSR 0 580210976Sjkim 581210976Sjkim/* next three definitions for Toshiba */ 582210976Sjkim#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */ 583210976Sjkim#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */ 584210976Sjkim#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits, 585210976Sjkim 1 = 8 bits (R/W) */ 586210976Sjkim#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ 587210976Sjkim#define ED_WD_MSR_MENB 0x40 /* Memory enable */ 588210976Sjkim#define ED_WD_MSR_RST 0x80 /* Reset board */ 589210976Sjkim 590210976Sjkim/* 591210976Sjkim * Interface Configuration Register (ICR) 592210976Sjkim */ 593210976Sjkim#define ED_WD_ICR 1 594210976Sjkim 595210976Sjkim#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */ 596210976Sjkim#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */ 597210976Sjkim#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */ 598210976Sjkim#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ 599228110Sjkim#define ED_WD_ICR_RLA 0x10 /* recall LAN address */ 600228110Sjkim#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */ 601245582Sjkim#define ED_WD_ICR_RIO 0x40 /* recall i/o address */ 602228110Sjkim#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */ 603228110Sjkim#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */ 604228110Sjkim#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K, 605228110Sjkim 0x02 = 16K, 0x01 = 8K */ 606228110Sjkim /* 64K can only be used if mem address 607228110Sjkim above 1Mb */ 608228110Sjkim /* IAR holds address A23-A16 (R/W) */ 609228110Sjkim 610228110Sjkim/* 611228110Sjkim * IO Address Register (IAR) 612228110Sjkim */ 613228110Sjkim#define ED_WD_IAR 2 614228110Sjkim 615245582Sjkim/* 616228110Sjkim * EEROM Address Register 617228110Sjkim */ 618228110Sjkim#define ED_WD_EAR 3 619228110Sjkim 620228110Sjkim/* 621228110Sjkim * Interrupt Request Register (IRR) 622228110Sjkim */ 623228110Sjkim#define ED_WD_IRR 4 624228110Sjkim 625228110Sjkim#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ 626228110Sjkim#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ 627228110Sjkim#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ 628228110Sjkim#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ 629228110Sjkim#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ 630228110Sjkim 631228110Sjkim/* 632228110Sjkim * The three bits of the encoded IRQ are decoded as follows: 633228110Sjkim * 634228110Sjkim * IR2 IR1 IR0 IRQ 635228110Sjkim * 0 0 0 2/9 636245582Sjkim * 0 0 1 3 637245582Sjkim * 0 1 0 5 638228110Sjkim * 0 1 1 7 639228110Sjkim * 1 0 0 10 640228110Sjkim * 1 0 1 11 641245582Sjkim * 1 1 0 15 642228110Sjkim * 1 1 1 4 643228110Sjkim */ 644228110Sjkim#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 645228110Sjkim#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 646228110Sjkim#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */ 647228110Sjkim 648228110Sjkim/* 649228110Sjkim * LA Address Register (LAAR) 650228110Sjkim */ 651228110Sjkim#define ED_WD_LAAR 5 652228110Sjkim 653228110Sjkim#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ 654228110Sjkim#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ 655228110Sjkim#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */ 656245582Sjkim#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */ 657228110Sjkim 658228110Sjkim/* i/o base offset to station address/card-ID PROM */ 659228110Sjkim#define ED_WD_PROM 8 660241973Sjkim 661228110Sjkim/* 662228110Sjkim * 83C790 specific registers 663228110Sjkim */ 664228110Sjkim/* 665228110Sjkim * Hardware Support Register (HWR) ('790) 666228110Sjkim */ 667228110Sjkim#define ED_WD790_HWR 4 668228110Sjkim 669228110Sjkim#define WD_WD790_HWR_NUKE 0x10 /* hardware reset */ 670228110Sjkim#define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */ 671151937Sjkim#define ED_WD790_HWR_SWH 0x80 /* switch register set */ 672151937Sjkim 673151937Sjkim/* 674151937Sjkim * ICR790 Interrupt Control Register for the 83C790 675151937Sjkim */ 676151937Sjkim#define ED_WD790_ICR 6 677151937Sjkim 678151937Sjkim#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */ 679151937Sjkim 680151937Sjkim/* 681151937Sjkim * REV/IOPA Revision / I/O Pipe register for the 83C79X 682151937Sjkim */ 683151937Sjkim#define ED_WD790_REV 7 684151937Sjkim 685151937Sjkim#define ED_WD790 0x20 686151937Sjkim#define ED_WD795 0x40 687151937Sjkim 688151937Sjkim/* 689151937Sjkim * 79X RAM Address Register (RAR) 690151937Sjkim * Enabled with SWH bit=1 in HWR register 691151937Sjkim */ 692151937Sjkim#define ED_WD790_RAR 0x0b 693151937Sjkim 694228110Sjkim#define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */ 695228110Sjkim#define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */ 696151937Sjkim#define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */ 697151937Sjkim#define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */ 698151937Sjkim 699151937Sjkim/* 700151937Sjkim * General Control Register (GCR) 701228110Sjkim * Enabled with SWH bit=1 in HWR register 702151937Sjkim */ 703151937Sjkim#define ED_WD790_GCR 0x0d 704151937Sjkim 705151937Sjkim#define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */ 706151937Sjkim#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */ 707151937Sjkim#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */ 708151937Sjkim#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */ 709228110Sjkim#define ED_WD790_GCR_LIT 0x01 /* Link Integrity Test Enable */ 710151937Sjkim/* 711151937Sjkim * The three bits of the encoded IRQ are decoded as follows: 712151937Sjkim * 713151937Sjkim * IR2 IR1 IR0 IRQ 714151937Sjkim * 0 0 0 none 715228110Sjkim * 0 0 1 9 716228110Sjkim * 0 1 0 3 717151937Sjkim * 0 1 1 5 718151937Sjkim * 1 0 0 7 719151937Sjkim * 1 0 1 10 720228110Sjkim * 1 1 0 11 721151937Sjkim * 1 1 1 15 722151937Sjkim */ 723151937Sjkim 724151937Sjkim/* i/o base offset to CARD ID */ 725151937Sjkim#define ED_WD_CARD_ID ED_WD_PROM+6 726151937Sjkim 727151937Sjkim/* Board type codes in card ID */ 728151937Sjkim#define ED_TYPE_WD8003S 0x02 729151937Sjkim#define ED_TYPE_WD8003E 0x03 730151937Sjkim#define ED_TYPE_WD8013EBT 0x05 731151937Sjkim#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */ 732151937Sjkim#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */ 733228110Sjkim#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */ 734151937Sjkim#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */ 735151937Sjkim#define ED_TYPE_WD8003W 0x24 736151937Sjkim#define ED_TYPE_WD8003EB 0x25 737151937Sjkim#define ED_TYPE_WD8013W 0x26 738151937Sjkim#define ED_TYPE_WD8013EP 0x27 739167802Sjkim#define ED_TYPE_WD8013WC 0x28 740151937Sjkim#define ED_TYPE_WD8013EPC 0x29 741151937Sjkim#define ED_TYPE_SMC8216T 0x2a 742151937Sjkim#define ED_TYPE_SMC8216C 0x2b 743151937Sjkim#define ED_TYPE_WD8013EBP 0x2c 744228110Sjkim 745228110Sjkim/* Bit definitions in card ID */ 746228110Sjkim#define ED_WD_REV_MASK 0x1f /* Revision mask */ 747228110Sjkim#define ED_WD_SOFTCONFIG 0x20 /* Soft config */ 748228110Sjkim#define ED_WD_LARGERAM 0x40 /* Large RAM */ 749245582Sjkim#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ 750245582Sjkim 751228110Sjkim/* 752228110Sjkim * Checksum total. All 8 bytes in station address PROM will add up to this 753228110Sjkim */ 754151937Sjkim#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF 755151937Sjkim#define ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER 0xA5 756151937Sjkim 757151937Sjkim#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */ 758151937Sjkim#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */ 759151937Sjkim#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */ 760151937Sjkim 761151937Sjkim#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */ 762151937Sjkim 763151937Sjkim/* 764151937Sjkim * Definitions for 3Com 3c503 765151937Sjkim */ 766151937Sjkim#define ED_3COM_NIC_OFFSET 0 767151937Sjkim#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ 768167802Sjkim 769151937Sjkim/* 770151937Sjkim * XXX - The I/O address range is fragmented in the 3c503; this is the 771151937Sjkim * number of regs at iobase. 772151937Sjkim */ 773151937Sjkim#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */ 774151937Sjkim 775151937Sjkim/* tx memory starts in second bank on 8bit cards */ 776151937Sjkim#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20 777245582Sjkim 778245582Sjkim/* tx memory starts in first bank on 16bit cards */ 779151937Sjkim#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0 780151937Sjkim 781151937Sjkim/* ...and rx memory starts in second bank */ 782151937Sjkim#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20 783151937Sjkim 784151937Sjkim 785151937Sjkim/* 786151937Sjkim * Page Start Register. Must match PSTART in NIC 787151937Sjkim */ 788151937Sjkim#define ED_3COM_PSTR 0 789151937Sjkim 790151937Sjkim/* 791151937Sjkim * Page Stop Register. Must match PSTOP in NIC 792151937Sjkim */ 793245582Sjkim#define ED_3COM_PSPR 1 794245582Sjkim 795151937Sjkim/* 796151937Sjkim * Drq Timer Register. Determines number of bytes to be transfered during 797151937Sjkim * a DMA burst. 798151937Sjkim */ 799151937Sjkim#define ED_3COM_DQTR 2 800151937Sjkim 801151937Sjkim/* 802245582Sjkim * Base Configuration Register. Read-only register which contains the 803245582Sjkim * board-configured I/O base address of the adapter. Bit encoded. 804151937Sjkim */ 805151937Sjkim#define ED_3COM_BCFR 3 806151937Sjkim 807245582Sjkim#define ED_3COM_BCFR_2E0 0x01 808151937Sjkim#define ED_3COM_BCFR_2A0 0x02 809151937Sjkim#define ED_3COM_BCFR_280 0x04 810151937Sjkim#define ED_3COM_BCFR_250 0x08 811151937Sjkim#define ED_3COM_BCFR_350 0x10 812151937Sjkim#define ED_3COM_BCFR_330 0x20 813151937Sjkim#define ED_3COM_BCFR_310 0x40 814151937Sjkim#define ED_3COM_BCFR_300 0x80 815151937Sjkim 816151937Sjkim/* 817245582Sjkim * EPROM Configuration Register. Read-only register which contains the 818151937Sjkim * board-configured memory base address. Bit encoded. 819151937Sjkim */ 820151937Sjkim#define ED_3COM_PCFR 4 821151937Sjkim 822151937Sjkim#define ED_3COM_PCFR_C8000 0x10 823151937Sjkim#define ED_3COM_PCFR_CC000 0x20 824151937Sjkim#define ED_3COM_PCFR_D8000 0x40 825151937Sjkim#define ED_3COM_PCFR_DC000 0x80 826151937Sjkim 827281075Sdim/* 828151937Sjkim * GA Configuration Register. Gate-Array Configuration Register. 829151937Sjkim */ 830151937Sjkim#define ED_3COM_GACFR 5 831151937Sjkim 832151937Sjkim/* 833151937Sjkim * mbs2 mbs1 mbs0 start address 834151937Sjkim * 0 0 0 0x0000 835151937Sjkim * 0 0 1 0x2000 836151937Sjkim * 0 1 0 0x4000 837245582Sjkim * 0 1 1 0x6000 838151937Sjkim * 839281075Sdim * Note that with adapters with only 8K, the setting for 0x2000 must 840281075Sdim * always be used. 841193267Sjkim */ 842151937Sjkim#define ED_3COM_GACFR_MBS0 0x01 843151937Sjkim#define ED_3COM_GACFR_MBS1 0x02 844151937Sjkim#define ED_3COM_GACFR_MBS2 0x04 845167802Sjkim 846151937Sjkim#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */ 847245582Sjkim#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */ 848151937Sjkim#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ 849245582Sjkim#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ 850151937Sjkim#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ 851151937Sjkim 852151937Sjkim/* 853151937Sjkim * Control Register. Miscellaneous control functions. 854151937Sjkim */ 855151937Sjkim#define ED_3COM_CR 6 856228110Sjkim 85773561Smsmith#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */ 858228110Sjkim#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 85973561Smsmith#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 860228110Sjkim#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 86173561Smsmith#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */ 862245582Sjkim#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */ 863245582Sjkim#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */ 86473561Smsmith#define ED_3COM_CR_START 0x80 /* Start DMA controller */ 86573561Smsmith 86673561Smsmith/* 867228110Sjkim * Status Register. Miscellaneous status information. 868228110Sjkim */ 869228110Sjkim#define ED_3COM_STREG 7 870228110Sjkim 87173561Smsmith#define ED_3COM_STREG_REV 0x07 /* GA revision */ 872228110Sjkim#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */ 873228110Sjkim#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */ 874228110Sjkim#define ED_3COM_STREG_OFLW 0x20 /* Overflow */ 875228110Sjkim#define ED_3COM_STREG_UFLW 0x40 /* Underflow */ 876228110Sjkim#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */ 877228110Sjkim 878228110Sjkim/* 879228110Sjkim * Interrupt/DMA Configuration Register 880228110Sjkim */ 881228110Sjkim#define ED_3COM_IDCFR 8 882228110Sjkim 883228110Sjkim#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ 884228110Sjkim#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ 885228110Sjkim#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ 886228110Sjkim#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */ 887228110Sjkim#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 888228110Sjkim#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 889228110Sjkim#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 890228110Sjkim#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 891228110Sjkim 892228110Sjkim/* 893228110Sjkim * DMA Address Register MSB 894228110Sjkim */ 895228110Sjkim#define ED_3COM_DAMSB 9 896151937Sjkim 897228110Sjkim/* 898228110Sjkim * DMA Address Register LSB 899228110Sjkim */ 900228110Sjkim#define ED_3COM_DALSB 0x0a 901228110Sjkim 902245582Sjkim/* 90373561Smsmith * Vector Pointer Register 2 90473561Smsmith */ 90573561Smsmith#define ED_3COM_VPTR2 0x0b 906228110Sjkim 907228110Sjkim/* 908228110Sjkim * Vector Pointer Register 1 909228110Sjkim */ 910228110Sjkim#define ED_3COM_VPTR1 0x0c 911228110Sjkim 91273561Smsmith/* 913228110Sjkim * Vector Pointer Register 0 91473561Smsmith */ 915228110Sjkim#define ED_3COM_VPTR0 0x0d 916228110Sjkim 917228110Sjkim/* 918228110Sjkim * Register File Access MSB 919228110Sjkim */ 920151937Sjkim#define ED_3COM_RFMSB 0x0e 921228110Sjkim 922151937Sjkim/* 92373561Smsmith * Register File Access LSB 924228110Sjkim */ 925228110Sjkim#define ED_3COM_RFLSB 0x0f 92673561Smsmith 92773561Smsmith/* 928245582Sjkim * Definitions for Novell NE1000/2000 boards 929245582Sjkim */ 93073561Smsmith 931228110Sjkim/* 93277424Smsmith * Board type codes 93377424Smsmith */ 934228110Sjkim#define ED_TYPE_NE1000 0x01 935228110Sjkim#define ED_TYPE_NE2000 0x02 936228110Sjkim 93777424Smsmith/* 938245582Sjkim * Register offsets/total 939228110Sjkim */ 940228110Sjkim#define ED_NOVELL_NIC_OFFSET 0x00 941228110Sjkim#define ED_NOVELL_ASIC_OFFSET 0x10 942228110Sjkim#define ED_NOVELL_IO_PORTS 32 943228110Sjkim 944228110Sjkim/* 945151937Sjkim * Remote DMA data register; for reading or writing to the NIC mem 946245582Sjkim * via programmed I/O (offset from ASIC base) 947245582Sjkim */ 94873561Smsmith#define ED_NOVELL_DATA 0x00 949245582Sjkim 950228110Sjkim/* 951228110Sjkim * Reset register; reading from this register causes a board reset 952228110Sjkim */ 953228110Sjkim#define ED_NOVELL_RESET 0x0f 954228110Sjkim 955228110Sjkim/* 95673561Smsmith * Definitions for PCCARD 957228110Sjkim */ 95877424Smsmith#define ED_PC_PAGE_OFFSET 0x40 /* page offset for NIC access to mem */ 95977424Smsmith#define ED_PC_IO_PORTS 32 96077424Smsmith#define ED_PC_ASIC_OFFSET 0x10 96177424Smsmith#define ED_PC_RESET 0x0f /* Reset(offset from ASIC base) */ 96283174Smsmith#define ED_PC_MISC 0x08 /* Misc (offset from ASIC base) */ 96383174Smsmith 964228110Sjkim/* 965228110Sjkim * if_ze.h constants 966228110Sjkim */ 96777424Smsmith 968245582Sjkim#define ZE_PAGE_OFFSET 0x40 /* mem buffer starts at 0x4000 */ 969245582Sjkim 97077424Smsmith#define ZE_DATA_IO 0x10 971245582Sjkim#define ZE_MISC 0x18 972228110Sjkim#define ZE_RESET 0x1F 973228110Sjkim 974228110Sjkim/* 975228110Sjkim * Definitions for HP PC LAN Adapter Plus; based on the CRYNWR packet 976228110Sjkim * driver for the card. 977228110Sjkim */ 978151937Sjkim 979245582Sjkim#define ED_HPP_ASIC_OFFSET 0x00 /* Offset to ASIC registers */ 98077424Smsmith#define ED_HPP_NIC_OFFSET 0x10 /* Offset to 8390 registers */ 981228110Sjkim 982228110Sjkim#define ED_HPP_ID 0x00 /* ID register, always 0x4850 */ 983228110Sjkim#define ED_HPP_PAGING 0x02 /* Page select register */ 984228110Sjkim#define ED_HPP_OPTION 0x04 /* Bitmask of supported options */ 985228110Sjkim#define ED_HPP_PAGE_0 0x08 /* Page 0 */ 986228110Sjkim#define ED_HPP_PAGE_2 0x0A /* Page 2 */ 987228110Sjkim#define ED_HPP_PAGE_4 0x0C /* Page 4 */ 988228110Sjkim#define ED_HPP_PAGE_6 0x0E /* Page 6 */ 98977424Smsmith 990245582Sjkim/* PERF PAGE */ 991151937Sjkim#define ED_HPP_OUT_ADDR ED_HPP_PAGE_0 /* I/O output location */ 992245582Sjkim#define ED_HPP_IN_ADDR ED_HPP_PAGE_2 /* I/O input location */ 993245582Sjkim#define ED_HPP_DATAPORT ED_HPP_PAGE_4 /* I/O data transfer */ 99477424Smsmith/* MAC PAGE */ 995245582Sjkim#define ED_HPP_MAC_ADDR 0x08 /* Offset of MAC address in MAC page */ 996228110Sjkim 997228110Sjkim#define ED_HPP_IO_PORTS 32 /* Number of IO ports */ 998228110Sjkim 999228110Sjkim#define ED_HPP_TX_PAGE_OFFSET 0x00 /* first page of TX buffer */ 1000228110Sjkim#define ED_HPP_RX_PAGE_START 0x06 /* start at page 6 */ 1001228110Sjkim#define ED_HPP_RX_PAGE_STOP 0x80 /* end at page 128 */ 1002151937Sjkim 1003245582Sjkim/* 1004245582Sjkim * Register pages supported. 1005245582Sjkim */ 1006245582Sjkim 1007245582Sjkim#define ED_HPP_PAGE_PERF 0 /* Normal operation */ 1008245582Sjkim#define ED_HPP_PAGE_MAC 1 /* The ethernet address and checksum */ 1009245582Sjkim#define ED_HPP_PAGE_HW 2 /* Hardware parameters in EEPROM */ 1010245582Sjkim#define ED_HPP_PAGE_LAN 4 /* Transciever selection etc */ 1011245582Sjkim#define ED_HPP_PAGE_ID 6 /* ID */ 1012245582Sjkim 1013245582Sjkim/* 1014228110Sjkim * Options supported. 1015151937Sjkim */ 1016228110Sjkim 1017245582Sjkim#define ED_HPP_OPTION_NIC_RESET 0x0001 /* active low */ 1018151937Sjkim#define ED_HPP_OPTION_CHIP_RESET 0x0002 /* active low */ 1019228110Sjkim#define ED_HPP_OPTION_ENABLE_IRQ 0x0004 1020245582Sjkim#define ED_HPP_OPTION_FAKE_INTR 0x0008 1021245582Sjkim#define ED_HPP_OPTION_BOOT_ROM_ENB 0x0010 1022245582Sjkim#define ED_HPP_OPTION_IO_ENB 0x0020 1023228110Sjkim#define ED_HPP_OPTION_MEM_ENABLE 0x0040 1024245582Sjkim#define ED_HPP_OPTION_ZERO_WAIT 0x0080 1025151937Sjkim#define ED_HPP_OPTION_MEM_DISABLE 0x1000 1026228110Sjkim 1027228110Sjkim/* 1028246849Sjkim * Page ID configuration. 1029246849Sjkim */ 1030245582Sjkim 1031228110Sjkim#define ED_HPP_ID_REVISION_MASK 0x0300 /* revision id */ 1032228110Sjkim#define ED_HPP_ID_SOFT_MODEL_MASK 0xFC00 /* soft model number */ 1033228110Sjkim#define ED_HPP_ID_16_BIT_ACCESS 0x0010 /* if set use 16 bit accesses */ 1034228110Sjkim#define ED_HPP_ID_TWISTED_PAIR 0x0040 1035245582Sjkim 1036228110Sjkim/* 1037245582Sjkim * Hardware configuration. 1038245582Sjkim */ 1039281075Sdim 104091116Smsmith#define ED_HPP_HW_MEM_MAP 0x09 /* low mem map location in HW page */ 104183174Smsmith#define ED_HPP_HW_ID 0x0C /* revision number, capabilities */ 104291116Smsmith#define ED_HPP_HW_IRQ 0x0D /* IRQ channel register in HW page */ 104377424Smsmith#define ED_HPP_HW_WRAP 0x0E /* mem wrap page for rcv */ 104483174Smsmith 104583174Smsmith/* 1046228110Sjkim * Lan configuration 1047228110Sjkim */ 1048228110Sjkim 104977424Smsmith#define ED_HPP_LAN_AUI 0x01 /* Use AUI */ 1050245582Sjkim#define ED_HPP_LAN_TL 0x40 /* Don't use AUI */ 1051245582Sjkim 105277424Smsmith/* 1053245582Sjkim * Card types. 1054228110Sjkim */ 1055228110Sjkim 1056228110Sjkim#define ED_TYPE_HP_PCLANPLUS 0x00 1057228110Sjkim 1058228110Sjkim/* 1059228110Sjkim * Definitions for Allied-Telesis SIC 1060151937Sjkim */ 1061245582Sjkim#define ED_SIC_NIC_OFFSET 0 1062245582Sjkim#define ED_SIC_ASIC_OFFSET 0x10 /* offset to nic i/o regs */ 1063228110Sjkim 1064245582Sjkim#define ED_SIC_IO_PORTS 17 /* # of i/o addresses used */ 1065228110Sjkim 1066228110Sjkim/* 1067228110Sjkim * Chip types. 1068228110Sjkim */ 1069228110Sjkim 1070228110Sjkim#define ED_CHIP_TYPE_DP8390 0 1071228110Sjkim#define ED_CHIP_TYPE_WD790 1 1072228110Sjkim#define ED_CHIP_TYPE_AX88190 2 107373561Smsmith#define ED_CHIP_TYPE_DL10019 3 107473561Smsmith#define ED_CHIP_TYPE_DL10022 4 107577424Smsmith#define ED_CHIP_TYPE_TC5299J 5 1076228110Sjkim#define ED_CHIP_TYPE_RTL8019 6 1077228110Sjkim#define ED_CHIP_TYPE_RTL8029 7 1078228110Sjkim#define ED_CHIP_TYPE_AX88790 8 1079228110Sjkim 108073561Smsmith/* 1081228110Sjkim * MII bus definitions. These are common to both DL100xx and AX88x90 1082228110Sjkim * MII definitions, most likely because they are standards based. 1083245582Sjkim */ 1084245582Sjkim#define ED_MII_STARTDELIM 0x01 1085228110Sjkim#define ED_MII_WRITEOP 0x01 1086245582Sjkim#define ED_MII_READOP 0x02 1087228110Sjkim#define ED_MII_TURNAROUND 0x02 1088228110Sjkim#define ED_MII_IDLE 0x01 1089228110Sjkim 1090228110Sjkim#define ED_MII_STARTDELIM_BITS 2 1091228110Sjkim#define ED_MII_OP_BITS 2 1092228110Sjkim#define ED_MII_PHY_BITS 5 1093228110Sjkim#define ED_MII_REG_BITS 5 1094245582Sjkim#define ED_MII_TURNAROUND_BITS 2 1095245582Sjkim#define ED_MII_ACK_BITS 1 1096228110Sjkim#define ED_MII_DATA_BITS 16 1097245582Sjkim#define ED_MII_IDLE_BITS 1 1098228110Sjkim