if_edreg.h revision 1015
156160Sru/* 2100513Sru * National Semiconductor DS8390 NIC register definitions 321495Sjmacd * 493139Sru * $Id: if_edreg.h,v 1.10 1994/01/11 21:28:29 ats Exp $ 593139Sru * 621495Sjmacd * Modification history 721495Sjmacd * 821495Sjmacd * Revision 2.2 1993/11/29 16:33:39 davidg 921495Sjmacd * From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk> 1021495Sjmacd * Add support for the 8013W board type 1121495Sjmacd * 1221495Sjmacd * Revision 2.1 1993/11/22 10:52:33 davidg 1321495Sjmacd * patch to add support for SMC8216 (Elite-Ultra) boards 1421495Sjmacd * from Glen H. Lowe 1521495Sjmacd * 1621495Sjmacd * Revision 2.0 93/09/29 00:37:15 davidg 1721495Sjmacd * changed double buffering flag to multi buffering 1821495Sjmacd * made changes/additions for 3c503 multi-buffering 1921495Sjmacd * ...companion to Rev. 2.0 of 'ed' driver. 2021495Sjmacd * 2142660Smarkm * Revision 1.1 93/06/23 03:01:07 davidg 2242660Smarkm * Initial revision 2321495Sjmacd * 2456160Sru */ 2556160Sru 2621495Sjmacd/* 2721495Sjmacd * Page 0 register offsets 2821495Sjmacd */ 2921495Sjmacd#define ED_P0_CR 0x00 /* Command Register */ 3021495Sjmacd 3121495Sjmacd#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 3221495Sjmacd#define ED_P0_PSTART 0x01 /* Page Start register (write) */ 3321495Sjmacd 3421495Sjmacd#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 3521495Sjmacd#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ 3621495Sjmacd 3721495Sjmacd#define ED_P0_BNRY 0x03 /* Boundary Pointer */ 3821495Sjmacd 3921495Sjmacd#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ 4021495Sjmacd#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ 4121495Sjmacd 4221495Sjmacd#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 4321495Sjmacd#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 4421495Sjmacd 4521495Sjmacd#define ED_P0_FIFO 0x06 /* FIFO register (read) */ 4621495Sjmacd#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 4721495Sjmacd 4821495Sjmacd#define ED_P0_ISR 0x07 /* Interrupt Status Register */ 4921495Sjmacd 5021495Sjmacd#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 5121495Sjmacd#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 5242660Smarkm 5321495Sjmacd#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 5442660Smarkm#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 5542660Smarkm 5621495Sjmacd#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 5742660Smarkm 5821495Sjmacd#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 5921495Sjmacd 6021495Sjmacd#define ED_P0_RSR 0x0c /* Receive Status (read) */ 6121495Sjmacd#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 6221495Sjmacd 6342660Smarkm#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 6442660Smarkm#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 6542660Smarkm 6642660Smarkm#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ 6742660Smarkm#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ 6842660Smarkm 6942660Smarkm#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ 7042660Smarkm#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 7142660Smarkm 7242660Smarkm/* 7321495Sjmacd * Page 1 register offsets 7421495Sjmacd */ 7521495Sjmacd#define ED_P1_CR 0x00 /* Command Register */ 7621495Sjmacd#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ 7721495Sjmacd#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ 7821495Sjmacd#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ 7921495Sjmacd#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ 8021495Sjmacd#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ 8121495Sjmacd#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ 8221495Sjmacd#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ 8321495Sjmacd#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ 8421495Sjmacd#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ 8521495Sjmacd#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ 8621495Sjmacd#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ 8721495Sjmacd#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ 8821495Sjmacd#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ 8921495Sjmacd#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ 9021495Sjmacd#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ 9121495Sjmacd 9221495Sjmacd/* 9321495Sjmacd * Page 2 register offsets 9421495Sjmacd */ 9521495Sjmacd#define ED_P2_CR 0x00 /* Command Register */ 9621495Sjmacd#define ED_P2_PSTART 0x01 /* Page Start (read) */ 9721495Sjmacd#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 9821495Sjmacd#define ED_P2_PSTOP 0x02 /* Page Stop (read) */ 9921495Sjmacd#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 10021495Sjmacd#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 10121495Sjmacd#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ 10221495Sjmacd#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ 10321495Sjmacd#define ED_P2_ACU 0x06 /* Address Counter Upper */ 10421495Sjmacd#define ED_P2_ACL 0x07 /* Address Counter Lower */ 10521495Sjmacd#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ 10621495Sjmacd#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 10721495Sjmacd#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ 10821495Sjmacd#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 10921495Sjmacd 11021495Sjmacd/* 11121495Sjmacd * Command Register (CR) definitions 11221495Sjmacd */ 11321495Sjmacd 11421495Sjmacd/* 11521495Sjmacd * STP: SToP. Software reset command. Takes the controller offline. No 11621495Sjmacd * packets will be received or transmitted. Any reception or 11721495Sjmacd * transmission in progress will continue to completion before 11821495Sjmacd * entering reset state. To exit this state, the STP bit must 11921495Sjmacd * reset and the STA bit must be set. The software reset has 12021495Sjmacd * executed only when indicated by the RST bit in the ISR being 12121495Sjmacd * set. 12221495Sjmacd */ 12321495Sjmacd#define ED_CR_STP 0x01 12421495Sjmacd 12521495Sjmacd/* 12621495Sjmacd * STA: STArt. This bit is used to activate the NIC after either power-up, 12721495Sjmacd * or when the NIC has been put in reset mode by software command 12821495Sjmacd * or error. 12921495Sjmacd */ 13021495Sjmacd#define ED_CR_STA 0x02 13121495Sjmacd 13221495Sjmacd/* 13321495Sjmacd * TXP: Transmit Packet. This bit must be set to indicate transmission of 13421495Sjmacd * a packet. TXP is internally reset either after the transmission is 13521495Sjmacd * completed or aborted. This bit should be set only after the Transmit 13621495Sjmacd * Byte Count and Transmit Page Start register have been programmed. 13721495Sjmacd */ 13821495Sjmacd#define ED_CR_TXP 0x04 13921495Sjmacd 14021495Sjmacd/* 14121495Sjmacd * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 14221495Sjmacd * of the remote DMA channel. RD2 can be set to abort any remote DMA 14321495Sjmacd * command in progress. The Remote Byte Count registers should be cleared 14442660Smarkm * when a remote DMA has been aborted. The Remote Start Addresses are not 14521495Sjmacd * restored to the starting address if the remote DMA is aborted. 14621495Sjmacd * 14721495Sjmacd * RD2 RD1 RD0 function 14821495Sjmacd * 0 0 0 not allowed 14921495Sjmacd * 0 0 1 remote read 15021495Sjmacd * 0 1 0 remote write 15121495Sjmacd * 0 1 1 send packet 15221495Sjmacd * 1 X X abort 15321495Sjmacd */ 15442660Smarkm#define ED_CR_RD0 0x08 15542660Smarkm#define ED_CR_RD1 0x10 15642660Smarkm#define ED_CR_RD2 0x20 15742660Smarkm 15842660Smarkm/* 15942660Smarkm * PS0, PS1: Page Select. The two bits select which register set or 'page' to 16042660Smarkm * access. 16142660Smarkm * 16242660Smarkm * PS1 PS0 page 16321495Sjmacd * 0 0 0 16421495Sjmacd * 0 1 1 16521495Sjmacd * 1 0 2 16621495Sjmacd * 1 1 reserved 16721495Sjmacd */ 16821495Sjmacd#define ED_CR_PS0 0x40 16921495Sjmacd#define ED_CR_PS1 0x80 17021495Sjmacd/* bit encoded aliases */ 17121495Sjmacd#define ED_CR_PAGE_0 0x00 /* (for consistency) */ 17221495Sjmacd#define ED_CR_PAGE_1 0x40 17321495Sjmacd#define ED_CR_PAGE_2 0x80 17421495Sjmacd 17521495Sjmacd/* 17621495Sjmacd * Interrupt Status Register (ISR) definitions 17721495Sjmacd */ 17821495Sjmacd 17921495Sjmacd/* 18021495Sjmacd * PRX: Packet Received. Indicates packet received with no errors. 18121495Sjmacd */ 18221495Sjmacd#define ED_ISR_PRX 0x01 18321495Sjmacd 18421495Sjmacd/* 18521495Sjmacd * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 18621495Sjmacd */ 18721495Sjmacd#define ED_ISR_PTX 0x02 18821495Sjmacd 18921495Sjmacd/* 19021495Sjmacd * RXE: Receive Error. Indicates that a packet was received with one or more 19156160Sru * the following errors: CRC error, frame alignment error, FIFO overrun, 19221495Sjmacd * missed packet. 19356160Sru */ 19421495Sjmacd#define ED_ISR_RXE 0x04 19521495Sjmacd 19621495Sjmacd/* 19742660Smarkm * TXE: Transmission Error. Indicates that an attempt to transmit a packet 19856160Sru * resulted in one or more of the following errors: excessive 19956160Sru * collisions, FIFO underrun. 20056160Sru */ 20156160Sru#define ED_ISR_TXE 0x08 20256160Sru 20356160Sru/* 20456160Sru * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 20556160Sru * would exceed (has exceeded?) the boundry pointer, resulting in data 20656160Sru * that was previously received and not yet read from the buffer to be 20756160Sru * overwritten. 20856160Sru */ 20921495Sjmacd#define ED_ISR_OVW 0x10 21056160Sru 21121495Sjmacd/* 21221495Sjmacd * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley 21321495Sjmacd * Counters has been set. 21421495Sjmacd */ 21521495Sjmacd#define ED_ISR_CNT 0x20 21642660Smarkm 21742660Smarkm/* 21842660Smarkm * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed. 21921495Sjmacd */ 22021495Sjmacd#define ED_ISR_RDC 0x40 22142660Smarkm 22242660Smarkm/* 22321495Sjmacd * RST: Reset status. Set when the NIC enters the reset state and cleared when a 22442660Smarkm * Start Command is issued to the CR. This bit is also set when a receive 22521495Sjmacd * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 22621495Sjmacd * packets have been removed from the ring. This is a read-only bit. 22721495Sjmacd */ 22856160Sru#define ED_ISR_RST 0x80 22956160Sru 23042660Smarkm/* 23121495Sjmacd * Interrupt Mask Register (IMR) definitions 23221495Sjmacd */ 23321495Sjmacd 23421495Sjmacd/* 23521495Sjmacd * PRXE: Packet Received interrupt Enable. If set, a received packet will cause 23621495Sjmacd * an interrupt. 23721495Sjmacd */ 23821495Sjmacd#define ED_IMR_PRXE 0x01 23921495Sjmacd 24021495Sjmacd/* 24121495Sjmacd * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when 24221495Sjmacd * a packet transmission completes. 24321495Sjmacd */ 24456160Sru#define ED_IMR_PTXE 0x02 24556160Sru 24621495Sjmacd/* 24742660Smarkm * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a 24821495Sjmacd * packet is received with an error. 24942660Smarkm */ 25021495Sjmacd#define ED_IMR_RXEE 0x04 25142660Smarkm 25221495Sjmacd/* 25342660Smarkm * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever 25421495Sjmacd * a transmission results in an error. 25521495Sjmacd */ 25621495Sjmacd#define ED_IMR_TXEE 0x08 25721495Sjmacd 25821495Sjmacd/* 25921495Sjmacd * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever 26021495Sjmacd * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded. 26121495Sjmacd */ 26221495Sjmacd#define ED_IMR_OVWE 0x10 26321495Sjmacd 26442660Smarkm/* 26542660Smarkm * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever 26621495Sjmacd * the MSB of one or more of the Network Statistics counters has been set. 26756160Sru */ 26856160Sru#define ED_IMR_CNTE 0x20 26956160Sru 27042660Smarkm/* 27121495Sjmacd * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated 27221495Sjmacd * when a remote DMA transfer has completed. 27321495Sjmacd */ 27456160Sru#define ED_IMR_RDCE 0x40 27556160Sru 27621495Sjmacd/* 27742660Smarkm * bit 7 is unused/reserved 27821495Sjmacd */ 27921495Sjmacd 28042660Smarkm/* 28142660Smarkm * Data Configuration Register (DCR) definitions 28221495Sjmacd */ 28321495Sjmacd 28442660Smarkm/* 28521495Sjmacd * WTS: Word Transfer Select. WTS establishes byte or word transfers for 28656160Sru * both remote and local DMA transfers 28756160Sru */ 28856160Sru#define ED_DCR_WTS 0x01 289100513Sru 290100513Sru/* 29121495Sjmacd * BOS: Byte Order Select. BOS sets the byte order for the host. 29256160Sru * Should be 0 for 80x86, and 1 for 68000 series processors 29321495Sjmacd */ 29421495Sjmacd#define ED_DCR_BOS 0x02 29521495Sjmacd 29621495Sjmacd/* 29721495Sjmacd * LAS: Long Address Select. When LAS is 1, the contents of the remote 29821495Sjmacd * DMA registers RSAR0 and RSAR1 are used to provide A16-A31 29921495Sjmacd */ 30021495Sjmacd#define ED_DCR_LAS 0x04 30121495Sjmacd 30221495Sjmacd/* 30321495Sjmacd * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 30421495Sjmacd * of the TCR must also be programmed for loopback operation. 30521495Sjmacd * When 1, normal operation is selected. 30621495Sjmacd */ 30721495Sjmacd#define ED_DCR_LS 0x08 30821495Sjmacd 30921495Sjmacd/* 31021495Sjmacd * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 31156160Sru * under program control. When 1, remote DMA is automatically initiated 31221495Sjmacd * and the boundry pointer is automatically updated 31356160Sru */ 31456160Sru#define ED_DCR_AR 0x10 31556160Sru 31621495Sjmacd/* 31721495Sjmacd * FT0, FT1: Fifo Threshold select. 31821495Sjmacd * FT1 FT0 Word-width Byte-width 31921495Sjmacd * 0 0 1 word 2 bytes 32021495Sjmacd * 0 1 2 words 4 bytes 32121495Sjmacd * 1 0 4 words 8 bytes 32221495Sjmacd * 1 1 8 words 12 bytes 32321495Sjmacd * 32421495Sjmacd * During transmission, the FIFO threshold indicates the number of bytes 32521495Sjmacd * or words that the FIFO has filled from the local DMA before BREQ is 32621495Sjmacd * asserted. The transmission threshold is 16 bytes minus the receiver 32721495Sjmacd * threshold. 32821495Sjmacd */ 32921495Sjmacd#define ED_DCR_FT0 0x20 33021495Sjmacd#define ED_DCR_FT1 0x40 33121495Sjmacd 33221495Sjmacd/* 33342660Smarkm * bit 7 (0x80) is unused/reserved 33442660Smarkm */ 33542660Smarkm 33642660Smarkm/* 33756160Sru * Transmit Configuration Register (TCR) definitions 33856160Sru */ 33921495Sjmacd 34021495Sjmacd/* 34142660Smarkm * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 34293139Sru * is not appended by the transmitter. 34356160Sru */ 34442660Smarkm#define ED_TCR_CRC 0x01 34542660Smarkm 34642660Smarkm/* 34742660Smarkm * LB0, LB1: Loopback control. These two bits set the type of loopback that is 34842660Smarkm * to be performed. 34942660Smarkm * 35042660Smarkm * LB1 LB0 mode 35142660Smarkm * 0 0 0 - normal operation (DCR_LS = 0) 35242660Smarkm * 0 1 1 - internal loopback (DCR_LS = 0) 35342660Smarkm * 1 0 2 - external loopback (DCR_LS = 1) 35442660Smarkm * 1 1 3 - external loopback (DCR_LS = 0) 35542660Smarkm */ 35642660Smarkm#define ED_TCR_LB0 0x02 35742660Smarkm#define ED_TCR_LB1 0x04 35842660Smarkm 35942660Smarkm/* 36042660Smarkm * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 36142660Smarkm * another station to disable the NIC's transmitter by transmitting to 36242660Smarkm * a multicast address hashing to bit 62. Reception of a multicast address 36342660Smarkm * hashing to bit 63 enables the transmitter. 36442660Smarkm */ 36542660Smarkm#define ED_TCR_ATD 0x08 36642660Smarkm 36742660Smarkm/* 36842660Smarkm * OFST: Collision Offset enable. This bit when set modifies the backoff 36942660Smarkm * algorithm to allow prioritization of nodes. 37021495Sjmacd */ 37142660Smarkm#define ED_TCR_OFST 0x10 37242660Smarkm 37342660Smarkm/* 37442660Smarkm * bits 5, 6, and 7 are unused/reserved 37521495Sjmacd */ 37621495Sjmacd 37721495Sjmacd/* 37821495Sjmacd * Transmit Status Register (TSR) definitions 37921495Sjmacd */ 38021495Sjmacd 38121495Sjmacd/* 38221495Sjmacd * PTX: Packet Transmitted. Indicates successful transmission of packet. 38321495Sjmacd */ 38421495Sjmacd#define ED_TSR_PTX 0x01 38521495Sjmacd 38656160Sru/* 38721495Sjmacd * bit 1 (0x02) is unused/reserved 38821495Sjmacd */ 38921495Sjmacd 39021495Sjmacd/* 39156160Sru * COL: Transmit Collided. Indicates that the transmission collided at least 39221495Sjmacd * once with another station on the network. 39321495Sjmacd */ 39421495Sjmacd#define ED_TSR_COL 0x04 39521495Sjmacd 39621495Sjmacd/* 39721495Sjmacd * ABT: Transmit aborted. Indicates that the transmission was aborted due to 39821495Sjmacd * excessive collisions. 39921495Sjmacd */ 40021495Sjmacd#define ED_TSR_ABT 0x08 40121495Sjmacd 40221495Sjmacd/* 40321495Sjmacd * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 40421495Sjmacd * transmission of the packet. (Transmission is not aborted because 40521495Sjmacd * of a loss of carrier) 40621495Sjmacd */ 40721495Sjmacd#define ED_TSR_CRS 0x10 40821495Sjmacd 40921495Sjmacd/* 41021495Sjmacd * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 41121495Sjmacd * transmission memory before the FIFO emptied. Transmission of the 41221495Sjmacd * packet was aborted. 41321495Sjmacd */ 41421495Sjmacd#define ED_TSR_FU 0x20 41521495Sjmacd 41621495Sjmacd/* 41721495Sjmacd * CDH: CD Heartbeat. Indicates that the collision detection circuitry 41821495Sjmacd * isn't working correctly during a collision heartbeat test. 41921495Sjmacd */ 42021495Sjmacd#define ED_TSR_CDH 0x40 42121495Sjmacd 42221495Sjmacd/* 42321495Sjmacd * OWC: Out of Window Collision: Indicates that a collision occurred after 42421495Sjmacd * a slot time (51.2us). The transmission is rescheduled just as in 42521495Sjmacd * normal collisions. 42642660Smarkm */ 42721495Sjmacd#define ED_TSR_OWC 0x80 42842660Smarkm 42942660Smarkm/* 43042660Smarkm * Receiver Configuration Register (RCR) definitions 43142660Smarkm */ 43242660Smarkm 43321495Sjmacd/* 43421495Sjmacd * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 43542660Smarkm * packets with CRC and frame errors are not discarded. 43621495Sjmacd */ 43721495Sjmacd#define ED_RCR_SEP 0x01 43821495Sjmacd 43921495Sjmacd/* 44021495Sjmacd * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 44121495Sjmacd * If set to 1, packets with less than 64 byte are not discarded. 44221495Sjmacd */ 44321495Sjmacd#define ED_RCR_AR 0x02 44421495Sjmacd 44521495Sjmacd/* 44621495Sjmacd * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 44721495Sjmacd * accepted. 44821495Sjmacd */ 44921495Sjmacd#define ED_RCR_AB 0x04 45021495Sjmacd 45121495Sjmacd/* 45221495Sjmacd * AM: Accept Multicast. If set, packets sent to a multicast address are checked 45321495Sjmacd * for a match in the hashing array. If clear, multicast packets are ignored. 45421495Sjmacd */ 45542660Smarkm#define ED_RCR_AM 0x08 45621495Sjmacd 45742660Smarkm/* 45821495Sjmacd * PRO: Promiscuous Physical. If set, all packets with a physical addresses are 45921495Sjmacd * accepted. If clear, a physical destination address must match this 46021495Sjmacd * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM 46121495Sjmacd * must also be set. In addition, the multicast hashing array must be set 46221495Sjmacd * to all 1's so that all multicast addresses are accepted. 46342660Smarkm */ 46421495Sjmacd#define ED_RCR_PRO 0x10 46521495Sjmacd 46621495Sjmacd/* 46742660Smarkm * MON: Monitor Mode. If set, packets will be checked for good CRC and framing, 46821495Sjmacd * but are not stored in the ring-buffer. If clear, packets are stored (normal 46921495Sjmacd * operation). 47021495Sjmacd */ 47121495Sjmacd#define ED_RCR_MON 0x20 47221495Sjmacd 47321495Sjmacd/* 47421495Sjmacd * bits 6 and 7 are unused/reserved. 47521495Sjmacd */ 47621495Sjmacd 47721495Sjmacd/* 47821495Sjmacd * Receiver Status Register (RSR) definitions 47921495Sjmacd */ 48021495Sjmacd 48121495Sjmacd/* 48221495Sjmacd * PRX: Packet Received without error. 48321495Sjmacd */ 48442660Smarkm#define ED_RSR_PRX 0x01 48521495Sjmacd 48642660Smarkm/* 48742660Smarkm * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame 48842660Smarkm * alignment errors. 48942660Smarkm */ 49042660Smarkm#define ED_RSR_CRC 0x02 49121495Sjmacd 49221495Sjmacd/* 49342660Smarkm * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on 49421495Sjmacd * a byte boundry and the CRC did not match at the last byte boundry. 49521495Sjmacd */ 49621495Sjmacd#define ED_RSR_FAE 0x04 49721495Sjmacd 49821495Sjmacd/* 49921495Sjmacd * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA) 50021495Sjmacd * causing it to overrun. Reception of the packet is aborted. 50121495Sjmacd */ 50221495Sjmacd#define ED_RSR_FO 0x08 50321495Sjmacd 50421495Sjmacd/* 50521495Sjmacd * MPA: Missed Packet. Indicates that the received packet couldn't be stored in 50621495Sjmacd * the ring-buffer because of insufficient buffer space (exceeding the 50721495Sjmacd * boundry pointer), or because the transfer to the ring-buffer was inhibited 50821495Sjmacd * by RCR_MON - monitor mode. 50921495Sjmacd */ 51021495Sjmacd#define ED_RSR_MPA 0x10 51121495Sjmacd 51221495Sjmacd/* 51321495Sjmacd * PHY: Physical address. If 0, the packet received was sent to a physical address. 51421495Sjmacd * If 1, the packet was accepted because of a multicast/broadcast address 51521495Sjmacd * match. 51621495Sjmacd */ 51721495Sjmacd#define ED_RSR_PHY 0x20 51821495Sjmacd 51942660Smarkm/* 52021495Sjmacd * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor 52142660Smarkm * mode. Cleared when the receiver exits monitor mode. 52242660Smarkm */ 52342660Smarkm#define ED_RSR_DIS 0x40 52442660Smarkm 52542660Smarkm/* 52621495Sjmacd * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs 52721495Sjmacd * are active, and the transceiver has set the CD line as a result of the 52842660Smarkm * jabber. 52921495Sjmacd */ 53021495Sjmacd#define ED_RSR_DFR 0x80 53121495Sjmacd 53221495Sjmacd/* 53321495Sjmacd * receive ring discriptor 53421495Sjmacd * 53521495Sjmacd * The National Semiconductor DS8390 Network interface controller uses 53621495Sjmacd * the following receive ring headers. The way this works is that the 53721495Sjmacd * memory on the interface card is chopped up into 256 bytes blocks. 53821495Sjmacd * A contiguous portion of those blocks are marked for receive packets 53921495Sjmacd * by setting start and end block #'s in the NIC. For each packet that 54021495Sjmacd * is put into the receive ring, one of these headers (4 bytes each) is 54121495Sjmacd * tacked onto the front. 54221495Sjmacd */ 54321495Sjmacdstruct ed_ring { 54421495Sjmacd struct edr_status { /* received packet status */ 54521495Sjmacd u_char rs_prx:1, /* packet received intack */ 54621495Sjmacd rs_crc:1, /* crc error */ 54721495Sjmacd rs_fae:1, /* frame alignment error */ 54821495Sjmacd rs_fo:1, /* fifo overrun */ 54921495Sjmacd rs_mpa:1, /* packet received intack */ 55021495Sjmacd rs_phy:1, /* packet received intack */ 55142660Smarkm rs_dis:1, /* packet received intack */ 55221495Sjmacd rs_dfr:1; /* packet received intack */ 55321495Sjmacd } ed_rcv_status; /* received packet status */ 55421495Sjmacd u_char next_packet; /* pointer to next packet */ 55542660Smarkm u_short count; /* bytes in packet (length + 4) */ 55621495Sjmacd}; 55742660Smarkm 55842660Smarkm/* 55942660Smarkm * Common constants 56042660Smarkm */ 56142660Smarkm#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 56221495Sjmacd#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 56321495Sjmacd 56421495Sjmacd/* 56521495Sjmacd * Vendor types 56621495Sjmacd */ 56742660Smarkm#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ 56821495Sjmacd#define ED_VENDOR_3COM 0x01 /* 3Com */ 56921495Sjmacd#define ED_VENDOR_NOVELL 0x02 /* Novell */ 57021495Sjmacd 57121495Sjmacd/* 57221495Sjmacd * Compile-time config flags 57321495Sjmacd */ 57421495Sjmacd/* 57521495Sjmacd * this sets the default for enabling/disablng the tranceiver 57621495Sjmacd */ 57721495Sjmacd#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001 57821495Sjmacd 57921495Sjmacd/* 58021495Sjmacd * This forces the board to be used in 8/16bit mode even if it 58121495Sjmacd * autoconfigs differently 58221495Sjmacd */ 58321495Sjmacd#define ED_FLAGS_FORCE_8BIT_MODE 0x0002 58421495Sjmacd#define ED_FLAGS_FORCE_16BIT_MODE 0x0004 58521495Sjmacd 58621495Sjmacd/* 58721495Sjmacd * This disables the use of double transmit buffers. 58821495Sjmacd */ 58921495Sjmacd#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008 59021495Sjmacd 59121495Sjmacd/* 59242660Smarkm * This forces all operations with the NIC memory to use Programmed 59321495Sjmacd * I/O (i.e. not via shared memory) 59442660Smarkm */ 59521495Sjmacd#define ED_FLAGS_FORCE_PIO 0x0010 59642660Smarkm 59721495Sjmacd/* 59821495Sjmacd * Definitions for Western digital/SMC WD80x3 series ASIC 59921495Sjmacd */ 60021495Sjmacd/* 60121495Sjmacd * Memory Select Register (MSR) 60221495Sjmacd */ 60321495Sjmacd#define ED_WD_MSR 0 60421495Sjmacd 60542660Smarkm#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ 60621495Sjmacd#define ED_WD_MSR_MENB 0x40 /* Memory enable */ 60721495Sjmacd#define ED_WD_MSR_RST 0x80 /* Reset board */ 60821495Sjmacd#ifdef TOSH_ETHER 60921495Sjmacd#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */ 61021495Sjmacd#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */ 61121495Sjmacd#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits, 61221495Sjmacd 1 = 8 bits (R/W) */ 61321495Sjmacd#endif 61421495Sjmacd 61521495Sjmacd 61621495Sjmacd/* 61721495Sjmacd * Interface Configuration Register (ICR) 61821495Sjmacd */ 61921495Sjmacd#define ED_WD_ICR 1 62021495Sjmacd 62121495Sjmacd#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */ 62221495Sjmacd#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */ 62321495Sjmacd#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */ 62421495Sjmacd#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ 62521495Sjmacd#define ED_WD_ICR_RLA 0x10 /* recall LAN address */ 62621495Sjmacd#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */ 62721495Sjmacd#define ED_WD_ICR_RIO 0x40 /* recall i/o address */ 62821495Sjmacd#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */ 62942660Smarkm#ifdef TOSH_ETHER 63021495Sjmacd#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */ 63142660Smarkm#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K, 63221495Sjmacd 0x02 = 16K, 0x01 = 8K */ 63342660Smarkm /* 64K can only be used if mem address 63442660Smarkm above 1Mb */ 63542660Smarkm /* IAR holds address A23-A16 (R/W) */ 63642660Smarkm#endif 63742660Smarkm 63842660Smarkm/* 63942660Smarkm * IO Address Register (IAR) 64042660Smarkm */ 64142660Smarkm#define ED_WD_IAR 2 64221495Sjmacd 64321495Sjmacd/* 64421495Sjmacd * EEROM Address Register 64521495Sjmacd */ 64621495Sjmacd#define ED_WD_EAR 3 64721495Sjmacd 64821495Sjmacd/* 64921495Sjmacd * Interrupt Request Register (IRR) 65021495Sjmacd */ 65121495Sjmacd#define ED_WD_IRR 4 65221495Sjmacd 65321495Sjmacd#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ 65421495Sjmacd#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ 65521495Sjmacd#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ 65621495Sjmacd#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ 65742660Smarkm#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ 65821495Sjmacd 65921495Sjmacd/* 66021495Sjmacd * The three bit of the encoded IRQ are decoded as follows: 66121495Sjmacd * 66221495Sjmacd * IR2 IR1 IR0 IRQ 66321495Sjmacd * 0 0 0 2/9 66421495Sjmacd * 0 0 1 3 66521495Sjmacd * 0 1 0 5 66621495Sjmacd * 0 1 1 7 66721495Sjmacd * 1 0 0 10 66821495Sjmacd * 1 0 1 11 66921495Sjmacd * 1 1 0 15 67021495Sjmacd * 1 1 1 4 67121495Sjmacd */ 67221495Sjmacd#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 67321495Sjmacd#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 67421495Sjmacd#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */ 67521495Sjmacd 67621495Sjmacd/* 67721495Sjmacd * LA Address Register (LAAR) 67821495Sjmacd */ 67942660Smarkm#define ED_WD_LAAR 5 68021495Sjmacd 68142660Smarkm#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ 68221495Sjmacd#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ 68342660Smarkm#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */ 68421495Sjmacd#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */ 68521495Sjmacd 68621495Sjmacd/* i/o base offset to station address/card-ID PROM */ 68721495Sjmacd#define ED_WD_PROM 8 68821495Sjmacd 68921495Sjmacd/* i/o base offset to CARD ID */ 69021495Sjmacd#define ED_WD_CARD_ID ED_WD_PROM+6 69121495Sjmacd 69221495Sjmacd/* Board type codes in card ID */ 69321495Sjmacd#define ED_TYPE_WD8003S 0x02 69421495Sjmacd#define ED_TYPE_WD8003E 0x03 69521495Sjmacd#define ED_TYPE_WD8013EBT 0x05 69642660Smarkm#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */ 69721495Sjmacd#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */ 69821495Sjmacd#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */ 69921495Sjmacd#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */ 70021495Sjmacd#define ED_TYPE_WD8013W 0x26 70121495Sjmacd#define ED_TYPE_WD8013EP 0x27 70221495Sjmacd#define ED_TYPE_WD8013WC 0x28 70321495Sjmacd#define ED_TYPE_WD8013EBP 0x2c 70421495Sjmacd#define ED_TYPE_WD8013EPC 0x29 70521495Sjmacd#define ED_TYPE_SMC8216T 0x2a 70621495Sjmacd#define ED_TYPE_SMC8216C 0x2b 70721495Sjmacd 70821495Sjmacd/* Bit definitions in card ID */ 70921495Sjmacd#define ED_WD_REV_MASK 0x1f /* Revision mask */ 71021495Sjmacd#define ED_WD_SOFTCONFIG 0x20 /* Soft config */ 71121495Sjmacd#define ED_WD_LARGERAM 0x40 /* Large RAM */ 71221495Sjmacd#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ 71321495Sjmacd 71421495Sjmacd/* 71521495Sjmacd * Checksum total. All 8 bytes in station address PROM will add up to this 71621495Sjmacd */ 71721495Sjmacd#ifdef TOSH_ETHER 71821495Sjmacd#define ED_WD_ROM_CHECKSUM_TOTAL 0xA5 71921495Sjmacd#else 72021495Sjmacd#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF 72121495Sjmacd#endif 72221495Sjmacd 72321495Sjmacd#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */ 72421495Sjmacd#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */ 72521495Sjmacd#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */ 72621495Sjmacd 72721495Sjmacd#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */ 72821495Sjmacd 72921495Sjmacd/* 73021495Sjmacd * Definitions for 3Com 3c503 73121495Sjmacd */ 73221495Sjmacd#define ED_3COM_NIC_OFFSET 0 73321495Sjmacd#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ 73421495Sjmacd 73521495Sjmacd/* 73621495Sjmacd * XXX - The I/O address range is fragmented in the 3c503; this is the 73721495Sjmacd * number of regs at iobase. 73821495Sjmacd */ 73921495Sjmacd#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */ 74021495Sjmacd 74121495Sjmacd/* tx memory starts in second bank on 8bit cards */ 74242660Smarkm#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20 74321495Sjmacd 74442660Smarkm/* tx memory starts in first bank on 16bit cards */ 74521495Sjmacd#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0 74621495Sjmacd 74721495Sjmacd/* ...and rx memory starts in second bank */ 74821495Sjmacd#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20 74921495Sjmacd 75042660Smarkm 75121495Sjmacd/* 75242660Smarkm * Page Start Register. Must match PSTART in NIC 75321495Sjmacd */ 75421495Sjmacd#define ED_3COM_PSTR 0 75521495Sjmacd 75621495Sjmacd/* 75721495Sjmacd * Page Stop Register. Must match PSTOP in NIC 75821495Sjmacd */ 75921495Sjmacd#define ED_3COM_PSPR 1 76021495Sjmacd 76121495Sjmacd/* 76221495Sjmacd * Drq Timer Register. Determines number of bytes to be transfered during 76342660Smarkm * a DMA burst. 76442660Smarkm */ 76521495Sjmacd#define ED_3COM_DQTR 2 76642660Smarkm 76742660Smarkm/* 76842660Smarkm * Base Configuration Register. Read-only register which contains the 76942660Smarkm * board-configured I/O base address of the adapter. Bit encoded. 77042660Smarkm */ 77142660Smarkm#define ED_3COM_BCFR 3 77242660Smarkm 77342660Smarkm#define ED_3COM_BCFR_2E0 0x01 77421495Sjmacd#define ED_3COM_BCFR_2A0 0x02 77542660Smarkm#define ED_3COM_BCFR_280 0x04 77642660Smarkm#define ED_3COM_BCFR_250 0x08 77742660Smarkm#define ED_3COM_BCFR_350 0x10 77842660Smarkm#define ED_3COM_BCFR_330 0x20 77942660Smarkm#define ED_3COM_BCFR_310 0x40 78021495Sjmacd#define ED_3COM_BCFR_300 0x80 78121495Sjmacd 78221495Sjmacd/* 78321495Sjmacd * EPROM Configuration Register. Read-only register which contains the 78421495Sjmacd * board-configured memory base address. Bit encoded. 78542660Smarkm */ 78642660Smarkm#define ED_3COM_PCFR 4 78721495Sjmacd 78842660Smarkm#define ED_3COM_PCFR_C8000 0x10 78942660Smarkm#define ED_3COM_PCFR_CC000 0x20 79042660Smarkm#define ED_3COM_PCFR_D8000 0x40 79142660Smarkm#define ED_3COM_PCFR_DC000 0x80 79242660Smarkm 79342660Smarkm/* 79442660Smarkm * GA Configuration Register. Gate-Array Configuration Register. 79542660Smarkm */ 79621495Sjmacd#define ED_3COM_GACFR 5 79742660Smarkm 79842660Smarkm/* 79942660Smarkm * mbs2 mbs1 mbs0 start address 80042660Smarkm * 0 0 0 0x0000 80142660Smarkm * 0 0 1 0x2000 80242660Smarkm * 0 1 0 0x4000 80321495Sjmacd * 0 1 1 0x6000 80421495Sjmacd * 80521495Sjmacd * Note that with adapters with only 8K, the setting for 0x2000 must 80621495Sjmacd * always be used. 80721495Sjmacd */ 80821495Sjmacd#define ED_3COM_GACFR_MBS0 0x01 80921495Sjmacd#define ED_3COM_GACFR_MBS1 0x02 81021495Sjmacd#define ED_3COM_GACFR_MBS2 0x04 81121495Sjmacd 81221495Sjmacd#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */ 81321495Sjmacd#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */ 81421495Sjmacd#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ 81521495Sjmacd#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ 81621495Sjmacd#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ 81721495Sjmacd 81821495Sjmacd/* 81921495Sjmacd * Control Register. Miscellaneous control functions. 82021495Sjmacd */ 82121495Sjmacd#define ED_3COM_CR 6 82221495Sjmacd 82321495Sjmacd#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */ 82421495Sjmacd#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 82521495Sjmacd#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 82621495Sjmacd#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 82721495Sjmacd#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */ 82821495Sjmacd#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */ 82921495Sjmacd#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */ 83021495Sjmacd#define ED_3COM_CR_START 0x80 /* Start DMA controller */ 83121495Sjmacd 83221495Sjmacd/* 83321495Sjmacd * Status Register. Miscellaneous status information. 83421495Sjmacd */ 83521495Sjmacd#define ED_3COM_STREG 7 83621495Sjmacd 83721495Sjmacd#define ED_3COM_STREG_REV 0x07 /* GA revision */ 83821495Sjmacd#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */ 83921495Sjmacd#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */ 84021495Sjmacd#define ED_3COM_STREG_OFLW 0x20 /* Overflow */ 84121495Sjmacd#define ED_3COM_STREG_UFLW 0x40 /* Underflow */ 84221495Sjmacd#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */ 84321495Sjmacd 84442660Smarkm/* 84542660Smarkm * Interrupt/DMA Configuration Register 84642660Smarkm */ 84742660Smarkm#define ED_3COM_IDCFR 8 84842660Smarkm 84942660Smarkm#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ 85021495Sjmacd#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ 85142660Smarkm#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ 85242660Smarkm#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */ 85342660Smarkm#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 85442660Smarkm#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 85521495Sjmacd#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 85621495Sjmacd#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 85721495Sjmacd 85821495Sjmacd/* 85921495Sjmacd * DMA Address Register MSB 86021495Sjmacd */ 86121495Sjmacd#define ED_3COM_DAMSB 9 86221495Sjmacd 86321495Sjmacd/* 86421495Sjmacd * DMA Address Register LSB 86521495Sjmacd */ 86621495Sjmacd#define ED_3COM_DALSB 0x0a 86756160Sru 86821495Sjmacd/* 86921495Sjmacd * Vector Pointer Register 2 87021495Sjmacd */ 87121495Sjmacd#define ED_3COM_VPTR2 0x0b 87221495Sjmacd 87321495Sjmacd/* 87421495Sjmacd * Vector Pointer Register 1 87521495Sjmacd */ 87621495Sjmacd#define ED_3COM_VPTR1 0x0c 87721495Sjmacd 87821495Sjmacd/* 87921495Sjmacd * Vector Pointer Register 0 88021495Sjmacd */ 88121495Sjmacd#define ED_3COM_VPTR0 0x0d 88221495Sjmacd 88321495Sjmacd/* 88421495Sjmacd * Register File Access MSB 88521495Sjmacd */ 88621495Sjmacd#define ED_3COM_RFMSB 0x0e 88742660Smarkm 88821495Sjmacd/* 88921495Sjmacd * Register File Access LSB 89021495Sjmacd */ 89121495Sjmacd#define ED_3COM_RFLSB 0x0f 89221495Sjmacd 89321495Sjmacd/* 89421495Sjmacd * Definitions for Novell NE1000/2000 boards 89521495Sjmacd */ 89621495Sjmacd 89721495Sjmacd/* 89821495Sjmacd * Board type codes 89921495Sjmacd */ 90021495Sjmacd#define ED_TYPE_NE1000 0x01 90142660Smarkm#define ED_TYPE_NE2000 0x02 90221495Sjmacd 90321495Sjmacd/* 90421495Sjmacd * Register offsets/total 90542660Smarkm */ 90621495Sjmacd#define ED_NOVELL_NIC_OFFSET 0x00 90721495Sjmacd#define ED_NOVELL_ASIC_OFFSET 0x10 90842660Smarkm#define ED_NOVELL_IO_PORTS 32 90942660Smarkm 91042660Smarkm/* 91142660Smarkm * Remote DMA data register; for reading or writing to the NIC mem 91221495Sjmacd * via programmed I/O (offset from ASIC base) 91342660Smarkm */ 91421495Sjmacd#define ED_NOVELL_DATA 0x00 91542660Smarkm 91642660Smarkm/* 91742660Smarkm * Reset register; reading from this register causes a board reset 91821495Sjmacd */ 91942660Smarkm#define ED_NOVELL_RESET 0x0f 92042660Smarkm