if_edreg.h revision 50477
16Sdg/* 21817Sdg * Copyright (C) 1993, David Greenman. This software may be used, modified, 31817Sdg * copied, distributed, and sold, in both source and binary form provided 41817Sdg * that the above copyright and these terms are retained. Under no 51817Sdg * circumstances is the author responsible for the proper functioning 61817Sdg * of this software, nor does the author assume any responsibility 71817Sdg * for damages incurred with its use. 81817Sdg * 950477Speter * $FreeBSD: head/sys/dev/ed/if_edreg.h 50477 1999-08-28 01:08:13Z peter $ 101817Sdg */ 111817Sdg/* 128876Srgrimes * National Semiconductor DS8390 NIC register definitions 1343Sdg * 14498Sdg * 15498Sdg * Modification history 16498Sdg * 17808Sdg * Revision 2.2 1993/11/29 16:33:39 davidg 18808Sdg * From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk> 19808Sdg * Add support for the 8013W board type 20808Sdg * 21791Sdg * Revision 2.1 1993/11/22 10:52:33 davidg 22791Sdg * patch to add support for SMC8216 (Elite-Ultra) boards 23791Sdg * from Glen H. Lowe 24791Sdg * 25520Sdg * Revision 2.0 93/09/29 00:37:15 davidg 26520Sdg * changed double buffering flag to multi buffering 27520Sdg * made changes/additions for 3c503 multi-buffering 28520Sdg * ...companion to Rev. 2.0 of 'ed' driver. 298876Srgrimes * 3043Sdg * Revision 1.1 93/06/23 03:01:07 davidg 3143Sdg * Initial revision 328876Srgrimes * 336Sdg */ 346Sdg 356Sdg/* 366Sdg * Page 0 register offsets 376Sdg */ 386Sdg#define ED_P0_CR 0x00 /* Command Register */ 396Sdg 406Sdg#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 416Sdg#define ED_P0_PSTART 0x01 /* Page Start register (write) */ 426Sdg 436Sdg#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 446Sdg#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ 456Sdg 466Sdg#define ED_P0_BNRY 0x03 /* Boundary Pointer */ 476Sdg 486Sdg#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ 496Sdg#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ 506Sdg 516Sdg#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 526Sdg#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 536Sdg 546Sdg#define ED_P0_FIFO 0x06 /* FIFO register (read) */ 556Sdg#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 566Sdg 576Sdg#define ED_P0_ISR 0x07 /* Interrupt Status Register */ 586Sdg 596Sdg#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 606Sdg#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 616Sdg 626Sdg#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 636Sdg#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 646Sdg 656Sdg#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 666Sdg 676Sdg#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 686Sdg 696Sdg#define ED_P0_RSR 0x0c /* Receive Status (read) */ 706Sdg#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 716Sdg 726Sdg#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 736Sdg#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 746Sdg 756Sdg#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ 766Sdg#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ 776Sdg 786Sdg#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ 796Sdg#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 806Sdg 816Sdg/* 826Sdg * Page 1 register offsets 836Sdg */ 846Sdg#define ED_P1_CR 0x00 /* Command Register */ 856Sdg#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ 866Sdg#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ 876Sdg#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ 886Sdg#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ 896Sdg#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ 906Sdg#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ 916Sdg#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ 926Sdg#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ 936Sdg#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ 946Sdg#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ 956Sdg#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ 966Sdg#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ 976Sdg#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ 986Sdg#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ 996Sdg#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ 1006Sdg 1016Sdg/* 1026Sdg * Page 2 register offsets 1036Sdg */ 1046Sdg#define ED_P2_CR 0x00 /* Command Register */ 1056Sdg#define ED_P2_PSTART 0x01 /* Page Start (read) */ 1066Sdg#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 1076Sdg#define ED_P2_PSTOP 0x02 /* Page Stop (read) */ 1086Sdg#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 1096Sdg#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 1106Sdg#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ 1116Sdg#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ 1126Sdg#define ED_P2_ACU 0x06 /* Address Counter Upper */ 1136Sdg#define ED_P2_ACL 0x07 /* Address Counter Lower */ 1146Sdg#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ 1156Sdg#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 1166Sdg#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ 1176Sdg#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 1186Sdg 1196Sdg/* 1206Sdg * Command Register (CR) definitions 1216Sdg */ 1226Sdg 1236Sdg/* 1246Sdg * STP: SToP. Software reset command. Takes the controller offline. No 1256Sdg * packets will be received or transmitted. Any reception or 1266Sdg * transmission in progress will continue to completion before 1276Sdg * entering reset state. To exit this state, the STP bit must 1286Sdg * reset and the STA bit must be set. The software reset has 1296Sdg * executed only when indicated by the RST bit in the ISR being 1306Sdg * set. 1316Sdg */ 1326Sdg#define ED_CR_STP 0x01 1336Sdg 1346Sdg/* 1356Sdg * STA: STArt. This bit is used to activate the NIC after either power-up, 1366Sdg * or when the NIC has been put in reset mode by software command 1376Sdg * or error. 1386Sdg */ 1396Sdg#define ED_CR_STA 0x02 1406Sdg 1416Sdg/* 1426Sdg * TXP: Transmit Packet. This bit must be set to indicate transmission of 1436Sdg * a packet. TXP is internally reset either after the transmission is 1446Sdg * completed or aborted. This bit should be set only after the Transmit 1456Sdg * Byte Count and Transmit Page Start register have been programmed. 1466Sdg */ 1476Sdg#define ED_CR_TXP 0x04 1486Sdg 1496Sdg/* 1506Sdg * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 1516Sdg * of the remote DMA channel. RD2 can be set to abort any remote DMA 1526Sdg * command in progress. The Remote Byte Count registers should be cleared 1536Sdg * when a remote DMA has been aborted. The Remote Start Addresses are not 1546Sdg * restored to the starting address if the remote DMA is aborted. 1556Sdg * 1566Sdg * RD2 RD1 RD0 function 1576Sdg * 0 0 0 not allowed 1586Sdg * 0 0 1 remote read 1596Sdg * 0 1 0 remote write 1606Sdg * 0 1 1 send packet 1616Sdg * 1 X X abort 1626Sdg */ 1636Sdg#define ED_CR_RD0 0x08 1646Sdg#define ED_CR_RD1 0x10 1656Sdg#define ED_CR_RD2 0x20 1666Sdg 1676Sdg/* 1686Sdg * PS0, PS1: Page Select. The two bits select which register set or 'page' to 1696Sdg * access. 1706Sdg * 1716Sdg * PS1 PS0 page 1726Sdg * 0 0 0 1736Sdg * 0 1 1 1746Sdg * 1 0 2 1756Sdg * 1 1 reserved 1766Sdg */ 1776Sdg#define ED_CR_PS0 0x40 1786Sdg#define ED_CR_PS1 0x80 1796Sdg/* bit encoded aliases */ 1806Sdg#define ED_CR_PAGE_0 0x00 /* (for consistency) */ 1816Sdg#define ED_CR_PAGE_1 0x40 1826Sdg#define ED_CR_PAGE_2 0x80 1836Sdg 1846Sdg/* 1856Sdg * Interrupt Status Register (ISR) definitions 1866Sdg */ 1876Sdg 1886Sdg/* 1896Sdg * PRX: Packet Received. Indicates packet received with no errors. 1906Sdg */ 1916Sdg#define ED_ISR_PRX 0x01 1926Sdg 1936Sdg/* 1946Sdg * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 1956Sdg */ 1966Sdg#define ED_ISR_PTX 0x02 1976Sdg 1986Sdg/* 1996Sdg * RXE: Receive Error. Indicates that a packet was received with one or more 2006Sdg * the following errors: CRC error, frame alignment error, FIFO overrun, 2016Sdg * missed packet. 2026Sdg */ 2036Sdg#define ED_ISR_RXE 0x04 2046Sdg 2056Sdg/* 2066Sdg * TXE: Transmission Error. Indicates that an attempt to transmit a packet 2076Sdg * resulted in one or more of the following errors: excessive 2086Sdg * collisions, FIFO underrun. 2096Sdg */ 2106Sdg#define ED_ISR_TXE 0x08 2116Sdg 2126Sdg/* 2136Sdg * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 21413765Smpp * would exceed (has exceeded?) the boundary pointer, resulting in data 2156Sdg * that was previously received and not yet read from the buffer to be 2166Sdg * overwritten. 2176Sdg */ 2186Sdg#define ED_ISR_OVW 0x10 2196Sdg 2206Sdg/* 2216Sdg * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley 2226Sdg * Counters has been set. 2236Sdg */ 2246Sdg#define ED_ISR_CNT 0x20 2256Sdg 2266Sdg/* 2276Sdg * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed. 2286Sdg */ 2296Sdg#define ED_ISR_RDC 0x40 2306Sdg 2316Sdg/* 2326Sdg * RST: Reset status. Set when the NIC enters the reset state and cleared when a 2336Sdg * Start Command is issued to the CR. This bit is also set when a receive 2346Sdg * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 2356Sdg * packets have been removed from the ring. This is a read-only bit. 2366Sdg */ 2376Sdg#define ED_ISR_RST 0x80 2386Sdg 2396Sdg/* 2406Sdg * Interrupt Mask Register (IMR) definitions 2416Sdg */ 2426Sdg 2436Sdg/* 2446Sdg * PRXE: Packet Received interrupt Enable. If set, a received packet will cause 2456Sdg * an interrupt. 2466Sdg */ 2476Sdg#define ED_IMR_PRXE 0x01 2486Sdg 2496Sdg/* 2506Sdg * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when 2516Sdg * a packet transmission completes. 2526Sdg */ 2536Sdg#define ED_IMR_PTXE 0x02 2546Sdg 2556Sdg/* 2566Sdg * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a 2576Sdg * packet is received with an error. 2586Sdg */ 2596Sdg#define ED_IMR_RXEE 0x04 2606Sdg 2616Sdg/* 2626Sdg * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever 2636Sdg * a transmission results in an error. 2646Sdg */ 2656Sdg#define ED_IMR_TXEE 0x08 2666Sdg 2676Sdg/* 2686Sdg * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever 26913765Smpp * the receive ring-buffer is overrun. i.e. when the boundary pointer is exceeded. 2706Sdg */ 2716Sdg#define ED_IMR_OVWE 0x10 2726Sdg 2736Sdg/* 2746Sdg * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever 2756Sdg * the MSB of one or more of the Network Statistics counters has been set. 2766Sdg */ 2776Sdg#define ED_IMR_CNTE 0x20 2786Sdg 2796Sdg/* 2806Sdg * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated 2816Sdg * when a remote DMA transfer has completed. 2826Sdg */ 2836Sdg#define ED_IMR_RDCE 0x40 2846Sdg 2856Sdg/* 2866Sdg * bit 7 is unused/reserved 2876Sdg */ 2886Sdg 2896Sdg/* 2906Sdg * Data Configuration Register (DCR) definitions 2916Sdg */ 2926Sdg 2936Sdg/* 2946Sdg * WTS: Word Transfer Select. WTS establishes byte or word transfers for 2956Sdg * both remote and local DMA transfers 2966Sdg */ 2976Sdg#define ED_DCR_WTS 0x01 2986Sdg 2996Sdg/* 3006Sdg * BOS: Byte Order Select. BOS sets the byte order for the host. 3016Sdg * Should be 0 for 80x86, and 1 for 68000 series processors 3026Sdg */ 3036Sdg#define ED_DCR_BOS 0x02 3046Sdg 3056Sdg/* 3066Sdg * LAS: Long Address Select. When LAS is 1, the contents of the remote 3076Sdg * DMA registers RSAR0 and RSAR1 are used to provide A16-A31 3086Sdg */ 3096Sdg#define ED_DCR_LAS 0x04 3106Sdg 3116Sdg/* 3126Sdg * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 3136Sdg * of the TCR must also be programmed for loopback operation. 3146Sdg * When 1, normal operation is selected. 3156Sdg */ 3166Sdg#define ED_DCR_LS 0x08 3176Sdg 3186Sdg/* 3196Sdg * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 3206Sdg * under program control. When 1, remote DMA is automatically initiated 32113765Smpp * and the boundary pointer is automatically updated 3226Sdg */ 3236Sdg#define ED_DCR_AR 0x10 3246Sdg 3256Sdg/* 3266Sdg * FT0, FT1: Fifo Threshold select. 3276Sdg * FT1 FT0 Word-width Byte-width 3286Sdg * 0 0 1 word 2 bytes 3296Sdg * 0 1 2 words 4 bytes 3306Sdg * 1 0 4 words 8 bytes 3316Sdg * 1 1 8 words 12 bytes 3326Sdg * 3336Sdg * During transmission, the FIFO threshold indicates the number of bytes 3346Sdg * or words that the FIFO has filled from the local DMA before BREQ is 3356Sdg * asserted. The transmission threshold is 16 bytes minus the receiver 3366Sdg * threshold. 3376Sdg */ 3386Sdg#define ED_DCR_FT0 0x20 3396Sdg#define ED_DCR_FT1 0x40 3406Sdg 3416Sdg/* 3426Sdg * bit 7 (0x80) is unused/reserved 3436Sdg */ 3446Sdg 3456Sdg/* 3466Sdg * Transmit Configuration Register (TCR) definitions 3476Sdg */ 3486Sdg 3496Sdg/* 3506Sdg * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 3516Sdg * is not appended by the transmitter. 3526Sdg */ 3536Sdg#define ED_TCR_CRC 0x01 3546Sdg 3556Sdg/* 3566Sdg * LB0, LB1: Loopback control. These two bits set the type of loopback that is 3576Sdg * to be performed. 3586Sdg * 3596Sdg * LB1 LB0 mode 3606Sdg * 0 0 0 - normal operation (DCR_LS = 0) 3616Sdg * 0 1 1 - internal loopback (DCR_LS = 0) 3626Sdg * 1 0 2 - external loopback (DCR_LS = 1) 3636Sdg * 1 1 3 - external loopback (DCR_LS = 0) 3646Sdg */ 3656Sdg#define ED_TCR_LB0 0x02 3666Sdg#define ED_TCR_LB1 0x04 3676Sdg 3686Sdg/* 3696Sdg * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 3706Sdg * another station to disable the NIC's transmitter by transmitting to 3716Sdg * a multicast address hashing to bit 62. Reception of a multicast address 3726Sdg * hashing to bit 63 enables the transmitter. 3736Sdg */ 3746Sdg#define ED_TCR_ATD 0x08 3756Sdg 3766Sdg/* 3776Sdg * OFST: Collision Offset enable. This bit when set modifies the backoff 3786Sdg * algorithm to allow prioritization of nodes. 3796Sdg */ 3806Sdg#define ED_TCR_OFST 0x10 3818876Srgrimes 3826Sdg/* 3836Sdg * bits 5, 6, and 7 are unused/reserved 3846Sdg */ 3856Sdg 3866Sdg/* 3876Sdg * Transmit Status Register (TSR) definitions 3886Sdg */ 3896Sdg 3906Sdg/* 3916Sdg * PTX: Packet Transmitted. Indicates successful transmission of packet. 3926Sdg */ 3936Sdg#define ED_TSR_PTX 0x01 3946Sdg 3956Sdg/* 3966Sdg * bit 1 (0x02) is unused/reserved 3976Sdg */ 3986Sdg 3996Sdg/* 4006Sdg * COL: Transmit Collided. Indicates that the transmission collided at least 4016Sdg * once with another station on the network. 4026Sdg */ 4036Sdg#define ED_TSR_COL 0x04 4046Sdg 4056Sdg/* 4066Sdg * ABT: Transmit aborted. Indicates that the transmission was aborted due to 4076Sdg * excessive collisions. 4086Sdg */ 4096Sdg#define ED_TSR_ABT 0x08 4106Sdg 4116Sdg/* 4126Sdg * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 4136Sdg * transmission of the packet. (Transmission is not aborted because 4146Sdg * of a loss of carrier) 4156Sdg */ 4166Sdg#define ED_TSR_CRS 0x10 4176Sdg 4186Sdg/* 4196Sdg * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 4206Sdg * transmission memory before the FIFO emptied. Transmission of the 4216Sdg * packet was aborted. 4226Sdg */ 4236Sdg#define ED_TSR_FU 0x20 4246Sdg 4256Sdg/* 4266Sdg * CDH: CD Heartbeat. Indicates that the collision detection circuitry 4276Sdg * isn't working correctly during a collision heartbeat test. 4286Sdg */ 4296Sdg#define ED_TSR_CDH 0x40 4306Sdg 4316Sdg/* 4326Sdg * OWC: Out of Window Collision: Indicates that a collision occurred after 4336Sdg * a slot time (51.2us). The transmission is rescheduled just as in 4346Sdg * normal collisions. 4356Sdg */ 4366Sdg#define ED_TSR_OWC 0x80 4376Sdg 4386Sdg/* 4396Sdg * Receiver Configuration Register (RCR) definitions 4406Sdg */ 4416Sdg 4426Sdg/* 4436Sdg * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 4446Sdg * packets with CRC and frame errors are not discarded. 4456Sdg */ 4466Sdg#define ED_RCR_SEP 0x01 4476Sdg 4486Sdg/* 4496Sdg * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 4506Sdg * If set to 1, packets with less than 64 byte are not discarded. 4516Sdg */ 4526Sdg#define ED_RCR_AR 0x02 4536Sdg 4546Sdg/* 4556Sdg * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 4566Sdg * accepted. 4576Sdg */ 4586Sdg#define ED_RCR_AB 0x04 4596Sdg 4606Sdg/* 4616Sdg * AM: Accept Multicast. If set, packets sent to a multicast address are checked 4626Sdg * for a match in the hashing array. If clear, multicast packets are ignored. 4636Sdg */ 4646Sdg#define ED_RCR_AM 0x08 4656Sdg 4666Sdg/* 4676Sdg * PRO: Promiscuous Physical. If set, all packets with a physical addresses are 4686Sdg * accepted. If clear, a physical destination address must match this 4696Sdg * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM 4706Sdg * must also be set. In addition, the multicast hashing array must be set 4716Sdg * to all 1's so that all multicast addresses are accepted. 4726Sdg */ 4736Sdg#define ED_RCR_PRO 0x10 4746Sdg 4756Sdg/* 4766Sdg * MON: Monitor Mode. If set, packets will be checked for good CRC and framing, 4776Sdg * but are not stored in the ring-buffer. If clear, packets are stored (normal 4786Sdg * operation). 4796Sdg */ 4806Sdg#define ED_RCR_MON 0x20 4816Sdg 4826Sdg/* 4836Sdg * bits 6 and 7 are unused/reserved. 4846Sdg */ 4856Sdg 4866Sdg/* 4876Sdg * Receiver Status Register (RSR) definitions 4886Sdg */ 4896Sdg 4906Sdg/* 4916Sdg * PRX: Packet Received without error. 4926Sdg */ 4936Sdg#define ED_RSR_PRX 0x01 4946Sdg 4956Sdg/* 4966Sdg * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame 4976Sdg * alignment errors. 4986Sdg */ 4996Sdg#define ED_RSR_CRC 0x02 5006Sdg 5016Sdg/* 5026Sdg * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on 50313765Smpp * a byte boundary and the CRC did not match at the last byte boundary. 5046Sdg */ 5056Sdg#define ED_RSR_FAE 0x04 5066Sdg 5076Sdg/* 5086Sdg * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA) 5096Sdg * causing it to overrun. Reception of the packet is aborted. 5106Sdg */ 5116Sdg#define ED_RSR_FO 0x08 5126Sdg 5136Sdg/* 5146Sdg * MPA: Missed Packet. Indicates that the received packet couldn't be stored in 5156Sdg * the ring-buffer because of insufficient buffer space (exceeding the 51613765Smpp * boundary pointer), or because the transfer to the ring-buffer was inhibited 5176Sdg * by RCR_MON - monitor mode. 5186Sdg */ 5196Sdg#define ED_RSR_MPA 0x10 5206Sdg 5216Sdg/* 5226Sdg * PHY: Physical address. If 0, the packet received was sent to a physical address. 5236Sdg * If 1, the packet was accepted because of a multicast/broadcast address 5246Sdg * match. 5256Sdg */ 5266Sdg#define ED_RSR_PHY 0x20 5276Sdg 5286Sdg/* 52913765Smpp * DIS: Receiver Disabled. Set to indicate that the receiver has entered monitor 5306Sdg * mode. Cleared when the receiver exits monitor mode. 5316Sdg */ 5326Sdg#define ED_RSR_DIS 0x40 5336Sdg 5346Sdg/* 5356Sdg * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs 5366Sdg * are active, and the transceiver has set the CD line as a result of the 5376Sdg * jabber. 5386Sdg */ 5396Sdg#define ED_RSR_DFR 0x80 5406Sdg 5416Sdg/* 54213765Smpp * receive ring descriptor 5436Sdg * 5446Sdg * The National Semiconductor DS8390 Network interface controller uses 5456Sdg * the following receive ring headers. The way this works is that the 5466Sdg * memory on the interface card is chopped up into 256 bytes blocks. 5476Sdg * A contiguous portion of those blocks are marked for receive packets 5486Sdg * by setting start and end block #'s in the NIC. For each packet that 5496Sdg * is put into the receive ring, one of these headers (4 bytes each) is 5501831Sdg * tacked onto the front. The first byte is a copy of the receiver status 5511831Sdg * register at the time the packet was received. 5526Sdg */ 5536Sdgstruct ed_ring { 5541831Sdg u_char rsr; /* receiver status */ 5556Sdg u_char next_packet; /* pointer to next packet */ 5566Sdg u_short count; /* bytes in packet (length + 4) */ 5576Sdg}; 5586Sdg 5596Sdg/* 5606Sdg * Common constants 5616Sdg */ 5626Sdg#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 5636Sdg#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 5646Sdg 5656Sdg/* 5666Sdg * Vendor types 5676Sdg */ 5686Sdg#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ 5696Sdg#define ED_VENDOR_3COM 0x01 /* 3Com */ 570520Sdg#define ED_VENDOR_NOVELL 0x02 /* Novell */ 57111016Sphk#define ED_VENDOR_PCCARD 0x03 /* PCMCIA/PCCARD */ 57217465Sdg#define ED_VENDOR_HP 0x04 /* Hewlett Packard */ 5736Sdg 5746Sdg/* 57542Sdg * Compile-time config flags 57642Sdg */ 57742Sdg/* 57813765Smpp * this sets the default for enabling/disabling the transceiver 57942Sdg */ 580520Sdg#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001 58142Sdg 58242Sdg/* 583172Sdg * This forces the board to be used in 8/16bit mode even if it 584172Sdg * autoconfigs differently 585172Sdg */ 586520Sdg#define ED_FLAGS_FORCE_8BIT_MODE 0x0002 587520Sdg#define ED_FLAGS_FORCE_16BIT_MODE 0x0004 588172Sdg 589172Sdg/* 590172Sdg * This disables the use of double transmit buffers. 591172Sdg */ 592520Sdg#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008 593172Sdg 594172Sdg/* 595520Sdg * This forces all operations with the NIC memory to use Programmed 596520Sdg * I/O (i.e. not via shared memory) 597520Sdg */ 598520Sdg#define ED_FLAGS_FORCE_PIO 0x0010 599520Sdg 600520Sdg/* 6016Sdg * Definitions for Western digital/SMC WD80x3 series ASIC 6026Sdg */ 6036Sdg/* 6046Sdg * Memory Select Register (MSR) 6056Sdg */ 6066Sdg#define ED_WD_MSR 0 6076Sdg 6081349Sdg/* next three definitions for Toshiba */ 6091015Sats#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */ 6101015Sats#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */ 6111015Sats#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits, 6121015Sats 1 = 8 bits (R/W) */ 6131349Sdg#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ 6141349Sdg#define ED_WD_MSR_MENB 0x40 /* Memory enable */ 6151349Sdg#define ED_WD_MSR_RST 0x80 /* Reset board */ 6166Sdg 6176Sdg/* 6186Sdg * Interface Configuration Register (ICR) 6196Sdg */ 6206Sdg#define ED_WD_ICR 1 6216Sdg 6226Sdg#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */ 6236Sdg#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */ 62443Sdg#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */ 6256Sdg#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ 6266Sdg#define ED_WD_ICR_RLA 0x10 /* recall LAN address */ 6276Sdg#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */ 6286Sdg#define ED_WD_ICR_RIO 0x40 /* recall i/o address */ 6296Sdg#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */ 6301015Sats#ifdef TOSH_ETHER 6311015Sats#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */ 6321015Sats#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K, 6331015Sats 0x02 = 16K, 0x01 = 8K */ 6341015Sats /* 64K can only be used if mem address 6351015Sats above 1Mb */ 6361015Sats /* IAR holds address A23-A16 (R/W) */ 6371015Sats#endif 6386Sdg 6396Sdg/* 64043Sdg * IO Address Register (IAR) 64143Sdg */ 64243Sdg#define ED_WD_IAR 2 64343Sdg 64443Sdg/* 64543Sdg * EEROM Address Register 64643Sdg */ 64743Sdg#define ED_WD_EAR 3 64843Sdg 64943Sdg/* 6506Sdg * Interrupt Request Register (IRR) 6516Sdg */ 6526Sdg#define ED_WD_IRR 4 6536Sdg 6546Sdg#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ 6556Sdg#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ 6566Sdg#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ 6576Sdg#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ 6586Sdg#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ 65943Sdg 66043Sdg/* 6611349Sdg * The three bits of the encoded IRQ are decoded as follows: 66243Sdg * 66343Sdg * IR2 IR1 IR0 IRQ 66443Sdg * 0 0 0 2/9 66543Sdg * 0 0 1 3 66643Sdg * 0 1 0 5 66743Sdg * 0 1 1 7 66843Sdg * 1 0 0 10 66943Sdg * 1 0 1 11 67043Sdg * 1 1 0 15 67143Sdg * 1 1 1 4 67243Sdg */ 67343Sdg#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 67443Sdg#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 6756Sdg#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */ 6766Sdg 6776Sdg/* 6786Sdg * LA Address Register (LAAR) 6796Sdg */ 6806Sdg#define ED_WD_LAAR 5 6816Sdg 6826Sdg#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ 6836Sdg#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ 6846Sdg#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */ 6856Sdg#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */ 6866Sdg 6876Sdg/* i/o base offset to station address/card-ID PROM */ 6886Sdg#define ED_WD_PROM 8 6896Sdg 6901349Sdg/* 6911349Sdg * 83C790 specific registers 6921349Sdg */ 6931349Sdg/* 6941349Sdg * Hardware Support Register (HWR) ('790) 6951349Sdg */ 6961349Sdg#define ED_WD790_HWR 4 6971349Sdg 6981349Sdg#define WD_WD790_HWR_NUKE 0x10 /* hardware reset */ 6991349Sdg#define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */ 7001349Sdg#define ED_WD790_HWR_SWH 0x80 /* switch register set */ 7011349Sdg 7021349Sdg/* 7031349Sdg * ICR790 Interrupt Control Register for the 83C790 7041349Sdg */ 7051349Sdg#define ED_WD790_ICR 6 7061349Sdg 7071349Sdg#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */ 7081349Sdg 7091349Sdg/* 7105807Sdg * REV/IOPA Revision / I/O Pipe register for the 83C79X 7115807Sdg */ 7125807Sdg#define ED_WD790_REV 7 7135807Sdg 7145807Sdg#define ED_WD790 0x20 7155807Sdg#define ED_WD795 0x40 7165807Sdg 7175807Sdg/* 7185807Sdg * 79X RAM Address Register (RAR) 7195807Sdg * Enabled with SWH bit=1 in HWR register 7205807Sdg */ 7215807Sdg#define ED_WD790_RAR 0x0b 7225807Sdg 7235807Sdg#define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */ 7245807Sdg#define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */ 7255807Sdg#define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */ 7265807Sdg#define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */ 7275807Sdg 7285807Sdg/* 7291349Sdg * General Control Register (GCR) 7301349Sdg * Enabled with SWH bit=1 in HWR register 7311349Sdg */ 7321349Sdg#define ED_WD790_GCR 0x0d 7331349Sdg 7341349Sdg#define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */ 7351349Sdg#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */ 7361349Sdg#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */ 7371349Sdg#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */ 7385807Sdg#define ED_WD790_GCR_LIT 0x01 /* Link Integrity Test Enable */ 7391349Sdg/* 7401349Sdg * The three bits of the encoded IRQ are decoded as follows: 7411349Sdg * 7421349Sdg * IR2 IR1 IR0 IRQ 7431349Sdg * 0 0 0 none 7441349Sdg * 0 0 1 9 7451349Sdg * 0 1 0 3 7461349Sdg * 0 1 1 5 7471349Sdg * 1 0 0 7 7481349Sdg * 1 0 1 10 7491349Sdg * 1 1 0 11 7501349Sdg * 1 1 1 15 7511349Sdg */ 7521349Sdg 7536Sdg/* i/o base offset to CARD ID */ 7546Sdg#define ED_WD_CARD_ID ED_WD_PROM+6 7556Sdg 756520Sdg/* Board type codes in card ID */ 7576Sdg#define ED_TYPE_WD8003S 0x02 7586Sdg#define ED_TYPE_WD8003E 0x03 7596Sdg#define ED_TYPE_WD8013EBT 0x05 7601015Sats#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */ 7611015Sats#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */ 7621015Sats#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */ 7631015Sats#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */ 7641073Sdg#define ED_TYPE_WD8003W 0x24 7651075Sdg#define ED_TYPE_WD8003EB 0x25 766808Sdg#define ED_TYPE_WD8013W 0x26 767426Sdg#define ED_TYPE_WD8013EP 0x27 768426Sdg#define ED_TYPE_WD8013WC 0x28 7696Sdg#define ED_TYPE_WD8013EPC 0x29 770791Sdg#define ED_TYPE_SMC8216T 0x2a 771791Sdg#define ED_TYPE_SMC8216C 0x2b 7721073Sdg#define ED_TYPE_WD8013EBP 0x2c 7736Sdg 7746Sdg/* Bit definitions in card ID */ 7756Sdg#define ED_WD_REV_MASK 0x1f /* Revision mask */ 7766Sdg#define ED_WD_SOFTCONFIG 0x20 /* Soft config */ 7776Sdg#define ED_WD_LARGERAM 0x40 /* Large RAM */ 7786Sdg#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ 7796Sdg 7806Sdg/* 7816Sdg * Checksum total. All 8 bytes in station address PROM will add up to this 7826Sdg */ 783968Sats#ifdef TOSH_ETHER 784968Sats#define ED_WD_ROM_CHECKSUM_TOTAL 0xA5 785968Sats#else 7866Sdg#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF 787968Sats#endif 7886Sdg 7896Sdg#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */ 7906Sdg#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */ 7916Sdg#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */ 7926Sdg 7936Sdg#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */ 7946Sdg 7956Sdg/* 7966Sdg * Definitions for 3Com 3c503 7976Sdg */ 7986Sdg#define ED_3COM_NIC_OFFSET 0 7996Sdg#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ 8006Sdg 8016Sdg/* 8026Sdg * XXX - The I/O address range is fragmented in the 3c503; this is the 8036Sdg * number of regs at iobase. 8046Sdg */ 8056Sdg#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */ 8066Sdg 807520Sdg/* tx memory starts in second bank on 8bit cards */ 808520Sdg#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20 8096Sdg 810520Sdg/* tx memory starts in first bank on 16bit cards */ 811520Sdg#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0 812520Sdg 813520Sdg/* ...and rx memory starts in second bank */ 814520Sdg#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20 815520Sdg 816520Sdg 8176Sdg/* 8186Sdg * Page Start Register. Must match PSTART in NIC 8196Sdg */ 8206Sdg#define ED_3COM_PSTR 0 8216Sdg 8226Sdg/* 8236Sdg * Page Stop Register. Must match PSTOP in NIC 8246Sdg */ 8256Sdg#define ED_3COM_PSPR 1 8266Sdg 8276Sdg/* 8286Sdg * Drq Timer Register. Determines number of bytes to be transfered during 8296Sdg * a DMA burst. 8306Sdg */ 8316Sdg#define ED_3COM_DQTR 2 8326Sdg 8336Sdg/* 8346Sdg * Base Configuration Register. Read-only register which contains the 8356Sdg * board-configured I/O base address of the adapter. Bit encoded. 8366Sdg */ 8376Sdg#define ED_3COM_BCFR 3 8386Sdg 8396Sdg#define ED_3COM_BCFR_2E0 0x01 8406Sdg#define ED_3COM_BCFR_2A0 0x02 8416Sdg#define ED_3COM_BCFR_280 0x04 8426Sdg#define ED_3COM_BCFR_250 0x08 8436Sdg#define ED_3COM_BCFR_350 0x10 8446Sdg#define ED_3COM_BCFR_330 0x20 8456Sdg#define ED_3COM_BCFR_310 0x40 8466Sdg#define ED_3COM_BCFR_300 0x80 8476Sdg 8486Sdg/* 8496Sdg * EPROM Configuration Register. Read-only register which contains the 8506Sdg * board-configured memory base address. Bit encoded. 8516Sdg */ 8526Sdg#define ED_3COM_PCFR 4 8536Sdg 8546Sdg#define ED_3COM_PCFR_C8000 0x10 8556Sdg#define ED_3COM_PCFR_CC000 0x20 8566Sdg#define ED_3COM_PCFR_D8000 0x40 8576Sdg#define ED_3COM_PCFR_DC000 0x80 8586Sdg 8596Sdg/* 8606Sdg * GA Configuration Register. Gate-Array Configuration Register. 8616Sdg */ 8626Sdg#define ED_3COM_GACFR 5 8636Sdg 8646Sdg/* 8656Sdg * mbs2 mbs1 mbs0 start address 8666Sdg * 0 0 0 0x0000 8676Sdg * 0 0 1 0x2000 8686Sdg * 0 1 0 0x4000 8696Sdg * 0 1 1 0x6000 8706Sdg * 8716Sdg * Note that with adapters with only 8K, the setting for 0x2000 must 8726Sdg * always be used. 8736Sdg */ 8746Sdg#define ED_3COM_GACFR_MBS0 0x01 8756Sdg#define ED_3COM_GACFR_MBS1 0x02 8766Sdg#define ED_3COM_GACFR_MBS2 0x04 8776Sdg 8786Sdg#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */ 8796Sdg#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */ 8806Sdg#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ 8816Sdg#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ 8826Sdg#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ 8836Sdg 8846Sdg/* 8856Sdg * Control Register. Miscellaneous control functions. 8866Sdg */ 8876Sdg#define ED_3COM_CR 6 8886Sdg 8896Sdg#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */ 8906Sdg#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 8916Sdg#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 8926Sdg#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 8936Sdg#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */ 8946Sdg#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */ 8956Sdg#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */ 8966Sdg#define ED_3COM_CR_START 0x80 /* Start DMA controller */ 8976Sdg 8986Sdg/* 8996Sdg * Status Register. Miscellaneous status information. 9006Sdg */ 9016Sdg#define ED_3COM_STREG 7 9026Sdg 9036Sdg#define ED_3COM_STREG_REV 0x07 /* GA revision */ 9046Sdg#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */ 9056Sdg#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */ 9066Sdg#define ED_3COM_STREG_OFLW 0x20 /* Overflow */ 9076Sdg#define ED_3COM_STREG_UFLW 0x40 /* Underflow */ 9086Sdg#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */ 9096Sdg 9106Sdg/* 9116Sdg * Interrupt/DMA Configuration Register 9126Sdg */ 9136Sdg#define ED_3COM_IDCFR 8 9146Sdg 9156Sdg#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ 9166Sdg#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ 9176Sdg#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ 9186Sdg#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */ 9196Sdg#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 9206Sdg#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 9216Sdg#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 9226Sdg#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 9236Sdg 9246Sdg/* 9256Sdg * DMA Address Register MSB 9266Sdg */ 9276Sdg#define ED_3COM_DAMSB 9 9286Sdg 9296Sdg/* 9306Sdg * DMA Address Register LSB 9316Sdg */ 9326Sdg#define ED_3COM_DALSB 0x0a 9336Sdg 9346Sdg/* 9356Sdg * Vector Pointer Register 2 9366Sdg */ 9376Sdg#define ED_3COM_VPTR2 0x0b 9386Sdg 9396Sdg/* 9406Sdg * Vector Pointer Register 1 9416Sdg */ 9426Sdg#define ED_3COM_VPTR1 0x0c 9436Sdg 9446Sdg/* 9456Sdg * Vector Pointer Register 0 9466Sdg */ 9476Sdg#define ED_3COM_VPTR0 0x0d 9486Sdg 9496Sdg/* 9506Sdg * Register File Access MSB 9516Sdg */ 9526Sdg#define ED_3COM_RFMSB 0x0e 9536Sdg 9546Sdg/* 9556Sdg * Register File Access LSB 9566Sdg */ 9576Sdg#define ED_3COM_RFLSB 0x0f 958520Sdg 959520Sdg/* 960520Sdg * Definitions for Novell NE1000/2000 boards 961520Sdg */ 962520Sdg 963520Sdg/* 964520Sdg * Board type codes 965520Sdg */ 966520Sdg#define ED_TYPE_NE1000 0x01 967520Sdg#define ED_TYPE_NE2000 0x02 968520Sdg 969520Sdg/* 970520Sdg * Register offsets/total 971520Sdg */ 972520Sdg#define ED_NOVELL_NIC_OFFSET 0x00 973520Sdg#define ED_NOVELL_ASIC_OFFSET 0x10 974520Sdg#define ED_NOVELL_IO_PORTS 32 975520Sdg 976520Sdg/* 977520Sdg * Remote DMA data register; for reading or writing to the NIC mem 978520Sdg * via programmed I/O (offset from ASIC base) 979520Sdg */ 980520Sdg#define ED_NOVELL_DATA 0x00 981520Sdg 982520Sdg/* 983520Sdg * Reset register; reading from this register causes a board reset 984520Sdg */ 985520Sdg#define ED_NOVELL_RESET 0x0f 98611016Sphk 98711016Sphk/* 98811016Sphk * Definitions for PCCARD 98911016Sphk */ 99011016Sphk#define ED_PC_PAGE_OFFSET 0x40 /* page offset for NIC access to mem */ 99111016Sphk#define ED_PC_IO_PORTS 32 99211016Sphk#define ED_PC_RESET 0x1f 99311016Sphk#define ED_PC_MISC 0x18 99411016Sphk 99511016Sphk/* 99611016Sphk * if_ze.h constants 99711016Sphk */ 99811016Sphk 99911016Sphk#define ZE_PAGE_OFFSET 0x40 /* mem buffer starts at 0x4000 */ 100011016Sphk 100111016Sphk#define ZE_DATA_IO 0x10 100211016Sphk#define ZE_MISC 0x18 100311016Sphk#define ZE_RESET 0x1F 100411016Sphk 100517465Sdg/* 100617465Sdg * Definitions for HP PC LAN Adapter Plus; based on the CRYNWR packet 100717465Sdg * driver for the card. 100817465Sdg */ 100917465Sdg 101017465Sdg#define ED_HPP_ASIC_OFFSET 0x00 /* Offset to ASIC registers */ 101117465Sdg#define ED_HPP_NIC_OFFSET 0x10 /* Offset to 8390 registers */ 101217465Sdg 101317465Sdg#define ED_HPP_ID 0x00 /* ID register, always 0x4850 */ 101417465Sdg#define ED_HPP_PAGING 0x02 /* Page select register */ 101517465Sdg#define ED_HPP_OPTION 0x04 /* Bitmask of supported options */ 101617465Sdg#define ED_HPP_PAGE_0 0x08 /* Page 0 */ 101717465Sdg#define ED_HPP_PAGE_2 0x0A /* Page 2 */ 101817465Sdg#define ED_HPP_PAGE_4 0x0C /* Page 4 */ 101917465Sdg#define ED_HPP_PAGE_6 0x0E /* Page 6 */ 102017465Sdg 102117465Sdg/* PERF PAGE */ 102217465Sdg#define ED_HPP_OUT_ADDR ED_HPP_PAGE_0 /* I/O output location */ 102317465Sdg#define ED_HPP_IN_ADDR ED_HPP_PAGE_2 /* I/O input location */ 102417465Sdg#define ED_HPP_DATAPORT ED_HPP_PAGE_4 /* I/O data transfer */ 102517465Sdg/* MAC PAGE */ 102617465Sdg#define ED_HPP_MAC_ADDR 0x08 /* Offset of MAC address in MAC page */ 102717465Sdg 102817465Sdg#define ED_HPP_IO_PORTS 32 /* Number of IO ports */ 102917465Sdg 103017465Sdg#define ED_HPP_TX_PAGE_OFFSET 0x00 /* first page of TX buffer */ 103117465Sdg#define ED_HPP_RX_PAGE_START 0x06 /* start at page 6 */ 103217465Sdg#define ED_HPP_RX_PAGE_STOP 0x80 /* end at page 128 */ 103317465Sdg 103417465Sdg/* 103517465Sdg * Register pages supported. 103617465Sdg */ 103717465Sdg 103817465Sdg#define ED_HPP_PAGE_PERF 0 /* Normal operation */ 103917465Sdg#define ED_HPP_PAGE_MAC 1 /* The ethernet address and checksum */ 104017465Sdg#define ED_HPP_PAGE_HW 2 /* Hardware parameters in EEPROM */ 104117465Sdg#define ED_HPP_PAGE_LAN 4 /* Transciever selection etc */ 104217465Sdg#define ED_HPP_PAGE_ID 6 /* ID */ 104317465Sdg 104417465Sdg/* 104517465Sdg * Options supported. 104617465Sdg */ 104717465Sdg 104817465Sdg#define ED_HPP_OPTION_NIC_RESET 0x0001 /* active low */ 104917465Sdg#define ED_HPP_OPTION_CHIP_RESET 0x0002 /* active low */ 105017465Sdg#define ED_HPP_OPTION_ENABLE_IRQ 0x0004 105117465Sdg#define ED_HPP_OPTION_FAKE_INTR 0x0008 105217465Sdg#define ED_HPP_OPTION_BOOT_ROM_ENB 0x0010 105317465Sdg#define ED_HPP_OPTION_IO_ENB 0x0020 105417465Sdg#define ED_HPP_OPTION_MEM_ENABLE 0x0040 105517465Sdg#define ED_HPP_OPTION_ZERO_WAIT 0x0080 105617465Sdg#define ED_HPP_OPTION_MEM_DISABLE 0x1000 105717465Sdg 105817465Sdg/* 105917465Sdg * Page ID configuration. 106017465Sdg */ 106117465Sdg 106217465Sdg#define ED_HPP_ID_REVISION_MASK 0x0300 /* revision id */ 106317465Sdg#define ED_HPP_ID_SOFT_MODEL_MASK 0xFC00 /* soft model number */ 106417465Sdg#define ED_HPP_ID_16_BIT_ACCESS 0x0010 /* if set use 16 bit accesses */ 106517465Sdg#define ED_HPP_ID_TWISTED_PAIR 0x0040 106617465Sdg 106717465Sdg/* 106817465Sdg * Hardware configuration. 106917465Sdg */ 107017465Sdg 107117465Sdg#define ED_HPP_HW_MEM_MAP 0x09 /* low mem map location in HW page */ 107217465Sdg#define ED_HPP_HW_ID 0x0C /* revision number, capabilities */ 107317465Sdg#define ED_HPP_HW_IRQ 0x0D /* IRQ channel register in HW page */ 107417465Sdg#define ED_HPP_HW_WRAP 0x0E /* mem wrap page for rcv */ 107517465Sdg 107617465Sdg/* 107717465Sdg * Lan configuration 107817465Sdg */ 107917465Sdg 108017465Sdg#define ED_HPP_LAN_AUI 0x01 /* Use AUI */ 108117465Sdg#define ED_HPP_LAN_TL 0x40 /* Don't use AUI */ 108217465Sdg 108317465Sdg/* 108417465Sdg * Card types. 108517465Sdg */ 108617465Sdg 108717465Sdg#define ED_TYPE_HP_PCLANPLUS 0x00 1088