e1000_phy.h revision 177867
1/******************************************************************************
2
3  Copyright (c) 2001-2008, Intel Corporation
4  All rights reserved.
5
6  Redistribution and use in source and binary forms, with or without
7  modification, are permitted provided that the following conditions are met:
8
9   1. Redistributions of source code must retain the above copyright notice,
10      this list of conditions and the following disclaimer.
11
12   2. Redistributions in binary form must reproduce the above copyright
13      notice, this list of conditions and the following disclaimer in the
14      documentation and/or other materials provided with the distribution.
15
16   3. Neither the name of the Intel Corporation nor the names of its
17      contributors may be used to endorse or promote products derived from
18      this software without specific prior written permission.
19
20  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/em/e1000_phy.h 177867 2008-04-02 22:00:36Z jfv $*/
34
35#ifndef _E1000_PHY_H_
36#define _E1000_PHY_H_
37
38typedef enum {
39	e1000_ms_hw_default = 0,
40	e1000_ms_force_master,
41	e1000_ms_force_slave,
42	e1000_ms_auto
43} e1000_ms_type;
44
45typedef enum {
46	e1000_smart_speed_default = 0,
47	e1000_smart_speed_on,
48	e1000_smart_speed_off
49} e1000_smart_speed;
50
51void e1000_init_phy_ops_generic(struct e1000_hw *hw);
52s32  e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
53void e1000_null_phy_generic(struct e1000_hw *hw);
54s32  e1000_null_lplu_state(struct e1000_hw *hw, bool active);
55s32  e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
56s32  e1000_check_downshift_generic(struct e1000_hw *hw);
57s32  e1000_check_polarity_m88(struct e1000_hw *hw);
58s32  e1000_check_polarity_igp(struct e1000_hw *hw);
59s32  e1000_check_reset_block_generic(struct e1000_hw *hw);
60s32  e1000_copper_link_autoneg(struct e1000_hw *hw);
61s32  e1000_copper_link_setup_igp(struct e1000_hw *hw);
62s32  e1000_copper_link_setup_m88(struct e1000_hw *hw);
63s32  e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
64s32  e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
65s32  e1000_get_cable_length_m88(struct e1000_hw *hw);
66s32  e1000_get_cable_length_igp_2(struct e1000_hw *hw);
67s32  e1000_get_cfg_done_generic(struct e1000_hw *hw);
68s32  e1000_get_phy_id(struct e1000_hw *hw);
69s32  e1000_get_phy_info_igp(struct e1000_hw *hw);
70s32  e1000_get_phy_info_m88(struct e1000_hw *hw);
71s32  e1000_phy_sw_reset_generic(struct e1000_hw *hw);
72void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
73s32  e1000_phy_hw_reset_generic(struct e1000_hw *hw);
74s32  e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
75s32  e1000_phy_setup_autoneg(struct e1000_hw *hw);
76s32  e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
77s32  e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
78s32  e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
79s32  e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
80s32  e1000_setup_copper_link_generic(struct e1000_hw *hw);
81s32  e1000_wait_autoneg_generic(struct e1000_hw *hw);
82s32  e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
83s32  e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
84s32  e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
85s32  e1000_phy_reset_dsp(struct e1000_hw *hw);
86s32  e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
87                                u32 usec_interval, bool *success);
88s32  e1000_phy_init_script_igp3(struct e1000_hw *hw);
89e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
90s32 e1000_determine_phy_address(struct e1000_hw* hw);
91s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
92s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
93s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data,
94                                   bool read);
95void e1000_power_up_phy_copper(struct e1000_hw *hw);
96void e1000_power_down_phy_copper(struct e1000_hw *hw);
97s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
98s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
99
100#define E1000_MAX_PHY_ADDR                4
101
102/* IGP01E1000 Specific Registers */
103#define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
104#define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
105#define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
106#define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
107#define IGP01E1000_GMII_FIFO              0x14 /* GMII FIFO */
108#define IGP01E1000_PHY_CHANNEL_QUALITY    0x15 /* PHY Channel Quality */
109#define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
110#define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
111#define BM_PHY_PAGE_SELECT                22   /* Page Select for BM */
112#define IGP_PAGE_SHIFT                    5
113#define PHY_REG_MASK                      0x1F
114
115#define BM_WUC_PAGE                       800
116#define BM_WUC_ADDRESS_OPCODE             0x11
117#define BM_WUC_DATA_OPCODE                0x12
118#define BM_WUC_ENABLE_PAGE                769
119#define BM_WUC_ENABLE_REG                 17
120#define BM_WUC_ENABLE_BIT                 (1 << 2)
121#define BM_WUC_HOST_WU_BIT                (1 << 4)
122
123/* BM PHY Copper Specific Control 1 */
124#define BM_CS_CTRL1                       16
125#define BM_CS_CTRL1_ENERGY_DETECT         0x0300 /* Enable Energy Detect */
126
127/* BM PHY Copper Specific States */
128#define BM_CS_STATUS                      17
129#define BM_CS_STATUS_ENERGY_DETECT        0x0010 /* Energy Detect Status */
130
131#define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
132#define IGP01E1000_PHY_POLARITY_MASK      0x0078
133
134#define IGP01E1000_PSCR_AUTO_MDIX         0x1000
135#define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
136
137#define IGP01E1000_PSCFR_SMART_SPEED      0x0080
138
139/* Enable flexible speed on link-up */
140#define IGP01E1000_GMII_FLEX_SPD          0x0010
141#define IGP01E1000_GMII_SPD               0x0020 /* Enable SPD */
142
143#define IGP02E1000_PM_SPD                 0x0001 /* Smart Power Down */
144#define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
145#define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
146
147#define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
148
149#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
150#define IGP01E1000_PSSR_MDIX              0x0008
151#define IGP01E1000_PSSR_SPEED_MASK        0xC000
152#define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
153
154#define IGP02E1000_PHY_CHANNEL_NUM        4
155#define IGP02E1000_PHY_AGC_A              0x11B1
156#define IGP02E1000_PHY_AGC_B              0x12B1
157#define IGP02E1000_PHY_AGC_C              0x14B1
158#define IGP02E1000_PHY_AGC_D              0x18B1
159
160#define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
161#define IGP02E1000_AGC_LENGTH_MASK        0x7F
162#define IGP02E1000_AGC_RANGE              15
163
164#define IGP03E1000_PHY_MISC_CTRL          0x1B
165#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET  0x1000 /* Manually Set Duplex */
166
167#define E1000_CABLE_LENGTH_UNDEFINED      0xFF
168
169#define E1000_KMRNCTRLSTA_OFFSET          0x001F0000
170#define E1000_KMRNCTRLSTA_OFFSET_SHIFT    16
171#define E1000_KMRNCTRLSTA_REN             0x00200000
172#define E1000_KMRNCTRLSTA_DIAG_OFFSET     0x3    /* Kumeran Diagnostic */
173#define E1000_KMRNCTRLSTA_DIAG_NELPBK     0x1000 /* Nearend Loopback mode */
174
175#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
176#define IFE_PHY_SPECIAL_CONTROL     0x11 /* 100BaseTx PHY Special Control */
177#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
178#define IFE_PHY_MDIX_CONTROL        0x1C /* MDI/MDI-X Control */
179
180/* IFE PHY Extended Status Control */
181#define IFE_PESC_POLARITY_REVERSED    0x0100
182
183/* IFE PHY Special Control */
184#define IFE_PSC_AUTO_POLARITY_DISABLE      0x0010
185#define IFE_PSC_FORCE_POLARITY             0x0020
186#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
187
188/* IFE PHY Special Control and LED Control */
189#define IFE_PSCL_PROBE_MODE            0x0020
190#define IFE_PSCL_PROBE_LEDS_OFF        0x0006 /* Force LEDs 0 and 2 off */
191#define IFE_PSCL_PROBE_LEDS_ON         0x0007 /* Force LEDs 0 and 2 on */
192
193/* IFE PHY MDIX Control */
194#define IFE_PMC_MDIX_STATUS      0x0020 /* 1=MDI-X, 0=MDI */
195#define IFE_PMC_FORCE_MDIX       0x0040 /* 1=force MDI-X, 0=force MDI */
196#define IFE_PMC_AUTO_MDIX        0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
197
198#endif
199