1200243Sjfv/****************************************************************************** 2169240Sjfv 3256200Sjfv Copyright (c) 2001-2013, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32200243Sjfv******************************************************************************/ 33200243Sjfv/*$FreeBSD$*/ 34169240Sjfv 35169240Sjfv#ifndef _E1000_80003ES2LAN_H_ 36169240Sjfv#define _E1000_80003ES2LAN_H_ 37169240Sjfv 38228386Sjfv#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 39228386Sjfv#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 40228386Sjfv#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 41228386Sjfv#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F 42169240Sjfv 43228386Sjfv#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 44228386Sjfv#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 45228386Sjfv#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 46169240Sjfv 47169240Sjfv#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 48228386Sjfv#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 49228386Sjfv#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 50169240Sjfv 51228386Sjfv#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C 52228386Sjfv#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004 53200243Sjfv 54256200Sjfv#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */ 55228386Sjfv#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 56169240Sjfv 57228386Sjfv#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 58228386Sjfv#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 59169240Sjfv 60169240Sjfv/* GG82563 PHY Specific Status Register (Page 0, Register 16 */ 61256200Sjfv#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */ 62228386Sjfv#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 63228386Sjfv#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ 64228386Sjfv#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ 65228386Sjfv#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ 66169240Sjfv 67169240Sjfv/* PHY Specific Control Register 2 (Page 0, Register 26) */ 68256200Sjfv#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */ 69169240Sjfv 70169240Sjfv/* MAC Specific Control Register (Page 2, Register 21) */ 71169240Sjfv/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ 72228386Sjfv#define GG82563_MSCR_TX_CLK_MASK 0x0007 73228386Sjfv#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 74228386Sjfv#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 75228386Sjfv#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 76169240Sjfv 77228386Sjfv#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ 78169240Sjfv 79256200Sjfv/* DSP Distance Register (Page 5, Register 26) 80173788Sjfv * 0 = <50M 81173788Sjfv * 1 = 50-80M 82173788Sjfv * 2 = 80-100M 83173788Sjfv * 3 = 110-140M 84173788Sjfv * 4 = >140M 85173788Sjfv */ 86228386Sjfv#define GG82563_DSPD_CABLE_LENGTH 0x0007 87169240Sjfv 88169240Sjfv/* Kumeran Mode Control Register (Page 193, Register 16) */ 89228386Sjfv#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 90169240Sjfv 91169589Sjfv/* Max number of times Kumeran read/write should be validated */ 92228386Sjfv#define GG82563_MAX_KMRN_RETRY 0x5 93169589Sjfv 94169240Sjfv/* Power Management Control Register (Page 193, Register 20) */ 95228386Sjfv/* 1=Enable SERDES Electrical Idle */ 96228386Sjfv#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 97169240Sjfv 98169240Sjfv/* In-Band Control Register (Page 194, Register 18) */ 99228386Sjfv#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ 100169240Sjfv 101169240Sjfv#endif 102