1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2011 Advanced Micro Devices, Inc. 3254885Sdumbbell * 4254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 5254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 6254885Sdumbbell * to deal in the Software without restriction, including without limitation 7254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 9254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 10254885Sdumbbell * 11254885Sdumbbell * The above copyright notice and this permission notice shall be included in 12254885Sdumbbell * all copies or substantial portions of the Software. 13254885Sdumbbell * 14254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 21254885Sdumbbell * 22254885Sdumbbell * Authors: Alex Deucher 23254885Sdumbbell */ 24254885Sdumbbell#ifndef SI_H 25254885Sdumbbell#define SI_H 26254885Sdumbbell 27254885Sdumbbell#include <sys/cdefs.h> 28254885Sdumbbell__FBSDID("$FreeBSD$"); 29254885Sdumbbell 30254885Sdumbbell#define TAHITI_RB_BITMAP_WIDTH_PER_SH 2 31254885Sdumbbell 32254885Sdumbbell#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 33254885Sdumbbell#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 34254885Sdumbbell 35254885Sdumbbell#define CG_MULT_THERMAL_STATUS 0x714 36254885Sdumbbell#define ASIC_MAX_TEMP(x) ((x) << 0) 37254885Sdumbbell#define ASIC_MAX_TEMP_MASK 0x000001ff 38254885Sdumbbell#define ASIC_MAX_TEMP_SHIFT 0 39254885Sdumbbell#define CTF_TEMP(x) ((x) << 9) 40254885Sdumbbell#define CTF_TEMP_MASK 0x0003fe00 41254885Sdumbbell#define CTF_TEMP_SHIFT 9 42254885Sdumbbell 43254885Sdumbbell#define SI_MAX_SH_GPRS 256 44254885Sdumbbell#define SI_MAX_TEMP_GPRS 16 45254885Sdumbbell#define SI_MAX_SH_THREADS 256 46254885Sdumbbell#define SI_MAX_SH_STACK_ENTRIES 4096 47254885Sdumbbell#define SI_MAX_FRC_EOV_CNT 16384 48254885Sdumbbell#define SI_MAX_BACKENDS 8 49254885Sdumbbell#define SI_MAX_BACKENDS_MASK 0xFF 50254885Sdumbbell#define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 51254885Sdumbbell#define SI_MAX_SIMDS 12 52254885Sdumbbell#define SI_MAX_SIMDS_MASK 0x0FFF 53254885Sdumbbell#define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 54254885Sdumbbell#define SI_MAX_PIPES 8 55254885Sdumbbell#define SI_MAX_PIPES_MASK 0xFF 56254885Sdumbbell#define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 57254885Sdumbbell#define SI_MAX_LDS_NUM 0xFFFF 58254885Sdumbbell#define SI_MAX_TCC 16 59254885Sdumbbell#define SI_MAX_TCC_MASK 0xFFFF 60254885Sdumbbell 61254885Sdumbbell#define VGA_HDP_CONTROL 0x328 62254885Sdumbbell#define VGA_MEMORY_DISABLE (1 << 4) 63254885Sdumbbell 64254885Sdumbbell#define DMIF_ADDR_CONFIG 0xBD4 65254885Sdumbbell 66254885Sdumbbell#define SRBM_STATUS 0xE50 67254885Sdumbbell 68254885Sdumbbell#define SRBM_SOFT_RESET 0x0E60 69254885Sdumbbell#define SOFT_RESET_BIF (1 << 1) 70254885Sdumbbell#define SOFT_RESET_DC (1 << 5) 71254885Sdumbbell#define SOFT_RESET_DMA1 (1 << 6) 72254885Sdumbbell#define SOFT_RESET_GRBM (1 << 8) 73254885Sdumbbell#define SOFT_RESET_HDP (1 << 9) 74254885Sdumbbell#define SOFT_RESET_IH (1 << 10) 75254885Sdumbbell#define SOFT_RESET_MC (1 << 11) 76254885Sdumbbell#define SOFT_RESET_ROM (1 << 14) 77254885Sdumbbell#define SOFT_RESET_SEM (1 << 15) 78254885Sdumbbell#define SOFT_RESET_VMC (1 << 17) 79254885Sdumbbell#define SOFT_RESET_DMA (1 << 20) 80254885Sdumbbell#define SOFT_RESET_TST (1 << 21) 81254885Sdumbbell#define SOFT_RESET_REGBB (1 << 22) 82254885Sdumbbell#define SOFT_RESET_ORB (1 << 23) 83254885Sdumbbell 84254885Sdumbbell#define CC_SYS_RB_BACKEND_DISABLE 0xe80 85254885Sdumbbell#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 86254885Sdumbbell 87254885Sdumbbell#define VM_L2_CNTL 0x1400 88254885Sdumbbell#define ENABLE_L2_CACHE (1 << 0) 89254885Sdumbbell#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 90254885Sdumbbell#define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 91254885Sdumbbell#define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 92254885Sdumbbell#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 93254885Sdumbbell#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 94254885Sdumbbell#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 95254885Sdumbbell#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 96254885Sdumbbell#define VM_L2_CNTL2 0x1404 97254885Sdumbbell#define INVALIDATE_ALL_L1_TLBS (1 << 0) 98254885Sdumbbell#define INVALIDATE_L2_CACHE (1 << 1) 99254885Sdumbbell#define INVALIDATE_CACHE_MODE(x) ((x) << 26) 100254885Sdumbbell#define INVALIDATE_PTE_AND_PDE_CACHES 0 101254885Sdumbbell#define INVALIDATE_ONLY_PTE_CACHES 1 102254885Sdumbbell#define INVALIDATE_ONLY_PDE_CACHES 2 103254885Sdumbbell#define VM_L2_CNTL3 0x1408 104254885Sdumbbell#define BANK_SELECT(x) ((x) << 0) 105254885Sdumbbell#define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 106254885Sdumbbell#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 107254885Sdumbbell#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 108254885Sdumbbell#define VM_L2_STATUS 0x140C 109254885Sdumbbell#define L2_BUSY (1 << 0) 110254885Sdumbbell#define VM_CONTEXT0_CNTL 0x1410 111254885Sdumbbell#define ENABLE_CONTEXT (1 << 0) 112254885Sdumbbell#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 113254885Sdumbbell#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 114254885Sdumbbell#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 115254885Sdumbbell#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 116254885Sdumbbell#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 117254885Sdumbbell#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 118254885Sdumbbell#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 119254885Sdumbbell#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 120254885Sdumbbell#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 121254885Sdumbbell#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 122254885Sdumbbell#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 123254885Sdumbbell#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 124254885Sdumbbell#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 125254885Sdumbbell#define VM_CONTEXT1_CNTL 0x1414 126254885Sdumbbell#define VM_CONTEXT0_CNTL2 0x1430 127254885Sdumbbell#define VM_CONTEXT1_CNTL2 0x1434 128254885Sdumbbell#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 129254885Sdumbbell#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 130254885Sdumbbell#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 131254885Sdumbbell#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 132254885Sdumbbell#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 133254885Sdumbbell#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 134254885Sdumbbell#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 135254885Sdumbbell#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 136254885Sdumbbell 137254885Sdumbbell#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 138254885Sdumbbell#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 139254885Sdumbbell 140254885Sdumbbell#define VM_INVALIDATE_REQUEST 0x1478 141254885Sdumbbell#define VM_INVALIDATE_RESPONSE 0x147c 142254885Sdumbbell 143254885Sdumbbell#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 144254885Sdumbbell#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 145254885Sdumbbell 146254885Sdumbbell#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 147254885Sdumbbell#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 148254885Sdumbbell#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 149254885Sdumbbell#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 150254885Sdumbbell#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 151254885Sdumbbell#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 152254885Sdumbbell#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 153254885Sdumbbell#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 154254885Sdumbbell#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 155254885Sdumbbell#define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 156254885Sdumbbell 157254885Sdumbbell#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 158254885Sdumbbell#define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 159254885Sdumbbell 160254885Sdumbbell#define MC_SHARED_CHMAP 0x2004 161254885Sdumbbell#define NOOFCHAN_SHIFT 12 162254885Sdumbbell#define NOOFCHAN_MASK 0x0000f000 163254885Sdumbbell#define MC_SHARED_CHREMAP 0x2008 164254885Sdumbbell 165254885Sdumbbell#define MC_VM_FB_LOCATION 0x2024 166254885Sdumbbell#define MC_VM_AGP_TOP 0x2028 167254885Sdumbbell#define MC_VM_AGP_BOT 0x202C 168254885Sdumbbell#define MC_VM_AGP_BASE 0x2030 169254885Sdumbbell#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 170254885Sdumbbell#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 171254885Sdumbbell#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 172254885Sdumbbell 173254885Sdumbbell#define MC_VM_MX_L1_TLB_CNTL 0x2064 174254885Sdumbbell#define ENABLE_L1_TLB (1 << 0) 175254885Sdumbbell#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 176254885Sdumbbell#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 177254885Sdumbbell#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 178254885Sdumbbell#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 179254885Sdumbbell#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 180254885Sdumbbell#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 181254885Sdumbbell#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 182254885Sdumbbell 183254885Sdumbbell#define MC_SHARED_BLACKOUT_CNTL 0x20ac 184254885Sdumbbell 185254885Sdumbbell#define MC_ARB_RAMCFG 0x2760 186254885Sdumbbell#define NOOFBANK_SHIFT 0 187254885Sdumbbell#define NOOFBANK_MASK 0x00000003 188254885Sdumbbell#define NOOFRANK_SHIFT 2 189254885Sdumbbell#define NOOFRANK_MASK 0x00000004 190254885Sdumbbell#define NOOFROWS_SHIFT 3 191254885Sdumbbell#define NOOFROWS_MASK 0x00000038 192254885Sdumbbell#define NOOFCOLS_SHIFT 6 193254885Sdumbbell#define NOOFCOLS_MASK 0x000000C0 194254885Sdumbbell#define CHANSIZE_SHIFT 8 195254885Sdumbbell#define CHANSIZE_MASK 0x00000100 196254885Sdumbbell#define CHANSIZE_OVERRIDE (1 << 11) 197254885Sdumbbell#define NOOFGROUPS_SHIFT 12 198254885Sdumbbell#define NOOFGROUPS_MASK 0x00001000 199254885Sdumbbell 200254885Sdumbbell#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 201254885Sdumbbell#define TRAIN_DONE_D0 (1 << 30) 202254885Sdumbbell#define TRAIN_DONE_D1 (1 << 31) 203254885Sdumbbell 204254885Sdumbbell#define MC_SEQ_SUP_CNTL 0x28c8 205254885Sdumbbell#define RUN_MASK (1 << 0) 206254885Sdumbbell#define MC_SEQ_SUP_PGM 0x28cc 207254885Sdumbbell 208254885Sdumbbell#define MC_IO_PAD_CNTL_D0 0x29d0 209254885Sdumbbell#define MEM_FALL_OUT_CMD (1 << 8) 210254885Sdumbbell 211254885Sdumbbell#define MC_SEQ_IO_DEBUG_INDEX 0x2a44 212254885Sdumbbell#define MC_SEQ_IO_DEBUG_DATA 0x2a48 213254885Sdumbbell 214254885Sdumbbell#define HDP_HOST_PATH_CNTL 0x2C00 215254885Sdumbbell#define HDP_NONSURFACE_BASE 0x2C04 216254885Sdumbbell#define HDP_NONSURFACE_INFO 0x2C08 217254885Sdumbbell#define HDP_NONSURFACE_SIZE 0x2C0C 218254885Sdumbbell 219254885Sdumbbell#define HDP_ADDR_CONFIG 0x2F48 220254885Sdumbbell#define HDP_MISC_CNTL 0x2F4C 221254885Sdumbbell#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 222254885Sdumbbell 223254885Sdumbbell#define IH_RB_CNTL 0x3e00 224254885Sdumbbell# define IH_RB_ENABLE (1 << 0) 225254885Sdumbbell# define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 226254885Sdumbbell# define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 227254885Sdumbbell# define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 228254885Sdumbbell# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 229254885Sdumbbell# define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 230254885Sdumbbell# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 231254885Sdumbbell#define IH_RB_BASE 0x3e04 232254885Sdumbbell#define IH_RB_RPTR 0x3e08 233254885Sdumbbell#define IH_RB_WPTR 0x3e0c 234254885Sdumbbell# define RB_OVERFLOW (1 << 0) 235254885Sdumbbell# define WPTR_OFFSET_MASK 0x3fffc 236254885Sdumbbell#define IH_RB_WPTR_ADDR_HI 0x3e10 237254885Sdumbbell#define IH_RB_WPTR_ADDR_LO 0x3e14 238254885Sdumbbell#define IH_CNTL 0x3e18 239254885Sdumbbell# define ENABLE_INTR (1 << 0) 240254885Sdumbbell# define IH_MC_SWAP(x) ((x) << 1) 241254885Sdumbbell# define IH_MC_SWAP_NONE 0 242254885Sdumbbell# define IH_MC_SWAP_16BIT 1 243254885Sdumbbell# define IH_MC_SWAP_32BIT 2 244254885Sdumbbell# define IH_MC_SWAP_64BIT 3 245254885Sdumbbell# define RPTR_REARM (1 << 4) 246254885Sdumbbell# define MC_WRREQ_CREDIT(x) ((x) << 15) 247254885Sdumbbell# define MC_WR_CLEAN_CNT(x) ((x) << 20) 248254885Sdumbbell# define MC_VMID(x) ((x) << 25) 249254885Sdumbbell 250254885Sdumbbell#define CONFIG_MEMSIZE 0x5428 251254885Sdumbbell 252254885Sdumbbell#define INTERRUPT_CNTL 0x5468 253254885Sdumbbell# define IH_DUMMY_RD_OVERRIDE (1 << 0) 254254885Sdumbbell# define IH_DUMMY_RD_EN (1 << 1) 255254885Sdumbbell# define IH_REQ_NONSNOOP_EN (1 << 3) 256254885Sdumbbell# define GEN_IH_INT_EN (1 << 8) 257254885Sdumbbell#define INTERRUPT_CNTL2 0x546c 258254885Sdumbbell 259254885Sdumbbell#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 260254885Sdumbbell 261254885Sdumbbell#define BIF_FB_EN 0x5490 262254885Sdumbbell#define FB_READ_EN (1 << 0) 263254885Sdumbbell#define FB_WRITE_EN (1 << 1) 264254885Sdumbbell 265254885Sdumbbell#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 266254885Sdumbbell 267254885Sdumbbell#define DC_LB_MEMORY_SPLIT 0x6b0c 268254885Sdumbbell#define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 269254885Sdumbbell 270254885Sdumbbell#define PRIORITY_A_CNT 0x6b18 271254885Sdumbbell#define PRIORITY_MARK_MASK 0x7fff 272254885Sdumbbell#define PRIORITY_OFF (1 << 16) 273254885Sdumbbell#define PRIORITY_ALWAYS_ON (1 << 20) 274254885Sdumbbell#define PRIORITY_B_CNT 0x6b1c 275254885Sdumbbell 276254885Sdumbbell#define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 277254885Sdumbbell# define LATENCY_WATERMARK_MASK(x) ((x) << 16) 278254885Sdumbbell#define DPG_PIPE_LATENCY_CONTROL 0x6ccc 279254885Sdumbbell# define LATENCY_LOW_WATERMARK(x) ((x) << 0) 280254885Sdumbbell# define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 281254885Sdumbbell 282254885Sdumbbell/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 283254885Sdumbbell#define VLINE_STATUS 0x6bb8 284254885Sdumbbell# define VLINE_OCCURRED (1 << 0) 285254885Sdumbbell# define VLINE_ACK (1 << 4) 286254885Sdumbbell# define VLINE_STAT (1 << 12) 287254885Sdumbbell# define VLINE_INTERRUPT (1 << 16) 288254885Sdumbbell# define VLINE_INTERRUPT_TYPE (1 << 17) 289254885Sdumbbell/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 290254885Sdumbbell#define VBLANK_STATUS 0x6bbc 291254885Sdumbbell# define VBLANK_OCCURRED (1 << 0) 292254885Sdumbbell# define VBLANK_ACK (1 << 4) 293254885Sdumbbell# define VBLANK_STAT (1 << 12) 294254885Sdumbbell# define VBLANK_INTERRUPT (1 << 16) 295254885Sdumbbell# define VBLANK_INTERRUPT_TYPE (1 << 17) 296254885Sdumbbell 297254885Sdumbbell/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 298254885Sdumbbell#define INT_MASK 0x6b40 299254885Sdumbbell# define VBLANK_INT_MASK (1 << 0) 300254885Sdumbbell# define VLINE_INT_MASK (1 << 4) 301254885Sdumbbell 302254885Sdumbbell#define DISP_INTERRUPT_STATUS 0x60f4 303254885Sdumbbell# define LB_D1_VLINE_INTERRUPT (1 << 2) 304254885Sdumbbell# define LB_D1_VBLANK_INTERRUPT (1 << 3) 305254885Sdumbbell# define DC_HPD1_INTERRUPT (1 << 17) 306254885Sdumbbell# define DC_HPD1_RX_INTERRUPT (1 << 18) 307254885Sdumbbell# define DACA_AUTODETECT_INTERRUPT (1 << 22) 308254885Sdumbbell# define DACB_AUTODETECT_INTERRUPT (1 << 23) 309254885Sdumbbell# define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 310254885Sdumbbell# define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 311254885Sdumbbell#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 312254885Sdumbbell# define LB_D2_VLINE_INTERRUPT (1 << 2) 313254885Sdumbbell# define LB_D2_VBLANK_INTERRUPT (1 << 3) 314254885Sdumbbell# define DC_HPD2_INTERRUPT (1 << 17) 315254885Sdumbbell# define DC_HPD2_RX_INTERRUPT (1 << 18) 316254885Sdumbbell# define DISP_TIMER_INTERRUPT (1 << 24) 317254885Sdumbbell#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 318254885Sdumbbell# define LB_D3_VLINE_INTERRUPT (1 << 2) 319254885Sdumbbell# define LB_D3_VBLANK_INTERRUPT (1 << 3) 320254885Sdumbbell# define DC_HPD3_INTERRUPT (1 << 17) 321254885Sdumbbell# define DC_HPD3_RX_INTERRUPT (1 << 18) 322254885Sdumbbell#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 323254885Sdumbbell# define LB_D4_VLINE_INTERRUPT (1 << 2) 324254885Sdumbbell# define LB_D4_VBLANK_INTERRUPT (1 << 3) 325254885Sdumbbell# define DC_HPD4_INTERRUPT (1 << 17) 326254885Sdumbbell# define DC_HPD4_RX_INTERRUPT (1 << 18) 327254885Sdumbbell#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 328254885Sdumbbell# define LB_D5_VLINE_INTERRUPT (1 << 2) 329254885Sdumbbell# define LB_D5_VBLANK_INTERRUPT (1 << 3) 330254885Sdumbbell# define DC_HPD5_INTERRUPT (1 << 17) 331254885Sdumbbell# define DC_HPD5_RX_INTERRUPT (1 << 18) 332254885Sdumbbell#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 333254885Sdumbbell# define LB_D6_VLINE_INTERRUPT (1 << 2) 334254885Sdumbbell# define LB_D6_VBLANK_INTERRUPT (1 << 3) 335254885Sdumbbell# define DC_HPD6_INTERRUPT (1 << 17) 336254885Sdumbbell# define DC_HPD6_RX_INTERRUPT (1 << 18) 337254885Sdumbbell 338254885Sdumbbell/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 339254885Sdumbbell#define GRPH_INT_STATUS 0x6858 340254885Sdumbbell# define GRPH_PFLIP_INT_OCCURRED (1 << 0) 341254885Sdumbbell# define GRPH_PFLIP_INT_CLEAR (1 << 8) 342254885Sdumbbell/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 343254885Sdumbbell#define GRPH_INT_CONTROL 0x685c 344254885Sdumbbell# define GRPH_PFLIP_INT_MASK (1 << 0) 345254885Sdumbbell# define GRPH_PFLIP_INT_TYPE (1 << 8) 346254885Sdumbbell 347254885Sdumbbell#define DACA_AUTODETECT_INT_CONTROL 0x66c8 348254885Sdumbbell 349254885Sdumbbell#define DC_HPD1_INT_STATUS 0x601c 350254885Sdumbbell#define DC_HPD2_INT_STATUS 0x6028 351254885Sdumbbell#define DC_HPD3_INT_STATUS 0x6034 352254885Sdumbbell#define DC_HPD4_INT_STATUS 0x6040 353254885Sdumbbell#define DC_HPD5_INT_STATUS 0x604c 354254885Sdumbbell#define DC_HPD6_INT_STATUS 0x6058 355254885Sdumbbell# define DC_HPDx_INT_STATUS (1 << 0) 356254885Sdumbbell# define DC_HPDx_SENSE (1 << 1) 357254885Sdumbbell# define DC_HPDx_RX_INT_STATUS (1 << 8) 358254885Sdumbbell 359254885Sdumbbell#define DC_HPD1_INT_CONTROL 0x6020 360254885Sdumbbell#define DC_HPD2_INT_CONTROL 0x602c 361254885Sdumbbell#define DC_HPD3_INT_CONTROL 0x6038 362254885Sdumbbell#define DC_HPD4_INT_CONTROL 0x6044 363254885Sdumbbell#define DC_HPD5_INT_CONTROL 0x6050 364254885Sdumbbell#define DC_HPD6_INT_CONTROL 0x605c 365254885Sdumbbell# define DC_HPDx_INT_ACK (1 << 0) 366254885Sdumbbell# define DC_HPDx_INT_POLARITY (1 << 8) 367254885Sdumbbell# define DC_HPDx_INT_EN (1 << 16) 368254885Sdumbbell# define DC_HPDx_RX_INT_ACK (1 << 20) 369254885Sdumbbell# define DC_HPDx_RX_INT_EN (1 << 24) 370254885Sdumbbell 371254885Sdumbbell#define DC_HPD1_CONTROL 0x6024 372254885Sdumbbell#define DC_HPD2_CONTROL 0x6030 373254885Sdumbbell#define DC_HPD3_CONTROL 0x603c 374254885Sdumbbell#define DC_HPD4_CONTROL 0x6048 375254885Sdumbbell#define DC_HPD5_CONTROL 0x6054 376254885Sdumbbell#define DC_HPD6_CONTROL 0x6060 377254885Sdumbbell# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 378254885Sdumbbell# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 379254885Sdumbbell# define DC_HPDx_EN (1 << 28) 380254885Sdumbbell 381254885Sdumbbell/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 382254885Sdumbbell#define CRTC_STATUS_FRAME_COUNT 0x6e98 383254885Sdumbbell 384254885Sdumbbell#define GRBM_CNTL 0x8000 385254885Sdumbbell#define GRBM_READ_TIMEOUT(x) ((x) << 0) 386254885Sdumbbell 387254885Sdumbbell#define GRBM_STATUS2 0x8008 388254885Sdumbbell#define RLC_RQ_PENDING (1 << 0) 389254885Sdumbbell#define RLC_BUSY (1 << 8) 390254885Sdumbbell#define TC_BUSY (1 << 9) 391254885Sdumbbell 392254885Sdumbbell#define GRBM_STATUS 0x8010 393254885Sdumbbell#define CMDFIFO_AVAIL_MASK 0x0000000F 394254885Sdumbbell#define RING2_RQ_PENDING (1 << 4) 395254885Sdumbbell#define SRBM_RQ_PENDING (1 << 5) 396254885Sdumbbell#define RING1_RQ_PENDING (1 << 6) 397254885Sdumbbell#define CF_RQ_PENDING (1 << 7) 398254885Sdumbbell#define PF_RQ_PENDING (1 << 8) 399254885Sdumbbell#define GDS_DMA_RQ_PENDING (1 << 9) 400254885Sdumbbell#define GRBM_EE_BUSY (1 << 10) 401254885Sdumbbell#define DB_CLEAN (1 << 12) 402254885Sdumbbell#define CB_CLEAN (1 << 13) 403254885Sdumbbell#define TA_BUSY (1 << 14) 404254885Sdumbbell#define GDS_BUSY (1 << 15) 405254885Sdumbbell#define VGT_BUSY (1 << 17) 406254885Sdumbbell#define IA_BUSY_NO_DMA (1 << 18) 407254885Sdumbbell#define IA_BUSY (1 << 19) 408254885Sdumbbell#define SX_BUSY (1 << 20) 409254885Sdumbbell#define SPI_BUSY (1 << 22) 410254885Sdumbbell#define BCI_BUSY (1 << 23) 411254885Sdumbbell#define SC_BUSY (1 << 24) 412254885Sdumbbell#define PA_BUSY (1 << 25) 413254885Sdumbbell#define DB_BUSY (1 << 26) 414254885Sdumbbell#define CP_COHERENCY_BUSY (1 << 28) 415254885Sdumbbell#define CP_BUSY (1 << 29) 416254885Sdumbbell#define CB_BUSY (1 << 30) 417254885Sdumbbell#define GUI_ACTIVE (1 << 31) 418254885Sdumbbell#define GRBM_STATUS_SE0 0x8014 419254885Sdumbbell#define GRBM_STATUS_SE1 0x8018 420254885Sdumbbell#define SE_DB_CLEAN (1 << 1) 421254885Sdumbbell#define SE_CB_CLEAN (1 << 2) 422254885Sdumbbell#define SE_BCI_BUSY (1 << 22) 423254885Sdumbbell#define SE_VGT_BUSY (1 << 23) 424254885Sdumbbell#define SE_PA_BUSY (1 << 24) 425254885Sdumbbell#define SE_TA_BUSY (1 << 25) 426254885Sdumbbell#define SE_SX_BUSY (1 << 26) 427254885Sdumbbell#define SE_SPI_BUSY (1 << 27) 428254885Sdumbbell#define SE_SC_BUSY (1 << 29) 429254885Sdumbbell#define SE_DB_BUSY (1 << 30) 430254885Sdumbbell#define SE_CB_BUSY (1 << 31) 431254885Sdumbbell 432254885Sdumbbell#define GRBM_SOFT_RESET 0x8020 433254885Sdumbbell#define SOFT_RESET_CP (1 << 0) 434254885Sdumbbell#define SOFT_RESET_CB (1 << 1) 435254885Sdumbbell#define SOFT_RESET_RLC (1 << 2) 436254885Sdumbbell#define SOFT_RESET_DB (1 << 3) 437254885Sdumbbell#define SOFT_RESET_GDS (1 << 4) 438254885Sdumbbell#define SOFT_RESET_PA (1 << 5) 439254885Sdumbbell#define SOFT_RESET_SC (1 << 6) 440254885Sdumbbell#define SOFT_RESET_BCI (1 << 7) 441254885Sdumbbell#define SOFT_RESET_SPI (1 << 8) 442254885Sdumbbell#define SOFT_RESET_SX (1 << 10) 443254885Sdumbbell#define SOFT_RESET_TC (1 << 11) 444254885Sdumbbell#define SOFT_RESET_TA (1 << 12) 445254885Sdumbbell#define SOFT_RESET_VGT (1 << 14) 446254885Sdumbbell#define SOFT_RESET_IA (1 << 15) 447254885Sdumbbell 448254885Sdumbbell#define GRBM_GFX_INDEX 0x802C 449254885Sdumbbell#define INSTANCE_INDEX(x) ((x) << 0) 450254885Sdumbbell#define SH_INDEX(x) ((x) << 8) 451254885Sdumbbell#define SE_INDEX(x) ((x) << 16) 452254885Sdumbbell#define SH_BROADCAST_WRITES (1 << 29) 453254885Sdumbbell#define INSTANCE_BROADCAST_WRITES (1 << 30) 454254885Sdumbbell#define SE_BROADCAST_WRITES (1 << 31) 455254885Sdumbbell 456254885Sdumbbell#define GRBM_INT_CNTL 0x8060 457254885Sdumbbell# define RDERR_INT_ENABLE (1 << 0) 458254885Sdumbbell# define GUI_IDLE_INT_ENABLE (1 << 19) 459254885Sdumbbell 460254885Sdumbbell#define CP_STRMOUT_CNTL 0x84FC 461254885Sdumbbell#define SCRATCH_REG0 0x8500 462254885Sdumbbell#define SCRATCH_REG1 0x8504 463254885Sdumbbell#define SCRATCH_REG2 0x8508 464254885Sdumbbell#define SCRATCH_REG3 0x850C 465254885Sdumbbell#define SCRATCH_REG4 0x8510 466254885Sdumbbell#define SCRATCH_REG5 0x8514 467254885Sdumbbell#define SCRATCH_REG6 0x8518 468254885Sdumbbell#define SCRATCH_REG7 0x851C 469254885Sdumbbell 470254885Sdumbbell#define SCRATCH_UMSK 0x8540 471254885Sdumbbell#define SCRATCH_ADDR 0x8544 472254885Sdumbbell 473254885Sdumbbell#define CP_SEM_WAIT_TIMER 0x85BC 474254885Sdumbbell 475254885Sdumbbell#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 476254885Sdumbbell 477254885Sdumbbell#define CP_ME_CNTL 0x86D8 478254885Sdumbbell#define CP_CE_HALT (1 << 24) 479254885Sdumbbell#define CP_PFP_HALT (1 << 26) 480254885Sdumbbell#define CP_ME_HALT (1 << 28) 481254885Sdumbbell 482254885Sdumbbell#define CP_COHER_CNTL2 0x85E8 483254885Sdumbbell 484254885Sdumbbell#define CP_RB2_RPTR 0x86f8 485254885Sdumbbell#define CP_RB1_RPTR 0x86fc 486254885Sdumbbell#define CP_RB0_RPTR 0x8700 487254885Sdumbbell#define CP_RB_WPTR_DELAY 0x8704 488254885Sdumbbell 489254885Sdumbbell#define CP_QUEUE_THRESHOLDS 0x8760 490254885Sdumbbell#define ROQ_IB1_START(x) ((x) << 0) 491254885Sdumbbell#define ROQ_IB2_START(x) ((x) << 8) 492254885Sdumbbell#define CP_MEQ_THRESHOLDS 0x8764 493254885Sdumbbell#define MEQ1_START(x) ((x) << 0) 494254885Sdumbbell#define MEQ2_START(x) ((x) << 8) 495254885Sdumbbell 496254885Sdumbbell#define CP_PERFMON_CNTL 0x87FC 497254885Sdumbbell 498254885Sdumbbell#define VGT_VTX_VECT_EJECT_REG 0x88B0 499254885Sdumbbell 500254885Sdumbbell#define VGT_CACHE_INVALIDATION 0x88C4 501254885Sdumbbell#define CACHE_INVALIDATION(x) ((x) << 0) 502254885Sdumbbell#define VC_ONLY 0 503254885Sdumbbell#define TC_ONLY 1 504254885Sdumbbell#define VC_AND_TC 2 505254885Sdumbbell#define AUTO_INVLD_EN(x) ((x) << 6) 506254885Sdumbbell#define NO_AUTO 0 507254885Sdumbbell#define ES_AUTO 1 508254885Sdumbbell#define GS_AUTO 2 509254885Sdumbbell#define ES_AND_GS_AUTO 3 510254885Sdumbbell#define VGT_ESGS_RING_SIZE 0x88C8 511254885Sdumbbell#define VGT_GSVS_RING_SIZE 0x88CC 512254885Sdumbbell 513254885Sdumbbell#define VGT_GS_VERTEX_REUSE 0x88D4 514254885Sdumbbell 515254885Sdumbbell#define VGT_PRIMITIVE_TYPE 0x8958 516254885Sdumbbell#define VGT_INDEX_TYPE 0x895C 517254885Sdumbbell 518254885Sdumbbell#define VGT_NUM_INDICES 0x8970 519254885Sdumbbell#define VGT_NUM_INSTANCES 0x8974 520254885Sdumbbell 521254885Sdumbbell#define VGT_TF_RING_SIZE 0x8988 522254885Sdumbbell 523254885Sdumbbell#define VGT_HS_OFFCHIP_PARAM 0x89B0 524254885Sdumbbell 525254885Sdumbbell#define VGT_TF_MEMORY_BASE 0x89B8 526254885Sdumbbell 527254885Sdumbbell#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 528254885Sdumbbell#define INACTIVE_CUS_MASK 0xFFFF0000 529254885Sdumbbell#define INACTIVE_CUS_SHIFT 16 530254885Sdumbbell#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 531254885Sdumbbell 532254885Sdumbbell#define PA_CL_ENHANCE 0x8A14 533254885Sdumbbell#define CLIP_VTX_REORDER_ENA (1 << 0) 534254885Sdumbbell#define NUM_CLIP_SEQ(x) ((x) << 1) 535254885Sdumbbell 536254885Sdumbbell#define PA_SU_LINE_STIPPLE_VALUE 0x8A60 537254885Sdumbbell 538254885Sdumbbell#define PA_SC_LINE_STIPPLE_STATE 0x8B10 539254885Sdumbbell 540254885Sdumbbell#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 541254885Sdumbbell#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 542254885Sdumbbell#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 543254885Sdumbbell 544254885Sdumbbell#define PA_SC_FIFO_SIZE 0x8BCC 545254885Sdumbbell#define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 546254885Sdumbbell#define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 547254885Sdumbbell#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 548254885Sdumbbell#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 549254885Sdumbbell 550254885Sdumbbell#define PA_SC_ENHANCE 0x8BF0 551254885Sdumbbell 552254885Sdumbbell#define SQ_CONFIG 0x8C00 553254885Sdumbbell 554254885Sdumbbell#define SQC_CACHES 0x8C08 555254885Sdumbbell 556254885Sdumbbell#define SX_DEBUG_1 0x9060 557254885Sdumbbell 558254885Sdumbbell#define SPI_STATIC_THREAD_MGMT_1 0x90E0 559254885Sdumbbell#define SPI_STATIC_THREAD_MGMT_2 0x90E4 560254885Sdumbbell#define SPI_STATIC_THREAD_MGMT_3 0x90E8 561254885Sdumbbell#define SPI_PS_MAX_WAVE_ID 0x90EC 562254885Sdumbbell 563254885Sdumbbell#define SPI_CONFIG_CNTL 0x9100 564254885Sdumbbell 565254885Sdumbbell#define SPI_CONFIG_CNTL_1 0x913C 566254885Sdumbbell#define VTX_DONE_DELAY(x) ((x) << 0) 567254885Sdumbbell#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 568254885Sdumbbell 569254885Sdumbbell#define CGTS_TCC_DISABLE 0x9148 570254885Sdumbbell#define CGTS_USER_TCC_DISABLE 0x914C 571254885Sdumbbell#define TCC_DISABLE_MASK 0xFFFF0000 572254885Sdumbbell#define TCC_DISABLE_SHIFT 16 573254885Sdumbbell 574254885Sdumbbell#define TA_CNTL_AUX 0x9508 575254885Sdumbbell 576254885Sdumbbell#define CC_RB_BACKEND_DISABLE 0x98F4 577254885Sdumbbell#define BACKEND_DISABLE(x) ((x) << 16) 578254885Sdumbbell#define GB_ADDR_CONFIG 0x98F8 579254885Sdumbbell#define NUM_PIPES(x) ((x) << 0) 580254885Sdumbbell#define NUM_PIPES_MASK 0x00000007 581254885Sdumbbell#define NUM_PIPES_SHIFT 0 582254885Sdumbbell#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 583254885Sdumbbell#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 584254885Sdumbbell#define PIPE_INTERLEAVE_SIZE_SHIFT 4 585254885Sdumbbell#define NUM_SHADER_ENGINES(x) ((x) << 12) 586254885Sdumbbell#define NUM_SHADER_ENGINES_MASK 0x00003000 587254885Sdumbbell#define NUM_SHADER_ENGINES_SHIFT 12 588254885Sdumbbell#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 589254885Sdumbbell#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 590254885Sdumbbell#define SHADER_ENGINE_TILE_SIZE_SHIFT 16 591254885Sdumbbell#define NUM_GPUS(x) ((x) << 20) 592254885Sdumbbell#define NUM_GPUS_MASK 0x00700000 593254885Sdumbbell#define NUM_GPUS_SHIFT 20 594254885Sdumbbell#define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 595254885Sdumbbell#define MULTI_GPU_TILE_SIZE_MASK 0x03000000 596254885Sdumbbell#define MULTI_GPU_TILE_SIZE_SHIFT 24 597254885Sdumbbell#define ROW_SIZE(x) ((x) << 28) 598254885Sdumbbell#define ROW_SIZE_MASK 0x30000000 599254885Sdumbbell#define ROW_SIZE_SHIFT 28 600254885Sdumbbell 601254885Sdumbbell#define GB_TILE_MODE0 0x9910 602254885Sdumbbell# define MICRO_TILE_MODE(x) ((x) << 0) 603254885Sdumbbell# define ADDR_SURF_DISPLAY_MICRO_TILING 0 604254885Sdumbbell# define ADDR_SURF_THIN_MICRO_TILING 1 605254885Sdumbbell# define ADDR_SURF_DEPTH_MICRO_TILING 2 606254885Sdumbbell# define ARRAY_MODE(x) ((x) << 2) 607254885Sdumbbell# define ARRAY_LINEAR_GENERAL 0 608254885Sdumbbell# define ARRAY_LINEAR_ALIGNED 1 609254885Sdumbbell# define ARRAY_1D_TILED_THIN1 2 610254885Sdumbbell# define ARRAY_2D_TILED_THIN1 4 611254885Sdumbbell# define PIPE_CONFIG(x) ((x) << 6) 612254885Sdumbbell# define ADDR_SURF_P2 0 613254885Sdumbbell# define ADDR_SURF_P4_8x16 4 614254885Sdumbbell# define ADDR_SURF_P4_16x16 5 615254885Sdumbbell# define ADDR_SURF_P4_16x32 6 616254885Sdumbbell# define ADDR_SURF_P4_32x32 7 617254885Sdumbbell# define ADDR_SURF_P8_16x16_8x16 8 618254885Sdumbbell# define ADDR_SURF_P8_16x32_8x16 9 619254885Sdumbbell# define ADDR_SURF_P8_32x32_8x16 10 620254885Sdumbbell# define ADDR_SURF_P8_16x32_16x16 11 621254885Sdumbbell# define ADDR_SURF_P8_32x32_16x16 12 622254885Sdumbbell# define ADDR_SURF_P8_32x32_16x32 13 623254885Sdumbbell# define ADDR_SURF_P8_32x64_32x32 14 624254885Sdumbbell# define TILE_SPLIT(x) ((x) << 11) 625254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_64B 0 626254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_128B 1 627254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_256B 2 628254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_512B 3 629254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_1KB 4 630254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_2KB 5 631254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_4KB 6 632254885Sdumbbell# define BANK_WIDTH(x) ((x) << 14) 633254885Sdumbbell# define ADDR_SURF_BANK_WIDTH_1 0 634254885Sdumbbell# define ADDR_SURF_BANK_WIDTH_2 1 635254885Sdumbbell# define ADDR_SURF_BANK_WIDTH_4 2 636254885Sdumbbell# define ADDR_SURF_BANK_WIDTH_8 3 637254885Sdumbbell# define BANK_HEIGHT(x) ((x) << 16) 638254885Sdumbbell# define ADDR_SURF_BANK_HEIGHT_1 0 639254885Sdumbbell# define ADDR_SURF_BANK_HEIGHT_2 1 640254885Sdumbbell# define ADDR_SURF_BANK_HEIGHT_4 2 641254885Sdumbbell# define ADDR_SURF_BANK_HEIGHT_8 3 642254885Sdumbbell# define MACRO_TILE_ASPECT(x) ((x) << 18) 643254885Sdumbbell# define ADDR_SURF_MACRO_ASPECT_1 0 644254885Sdumbbell# define ADDR_SURF_MACRO_ASPECT_2 1 645254885Sdumbbell# define ADDR_SURF_MACRO_ASPECT_4 2 646254885Sdumbbell# define ADDR_SURF_MACRO_ASPECT_8 3 647254885Sdumbbell# define NUM_BANKS(x) ((x) << 20) 648254885Sdumbbell# define ADDR_SURF_2_BANK 0 649254885Sdumbbell# define ADDR_SURF_4_BANK 1 650254885Sdumbbell# define ADDR_SURF_8_BANK 2 651254885Sdumbbell# define ADDR_SURF_16_BANK 3 652254885Sdumbbell 653254885Sdumbbell#define CB_PERFCOUNTER0_SELECT0 0x9a20 654254885Sdumbbell#define CB_PERFCOUNTER0_SELECT1 0x9a24 655254885Sdumbbell#define CB_PERFCOUNTER1_SELECT0 0x9a28 656254885Sdumbbell#define CB_PERFCOUNTER1_SELECT1 0x9a2c 657254885Sdumbbell#define CB_PERFCOUNTER2_SELECT0 0x9a30 658254885Sdumbbell#define CB_PERFCOUNTER2_SELECT1 0x9a34 659254885Sdumbbell#define CB_PERFCOUNTER3_SELECT0 0x9a38 660254885Sdumbbell#define CB_PERFCOUNTER3_SELECT1 0x9a3c 661254885Sdumbbell 662254885Sdumbbell#define GC_USER_RB_BACKEND_DISABLE 0x9B7C 663254885Sdumbbell#define BACKEND_DISABLE_MASK 0x00FF0000 664254885Sdumbbell#define BACKEND_DISABLE_SHIFT 16 665254885Sdumbbell 666254885Sdumbbell#define TCP_CHAN_STEER_LO 0xac0c 667254885Sdumbbell#define TCP_CHAN_STEER_HI 0xac10 668254885Sdumbbell 669254885Sdumbbell#define CP_RB0_BASE 0xC100 670254885Sdumbbell#define CP_RB0_CNTL 0xC104 671254885Sdumbbell#define RB_BUFSZ(x) ((x) << 0) 672254885Sdumbbell#define RB_BLKSZ(x) ((x) << 8) 673254885Sdumbbell#define BUF_SWAP_32BIT (2 << 16) 674254885Sdumbbell#define RB_NO_UPDATE (1 << 27) 675254885Sdumbbell#define RB_RPTR_WR_ENA (1 << 31) 676254885Sdumbbell 677254885Sdumbbell#define CP_RB0_RPTR_ADDR 0xC10C 678254885Sdumbbell#define CP_RB0_RPTR_ADDR_HI 0xC110 679254885Sdumbbell#define CP_RB0_WPTR 0xC114 680254885Sdumbbell 681254885Sdumbbell#define CP_PFP_UCODE_ADDR 0xC150 682254885Sdumbbell#define CP_PFP_UCODE_DATA 0xC154 683254885Sdumbbell#define CP_ME_RAM_RADDR 0xC158 684254885Sdumbbell#define CP_ME_RAM_WADDR 0xC15C 685254885Sdumbbell#define CP_ME_RAM_DATA 0xC160 686254885Sdumbbell 687254885Sdumbbell#define CP_CE_UCODE_ADDR 0xC168 688254885Sdumbbell#define CP_CE_UCODE_DATA 0xC16C 689254885Sdumbbell 690254885Sdumbbell#define CP_RB1_BASE 0xC180 691254885Sdumbbell#define CP_RB1_CNTL 0xC184 692254885Sdumbbell#define CP_RB1_RPTR_ADDR 0xC188 693254885Sdumbbell#define CP_RB1_RPTR_ADDR_HI 0xC18C 694254885Sdumbbell#define CP_RB1_WPTR 0xC190 695254885Sdumbbell#define CP_RB2_BASE 0xC194 696254885Sdumbbell#define CP_RB2_CNTL 0xC198 697254885Sdumbbell#define CP_RB2_RPTR_ADDR 0xC19C 698254885Sdumbbell#define CP_RB2_RPTR_ADDR_HI 0xC1A0 699254885Sdumbbell#define CP_RB2_WPTR 0xC1A4 700254885Sdumbbell#define CP_INT_CNTL_RING0 0xC1A8 701254885Sdumbbell#define CP_INT_CNTL_RING1 0xC1AC 702254885Sdumbbell#define CP_INT_CNTL_RING2 0xC1B0 703254885Sdumbbell# define CNTX_BUSY_INT_ENABLE (1 << 19) 704254885Sdumbbell# define CNTX_EMPTY_INT_ENABLE (1 << 20) 705254885Sdumbbell# define WAIT_MEM_SEM_INT_ENABLE (1 << 21) 706254885Sdumbbell# define TIME_STAMP_INT_ENABLE (1 << 26) 707254885Sdumbbell# define CP_RINGID2_INT_ENABLE (1 << 29) 708254885Sdumbbell# define CP_RINGID1_INT_ENABLE (1 << 30) 709254885Sdumbbell# define CP_RINGID0_INT_ENABLE (1 << 31) 710254885Sdumbbell#define CP_INT_STATUS_RING0 0xC1B4 711254885Sdumbbell#define CP_INT_STATUS_RING1 0xC1B8 712254885Sdumbbell#define CP_INT_STATUS_RING2 0xC1BC 713254885Sdumbbell# define WAIT_MEM_SEM_INT_STAT (1 << 21) 714254885Sdumbbell# define TIME_STAMP_INT_STAT (1 << 26) 715254885Sdumbbell# define CP_RINGID2_INT_STAT (1 << 29) 716254885Sdumbbell# define CP_RINGID1_INT_STAT (1 << 30) 717254885Sdumbbell# define CP_RINGID0_INT_STAT (1 << 31) 718254885Sdumbbell 719254885Sdumbbell#define CP_DEBUG 0xC1FC 720254885Sdumbbell 721254885Sdumbbell#define RLC_CNTL 0xC300 722254885Sdumbbell# define RLC_ENABLE (1 << 0) 723254885Sdumbbell#define RLC_RL_BASE 0xC304 724254885Sdumbbell#define RLC_RL_SIZE 0xC308 725254885Sdumbbell#define RLC_LB_CNTL 0xC30C 726254885Sdumbbell#define RLC_SAVE_AND_RESTORE_BASE 0xC310 727254885Sdumbbell#define RLC_LB_CNTR_MAX 0xC314 728254885Sdumbbell#define RLC_LB_CNTR_INIT 0xC318 729254885Sdumbbell 730254885Sdumbbell#define RLC_CLEAR_STATE_RESTORE_BASE 0xC320 731254885Sdumbbell 732254885Sdumbbell#define RLC_UCODE_ADDR 0xC32C 733254885Sdumbbell#define RLC_UCODE_DATA 0xC330 734254885Sdumbbell 735254885Sdumbbell#define RLC_GPU_CLOCK_COUNT_LSB 0xC338 736254885Sdumbbell#define RLC_GPU_CLOCK_COUNT_MSB 0xC33C 737254885Sdumbbell#define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340 738254885Sdumbbell#define RLC_MC_CNTL 0xC344 739254885Sdumbbell#define RLC_UCODE_CNTL 0xC348 740254885Sdumbbell 741254885Sdumbbell#define PA_SC_RASTER_CONFIG 0x28350 742254885Sdumbbell# define RASTER_CONFIG_RB_MAP_0 0 743254885Sdumbbell# define RASTER_CONFIG_RB_MAP_1 1 744254885Sdumbbell# define RASTER_CONFIG_RB_MAP_2 2 745254885Sdumbbell# define RASTER_CONFIG_RB_MAP_3 3 746254885Sdumbbell 747254885Sdumbbell#define VGT_EVENT_INITIATOR 0x28a90 748254885Sdumbbell# define SAMPLE_STREAMOUTSTATS1 (1 << 0) 749254885Sdumbbell# define SAMPLE_STREAMOUTSTATS2 (2 << 0) 750254885Sdumbbell# define SAMPLE_STREAMOUTSTATS3 (3 << 0) 751254885Sdumbbell# define CACHE_FLUSH_TS (4 << 0) 752254885Sdumbbell# define CACHE_FLUSH (6 << 0) 753254885Sdumbbell# define CS_PARTIAL_FLUSH (7 << 0) 754254885Sdumbbell# define VGT_STREAMOUT_RESET (10 << 0) 755254885Sdumbbell# define END_OF_PIPE_INCR_DE (11 << 0) 756254885Sdumbbell# define END_OF_PIPE_IB_END (12 << 0) 757254885Sdumbbell# define RST_PIX_CNT (13 << 0) 758254885Sdumbbell# define VS_PARTIAL_FLUSH (15 << 0) 759254885Sdumbbell# define PS_PARTIAL_FLUSH (16 << 0) 760254885Sdumbbell# define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 761254885Sdumbbell# define ZPASS_DONE (21 << 0) 762254885Sdumbbell# define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 763254885Sdumbbell# define PERFCOUNTER_START (23 << 0) 764254885Sdumbbell# define PERFCOUNTER_STOP (24 << 0) 765254885Sdumbbell# define PIPELINESTAT_START (25 << 0) 766254885Sdumbbell# define PIPELINESTAT_STOP (26 << 0) 767254885Sdumbbell# define PERFCOUNTER_SAMPLE (27 << 0) 768254885Sdumbbell# define SAMPLE_PIPELINESTAT (30 << 0) 769254885Sdumbbell# define SAMPLE_STREAMOUTSTATS (32 << 0) 770254885Sdumbbell# define RESET_VTX_CNT (33 << 0) 771254885Sdumbbell# define VGT_FLUSH (36 << 0) 772254885Sdumbbell# define BOTTOM_OF_PIPE_TS (40 << 0) 773254885Sdumbbell# define DB_CACHE_FLUSH_AND_INV (42 << 0) 774254885Sdumbbell# define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 775254885Sdumbbell# define FLUSH_AND_INV_DB_META (44 << 0) 776254885Sdumbbell# define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 777254885Sdumbbell# define FLUSH_AND_INV_CB_META (46 << 0) 778254885Sdumbbell# define CS_DONE (47 << 0) 779254885Sdumbbell# define PS_DONE (48 << 0) 780254885Sdumbbell# define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 781254885Sdumbbell# define THREAD_TRACE_START (51 << 0) 782254885Sdumbbell# define THREAD_TRACE_STOP (52 << 0) 783254885Sdumbbell# define THREAD_TRACE_FLUSH (54 << 0) 784254885Sdumbbell# define THREAD_TRACE_FINISH (55 << 0) 785254885Sdumbbell 786254885Sdumbbell/* 787254885Sdumbbell * PM4 788254885Sdumbbell */ 789254885Sdumbbell#define PACKET_TYPE0 0 790254885Sdumbbell#define PACKET_TYPE1 1 791254885Sdumbbell#define PACKET_TYPE2 2 792254885Sdumbbell#define PACKET_TYPE3 3 793254885Sdumbbell 794254885Sdumbbell#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 795254885Sdumbbell#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 796254885Sdumbbell#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 797254885Sdumbbell#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 798254885Sdumbbell#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 799254885Sdumbbell (((reg) >> 2) & 0xFFFF) | \ 800254885Sdumbbell ((n) & 0x3FFF) << 16) 801254885Sdumbbell#define CP_PACKET2 0x80000000 802254885Sdumbbell#define PACKET2_PAD_SHIFT 0 803254885Sdumbbell#define PACKET2_PAD_MASK (0x3fffffff << 0) 804254885Sdumbbell 805254885Sdumbbell#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 806254885Sdumbbell 807254885Sdumbbell#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 808254885Sdumbbell (((op) & 0xFF) << 8) | \ 809254885Sdumbbell ((n) & 0x3FFF) << 16) 810254885Sdumbbell 811254885Sdumbbell#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 812254885Sdumbbell 813254885Sdumbbell/* Packet 3 types */ 814254885Sdumbbell#define PACKET3_NOP 0x10 815254885Sdumbbell#define PACKET3_SET_BASE 0x11 816254885Sdumbbell#define PACKET3_BASE_INDEX(x) ((x) << 0) 817254885Sdumbbell#define GDS_PARTITION_BASE 2 818254885Sdumbbell#define CE_PARTITION_BASE 3 819254885Sdumbbell#define PACKET3_CLEAR_STATE 0x12 820254885Sdumbbell#define PACKET3_INDEX_BUFFER_SIZE 0x13 821254885Sdumbbell#define PACKET3_DISPATCH_DIRECT 0x15 822254885Sdumbbell#define PACKET3_DISPATCH_INDIRECT 0x16 823254885Sdumbbell#define PACKET3_ALLOC_GDS 0x1B 824254885Sdumbbell#define PACKET3_WRITE_GDS_RAM 0x1C 825254885Sdumbbell#define PACKET3_ATOMIC_GDS 0x1D 826254885Sdumbbell#define PACKET3_ATOMIC 0x1E 827254885Sdumbbell#define PACKET3_OCCLUSION_QUERY 0x1F 828254885Sdumbbell#define PACKET3_SET_PREDICATION 0x20 829254885Sdumbbell#define PACKET3_REG_RMW 0x21 830254885Sdumbbell#define PACKET3_COND_EXEC 0x22 831254885Sdumbbell#define PACKET3_PRED_EXEC 0x23 832254885Sdumbbell#define PACKET3_DRAW_INDIRECT 0x24 833254885Sdumbbell#define PACKET3_DRAW_INDEX_INDIRECT 0x25 834254885Sdumbbell#define PACKET3_INDEX_BASE 0x26 835254885Sdumbbell#define PACKET3_DRAW_INDEX_2 0x27 836254885Sdumbbell#define PACKET3_CONTEXT_CONTROL 0x28 837254885Sdumbbell#define PACKET3_INDEX_TYPE 0x2A 838254885Sdumbbell#define PACKET3_DRAW_INDIRECT_MULTI 0x2C 839254885Sdumbbell#define PACKET3_DRAW_INDEX_AUTO 0x2D 840254885Sdumbbell#define PACKET3_DRAW_INDEX_IMMD 0x2E 841254885Sdumbbell#define PACKET3_NUM_INSTANCES 0x2F 842254885Sdumbbell#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 843254885Sdumbbell#define PACKET3_INDIRECT_BUFFER_CONST 0x31 844254885Sdumbbell#define PACKET3_INDIRECT_BUFFER 0x32 845254885Sdumbbell#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 846254885Sdumbbell#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 847254885Sdumbbell#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 848254885Sdumbbell#define PACKET3_WRITE_DATA 0x37 849254885Sdumbbell#define WRITE_DATA_DST_SEL(x) ((x) << 8) 850254885Sdumbbell /* 0 - register 851254885Sdumbbell * 1 - memory (sync - via GRBM) 852254885Sdumbbell * 2 - tc/l2 853254885Sdumbbell * 3 - gds 854254885Sdumbbell * 4 - reserved 855254885Sdumbbell * 5 - memory (async - direct) 856254885Sdumbbell */ 857254885Sdumbbell#define WR_ONE_ADDR (1 << 16) 858254885Sdumbbell#define WR_CONFIRM (1 << 20) 859254885Sdumbbell#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 860254885Sdumbbell /* 0 - me 861254885Sdumbbell * 1 - pfp 862254885Sdumbbell * 2 - ce 863254885Sdumbbell */ 864254885Sdumbbell#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 865254885Sdumbbell#define PACKET3_MEM_SEMAPHORE 0x39 866254885Sdumbbell#define PACKET3_MPEG_INDEX 0x3A 867254885Sdumbbell#define PACKET3_COPY_DW 0x3B 868254885Sdumbbell#define PACKET3_WAIT_REG_MEM 0x3C 869254885Sdumbbell#define PACKET3_MEM_WRITE 0x3D 870254885Sdumbbell#define PACKET3_COPY_DATA 0x40 871254885Sdumbbell#define PACKET3_CP_DMA 0x41 872254885Sdumbbell/* 1. header 873254885Sdumbbell * 2. SRC_ADDR_LO or DATA [31:0] 874254885Sdumbbell * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 875254885Sdumbbell * SRC_ADDR_HI [7:0] 876254885Sdumbbell * 4. DST_ADDR_LO [31:0] 877254885Sdumbbell * 5. DST_ADDR_HI [7:0] 878254885Sdumbbell * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 879254885Sdumbbell */ 880254885Sdumbbell# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 881254885Sdumbbell /* 0 - SRC_ADDR 882254885Sdumbbell * 1 - GDS 883254885Sdumbbell */ 884254885Sdumbbell# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 885254885Sdumbbell /* 0 - ME 886254885Sdumbbell * 1 - PFP 887254885Sdumbbell */ 888254885Sdumbbell# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 889254885Sdumbbell /* 0 - SRC_ADDR 890254885Sdumbbell * 1 - GDS 891254885Sdumbbell * 2 - DATA 892254885Sdumbbell */ 893254885Sdumbbell# define PACKET3_CP_DMA_CP_SYNC (1 << 31) 894254885Sdumbbell/* COMMAND */ 895254885Sdumbbell# define PACKET3_CP_DMA_DIS_WC (1 << 21) 896254885Sdumbbell# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 897254885Sdumbbell /* 0 - none 898254885Sdumbbell * 1 - 8 in 16 899254885Sdumbbell * 2 - 8 in 32 900254885Sdumbbell * 3 - 8 in 64 901254885Sdumbbell */ 902254885Sdumbbell# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 903254885Sdumbbell /* 0 - none 904254885Sdumbbell * 1 - 8 in 16 905254885Sdumbbell * 2 - 8 in 32 906254885Sdumbbell * 3 - 8 in 64 907254885Sdumbbell */ 908254885Sdumbbell# define PACKET3_CP_DMA_CMD_SAS (1 << 26) 909254885Sdumbbell /* 0 - memory 910254885Sdumbbell * 1 - register 911254885Sdumbbell */ 912254885Sdumbbell# define PACKET3_CP_DMA_CMD_DAS (1 << 27) 913254885Sdumbbell /* 0 - memory 914254885Sdumbbell * 1 - register 915254885Sdumbbell */ 916254885Sdumbbell# define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 917254885Sdumbbell# define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 918254885Sdumbbell# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 919254885Sdumbbell#define PACKET3_PFP_SYNC_ME 0x42 920254885Sdumbbell#define PACKET3_SURFACE_SYNC 0x43 921254885Sdumbbell# define PACKET3_DEST_BASE_0_ENA (1 << 0) 922254885Sdumbbell# define PACKET3_DEST_BASE_1_ENA (1 << 1) 923254885Sdumbbell# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 924254885Sdumbbell# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 925254885Sdumbbell# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 926254885Sdumbbell# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 927254885Sdumbbell# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 928254885Sdumbbell# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 929254885Sdumbbell# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 930254885Sdumbbell# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 931254885Sdumbbell# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 932254885Sdumbbell# define PACKET3_DEST_BASE_2_ENA (1 << 19) 933254885Sdumbbell# define PACKET3_DEST_BASE_3_ENA (1 << 21) 934254885Sdumbbell# define PACKET3_TCL1_ACTION_ENA (1 << 22) 935254885Sdumbbell# define PACKET3_TC_ACTION_ENA (1 << 23) 936254885Sdumbbell# define PACKET3_CB_ACTION_ENA (1 << 25) 937254885Sdumbbell# define PACKET3_DB_ACTION_ENA (1 << 26) 938254885Sdumbbell# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 939254885Sdumbbell# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 940254885Sdumbbell#define PACKET3_ME_INITIALIZE 0x44 941254885Sdumbbell#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 942254885Sdumbbell#define PACKET3_COND_WRITE 0x45 943254885Sdumbbell#define PACKET3_EVENT_WRITE 0x46 944254885Sdumbbell#define EVENT_TYPE(x) ((x) << 0) 945254885Sdumbbell#define EVENT_INDEX(x) ((x) << 8) 946254885Sdumbbell /* 0 - any non-TS event 947254885Sdumbbell * 1 - ZPASS_DONE 948254885Sdumbbell * 2 - SAMPLE_PIPELINESTAT 949254885Sdumbbell * 3 - SAMPLE_STREAMOUTSTAT* 950254885Sdumbbell * 4 - *S_PARTIAL_FLUSH 951254885Sdumbbell * 5 - EOP events 952254885Sdumbbell * 6 - EOS events 953254885Sdumbbell * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 954254885Sdumbbell */ 955254885Sdumbbell#define INV_L2 (1 << 20) 956254885Sdumbbell /* INV TC L2 cache when EVENT_INDEX = 7 */ 957254885Sdumbbell#define PACKET3_EVENT_WRITE_EOP 0x47 958254885Sdumbbell#define DATA_SEL(x) ((x) << 29) 959254885Sdumbbell /* 0 - discard 960254885Sdumbbell * 1 - send low 32bit data 961254885Sdumbbell * 2 - send 64bit data 962254885Sdumbbell * 3 - send 64bit counter value 963254885Sdumbbell */ 964254885Sdumbbell#define INT_SEL(x) ((x) << 24) 965254885Sdumbbell /* 0 - none 966254885Sdumbbell * 1 - interrupt only (DATA_SEL = 0) 967254885Sdumbbell * 2 - interrupt when data write is confirmed 968254885Sdumbbell */ 969254885Sdumbbell#define PACKET3_EVENT_WRITE_EOS 0x48 970254885Sdumbbell#define PACKET3_PREAMBLE_CNTL 0x4A 971254885Sdumbbell# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 972254885Sdumbbell# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 973254885Sdumbbell#define PACKET3_ONE_REG_WRITE 0x57 974254885Sdumbbell#define PACKET3_LOAD_CONFIG_REG 0x5F 975254885Sdumbbell#define PACKET3_LOAD_CONTEXT_REG 0x60 976254885Sdumbbell#define PACKET3_LOAD_SH_REG 0x61 977254885Sdumbbell#define PACKET3_SET_CONFIG_REG 0x68 978254885Sdumbbell#define PACKET3_SET_CONFIG_REG_START 0x00008000 979254885Sdumbbell#define PACKET3_SET_CONFIG_REG_END 0x0000b000 980254885Sdumbbell#define PACKET3_SET_CONTEXT_REG 0x69 981254885Sdumbbell#define PACKET3_SET_CONTEXT_REG_START 0x00028000 982254885Sdumbbell#define PACKET3_SET_CONTEXT_REG_END 0x00029000 983254885Sdumbbell#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 984254885Sdumbbell#define PACKET3_SET_RESOURCE_INDIRECT 0x74 985254885Sdumbbell#define PACKET3_SET_SH_REG 0x76 986254885Sdumbbell#define PACKET3_SET_SH_REG_START 0x0000b000 987254885Sdumbbell#define PACKET3_SET_SH_REG_END 0x0000c000 988254885Sdumbbell#define PACKET3_SET_SH_REG_OFFSET 0x77 989254885Sdumbbell#define PACKET3_ME_WRITE 0x7A 990254885Sdumbbell#define PACKET3_SCRATCH_RAM_WRITE 0x7D 991254885Sdumbbell#define PACKET3_SCRATCH_RAM_READ 0x7E 992254885Sdumbbell#define PACKET3_CE_WRITE 0x7F 993254885Sdumbbell#define PACKET3_LOAD_CONST_RAM 0x80 994254885Sdumbbell#define PACKET3_WRITE_CONST_RAM 0x81 995254885Sdumbbell#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 996254885Sdumbbell#define PACKET3_DUMP_CONST_RAM 0x83 997254885Sdumbbell#define PACKET3_INCREMENT_CE_COUNTER 0x84 998254885Sdumbbell#define PACKET3_INCREMENT_DE_COUNTER 0x85 999254885Sdumbbell#define PACKET3_WAIT_ON_CE_COUNTER 0x86 1000254885Sdumbbell#define PACKET3_WAIT_ON_DE_COUNTER 0x87 1001254885Sdumbbell#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1002254885Sdumbbell#define PACKET3_SET_CE_DE_COUNTERS 0x89 1003254885Sdumbbell#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 1004254885Sdumbbell#define PACKET3_SWITCH_BUFFER 0x8B 1005254885Sdumbbell 1006254885Sdumbbell/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1007254885Sdumbbell#define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1008254885Sdumbbell#define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 1009254885Sdumbbell 1010254885Sdumbbell#define DMA_RB_CNTL 0xd000 1011254885Sdumbbell# define DMA_RB_ENABLE (1 << 0) 1012254885Sdumbbell# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1013254885Sdumbbell# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1014254885Sdumbbell# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1015254885Sdumbbell# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1016254885Sdumbbell# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1017254885Sdumbbell#define DMA_RB_BASE 0xd004 1018254885Sdumbbell#define DMA_RB_RPTR 0xd008 1019254885Sdumbbell#define DMA_RB_WPTR 0xd00c 1020254885Sdumbbell 1021254885Sdumbbell#define DMA_RB_RPTR_ADDR_HI 0xd01c 1022254885Sdumbbell#define DMA_RB_RPTR_ADDR_LO 0xd020 1023254885Sdumbbell 1024254885Sdumbbell#define DMA_IB_CNTL 0xd024 1025254885Sdumbbell# define DMA_IB_ENABLE (1 << 0) 1026254885Sdumbbell# define DMA_IB_SWAP_ENABLE (1 << 4) 1027254885Sdumbbell#define DMA_IB_RPTR 0xd028 1028254885Sdumbbell#define DMA_CNTL 0xd02c 1029254885Sdumbbell# define TRAP_ENABLE (1 << 0) 1030254885Sdumbbell# define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1031254885Sdumbbell# define SEM_WAIT_INT_ENABLE (1 << 2) 1032254885Sdumbbell# define DATA_SWAP_ENABLE (1 << 3) 1033254885Sdumbbell# define FENCE_SWAP_ENABLE (1 << 4) 1034254885Sdumbbell# define CTXEMPTY_INT_ENABLE (1 << 28) 1035254885Sdumbbell#define DMA_STATUS_REG 0xd034 1036254885Sdumbbell# define DMA_IDLE (1 << 0) 1037254885Sdumbbell#define DMA_TILING_CONFIG 0xd0b8 1038254885Sdumbbell 1039254885Sdumbbell#define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ 1040254885Sdumbbell (((b) & 0x1) << 26) | \ 1041254885Sdumbbell (((t) & 0x1) << 23) | \ 1042254885Sdumbbell (((s) & 0x1) << 22) | \ 1043254885Sdumbbell (((n) & 0xFFFFF) << 0)) 1044254885Sdumbbell 1045254885Sdumbbell#define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1046254885Sdumbbell (((vmid) & 0xF) << 20) | \ 1047254885Sdumbbell (((n) & 0xFFFFF) << 0)) 1048254885Sdumbbell 1049254885Sdumbbell#define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1050254885Sdumbbell (1 << 26) | \ 1051254885Sdumbbell (1 << 21) | \ 1052254885Sdumbbell (((n) & 0xFFFFF) << 0)) 1053254885Sdumbbell 1054254885Sdumbbell/* async DMA Packet types */ 1055254885Sdumbbell#define DMA_PACKET_WRITE 0x2 1056254885Sdumbbell#define DMA_PACKET_COPY 0x3 1057254885Sdumbbell#define DMA_PACKET_INDIRECT_BUFFER 0x4 1058254885Sdumbbell#define DMA_PACKET_SEMAPHORE 0x5 1059254885Sdumbbell#define DMA_PACKET_FENCE 0x6 1060254885Sdumbbell#define DMA_PACKET_TRAP 0x7 1061254885Sdumbbell#define DMA_PACKET_SRBM_WRITE 0x9 1062254885Sdumbbell#define DMA_PACKET_CONSTANT_FILL 0xd 1063254885Sdumbbell#define DMA_PACKET_NOP 0xf 1064254885Sdumbbell 1065254885Sdumbbell#endif 1066