1168404Spjd/* 2168404Spjd * Copyright �� 2007-2008 Intel Corporation 3168404Spjd * Jesse Barnes <jesse.barnes@intel.com> 4168404Spjd * 5168404Spjd * Permission is hereby granted, free of charge, to any person obtaining a 6168404Spjd * copy of this software and associated documentation files (the "Software"), 7168404Spjd * to deal in the Software without restriction, including without limitation 8168404Spjd * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9168404Spjd * and/or sell copies of the Software, and to permit persons to whom the 10168404Spjd * Software is furnished to do so, subject to the following conditions: 11168404Spjd * 12168404Spjd * The above copyright notice and this permission notice shall be included in 13168404Spjd * all copies or substantial portions of the Software. 14168404Spjd * 15168404Spjd * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16168404Spjd * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17168404Spjd * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18168404Spjd * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19168404Spjd * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20168404Spjd * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21168404Spjd * OTHER DEALINGS IN THE SOFTWARE. 22168404Spjd * 23219089Spjd * $FreeBSD$ 24227497Smm */ 25236155Smm#ifndef __DRM_EDID_H__ 26236145Smm#define __DRM_EDID_H__ 27236155Smm 28168404Spjd#include <sys/types.h> 29168404Spjd#include <dev/drm2/drmP.h> 30168404Spjd 31168404Spjd#define EDID_LENGTH 128 32168404Spjd#define DDC_ADDR 0x50 33168404Spjd 34168404Spjd#define CEA_EXT 0x02 35168404Spjd#define VTB_EXT 0x10 36168404Spjd#define DI_EXT 0x40 37168404Spjd#define LS_EXT 0x50 38168404Spjd#define MI_EXT 0x60 39168404Spjd 40168404Spjdstruct est_timings { 41168404Spjd u8 t1; 42168404Spjd u8 t2; 43168404Spjd u8 mfg_rsvd; 44168404Spjd} __attribute__((packed)); 45168404Spjd 46185029Spjd/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 47185029Spjd#define EDID_TIMING_ASPECT_SHIFT 6 48168404Spjd#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 49236155Smm 50168404Spjd/* need to add 60 */ 51168404Spjd#define EDID_TIMING_VFREQ_SHIFT 0 52168404Spjd#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 53168404Spjd 54168404Spjdstruct std_timing { 55168404Spjd u8 hsize; /* need to multiply by 8 then add 248 */ 56185029Spjd u8 vfreq_aspect; 57236884Smm} __attribute__((packed)); 58168404Spjd 59219089Spjd#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 60219089Spjd#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 61168404Spjd#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 62168404Spjd#define DRM_EDID_PT_STEREO (1 << 5) 63168404Spjd#define DRM_EDID_PT_INTERLACED (1 << 7) 64168404Spjd 65168404Spjd/* If detailed data is pixel timing */ 66224171Sgibbsstruct detailed_pixel_timing { 67168404Spjd u8 hactive_lo; 68168404Spjd u8 hblank_lo; 69168404Spjd u8 hactive_hblank_hi; 70168404Spjd u8 vactive_lo; 71168404Spjd u8 vblank_lo; 72168404Spjd u8 vactive_vblank_hi; 73168404Spjd u8 hsync_offset_lo; 74168404Spjd u8 hsync_pulse_width_lo; 75236155Smm u8 vsync_offset_pulse_width_lo; 76168404Spjd u8 hsync_vsync_offset_pulse_width_hi; 77228103Smm u8 width_mm_lo; 78228103Smm u8 height_mm_lo; 79168404Spjd u8 width_height_mm_hi; 80168404Spjd u8 hborder; 81168404Spjd u8 vborder; 82219089Spjd u8 misc; 83168404Spjd} __attribute__((packed)); 84168404Spjd 85168404Spjd/* If it's not pixel timing, it'll be one of the below */ 86168404Spjdstruct detailed_data_string { 87168404Spjd u8 str[13]; 88168404Spjd} __attribute__((packed)); 89168404Spjd 90168404Spjdstruct detailed_data_monitor_range { 91168404Spjd u8 min_vfreq; 92168404Spjd u8 max_vfreq; 93168404Spjd u8 min_hfreq_khz; 94168404Spjd u8 max_hfreq_khz; 95168404Spjd u8 pixel_clock_mhz; /* need to multiply by 10 */ 96168404Spjd u16 sec_gtf_toggle; /* A000=use above, 20=use below */ 97168404Spjd u8 hfreq_start_khz; /* need to multiply by 2 */ 98168404Spjd u8 c; /* need to divide by 2 */ 99168404Spjd u16 m; 100185029Spjd u8 k; 101185029Spjd u8 j; /* need to divide by 2 */ 102168404Spjd} __attribute__((packed)); 103168404Spjd 104168404Spjdstruct detailed_data_wpindex { 105168404Spjd u8 white_yx_lo; /* Lower 2 bits each */ 106168404Spjd u8 white_x_hi; 107168404Spjd u8 white_y_hi; 108168404Spjd u8 gamma; /* need to divide by 100 then add 1 */ 109168404Spjd} __attribute__((packed)); 110168404Spjd 111168404Spjdstruct detailed_data_color_point { 112168404Spjd u8 windex1; 113185029Spjd u8 wpindex1[3]; 114168404Spjd u8 windex2; 115168404Spjd u8 wpindex2[3]; 116168404Spjd} __attribute__((packed)); 117168404Spjd 118168404Spjdstruct cvt_timing { 119168404Spjd u8 code[3]; 120168404Spjd} __attribute__((packed)); 121168404Spjd 122168404Spjdstruct detailed_non_pixel { 123168404Spjd u8 pad1; 124168404Spjd u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 125168404Spjd fb=color point data, fa=standard timing data, 126224171Sgibbs f9=undefined, f8=mfg. reserved */ 127168404Spjd u8 pad2; 128168404Spjd union { 129168404Spjd struct detailed_data_string str; 130168404Spjd struct detailed_data_monitor_range range; 131168404Spjd struct detailed_data_wpindex color; 132168404Spjd struct std_timing timings[6]; 133168404Spjd struct cvt_timing cvt[4]; 134168404Spjd } data; 135168404Spjd} __attribute__((packed)); 136219089Spjd 137228103Smm#define EDID_DETAIL_EST_TIMINGS 0xf7 138236155Smm#define EDID_DETAIL_CVT_3BYTE 0xf8 139236155Smm#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 140168404Spjd#define EDID_DETAIL_STD_MODES 0xfa 141168404Spjd#define EDID_DETAIL_MONITOR_CPDATA 0xfb 142168404Spjd#define EDID_DETAIL_MONITOR_NAME 0xfc 143168404Spjd#define EDID_DETAIL_MONITOR_RANGE 0xfd 144168404Spjd#define EDID_DETAIL_MONITOR_STRING 0xfe 145168404Spjd#define EDID_DETAIL_MONITOR_SERIAL 0xff 146168404Spjd 147168404Spjdstruct detailed_timing { 148168404Spjd u16 pixel_clock; /* need to multiply by 10 KHz */ 149168404Spjd union { 150168404Spjd struct detailed_pixel_timing pixel_data; 151168404Spjd struct detailed_non_pixel other_data; 152168404Spjd } data; 153168404Spjd} __attribute__((packed)); 154168404Spjd 155168404Spjd#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 156168404Spjd#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 157168404Spjd#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 158168404Spjd#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 159168404Spjd#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 160168404Spjd#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 161168404Spjd#define DRM_EDID_INPUT_DIGITAL (1 << 7) 162168404Spjd#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) 163168404Spjd#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) 164168404Spjd#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) 165224171Sgibbs#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) 166224171Sgibbs#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) 167168404Spjd#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) 168168404Spjd#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) 169168404Spjd#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) 170168404Spjd#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) 171168404Spjd#define DRM_EDID_DIGITAL_TYPE_UNDEF (0) 172168404Spjd#define DRM_EDID_DIGITAL_TYPE_DVI (1) 173168404Spjd#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2) 174236155Smm#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3) 175168404Spjd#define DRM_EDID_DIGITAL_TYPE_MDDI (4) 176168404Spjd#define DRM_EDID_DIGITAL_TYPE_DP (5) 177168404Spjd 178168404Spjd#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 179219089Spjd#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 180168404Spjd#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 181168404Spjd#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 182168404Spjd/* If digital */ 183168404Spjd#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 184168404Spjd#define DRM_EDID_FEATURE_RGB (0 << 3) 185168404Spjd#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 186228103Smm#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 187168404Spjd#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 188168404Spjd 189168404Spjd#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 190168404Spjd#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 191168404Spjd#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 192168404Spjd 193168404Spjdstruct edid { 194168404Spjd u8 header[8]; 195248571Smm /* Vendor & product info */ 196185029Spjd u8 mfg_id[2]; 197248571Smm u8 prod_code[2]; 198219089Spjd u32 serial; /* FIXME: byte order */ 199219089Spjd u8 mfg_week; 200168404Spjd u8 mfg_year; 201168404Spjd /* EDID version */ 202168404Spjd u8 version; 203168404Spjd u8 revision; 204168404Spjd /* Display info: */ 205168404Spjd u8 input; 206168404Spjd u8 width_cm; 207185029Spjd u8 height_cm; 208168404Spjd u8 gamma; 209219089Spjd u8 features; 210168404Spjd /* Color characteristics */ 211236884Smm u8 red_green_lo; 212185029Spjd u8 black_white_lo; 213185029Spjd u8 red_x; 214168404Spjd u8 red_y; 215168404Spjd u8 green_x; 216168404Spjd u8 green_y; 217168404Spjd u8 blue_x; 218168404Spjd u8 blue_y; 219168404Spjd u8 white_x; 220168404Spjd u8 white_y; 221185029Spjd /* Est. timings and mfg rsvd timings*/ 222168404Spjd struct est_timings established_timings; 223168404Spjd /* Standard timings 1-8*/ 224219089Spjd struct std_timing standard_timings[8]; 225185029Spjd /* Detailing timings 1-4 */ 226219089Spjd struct detailed_timing detailed_timings[4]; 227219089Spjd /* Number of 128 byte ext. blocks */ 228185029Spjd u8 extensions; 229219089Spjd /* Checksum */ 230219089Spjd u8 checksum; 231219089Spjd} __attribute__((packed)); 232168404Spjd 233219089Spjd#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 234168404Spjd 235224171Sgibbsstruct drm_encoder; 236224171Sgibbsstruct drm_connector; 237168404Spjdstruct drm_display_mode; 238236960Smmvoid drm_edid_to_eld(struct drm_connector *connector, struct edid *edid); 239219089Spjdint drm_av_sync_delay(struct drm_connector *connector, 240168404Spjd struct drm_display_mode *mode); 241168404Spjdstruct drm_connector *drm_select_eld(struct drm_encoder *encoder, 242168404Spjd struct drm_display_mode *mode); 243228020Smm 244168404Spjd#endif /* __DRM_EDID_H__ */ 245168404Spjd