via_dmablit.h revision 203288
1183840Sraj/* via_dmablit.h -- PCI DMA BitBlt support for the VIA Unichrome/Pro 2183840Sraj * 3183840Sraj * Copyright 2005 Thomas Hellstrom. 4183840Sraj * All Rights Reserved. 5183840Sraj * 6183840Sraj * Permission is hereby granted, free of charge, to any person obtaining a 7183840Sraj * copy of this software and associated documentation files (the "Software"), 8183840Sraj * to deal in the Software without restriction, including without limitation 9183840Sraj * the rights to use, copy, modify, merge, publish, distribute, sub license, 10183840Sraj * and/or sell copies of the Software, and to permit persons to whom the 11183840Sraj * Software is furnished to do so, subject to the following conditions: 12183840Sraj * 13183840Sraj * The above copyright notice and this permission notice (including the 14183840Sraj * next paragraph) shall be included in all copies or substantial portions 15183840Sraj * of the Software. 16183840Sraj * 17183840Sraj * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18183840Sraj * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19183840Sraj * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 20183840Sraj * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 21183840Sraj * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 22183840Sraj * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 23183840Sraj * USE OR OTHER DEALINGS IN THE SOFTWARE. 24183840Sraj * 25183840Sraj * Authors: 26183840Sraj * Thomas Hellstrom. 27183840Sraj * Register info from Digeo Inc. 28183840Sraj */ 29183840Sraj 30183840Sraj#include <sys/cdefs.h> 31183840Sraj__FBSDID("$FreeBSD: head/sys/dev/drm/via_dmablit.h 203288 2010-01-31 14:30:39Z rnoland $"); 32183840Sraj 33183840Sraj#ifndef _VIA_DMABLIT_H 34183840Sraj#define _VIA_DMABLIT_H 35183840Sraj 36183840Sraj#define VIA_NUM_BLIT_ENGINES 2 37183840Sraj#define VIA_NUM_BLIT_SLOTS 8 38183840Sraj 39209131Srajstruct _drm_via_descriptor; 40183840Sraj 41183840Srajtypedef struct _drm_via_sg_info { 42183840Sraj vm_page_t *pages; 43183840Sraj unsigned long num_pages; 44183840Sraj struct _drm_via_descriptor **desc_pages; 45183840Sraj int num_desc_pages; 46183840Sraj int num_desc; 47183840Sraj unsigned char *bounce_buffer; 48298627Sbr dma_addr_t chain_start; 49183840Sraj uint32_t free_on_sequence; 50183840Sraj unsigned int descriptors_per_page; 51183840Sraj int aborted; 52242531Sandrew enum { 53242531Sandrew dr_via_device_mapped, 54260327Snwhitehorn dr_via_desc_pages_alloc, 55242531Sandrew dr_via_pages_locked, 56266301Sandrew dr_via_pages_alloc, 57183840Sraj dr_via_sg_init 58300533Sian } state; 59300533Sian} drm_via_sg_info_t; 60300533Sian 61300533Siantypedef struct _drm_via_blitq { 62300533Sian struct drm_device *dev; 63300533Sian uint32_t cur_blit_handle; 64209131Sraj uint32_t done_blit_handle; 65183840Sraj unsigned serviced; 66196531Sraj unsigned head; 67183840Sraj unsigned cur; 68242531Sandrew unsigned num_free; 69183840Sraj unsigned num_outstanding; 70209131Sraj unsigned long end; 71250292Sgber int aborting; 72250293Sgber int is_active; 73250292Sgber drm_via_sg_info_t *blits[VIA_NUM_BLIT_SLOTS]; 74250292Sgber struct mtx blit_lock; 75294425Szbb wait_queue_head_t blit_queue[VIA_NUM_BLIT_SLOTS]; 76294425Szbb wait_queue_head_t busy_queue; 77294426Szbb struct task wq; 78294438Szbb struct callout poll_timer; 79294425Szbb} drm_via_blitq_t; 80183840Sraj 81239277Sgonzo 82209131Sraj/* 83209131Sraj * PCI DMA Registers 84209131Sraj * Channels 2 & 3 don't seem to be implemented in hardware. 85209131Sraj */ 86209131Sraj 87209131Sraj#define VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */ 88209131Sraj#define VIA_PCI_DMA_DAR0 0xE44 /* Device Address Register of Channel 0 */ 89209131Sraj#define VIA_PCI_DMA_BCR0 0xE48 /* Byte Count Register of Channel 0 */ 90209131Sraj#define VIA_PCI_DMA_DPR0 0xE4C /* Descriptor Pointer Register of Channel 0 */ 91209131Sraj 92209131Sraj#define VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */ 93209131Sraj#define VIA_PCI_DMA_DAR1 0xE54 /* Device Address Register of Channel 1 */ 94209131Sraj#define VIA_PCI_DMA_BCR1 0xE58 /* Byte Count Register of Channel 1 */ 95209131Sraj#define VIA_PCI_DMA_DPR1 0xE5C /* Descriptor Pointer Register of Channel 1 */ 96209131Sraj 97209131Sraj#define VIA_PCI_DMA_MAR2 0xE60 /* Memory Address Register of Channel 2 */ 98209131Sraj#define VIA_PCI_DMA_DAR2 0xE64 /* Device Address Register of Channel 2 */ 99209131Sraj#define VIA_PCI_DMA_BCR2 0xE68 /* Byte Count Register of Channel 2 */ 100209131Sraj#define VIA_PCI_DMA_DPR2 0xE6C /* Descriptor Pointer Register of Channel 2 */ 101209131Sraj 102209131Sraj#define VIA_PCI_DMA_MAR3 0xE70 /* Memory Address Register of Channel 3 */ 103209131Sraj#define VIA_PCI_DMA_DAR3 0xE74 /* Device Address Register of Channel 3 */ 104209131Sraj#define VIA_PCI_DMA_BCR3 0xE78 /* Byte Count Register of Channel 3 */ 105228201Sjchandra#define VIA_PCI_DMA_DPR3 0xE7C /* Descriptor Pointer Register of Channel 3 */ 106209131Sraj 107209131Sraj#define VIA_PCI_DMA_MR0 0xE80 /* Mode Register of Channel 0 */ 108209131Sraj#define VIA_PCI_DMA_MR1 0xE84 /* Mode Register of Channel 1 */ 109209131Sraj#define VIA_PCI_DMA_MR2 0xE88 /* Mode Register of Channel 2 */ 110209131Sraj#define VIA_PCI_DMA_MR3 0xE8C /* Mode Register of Channel 3 */ 111228201Sjchandra 112209131Sraj#define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */ 113209131Sraj#define VIA_PCI_DMA_CSR1 0xE94 /* Command/Status Register of Channel 1 */ 114209131Sraj#define VIA_PCI_DMA_CSR2 0xE98 /* Command/Status Register of Channel 2 */ 115209131Sraj#define VIA_PCI_DMA_CSR3 0xE9C /* Command/Status Register of Channel 3 */ 116209131Sraj 117209131Sraj#define VIA_PCI_DMA_PTR 0xEA0 /* Priority Type Register */ 118239277Sgonzo 119239277Sgonzo/* Define for DMA engine */ 120239277Sgonzo/* DPR */ 121239277Sgonzo#define VIA_DMA_DPR_EC (1<<1) /* end of chain */ 122239277Sgonzo#define VIA_DMA_DPR_DDIE (1<<2) /* descriptor done interrupt enable */ 123209131Sraj#define VIA_DMA_DPR_DT (1<<3) /* direction of transfer (RO) */ 124209131Sraj 125209131Sraj/* MR */ 126209131Sraj#define VIA_DMA_MR_CM (1<<0) /* chaining mode */ 127209131Sraj#define VIA_DMA_MR_TDIE (1<<1) /* transfer done interrupt enable */ 128209131Sraj#define VIA_DMA_MR_HENDMACMD (1<<7) /* ? */ 129209131Sraj 130209131Sraj/* CSR */ 131209131Sraj#define VIA_DMA_CSR_DE (1<<0) /* DMA enable */ 132209131Sraj#define VIA_DMA_CSR_TS (1<<1) /* transfer start */ 133209131Sraj#define VIA_DMA_CSR_TA (1<<2) /* transfer abort */ 134209131Sraj#define VIA_DMA_CSR_TD (1<<3) /* transfer done */ 135209131Sraj#define VIA_DMA_CSR_DD (1<<4) /* descriptor done */ 136209131Sraj#define VIA_DMA_DPR_EC (1<<1) /* end of chain */ 137209131Sraj 138209131Sraj 139209131Sraj 140209131Sraj#endif 141209131Sraj