195584Sanholt/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
2152909Sanholt * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3152909Sanholt *
495584Sanholt * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
595584Sanholt * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
695584Sanholt * All rights reserved.
795584Sanholt *
895584Sanholt * Permission is hereby granted, free of charge, to any person obtaining a
995584Sanholt * copy of this software and associated documentation files (the "Software"),
1095584Sanholt * to deal in the Software without restriction, including without limitation
1195584Sanholt * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1295584Sanholt * and/or sell copies of the Software, and to permit persons to whom the
1395584Sanholt * Software is furnished to do so, subject to the following conditions:
1495584Sanholt *
1595584Sanholt * The above copyright notice and this permission notice (including the next
1695584Sanholt * paragraph) shall be included in all copies or substantial portions of the
1795584Sanholt * Software.
1895584Sanholt *
1995584Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
2095584Sanholt * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2195584Sanholt * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
2295584Sanholt * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
2395584Sanholt * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2495584Sanholt * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2595584Sanholt * OTHER DEALINGS IN THE SOFTWARE.
2695584Sanholt *
2795584Sanholt * Authors:
2895584Sanholt *    Gareth Hughes <gareth@valinux.com>
2995584Sanholt */
3095584Sanholt
31152909Sanholt#include <sys/cdefs.h>
32152909Sanholt__FBSDID("$FreeBSD$");
33152909Sanholt
3495584Sanholt#ifndef __MGA_DRV_H__
3595584Sanholt#define __MGA_DRV_H__
3695584Sanholt
37145132Sanholt/* General customization:
38145132Sanholt */
39145132Sanholt
40145132Sanholt#define DRIVER_AUTHOR		"Gareth Hughes, VA Linux Systems Inc."
41145132Sanholt
42145132Sanholt#define DRIVER_NAME		"mga"
43145132Sanholt#define DRIVER_DESC		"Matrox G200/G400"
44157617Sanholt#define DRIVER_DATE		"20060319"
45145132Sanholt
46145132Sanholt#define DRIVER_MAJOR		3
47152909Sanholt#define DRIVER_MINOR		2
48157617Sanholt#define DRIVER_PATCHLEVEL	2
49145132Sanholt
5095584Sanholttypedef struct drm_mga_primary_buffer {
5195584Sanholt	u8 *start;
5295584Sanholt	u8 *end;
5395584Sanholt	int size;
5495584Sanholt
5595584Sanholt	u32 tail;
5695584Sanholt	int space;
5795584Sanholt	volatile long wrapped;
5895584Sanholt
5995584Sanholt	volatile u32 *status;
6095584Sanholt
6195584Sanholt	u32 last_flush;
6295584Sanholt	u32 last_wrap;
6395584Sanholt
6495584Sanholt	u32 high_mark;
6595584Sanholt} drm_mga_primary_buffer_t;
6695584Sanholt
6795584Sanholttypedef struct drm_mga_freelist {
68145132Sanholt	struct drm_mga_freelist *next;
69145132Sanholt	struct drm_mga_freelist *prev;
7095584Sanholt	drm_mga_age_t age;
71182080Srnoland	struct drm_buf *buf;
7295584Sanholt} drm_mga_freelist_t;
7395584Sanholt
7495584Sanholttypedef struct {
75145132Sanholt	drm_mga_freelist_t *list_entry;
7695584Sanholt	int discard;
7795584Sanholt	int dispatched;
7895584Sanholt} drm_mga_buf_priv_t;
7995584Sanholt
8095584Sanholttypedef struct drm_mga_private {
8195584Sanholt	drm_mga_primary_buffer_t prim;
8295584Sanholt	drm_mga_sarea_t *sarea_priv;
8395584Sanholt
84145132Sanholt	drm_mga_freelist_t *head;
85145132Sanholt	drm_mga_freelist_t *tail;
8695584Sanholt
8795584Sanholt	unsigned int warp_pipe;
8895584Sanholt	unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
8995584Sanholt
9095584Sanholt	int chipset;
9195584Sanholt	int usec_timeout;
9295584Sanholt
93152909Sanholt	/**
94152909Sanholt	 * If set, the new DMA initialization sequence was used.  This is
95152909Sanholt	 * primarilly used to select how the driver should uninitialized its
96152909Sanholt	 * internal DMA structures.
97152909Sanholt	 */
98152909Sanholt	int used_new_dma_init;
99152909Sanholt
100152909Sanholt	/**
101152909Sanholt	 * If AGP memory is used for DMA buffers, this will be the value
102152909Sanholt	 * \c MGA_PAGPXFER.  Otherwise, it will be zero (for a PCI transfer).
103152909Sanholt	 */
104152909Sanholt	u32 dma_access;
105152909Sanholt
106152909Sanholt	/**
107152909Sanholt	 * If AGP memory is used for DMA buffers, this will be the value
108152909Sanholt	 * \c MGA_WAGP_ENABLE.  Otherwise, it will be zero (for a PCI
109152909Sanholt	 * transfer).
110152909Sanholt	 */
111152909Sanholt	u32 wagp_enable;
112152909Sanholt
113152909Sanholt	/**
114152909Sanholt	 * \name MMIO region parameters.
115182080Srnoland	 *
116152909Sanholt	 * \sa drm_mga_private_t::mmio
117152909Sanholt	 */
118152909Sanholt	/*@{*/
119182080Srnoland	u32 mmio_base;			/**< Bus address of base of MMIO. */
120182080Srnoland	u32 mmio_size;			/**< Size of the MMIO region. */
121152909Sanholt	/*@}*/
122152909Sanholt
12395584Sanholt	u32 clear_cmd;
12495584Sanholt	u32 maccess;
12595584Sanholt
126182080Srnoland	atomic_t vbl_received;		/**< Number of vblanks received. */
127152909Sanholt	wait_queue_head_t fence_queue;
128152909Sanholt	atomic_t last_fence_retired;
129152909Sanholt	u32 next_fence_to_post;
130152909Sanholt
13195584Sanholt	unsigned int fb_cpp;
13295584Sanholt	unsigned int front_offset;
13395584Sanholt	unsigned int front_pitch;
13495584Sanholt	unsigned int back_offset;
13595584Sanholt	unsigned int back_pitch;
13695584Sanholt
13795584Sanholt	unsigned int depth_cpp;
13895584Sanholt	unsigned int depth_offset;
13995584Sanholt	unsigned int depth_pitch;
14095584Sanholt
14195584Sanholt	unsigned int texture_offset;
14295584Sanholt	unsigned int texture_size;
14395584Sanholt
144112015Sanholt	drm_local_map_t *sarea;
145112015Sanholt	drm_local_map_t *mmio;
146112015Sanholt	drm_local_map_t *status;
147112015Sanholt	drm_local_map_t *warp;
148112015Sanholt	drm_local_map_t *primary;
149112015Sanholt	drm_local_map_t *agp_textures;
150182080Srnoland
151152909Sanholt	unsigned long agp_handle;
152152909Sanholt	unsigned int agp_size;
15395584Sanholt} drm_mga_private_t;
15495584Sanholt
155182080Srnolandextern struct drm_ioctl_desc mga_ioctls[];
156152909Sanholtextern int mga_max_ioctl;
157152909Sanholt
15895584Sanholt				/* mga_dma.c */
159182080Srnolandextern int mga_dma_bootstrap(struct drm_device *dev, void *data,
160182080Srnoland			     struct drm_file *file_priv);
161182080Srnolandextern int mga_dma_init(struct drm_device *dev, void *data,
162182080Srnoland			struct drm_file *file_priv);
163182080Srnolandextern int mga_dma_flush(struct drm_device *dev, void *data,
164182080Srnoland			 struct drm_file *file_priv);
165182080Srnolandextern int mga_dma_reset(struct drm_device *dev, void *data,
166182080Srnoland			 struct drm_file *file_priv);
167182080Srnolandextern int mga_dma_buffers(struct drm_device *dev, void *data,
168182080Srnoland			   struct drm_file *file_priv);
169182080Srnolandextern int mga_driver_load(struct drm_device *dev, unsigned long flags);
170182080Srnolandextern int mga_driver_unload(struct drm_device * dev);
171182080Srnolandextern void mga_driver_lastclose(struct drm_device * dev);
172182080Srnolandextern int mga_driver_dma_quiescent(struct drm_device * dev);
17395584Sanholt
174145132Sanholtextern int mga_do_wait_for_idle(drm_mga_private_t * dev_priv);
17595584Sanholt
176145132Sanholtextern void mga_do_dma_flush(drm_mga_private_t * dev_priv);
177145132Sanholtextern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv);
178145132Sanholtextern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv);
17995584Sanholt
180182080Srnolandextern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf);
18195584Sanholt
18295584Sanholt				/* mga_warp.c */
183152909Sanholtextern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv);
184145132Sanholtextern int mga_warp_install_microcode(drm_mga_private_t * dev_priv);
185145132Sanholtextern int mga_warp_init(drm_mga_private_t * dev_priv);
18695584Sanholt
187152909Sanholt				/* mga_irq.c */
188182080Srnolandextern int mga_enable_vblank(struct drm_device *dev, int crtc);
189182080Srnolandextern void mga_disable_vblank(struct drm_device *dev, int crtc);
190182080Srnolandextern u32 mga_get_vblank_counter(struct drm_device *dev, int crtc);
191182080Srnolandextern int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence);
192182080Srnolandextern int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence);
193145132Sanholtextern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS);
194182080Srnolandextern void mga_driver_irq_preinstall(struct drm_device * dev);
195182080Srnolandextern int mga_driver_irq_postinstall(struct drm_device * dev);
196182080Srnolandextern void mga_driver_irq_uninstall(struct drm_device * dev);
197152909Sanholtextern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
198152909Sanholt			     unsigned long arg);
199145132Sanholt
200119098Sanholt#define mga_flush_write_combine()	DRM_WRITEMEMORYBARRIER()
20195584Sanholt
202112015Sanholt#if defined(__linux__) && defined(__alpha__)
20395584Sanholt#define MGA_BASE( reg )		((unsigned long)(dev_priv->mmio->handle))
20495584Sanholt#define MGA_ADDR( reg )		(MGA_BASE(reg) + reg)
20595584Sanholt
20695584Sanholt#define MGA_DEREF( reg )	*(volatile u32 *)MGA_ADDR( reg )
20795584Sanholt#define MGA_DEREF8( reg )	*(volatile u8 *)MGA_ADDR( reg )
20895584Sanholt
20995584Sanholt#define MGA_READ( reg )		(_MGA_READ((u32 *)MGA_ADDR(reg)))
210112015Sanholt#define MGA_READ8( reg )	(_MGA_READ((u8 *)MGA_ADDR(reg)))
211119098Sanholt#define MGA_WRITE( reg, val )	do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
212119098Sanholt#define MGA_WRITE8( reg, val )  do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
21395584Sanholt
214145132Sanholtstatic inline u32 _MGA_READ(u32 * addr)
21595584Sanholt{
216119098Sanholt	DRM_MEMORYBARRIER();
21795584Sanholt	return *(volatile u32 *)addr;
21895584Sanholt}
21995584Sanholt#else
220112015Sanholt#define MGA_READ8( reg )	DRM_READ8(dev_priv->mmio, (reg))
221112015Sanholt#define MGA_READ( reg )		DRM_READ32(dev_priv->mmio, (reg))
222112015Sanholt#define MGA_WRITE8( reg, val )  DRM_WRITE8(dev_priv->mmio, (reg), (val))
223112015Sanholt#define MGA_WRITE( reg, val )	DRM_WRITE32(dev_priv->mmio, (reg), (val))
22495584Sanholt#endif
22595584Sanholt
226182080Srnoland#define DWGREG0		0x1c00
227182080Srnoland#define DWGREG0_END	0x1dff
22895584Sanholt#define DWGREG1		0x2c00
22995584Sanholt#define DWGREG1_END	0x2dff
23095584Sanholt
23195584Sanholt#define ISREG0(r)	(r >= DWGREG0 && r <= DWGREG0_END)
23295584Sanholt#define DMAREG0(r)	(u8)((r - DWGREG0) >> 2)
23395584Sanholt#define DMAREG1(r)	(u8)(((r - DWGREG1) >> 2) | 0x80)
23495584Sanholt#define DMAREG(r)	(ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
23595584Sanholt
23695584Sanholt/* ================================================================
23795584Sanholt * Helper macross...
23895584Sanholt */
23995584Sanholt
24095584Sanholt#define MGA_EMIT_STATE( dev_priv, dirty )				\
24195584Sanholtdo {									\
24295584Sanholt	if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) {			\
243152909Sanholt		if ( dev_priv->chipset >= MGA_CARD_TYPE_G400 ) {	\
24495584Sanholt			mga_g400_emit_state( dev_priv );		\
24595584Sanholt		} else {						\
24695584Sanholt			mga_g200_emit_state( dev_priv );		\
24795584Sanholt		}							\
24895584Sanholt	}								\
24995584Sanholt} while (0)
25095584Sanholt
25195584Sanholt#define WRAP_TEST_WITH_RETURN( dev_priv )				\
25295584Sanholtdo {									\
25395584Sanholt	if ( test_bit( 0, &dev_priv->prim.wrapped ) ) {			\
25495584Sanholt		if ( mga_is_idle( dev_priv ) ) {			\
25595584Sanholt			mga_do_dma_wrap_end( dev_priv );		\
25695584Sanholt		} else if ( dev_priv->prim.space <			\
25795584Sanholt			    dev_priv->prim.high_mark ) {		\
25895584Sanholt			if ( MGA_DMA_DEBUG )				\
259182080Srnoland				DRM_INFO( "wrap...\n");		\
260182080Srnoland			return -EBUSY;			\
26195584Sanholt		}							\
26295584Sanholt	}								\
26395584Sanholt} while (0)
26495584Sanholt
26595584Sanholt#define WRAP_WAIT_WITH_RETURN( dev_priv )				\
26695584Sanholtdo {									\
26795584Sanholt	if ( test_bit( 0, &dev_priv->prim.wrapped ) ) {			\
268112015Sanholt		if ( mga_do_wait_for_idle( dev_priv ) < 0 ) {		\
26995584Sanholt			if ( MGA_DMA_DEBUG )				\
270182080Srnoland				DRM_INFO( "wrap...\n");		\
271182080Srnoland			return -EBUSY;			\
27295584Sanholt		}							\
27395584Sanholt		mga_do_dma_wrap_end( dev_priv );			\
27495584Sanholt	}								\
27595584Sanholt} while (0)
27695584Sanholt
27795584Sanholt/* ================================================================
27895584Sanholt * Primary DMA command stream
27995584Sanholt */
28095584Sanholt
28195584Sanholt#define MGA_VERBOSE	0
28295584Sanholt
28395584Sanholt#define DMA_LOCALS	unsigned int write; volatile u8 *prim;
28495584Sanholt
28595584Sanholt#define DMA_BLOCK_SIZE	(5 * sizeof(u32))
28695584Sanholt
28795584Sanholt#define BEGIN_DMA( n )							\
28895584Sanholtdo {									\
28995584Sanholt	if ( MGA_VERBOSE ) {						\
290182080Srnoland		DRM_INFO( "BEGIN_DMA( %d )\n", (n) );		\
291228572Sse		DRM_INFO( "   space=0x%x req=0x%zx\n",			\
29295584Sanholt			  dev_priv->prim.space, (n) * DMA_BLOCK_SIZE );	\
29395584Sanholt	}								\
29495584Sanholt	prim = dev_priv->prim.start;					\
29595584Sanholt	write = dev_priv->prim.tail;					\
29695584Sanholt} while (0)
29795584Sanholt
29895584Sanholt#define BEGIN_DMA_WRAP()						\
29995584Sanholtdo {									\
30095584Sanholt	if ( MGA_VERBOSE ) {						\
301182080Srnoland		DRM_INFO( "BEGIN_DMA()\n" );				\
30295584Sanholt		DRM_INFO( "   space=0x%x\n", dev_priv->prim.space );	\
30395584Sanholt	}								\
30495584Sanholt	prim = dev_priv->prim.start;					\
30595584Sanholt	write = dev_priv->prim.tail;					\
30695584Sanholt} while (0)
30795584Sanholt
30895584Sanholt#define ADVANCE_DMA()							\
30995584Sanholtdo {									\
31095584Sanholt	dev_priv->prim.tail = write;					\
31195584Sanholt	if ( MGA_VERBOSE ) {						\
31295584Sanholt		DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n",	\
31395584Sanholt			  write, dev_priv->prim.space );		\
31495584Sanholt	}								\
31595584Sanholt} while (0)
31695584Sanholt
31795584Sanholt#define FLUSH_DMA()							\
31895584Sanholtdo {									\
31995584Sanholt	if ( 0 ) {							\
320182080Srnoland		DRM_INFO( "\n" );					\
32195584Sanholt		DRM_INFO( "   tail=0x%06x head=0x%06lx\n",		\
32295584Sanholt			  dev_priv->prim.tail,				\
32395584Sanholt			  MGA_READ( MGA_PRIMADDRESS ) -			\
32495584Sanholt			  dev_priv->primary->offset );			\
32595584Sanholt	}								\
32695584Sanholt	if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) {		\
32795584Sanholt		if ( dev_priv->prim.space <				\
32895584Sanholt		     dev_priv->prim.high_mark ) {			\
32995584Sanholt			mga_do_dma_wrap_start( dev_priv );		\
33095584Sanholt		} else {						\
33195584Sanholt			mga_do_dma_flush( dev_priv );			\
33295584Sanholt		}							\
33395584Sanholt	}								\
33495584Sanholt} while (0)
33595584Sanholt
33695584Sanholt/* Never use this, always use DMA_BLOCK(...) for primary DMA output.
33795584Sanholt */
33895584Sanholt#define DMA_WRITE( offset, val )					\
33995584Sanholtdo {									\
34095584Sanholt	if ( MGA_VERBOSE ) {						\
341228572Sse		DRM_INFO( "   DMA_WRITE( 0x%08x ) at 0x%04zx\n",	\
34295584Sanholt			  (u32)(val), write + (offset) * sizeof(u32) );	\
34395584Sanholt	}								\
34495584Sanholt	*(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val;	\
34595584Sanholt} while (0)
34695584Sanholt
34795584Sanholt#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 )	\
34895584Sanholtdo {									\
34995584Sanholt	DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) |				\
35095584Sanholt		       (DMAREG( reg1 ) << 8) |				\
35195584Sanholt		       (DMAREG( reg2 ) << 16) |				\
35295584Sanholt		       (DMAREG( reg3 ) << 24)) );			\
35395584Sanholt	DMA_WRITE( 1, val0 );						\
35495584Sanholt	DMA_WRITE( 2, val1 );						\
35595584Sanholt	DMA_WRITE( 3, val2 );						\
35695584Sanholt	DMA_WRITE( 4, val3 );						\
35795584Sanholt	write += DMA_BLOCK_SIZE;					\
35895584Sanholt} while (0)
35995584Sanholt
36095584Sanholt/* Buffer aging via primary DMA stream head pointer.
36195584Sanholt */
36295584Sanholt
36395584Sanholt#define SET_AGE( age, h, w )						\
36495584Sanholtdo {									\
36595584Sanholt	(age)->head = h;						\
36695584Sanholt	(age)->wrap = w;						\
36795584Sanholt} while (0)
36895584Sanholt
36995584Sanholt#define TEST_AGE( age, h, w )		( (age)->wrap < w ||		\
37095584Sanholt					  ( (age)->wrap == w &&		\
37195584Sanholt					    (age)->head < h ) )
37295584Sanholt
37395584Sanholt#define AGE_BUFFER( buf_priv )						\
37495584Sanholtdo {									\
37595584Sanholt	drm_mga_freelist_t *entry = (buf_priv)->list_entry;		\
37695584Sanholt	if ( (buf_priv)->dispatched ) {					\
37795584Sanholt		entry->age.head = (dev_priv->prim.tail +		\
37895584Sanholt				   dev_priv->primary->offset);		\
37995584Sanholt		entry->age.wrap = dev_priv->sarea_priv->last_wrap;	\
38095584Sanholt	} else {							\
38195584Sanholt		entry->age.head = 0;					\
38295584Sanholt		entry->age.wrap = 0;					\
38395584Sanholt	}								\
38495584Sanholt} while (0)
38595584Sanholt
38695584Sanholt#define MGA_ENGINE_IDLE_MASK		(MGA_SOFTRAPEN |		\
38795584Sanholt					 MGA_DWGENGSTS |		\
38895584Sanholt					 MGA_ENDPRDMASTS)
38995584Sanholt#define MGA_DMA_IDLE_MASK		(MGA_SOFTRAPEN |		\
39095584Sanholt					 MGA_ENDPRDMASTS)
39195584Sanholt
39295584Sanholt#define MGA_DMA_DEBUG			0
39395584Sanholt
39495584Sanholt/* A reduced set of the mga registers.
39595584Sanholt */
39695584Sanholt#define MGA_CRTC_INDEX			0x1fd4
397112015Sanholt#define MGA_CRTC_DATA			0x1fd5
39895584Sanholt
399112015Sanholt/* CRTC11 */
400112015Sanholt#define MGA_VINTCLR			(1 << 4)
401112015Sanholt#define MGA_VINTEN			(1 << 5)
402112015Sanholt
403182080Srnoland#define MGA_ALPHACTRL			0x2c7c
404182080Srnoland#define MGA_AR0				0x1c60
405182080Srnoland#define MGA_AR1				0x1c64
406182080Srnoland#define MGA_AR2				0x1c68
407182080Srnoland#define MGA_AR3				0x1c6c
408182080Srnoland#define MGA_AR4				0x1c70
409182080Srnoland#define MGA_AR5				0x1c74
410182080Srnoland#define MGA_AR6				0x1c78
41195584Sanholt
41295584Sanholt#define MGA_CXBNDRY			0x1c80
413182080Srnoland#define MGA_CXLEFT			0x1ca0
41495584Sanholt#define MGA_CXRIGHT			0x1ca4
41595584Sanholt
416182080Srnoland#define MGA_DMAPAD			0x1c54
417182080Srnoland#define MGA_DSTORG			0x2cb8
418182080Srnoland#define MGA_DWGCTL			0x1c00
41995584Sanholt#	define MGA_OPCOD_MASK			(15 << 0)
42095584Sanholt#	define MGA_OPCOD_TRAP			(4 << 0)
42195584Sanholt#	define MGA_OPCOD_TEXTURE_TRAP		(6 << 0)
42295584Sanholt#	define MGA_OPCOD_BITBLT			(8 << 0)
42395584Sanholt#	define MGA_OPCOD_ILOAD			(9 << 0)
42495584Sanholt#	define MGA_ATYPE_MASK			(7 << 4)
42595584Sanholt#	define MGA_ATYPE_RPL			(0 << 4)
42695584Sanholt#	define MGA_ATYPE_RSTR			(1 << 4)
42795584Sanholt#	define MGA_ATYPE_ZI			(3 << 4)
42895584Sanholt#	define MGA_ATYPE_BLK			(4 << 4)
42995584Sanholt#	define MGA_ATYPE_I			(7 << 4)
43095584Sanholt#	define MGA_LINEAR			(1 << 7)
43195584Sanholt#	define MGA_ZMODE_MASK			(7 << 8)
43295584Sanholt#	define MGA_ZMODE_NOZCMP			(0 << 8)
43395584Sanholt#	define MGA_ZMODE_ZE			(2 << 8)
43495584Sanholt#	define MGA_ZMODE_ZNE			(3 << 8)
43595584Sanholt#	define MGA_ZMODE_ZLT			(4 << 8)
43695584Sanholt#	define MGA_ZMODE_ZLTE			(5 << 8)
43795584Sanholt#	define MGA_ZMODE_ZGT			(6 << 8)
43895584Sanholt#	define MGA_ZMODE_ZGTE			(7 << 8)
43995584Sanholt#	define MGA_SOLID			(1 << 11)
44095584Sanholt#	define MGA_ARZERO			(1 << 12)
44195584Sanholt#	define MGA_SGNZERO			(1 << 13)
44295584Sanholt#	define MGA_SHIFTZERO			(1 << 14)
44395584Sanholt#	define MGA_BOP_MASK			(15 << 16)
44495584Sanholt#	define MGA_BOP_ZERO			(0 << 16)
44595584Sanholt#	define MGA_BOP_DST			(10 << 16)
44695584Sanholt#	define MGA_BOP_SRC			(12 << 16)
44795584Sanholt#	define MGA_BOP_ONE			(15 << 16)
44895584Sanholt#	define MGA_TRANS_SHIFT			20
44995584Sanholt#	define MGA_TRANS_MASK			(15 << 20)
45095584Sanholt#	define MGA_BLTMOD_MASK			(15 << 25)
45195584Sanholt#	define MGA_BLTMOD_BMONOLEF		(0 << 25)
45295584Sanholt#	define MGA_BLTMOD_BMONOWF		(4 << 25)
45395584Sanholt#	define MGA_BLTMOD_PLAN			(1 << 25)
45495584Sanholt#	define MGA_BLTMOD_BFCOL			(2 << 25)
45595584Sanholt#	define MGA_BLTMOD_BU32BGR		(3 << 25)
45695584Sanholt#	define MGA_BLTMOD_BU32RGB		(7 << 25)
45795584Sanholt#	define MGA_BLTMOD_BU24BGR		(11 << 25)
45895584Sanholt#	define MGA_BLTMOD_BU24RGB		(15 << 25)
45995584Sanholt#	define MGA_PATTERN			(1 << 29)
46095584Sanholt#	define MGA_TRANSC			(1 << 30)
46195584Sanholt#	define MGA_CLIPDIS			(1 << 31)
46295584Sanholt#define MGA_DWGSYNC			0x2c4c
46395584Sanholt
464182080Srnoland#define MGA_FCOL			0x1c24
465182080Srnoland#define MGA_FIFOSTATUS			0x1e10
466182080Srnoland#define MGA_FOGCOL			0x1cf4
46795584Sanholt#define MGA_FXBNDRY			0x1c84
468182080Srnoland#define MGA_FXLEFT			0x1ca8
46995584Sanholt#define MGA_FXRIGHT			0x1cac
47095584Sanholt
471182080Srnoland#define MGA_ICLEAR			0x1e18
47295584Sanholt#	define MGA_SOFTRAPICLR			(1 << 0)
473112015Sanholt#	define MGA_VLINEICLR			(1 << 5)
474182080Srnoland#define MGA_IEN				0x1e1c
47595584Sanholt#	define MGA_SOFTRAPIEN			(1 << 0)
476112015Sanholt#	define MGA_VLINEIEN			(1 << 5)
47795584Sanholt
478182080Srnoland#define MGA_LEN				0x1c5c
47995584Sanholt
48095584Sanholt#define MGA_MACCESS			0x1c04
48195584Sanholt
482182080Srnoland#define MGA_PITCH			0x1c8c
483182080Srnoland#define MGA_PLNWT			0x1c1c
484182080Srnoland#define MGA_PRIMADDRESS			0x1e58
48595584Sanholt#	define MGA_DMA_GENERAL			(0 << 0)
48695584Sanholt#	define MGA_DMA_BLIT			(1 << 0)
48795584Sanholt#	define MGA_DMA_VECTOR			(2 << 0)
48895584Sanholt#	define MGA_DMA_VERTEX			(3 << 0)
48995584Sanholt#define MGA_PRIMEND			0x1e5c
49095584Sanholt#	define MGA_PRIMNOSTART			(1 << 0)
49195584Sanholt#	define MGA_PAGPXFER			(1 << 1)
49295584Sanholt#define MGA_PRIMPTR			0x1e50
49395584Sanholt#	define MGA_PRIMPTREN0			(1 << 0)
49495584Sanholt#	define MGA_PRIMPTREN1			(1 << 1)
49595584Sanholt
496182080Srnoland#define MGA_RST				0x1e40
49795584Sanholt#	define MGA_SOFTRESET			(1 << 0)
49895584Sanholt#	define MGA_SOFTEXTRST			(1 << 1)
49995584Sanholt
500182080Srnoland#define MGA_SECADDRESS			0x2c40
501182080Srnoland#define MGA_SECEND			0x2c44
502182080Srnoland#define MGA_SETUPADDRESS		0x2cd0
503182080Srnoland#define MGA_SETUPEND			0x2cd4
50495584Sanholt#define MGA_SGN				0x1c58
50595584Sanholt#define MGA_SOFTRAP			0x2c48
506182080Srnoland#define MGA_SRCORG			0x2cb4
50795584Sanholt#	define MGA_SRMMAP_MASK			(1 << 0)
50895584Sanholt#	define MGA_SRCMAP_FB			(0 << 0)
50995584Sanholt#	define MGA_SRCMAP_SYSMEM		(1 << 0)
51095584Sanholt#	define MGA_SRCACC_MASK			(1 << 1)
51195584Sanholt#	define MGA_SRCACC_PCI			(0 << 1)
51295584Sanholt#	define MGA_SRCACC_AGP			(1 << 1)
513182080Srnoland#define MGA_STATUS			0x1e14
51495584Sanholt#	define MGA_SOFTRAPEN			(1 << 0)
515112015Sanholt#	define MGA_VSYNCPEN			(1 << 4)
516112015Sanholt#	define MGA_VLINEPEN			(1 << 5)
51795584Sanholt#	define MGA_DWGENGSTS			(1 << 16)
51895584Sanholt#	define MGA_ENDPRDMASTS			(1 << 17)
51995584Sanholt#define MGA_STENCIL			0x2cc8
520182080Srnoland#define MGA_STENCILCTL			0x2ccc
52195584Sanholt
522182080Srnoland#define MGA_TDUALSTAGE0			0x2cf8
523182080Srnoland#define MGA_TDUALSTAGE1			0x2cfc
524182080Srnoland#define MGA_TEXBORDERCOL		0x2c5c
525182080Srnoland#define MGA_TEXCTL			0x2c30
52695584Sanholt#define MGA_TEXCTL2			0x2c3c
52795584Sanholt#	define MGA_DUALTEX			(1 << 7)
52895584Sanholt#	define MGA_G400_TC2_MAGIC		(1 << 15)
52995584Sanholt#	define MGA_MAP1_ENABLE			(1 << 31)
530182080Srnoland#define MGA_TEXFILTER			0x2c58
531182080Srnoland#define MGA_TEXHEIGHT			0x2c2c
532182080Srnoland#define MGA_TEXORG			0x2c24
53395584Sanholt#	define MGA_TEXORGMAP_MASK		(1 << 0)
53495584Sanholt#	define MGA_TEXORGMAP_FB			(0 << 0)
53595584Sanholt#	define MGA_TEXORGMAP_SYSMEM		(1 << 0)
53695584Sanholt#	define MGA_TEXORGACC_MASK		(1 << 1)
53795584Sanholt#	define MGA_TEXORGACC_PCI		(0 << 1)
53895584Sanholt#	define MGA_TEXORGACC_AGP		(1 << 1)
53995584Sanholt#define MGA_TEXORG1			0x2ca4
54095584Sanholt#define MGA_TEXORG2			0x2ca8
54195584Sanholt#define MGA_TEXORG3			0x2cac
54295584Sanholt#define MGA_TEXORG4			0x2cb0
543182080Srnoland#define MGA_TEXTRANS			0x2c34
544182080Srnoland#define MGA_TEXTRANSHIGH		0x2c38
545182080Srnoland#define MGA_TEXWIDTH			0x2c28
54695584Sanholt
547182080Srnoland#define MGA_WACCEPTSEQ			0x1dd4
548182080Srnoland#define MGA_WCODEADDR			0x1e6c
549182080Srnoland#define MGA_WFLAG			0x1dc4
550182080Srnoland#define MGA_WFLAG1			0x1de0
55195584Sanholt#define MGA_WFLAGNB			0x1e64
552182080Srnoland#define MGA_WFLAGNB1			0x1e08
55395584Sanholt#define MGA_WGETMSB			0x1dc8
554182080Srnoland#define MGA_WIADDR			0x1dc0
55595584Sanholt#define MGA_WIADDR2			0x1dd8
55695584Sanholt#	define MGA_WMODE_SUSPEND		(0 << 0)
55795584Sanholt#	define MGA_WMODE_RESUME			(1 << 0)
55895584Sanholt#	define MGA_WMODE_JUMP			(2 << 0)
55995584Sanholt#	define MGA_WMODE_START			(3 << 0)
56095584Sanholt#	define MGA_WAGP_ENABLE			(1 << 2)
561182080Srnoland#define MGA_WMISC			0x1e70
56295584Sanholt#	define MGA_WUCODECACHE_ENABLE		(1 << 0)
56395584Sanholt#	define MGA_WMASTER_ENABLE		(1 << 1)
56495584Sanholt#	define MGA_WCACHEFLUSH_ENABLE		(1 << 3)
56595584Sanholt#define MGA_WVRTXSZ			0x1dcc
56695584Sanholt
567182080Srnoland#define MGA_YBOT			0x1c9c
568182080Srnoland#define MGA_YDST			0x1c90
56995584Sanholt#define MGA_YDSTLEN			0x1c88
57095584Sanholt#define MGA_YDSTORG			0x1c94
571182080Srnoland#define MGA_YTOP			0x1c98
57295584Sanholt
573182080Srnoland#define MGA_ZORG			0x1c0c
57495584Sanholt
57595584Sanholt/* This finishes the current batch of commands
57695584Sanholt */
577182080Srnoland#define MGA_EXEC			0x0100
57895584Sanholt
579152909Sanholt/* AGP PLL encoding (for G200 only).
580152909Sanholt */
581182080Srnoland#define MGA_AGP_PLL			0x1e4c
582152909Sanholt#	define MGA_AGP2XPLL_DISABLE		(0 << 0)
583152909Sanholt#	define MGA_AGP2XPLL_ENABLE		(1 << 0)
584152909Sanholt
58595584Sanholt/* Warp registers
58695584Sanholt */
58795584Sanholt#define MGA_WR0				0x2d00
58895584Sanholt#define MGA_WR1				0x2d04
58995584Sanholt#define MGA_WR2				0x2d08
59095584Sanholt#define MGA_WR3				0x2d0c
59195584Sanholt#define MGA_WR4				0x2d10
59295584Sanholt#define MGA_WR5				0x2d14
59395584Sanholt#define MGA_WR6				0x2d18
59495584Sanholt#define MGA_WR7				0x2d1c
59595584Sanholt#define MGA_WR8				0x2d20
59695584Sanholt#define MGA_WR9				0x2d24
59795584Sanholt#define MGA_WR10			0x2d28
59895584Sanholt#define MGA_WR11			0x2d2c
59995584Sanholt#define MGA_WR12			0x2d30
60095584Sanholt#define MGA_WR13			0x2d34
60195584Sanholt#define MGA_WR14			0x2d38
60295584Sanholt#define MGA_WR15			0x2d3c
60395584Sanholt#define MGA_WR16			0x2d40
60495584Sanholt#define MGA_WR17			0x2d44
60595584Sanholt#define MGA_WR18			0x2d48
60695584Sanholt#define MGA_WR19			0x2d4c
60795584Sanholt#define MGA_WR20			0x2d50
60895584Sanholt#define MGA_WR21			0x2d54
60995584Sanholt#define MGA_WR22			0x2d58
61095584Sanholt#define MGA_WR23			0x2d5c
61195584Sanholt#define MGA_WR24			0x2d60
61295584Sanholt#define MGA_WR25			0x2d64
61395584Sanholt#define MGA_WR26			0x2d68
61495584Sanholt#define MGA_WR27			0x2d6c
61595584Sanholt#define MGA_WR28			0x2d70
61695584Sanholt#define MGA_WR29			0x2d74
61795584Sanholt#define MGA_WR30			0x2d78
61895584Sanholt#define MGA_WR31			0x2d7c
61995584Sanholt#define MGA_WR32			0x2d80
62095584Sanholt#define MGA_WR33			0x2d84
62195584Sanholt#define MGA_WR34			0x2d88
62295584Sanholt#define MGA_WR35			0x2d8c
62395584Sanholt#define MGA_WR36			0x2d90
62495584Sanholt#define MGA_WR37			0x2d94
62595584Sanholt#define MGA_WR38			0x2d98
62695584Sanholt#define MGA_WR39			0x2d9c
62795584Sanholt#define MGA_WR40			0x2da0
62895584Sanholt#define MGA_WR41			0x2da4
62995584Sanholt#define MGA_WR42			0x2da8
63095584Sanholt#define MGA_WR43			0x2dac
63195584Sanholt#define MGA_WR44			0x2db0
63295584Sanholt#define MGA_WR45			0x2db4
63395584Sanholt#define MGA_WR46			0x2db8
63495584Sanholt#define MGA_WR47			0x2dbc
63595584Sanholt#define MGA_WR48			0x2dc0
63695584Sanholt#define MGA_WR49			0x2dc4
63795584Sanholt#define MGA_WR50			0x2dc8
63895584Sanholt#define MGA_WR51			0x2dcc
63995584Sanholt#define MGA_WR52			0x2dd0
64095584Sanholt#define MGA_WR53			0x2dd4
64195584Sanholt#define MGA_WR54			0x2dd8
64295584Sanholt#define MGA_WR55			0x2ddc
64395584Sanholt#define MGA_WR56			0x2de0
64495584Sanholt#define MGA_WR57			0x2de4
64595584Sanholt#define MGA_WR58			0x2de8
64695584Sanholt#define MGA_WR59			0x2dec
64795584Sanholt#define MGA_WR60			0x2df0
64895584Sanholt#define MGA_WR61			0x2df4
64995584Sanholt#define MGA_WR62			0x2df8
65095584Sanholt#define MGA_WR63			0x2dfc
65195584Sanholt#	define MGA_G400_WR_MAGIC		(1 << 6)
65295584Sanholt#	define MGA_G400_WR56_MAGIC		0x46480000	/* 12800.0f */
65395584Sanholt
65495584Sanholt#define MGA_ILOAD_ALIGN		64
65595584Sanholt#define MGA_ILOAD_MASK		(MGA_ILOAD_ALIGN - 1)
65695584Sanholt
65795584Sanholt#define MGA_DWGCTL_FLUSH	(MGA_OPCOD_TEXTURE_TRAP |		\
65895584Sanholt				 MGA_ATYPE_I |				\
65995584Sanholt				 MGA_ZMODE_NOZCMP |			\
66095584Sanholt				 MGA_ARZERO |				\
66195584Sanholt				 MGA_SGNZERO |				\
66295584Sanholt				 MGA_BOP_SRC |				\
66395584Sanholt				 (15 << MGA_TRANS_SHIFT))
66495584Sanholt
66595584Sanholt#define MGA_DWGCTL_CLEAR	(MGA_OPCOD_TRAP |			\
66695584Sanholt				 MGA_ZMODE_NOZCMP |			\
66795584Sanholt				 MGA_SOLID |				\
66895584Sanholt				 MGA_ARZERO |				\
66995584Sanholt				 MGA_SGNZERO |				\
67095584Sanholt				 MGA_SHIFTZERO |			\
67195584Sanholt				 MGA_BOP_SRC |				\
67295584Sanholt				 (0 << MGA_TRANS_SHIFT) |		\
67395584Sanholt				 MGA_BLTMOD_BMONOLEF |			\
67495584Sanholt				 MGA_TRANSC |				\
67595584Sanholt				 MGA_CLIPDIS)
67695584Sanholt
67795584Sanholt#define MGA_DWGCTL_COPY		(MGA_OPCOD_BITBLT |			\
67895584Sanholt				 MGA_ATYPE_RPL |			\
67995584Sanholt				 MGA_SGNZERO |				\
68095584Sanholt				 MGA_SHIFTZERO |			\
68195584Sanholt				 MGA_BOP_SRC |				\
68295584Sanholt				 (0 << MGA_TRANS_SHIFT) |		\
68395584Sanholt				 MGA_BLTMOD_BFCOL |			\
68495584Sanholt				 MGA_CLIPDIS)
68595584Sanholt
68695584Sanholt/* Simple idle test.
68795584Sanholt */
688145132Sanholtstatic __inline__ int mga_is_idle(drm_mga_private_t * dev_priv)
68995584Sanholt{
690145132Sanholt	u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
691145132Sanholt	return (status == MGA_ENDPRDMASTS);
69295584Sanholt}
69395584Sanholt
69495584Sanholt#endif
695