1/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*- 2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com 3 * 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD$"); 33 34#ifndef __MGA_DRV_H__ 35#define __MGA_DRV_H__ 36 37/* General customization: 38 */ 39 40#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." 41 42#define DRIVER_NAME "mga" 43#define DRIVER_DESC "Matrox G200/G400" 44#define DRIVER_DATE "20060319" 45 46#define DRIVER_MAJOR 3 47#define DRIVER_MINOR 2 48#define DRIVER_PATCHLEVEL 2 49 50typedef struct drm_mga_primary_buffer { 51 u8 *start; 52 u8 *end; 53 int size; 54 55 u32 tail; 56 int space; 57 volatile long wrapped; 58 59 volatile u32 *status; 60 61 u32 last_flush; 62 u32 last_wrap; 63 64 u32 high_mark; 65} drm_mga_primary_buffer_t; 66 67typedef struct drm_mga_freelist { 68 struct drm_mga_freelist *next; 69 struct drm_mga_freelist *prev; 70 drm_mga_age_t age; 71 struct drm_buf *buf; 72} drm_mga_freelist_t; 73 74typedef struct { 75 drm_mga_freelist_t *list_entry; 76 int discard; 77 int dispatched; 78} drm_mga_buf_priv_t; 79 80typedef struct drm_mga_private { 81 drm_mga_primary_buffer_t prim; 82 drm_mga_sarea_t *sarea_priv; 83 84 drm_mga_freelist_t *head; 85 drm_mga_freelist_t *tail; 86 87 unsigned int warp_pipe; 88 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; 89 90 int chipset; 91 int usec_timeout; 92 93 /** 94 * If set, the new DMA initialization sequence was used. This is 95 * primarilly used to select how the driver should uninitialized its 96 * internal DMA structures. 97 */ 98 int used_new_dma_init; 99 100 /** 101 * If AGP memory is used for DMA buffers, this will be the value 102 * \c MGA_PAGPXFER. Otherwise, it will be zero (for a PCI transfer). 103 */ 104 u32 dma_access; 105 106 /** 107 * If AGP memory is used for DMA buffers, this will be the value 108 * \c MGA_WAGP_ENABLE. Otherwise, it will be zero (for a PCI 109 * transfer). 110 */ 111 u32 wagp_enable; 112 113 /** 114 * \name MMIO region parameters. 115 * 116 * \sa drm_mga_private_t::mmio 117 */ 118 /*@{*/ 119 u32 mmio_base; /**< Bus address of base of MMIO. */ 120 u32 mmio_size; /**< Size of the MMIO region. */ 121 /*@}*/ 122 123 u32 clear_cmd; 124 u32 maccess; 125 126 atomic_t vbl_received; /**< Number of vblanks received. */ 127 wait_queue_head_t fence_queue; 128 atomic_t last_fence_retired; 129 u32 next_fence_to_post; 130 131 unsigned int fb_cpp; 132 unsigned int front_offset; 133 unsigned int front_pitch; 134 unsigned int back_offset; 135 unsigned int back_pitch; 136 137 unsigned int depth_cpp; 138 unsigned int depth_offset; 139 unsigned int depth_pitch; 140 141 unsigned int texture_offset; 142 unsigned int texture_size; 143 144 drm_local_map_t *sarea; 145 drm_local_map_t *mmio; 146 drm_local_map_t *status; 147 drm_local_map_t *warp; 148 drm_local_map_t *primary; 149 drm_local_map_t *agp_textures; 150 151 unsigned long agp_handle; 152 unsigned int agp_size; 153} drm_mga_private_t; 154 155extern struct drm_ioctl_desc mga_ioctls[]; 156extern int mga_max_ioctl; 157 158 /* mga_dma.c */ 159extern int mga_dma_bootstrap(struct drm_device *dev, void *data, 160 struct drm_file *file_priv); 161extern int mga_dma_init(struct drm_device *dev, void *data, 162 struct drm_file *file_priv); 163extern int mga_dma_flush(struct drm_device *dev, void *data, 164 struct drm_file *file_priv); 165extern int mga_dma_reset(struct drm_device *dev, void *data, 166 struct drm_file *file_priv); 167extern int mga_dma_buffers(struct drm_device *dev, void *data, 168 struct drm_file *file_priv); 169extern int mga_driver_load(struct drm_device *dev, unsigned long flags); 170extern int mga_driver_unload(struct drm_device * dev); 171extern void mga_driver_lastclose(struct drm_device * dev); 172extern int mga_driver_dma_quiescent(struct drm_device * dev); 173 174extern int mga_do_wait_for_idle(drm_mga_private_t * dev_priv); 175 176extern void mga_do_dma_flush(drm_mga_private_t * dev_priv); 177extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv); 178extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); 179 180extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf); 181 182 /* mga_warp.c */ 183extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv); 184extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv); 185extern int mga_warp_init(drm_mga_private_t * dev_priv); 186 187 /* mga_irq.c */ 188extern int mga_enable_vblank(struct drm_device *dev, int crtc); 189extern void mga_disable_vblank(struct drm_device *dev, int crtc); 190extern u32 mga_get_vblank_counter(struct drm_device *dev, int crtc); 191extern int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence); 192extern int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence); 193extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS); 194extern void mga_driver_irq_preinstall(struct drm_device * dev); 195extern int mga_driver_irq_postinstall(struct drm_device * dev); 196extern void mga_driver_irq_uninstall(struct drm_device * dev); 197extern long mga_compat_ioctl(struct file *filp, unsigned int cmd, 198 unsigned long arg); 199 200#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() 201 202#if defined(__linux__) && defined(__alpha__) 203#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) 204#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) 205 206#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) 207#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) 208 209#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) 210#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) 211#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) 212#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) 213 214static inline u32 _MGA_READ(u32 * addr) 215{ 216 DRM_MEMORYBARRIER(); 217 return *(volatile u32 *)addr; 218} 219#else 220#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) 221#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) 222#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) 223#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) 224#endif 225 226#define DWGREG0 0x1c00 227#define DWGREG0_END 0x1dff 228#define DWGREG1 0x2c00 229#define DWGREG1_END 0x2dff 230 231#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) 232#define DMAREG0(r) (u8)((r - DWGREG0) >> 2) 233#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) 234#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) 235 236/* ================================================================ 237 * Helper macross... 238 */ 239 240#define MGA_EMIT_STATE( dev_priv, dirty ) \ 241do { \ 242 if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \ 243 if ( dev_priv->chipset >= MGA_CARD_TYPE_G400 ) { \ 244 mga_g400_emit_state( dev_priv ); \ 245 } else { \ 246 mga_g200_emit_state( dev_priv ); \ 247 } \ 248 } \ 249} while (0) 250 251#define WRAP_TEST_WITH_RETURN( dev_priv ) \ 252do { \ 253 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 254 if ( mga_is_idle( dev_priv ) ) { \ 255 mga_do_dma_wrap_end( dev_priv ); \ 256 } else if ( dev_priv->prim.space < \ 257 dev_priv->prim.high_mark ) { \ 258 if ( MGA_DMA_DEBUG ) \ 259 DRM_INFO( "wrap...\n"); \ 260 return -EBUSY; \ 261 } \ 262 } \ 263} while (0) 264 265#define WRAP_WAIT_WITH_RETURN( dev_priv ) \ 266do { \ 267 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 268 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \ 269 if ( MGA_DMA_DEBUG ) \ 270 DRM_INFO( "wrap...\n"); \ 271 return -EBUSY; \ 272 } \ 273 mga_do_dma_wrap_end( dev_priv ); \ 274 } \ 275} while (0) 276 277/* ================================================================ 278 * Primary DMA command stream 279 */ 280 281#define MGA_VERBOSE 0 282 283#define DMA_LOCALS unsigned int write; volatile u8 *prim; 284 285#define DMA_BLOCK_SIZE (5 * sizeof(u32)) 286 287#define BEGIN_DMA( n ) \ 288do { \ 289 if ( MGA_VERBOSE ) { \ 290 DRM_INFO( "BEGIN_DMA( %d )\n", (n) ); \ 291 DRM_INFO( " space=0x%x req=0x%zx\n", \ 292 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ 293 } \ 294 prim = dev_priv->prim.start; \ 295 write = dev_priv->prim.tail; \ 296} while (0) 297 298#define BEGIN_DMA_WRAP() \ 299do { \ 300 if ( MGA_VERBOSE ) { \ 301 DRM_INFO( "BEGIN_DMA()\n" ); \ 302 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \ 303 } \ 304 prim = dev_priv->prim.start; \ 305 write = dev_priv->prim.tail; \ 306} while (0) 307 308#define ADVANCE_DMA() \ 309do { \ 310 dev_priv->prim.tail = write; \ 311 if ( MGA_VERBOSE ) { \ 312 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ 313 write, dev_priv->prim.space ); \ 314 } \ 315} while (0) 316 317#define FLUSH_DMA() \ 318do { \ 319 if ( 0 ) { \ 320 DRM_INFO( "\n" ); \ 321 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \ 322 dev_priv->prim.tail, \ 323 MGA_READ( MGA_PRIMADDRESS ) - \ 324 dev_priv->primary->offset ); \ 325 } \ 326 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 327 if ( dev_priv->prim.space < \ 328 dev_priv->prim.high_mark ) { \ 329 mga_do_dma_wrap_start( dev_priv ); \ 330 } else { \ 331 mga_do_dma_flush( dev_priv ); \ 332 } \ 333 } \ 334} while (0) 335 336/* Never use this, always use DMA_BLOCK(...) for primary DMA output. 337 */ 338#define DMA_WRITE( offset, val ) \ 339do { \ 340 if ( MGA_VERBOSE ) { \ 341 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04zx\n", \ 342 (u32)(val), write + (offset) * sizeof(u32) ); \ 343 } \ 344 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ 345} while (0) 346 347#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ 348do { \ 349 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \ 350 (DMAREG( reg1 ) << 8) | \ 351 (DMAREG( reg2 ) << 16) | \ 352 (DMAREG( reg3 ) << 24)) ); \ 353 DMA_WRITE( 1, val0 ); \ 354 DMA_WRITE( 2, val1 ); \ 355 DMA_WRITE( 3, val2 ); \ 356 DMA_WRITE( 4, val3 ); \ 357 write += DMA_BLOCK_SIZE; \ 358} while (0) 359 360/* Buffer aging via primary DMA stream head pointer. 361 */ 362 363#define SET_AGE( age, h, w ) \ 364do { \ 365 (age)->head = h; \ 366 (age)->wrap = w; \ 367} while (0) 368 369#define TEST_AGE( age, h, w ) ( (age)->wrap < w || \ 370 ( (age)->wrap == w && \ 371 (age)->head < h ) ) 372 373#define AGE_BUFFER( buf_priv ) \ 374do { \ 375 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ 376 if ( (buf_priv)->dispatched ) { \ 377 entry->age.head = (dev_priv->prim.tail + \ 378 dev_priv->primary->offset); \ 379 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ 380 } else { \ 381 entry->age.head = 0; \ 382 entry->age.wrap = 0; \ 383 } \ 384} while (0) 385 386#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ 387 MGA_DWGENGSTS | \ 388 MGA_ENDPRDMASTS) 389#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \ 390 MGA_ENDPRDMASTS) 391 392#define MGA_DMA_DEBUG 0 393 394/* A reduced set of the mga registers. 395 */ 396#define MGA_CRTC_INDEX 0x1fd4 397#define MGA_CRTC_DATA 0x1fd5 398 399/* CRTC11 */ 400#define MGA_VINTCLR (1 << 4) 401#define MGA_VINTEN (1 << 5) 402 403#define MGA_ALPHACTRL 0x2c7c 404#define MGA_AR0 0x1c60 405#define MGA_AR1 0x1c64 406#define MGA_AR2 0x1c68 407#define MGA_AR3 0x1c6c 408#define MGA_AR4 0x1c70 409#define MGA_AR5 0x1c74 410#define MGA_AR6 0x1c78 411 412#define MGA_CXBNDRY 0x1c80 413#define MGA_CXLEFT 0x1ca0 414#define MGA_CXRIGHT 0x1ca4 415 416#define MGA_DMAPAD 0x1c54 417#define MGA_DSTORG 0x2cb8 418#define MGA_DWGCTL 0x1c00 419# define MGA_OPCOD_MASK (15 << 0) 420# define MGA_OPCOD_TRAP (4 << 0) 421# define MGA_OPCOD_TEXTURE_TRAP (6 << 0) 422# define MGA_OPCOD_BITBLT (8 << 0) 423# define MGA_OPCOD_ILOAD (9 << 0) 424# define MGA_ATYPE_MASK (7 << 4) 425# define MGA_ATYPE_RPL (0 << 4) 426# define MGA_ATYPE_RSTR (1 << 4) 427# define MGA_ATYPE_ZI (3 << 4) 428# define MGA_ATYPE_BLK (4 << 4) 429# define MGA_ATYPE_I (7 << 4) 430# define MGA_LINEAR (1 << 7) 431# define MGA_ZMODE_MASK (7 << 8) 432# define MGA_ZMODE_NOZCMP (0 << 8) 433# define MGA_ZMODE_ZE (2 << 8) 434# define MGA_ZMODE_ZNE (3 << 8) 435# define MGA_ZMODE_ZLT (4 << 8) 436# define MGA_ZMODE_ZLTE (5 << 8) 437# define MGA_ZMODE_ZGT (6 << 8) 438# define MGA_ZMODE_ZGTE (7 << 8) 439# define MGA_SOLID (1 << 11) 440# define MGA_ARZERO (1 << 12) 441# define MGA_SGNZERO (1 << 13) 442# define MGA_SHIFTZERO (1 << 14) 443# define MGA_BOP_MASK (15 << 16) 444# define MGA_BOP_ZERO (0 << 16) 445# define MGA_BOP_DST (10 << 16) 446# define MGA_BOP_SRC (12 << 16) 447# define MGA_BOP_ONE (15 << 16) 448# define MGA_TRANS_SHIFT 20 449# define MGA_TRANS_MASK (15 << 20) 450# define MGA_BLTMOD_MASK (15 << 25) 451# define MGA_BLTMOD_BMONOLEF (0 << 25) 452# define MGA_BLTMOD_BMONOWF (4 << 25) 453# define MGA_BLTMOD_PLAN (1 << 25) 454# define MGA_BLTMOD_BFCOL (2 << 25) 455# define MGA_BLTMOD_BU32BGR (3 << 25) 456# define MGA_BLTMOD_BU32RGB (7 << 25) 457# define MGA_BLTMOD_BU24BGR (11 << 25) 458# define MGA_BLTMOD_BU24RGB (15 << 25) 459# define MGA_PATTERN (1 << 29) 460# define MGA_TRANSC (1 << 30) 461# define MGA_CLIPDIS (1 << 31) 462#define MGA_DWGSYNC 0x2c4c 463 464#define MGA_FCOL 0x1c24 465#define MGA_FIFOSTATUS 0x1e10 466#define MGA_FOGCOL 0x1cf4 467#define MGA_FXBNDRY 0x1c84 468#define MGA_FXLEFT 0x1ca8 469#define MGA_FXRIGHT 0x1cac 470 471#define MGA_ICLEAR 0x1e18 472# define MGA_SOFTRAPICLR (1 << 0) 473# define MGA_VLINEICLR (1 << 5) 474#define MGA_IEN 0x1e1c 475# define MGA_SOFTRAPIEN (1 << 0) 476# define MGA_VLINEIEN (1 << 5) 477 478#define MGA_LEN 0x1c5c 479 480#define MGA_MACCESS 0x1c04 481 482#define MGA_PITCH 0x1c8c 483#define MGA_PLNWT 0x1c1c 484#define MGA_PRIMADDRESS 0x1e58 485# define MGA_DMA_GENERAL (0 << 0) 486# define MGA_DMA_BLIT (1 << 0) 487# define MGA_DMA_VECTOR (2 << 0) 488# define MGA_DMA_VERTEX (3 << 0) 489#define MGA_PRIMEND 0x1e5c 490# define MGA_PRIMNOSTART (1 << 0) 491# define MGA_PAGPXFER (1 << 1) 492#define MGA_PRIMPTR 0x1e50 493# define MGA_PRIMPTREN0 (1 << 0) 494# define MGA_PRIMPTREN1 (1 << 1) 495 496#define MGA_RST 0x1e40 497# define MGA_SOFTRESET (1 << 0) 498# define MGA_SOFTEXTRST (1 << 1) 499 500#define MGA_SECADDRESS 0x2c40 501#define MGA_SECEND 0x2c44 502#define MGA_SETUPADDRESS 0x2cd0 503#define MGA_SETUPEND 0x2cd4 504#define MGA_SGN 0x1c58 505#define MGA_SOFTRAP 0x2c48 506#define MGA_SRCORG 0x2cb4 507# define MGA_SRMMAP_MASK (1 << 0) 508# define MGA_SRCMAP_FB (0 << 0) 509# define MGA_SRCMAP_SYSMEM (1 << 0) 510# define MGA_SRCACC_MASK (1 << 1) 511# define MGA_SRCACC_PCI (0 << 1) 512# define MGA_SRCACC_AGP (1 << 1) 513#define MGA_STATUS 0x1e14 514# define MGA_SOFTRAPEN (1 << 0) 515# define MGA_VSYNCPEN (1 << 4) 516# define MGA_VLINEPEN (1 << 5) 517# define MGA_DWGENGSTS (1 << 16) 518# define MGA_ENDPRDMASTS (1 << 17) 519#define MGA_STENCIL 0x2cc8 520#define MGA_STENCILCTL 0x2ccc 521 522#define MGA_TDUALSTAGE0 0x2cf8 523#define MGA_TDUALSTAGE1 0x2cfc 524#define MGA_TEXBORDERCOL 0x2c5c 525#define MGA_TEXCTL 0x2c30 526#define MGA_TEXCTL2 0x2c3c 527# define MGA_DUALTEX (1 << 7) 528# define MGA_G400_TC2_MAGIC (1 << 15) 529# define MGA_MAP1_ENABLE (1 << 31) 530#define MGA_TEXFILTER 0x2c58 531#define MGA_TEXHEIGHT 0x2c2c 532#define MGA_TEXORG 0x2c24 533# define MGA_TEXORGMAP_MASK (1 << 0) 534# define MGA_TEXORGMAP_FB (0 << 0) 535# define MGA_TEXORGMAP_SYSMEM (1 << 0) 536# define MGA_TEXORGACC_MASK (1 << 1) 537# define MGA_TEXORGACC_PCI (0 << 1) 538# define MGA_TEXORGACC_AGP (1 << 1) 539#define MGA_TEXORG1 0x2ca4 540#define MGA_TEXORG2 0x2ca8 541#define MGA_TEXORG3 0x2cac 542#define MGA_TEXORG4 0x2cb0 543#define MGA_TEXTRANS 0x2c34 544#define MGA_TEXTRANSHIGH 0x2c38 545#define MGA_TEXWIDTH 0x2c28 546 547#define MGA_WACCEPTSEQ 0x1dd4 548#define MGA_WCODEADDR 0x1e6c 549#define MGA_WFLAG 0x1dc4 550#define MGA_WFLAG1 0x1de0 551#define MGA_WFLAGNB 0x1e64 552#define MGA_WFLAGNB1 0x1e08 553#define MGA_WGETMSB 0x1dc8 554#define MGA_WIADDR 0x1dc0 555#define MGA_WIADDR2 0x1dd8 556# define MGA_WMODE_SUSPEND (0 << 0) 557# define MGA_WMODE_RESUME (1 << 0) 558# define MGA_WMODE_JUMP (2 << 0) 559# define MGA_WMODE_START (3 << 0) 560# define MGA_WAGP_ENABLE (1 << 2) 561#define MGA_WMISC 0x1e70 562# define MGA_WUCODECACHE_ENABLE (1 << 0) 563# define MGA_WMASTER_ENABLE (1 << 1) 564# define MGA_WCACHEFLUSH_ENABLE (1 << 3) 565#define MGA_WVRTXSZ 0x1dcc 566 567#define MGA_YBOT 0x1c9c 568#define MGA_YDST 0x1c90 569#define MGA_YDSTLEN 0x1c88 570#define MGA_YDSTORG 0x1c94 571#define MGA_YTOP 0x1c98 572 573#define MGA_ZORG 0x1c0c 574 575/* This finishes the current batch of commands 576 */ 577#define MGA_EXEC 0x0100 578 579/* AGP PLL encoding (for G200 only). 580 */ 581#define MGA_AGP_PLL 0x1e4c 582# define MGA_AGP2XPLL_DISABLE (0 << 0) 583# define MGA_AGP2XPLL_ENABLE (1 << 0) 584 585/* Warp registers 586 */ 587#define MGA_WR0 0x2d00 588#define MGA_WR1 0x2d04 589#define MGA_WR2 0x2d08 590#define MGA_WR3 0x2d0c 591#define MGA_WR4 0x2d10 592#define MGA_WR5 0x2d14 593#define MGA_WR6 0x2d18 594#define MGA_WR7 0x2d1c 595#define MGA_WR8 0x2d20 596#define MGA_WR9 0x2d24 597#define MGA_WR10 0x2d28 598#define MGA_WR11 0x2d2c 599#define MGA_WR12 0x2d30 600#define MGA_WR13 0x2d34 601#define MGA_WR14 0x2d38 602#define MGA_WR15 0x2d3c 603#define MGA_WR16 0x2d40 604#define MGA_WR17 0x2d44 605#define MGA_WR18 0x2d48 606#define MGA_WR19 0x2d4c 607#define MGA_WR20 0x2d50 608#define MGA_WR21 0x2d54 609#define MGA_WR22 0x2d58 610#define MGA_WR23 0x2d5c 611#define MGA_WR24 0x2d60 612#define MGA_WR25 0x2d64 613#define MGA_WR26 0x2d68 614#define MGA_WR27 0x2d6c 615#define MGA_WR28 0x2d70 616#define MGA_WR29 0x2d74 617#define MGA_WR30 0x2d78 618#define MGA_WR31 0x2d7c 619#define MGA_WR32 0x2d80 620#define MGA_WR33 0x2d84 621#define MGA_WR34 0x2d88 622#define MGA_WR35 0x2d8c 623#define MGA_WR36 0x2d90 624#define MGA_WR37 0x2d94 625#define MGA_WR38 0x2d98 626#define MGA_WR39 0x2d9c 627#define MGA_WR40 0x2da0 628#define MGA_WR41 0x2da4 629#define MGA_WR42 0x2da8 630#define MGA_WR43 0x2dac 631#define MGA_WR44 0x2db0 632#define MGA_WR45 0x2db4 633#define MGA_WR46 0x2db8 634#define MGA_WR47 0x2dbc 635#define MGA_WR48 0x2dc0 636#define MGA_WR49 0x2dc4 637#define MGA_WR50 0x2dc8 638#define MGA_WR51 0x2dcc 639#define MGA_WR52 0x2dd0 640#define MGA_WR53 0x2dd4 641#define MGA_WR54 0x2dd8 642#define MGA_WR55 0x2ddc 643#define MGA_WR56 0x2de0 644#define MGA_WR57 0x2de4 645#define MGA_WR58 0x2de8 646#define MGA_WR59 0x2dec 647#define MGA_WR60 0x2df0 648#define MGA_WR61 0x2df4 649#define MGA_WR62 0x2df8 650#define MGA_WR63 0x2dfc 651# define MGA_G400_WR_MAGIC (1 << 6) 652# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ 653 654#define MGA_ILOAD_ALIGN 64 655#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) 656 657#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \ 658 MGA_ATYPE_I | \ 659 MGA_ZMODE_NOZCMP | \ 660 MGA_ARZERO | \ 661 MGA_SGNZERO | \ 662 MGA_BOP_SRC | \ 663 (15 << MGA_TRANS_SHIFT)) 664 665#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \ 666 MGA_ZMODE_NOZCMP | \ 667 MGA_SOLID | \ 668 MGA_ARZERO | \ 669 MGA_SGNZERO | \ 670 MGA_SHIFTZERO | \ 671 MGA_BOP_SRC | \ 672 (0 << MGA_TRANS_SHIFT) | \ 673 MGA_BLTMOD_BMONOLEF | \ 674 MGA_TRANSC | \ 675 MGA_CLIPDIS) 676 677#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \ 678 MGA_ATYPE_RPL | \ 679 MGA_SGNZERO | \ 680 MGA_SHIFTZERO | \ 681 MGA_BOP_SRC | \ 682 (0 << MGA_TRANS_SHIFT) | \ 683 MGA_BLTMOD_BFCOL | \ 684 MGA_CLIPDIS) 685 686/* Simple idle test. 687 */ 688static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv) 689{ 690 u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; 691 return (status == MGA_ENDPRDMASTS); 692} 693 694#endif 695