i915_reg.h revision 189054
1285169Scy/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2132451Sroberto * All Rights Reserved. 354359Sroberto * 4285169Scy * Permission is hereby granted, free of charge, to any person obtaining a 5285169Scy * copy of this software and associated documentation files (the 654359Sroberto * "Software"), to deal in the Software without restriction, including 754359Sroberto * without limitation the rights to use, copy, modify, merge, publish, 854359Sroberto * distribute, sub license, and/or sell copies of the Software, and to 954359Sroberto * permit persons to whom the Software is furnished to do so, subject to 1054359Sroberto * the following conditions: 1154359Sroberto * 1254359Sroberto * The above copyright notice and this permission notice (including the 1354359Sroberto * next paragraph) shall be included in all copies or substantial portions 1454359Sroberto * of the Software. 15106163Sroberto * 16106163Sroberto * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17280849Scy * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 1854359Sroberto * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19285169Scy * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20285169Scy * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21285169Scy * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22285169Scy * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23285169Scy */ 24285169Scy 25285169Scy#include <sys/cdefs.h> 26285169Scy__FBSDID("$FreeBSD: head/sys/dev/drm/i915_reg.h 189054 2009-02-25 20:24:13Z rnoland $"); 27285169Scy 28285169Scy#ifndef _I915_REG_H_ 29285169Scy#define _I915_REG_H_ 30285169Scy 31285169Scy/* 32285169Scy * The Bridge device's PCI config space has information about the 33285169Scy * fb aperture size and the amount of pre-reserved memory. 34285169Scy */ 35285169Scy#define INTEL_GMCH_CTRL 0x52 36285169Scy#define INTEL_GMCH_ENABLED 0x4 37285169Scy#define INTEL_GMCH_MEM_MASK 0x1 38285169Scy#define INTEL_GMCH_MEM_64M 0x1 39285169Scy#define INTEL_GMCH_MEM_128M 0 40285169Scy 41285169Scy#define INTEL_855_GMCH_GMS_MASK (0x7 << 4) 42285169Scy#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) 43285169Scy#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) 44285169Scy#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) 45285169Scy#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4) 46285169Scy#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4) 47285169Scy#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4) 48285169Scy 49285169Scy#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4) 50285169Scy#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4) 51285169Scy 52285169Scy/* PCI config space */ 53285169Scy 54285169Scy#define HPLLCC 0xc0 /* 855 only */ 55285169Scy#define GC_CLOCK_CONTROL_MASK (3 << 0) 56285169Scy#define GC_CLOCK_133_200 (0 << 0) 57285169Scy#define GC_CLOCK_100_200 (1 << 0) 58285169Scy#define GC_CLOCK_100_133 (2 << 0) 59285169Scy#define GC_CLOCK_166_250 (3 << 0) 60285169Scy#define GCFGC 0xf0 /* 915+ only */ 61285169Scy#define GC_LOW_FREQUENCY_ENABLE (1 << 7) 62285169Scy#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 63285169Scy#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 64285169Scy#define GC_DISPLAY_CLOCK_MASK (7 << 4) 65285169Scy#define LBB 0xf4 66285169Scy 67285169Scy/* VGA stuff */ 68285169Scy 69285169Scy#define VGA_ST01_MDA 0x3ba 70285169Scy#define VGA_ST01_CGA 0x3da 71285169Scy 72285169Scy#define VGA_MSR_WRITE 0x3c2 73285169Scy#define VGA_MSR_READ 0x3cc 7454359Sroberto#define VGA_MSR_MEM_EN (1<<1) 75200576Sroberto#define VGA_MSR_CGA_MODE (1<<0) 7654359Sroberto 77200576Sroberto#define VGA_SR_INDEX 0x3c4 78132451Sroberto#define VGA_SR_DATA 0x3c5 79132451Sroberto 80132451Sroberto#define VGA_AR_INDEX 0x3c0 81132451Sroberto#define VGA_AR_VID_EN (1<<5) 8282498Sroberto#define VGA_AR_DATA_WRITE 0x3c0 83132451Sroberto#define VGA_AR_DATA_READ 0x3c1 8454359Sroberto 8554359Sroberto#define VGA_GR_INDEX 0x3ce 8654359Sroberto#define VGA_GR_DATA 0x3cf 8754359Sroberto/* GR05 */ 8854359Sroberto#define VGA_GR_MEM_READ_MODE_SHIFT 3 8954359Sroberto#define VGA_GR_MEM_READ_MODE_PLANE 1 9054359Sroberto/* GR06 */ 9154359Sroberto#define VGA_GR_MEM_MODE_MASK 0xc 92182007Sroberto#define VGA_GR_MEM_MODE_SHIFT 2 93182007Sroberto#define VGA_GR_MEM_A0000_AFFFF 0 94280849Scy#define VGA_GR_MEM_A0000_BFFFF 1 95280849Scy#define VGA_GR_MEM_B0000_B7FFF 2 96282408Scy#define VGA_GR_MEM_B0000_BFFFF 3 97280849Scy 98280849Scy#define VGA_DACMASK 0x3c6 99280849Scy#define VGA_DACRX 0x3c7 100280849Scy#define VGA_DACWX 0x3c8 101280849Scy#define VGA_DACDATA 0x3c9 102280849Scy 103280849Scy#define VGA_CR_INDEX_MDA 0x3b4 104280849Scy#define VGA_CR_DATA_MDA 0x3b5 105280849Scy#define VGA_CR_INDEX_CGA 0x3d4 106280849Scy#define VGA_CR_DATA_CGA 0x3d5 107280849Scy 108280849Scy/* 109280849Scy * Memory interface instructions used by the kernel 110280849Scy */ 111280849Scy#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 112316722Sdelphij 113280849Scy#define MI_NOOP MI_INSTR(0, 0) 114280849Scy#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 115280849Scy#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 116280849Scy#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 117280849Scy#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 118280849Scy#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 119280849Scy#define MI_FLUSH MI_INSTR(0x04, 0) 120280849Scy#define MI_READ_FLUSH (1 << 0) 121289764Sglebius#define MI_EXE_FLUSH (1 << 1) 122280849Scy#define MI_NO_WRITE_FLUSH (1 << 2) 123280849Scy#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 124280849Scy#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 125285169Scy#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 126280849Scy#define MI_REPORT_HEAD MI_INSTR(0x07, 0) 127280849Scy#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 128282408Scy#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 129282408Scy#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 130280849Scy#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 131280849Scy#define MI_STORE_DWORD_INDEX_SHIFT 2 132280849Scy#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1) 133182007Sroberto#define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 134182007Sroberto#define MI_BATCH_NON_SECURE (1) 135285169Scy#define MI_BATCH_NON_SECURE_I965 (1<<8) 136182007Sroberto#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 137182007Sroberto 138280849Scy/* 139200576Sroberto * 3D instructions used by the kernel 140280849Scy */ 141285169Scy#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 142285169Scy 143285169Scy#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 144285169Scy#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 145285169Scy#define SC_UPDATE_SCISSOR (0x1<<1) 146285169Scy#define SC_ENABLE_MASK (0x1<<0) 147285169Scy#define SC_ENABLE (0x1<<0) 148285169Scy#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 149285169Scy#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 150285169Scy#define SCI_YMIN_MASK (0xffff<<16) 151280849Scy#define SCI_XMIN_MASK (0xffff<<0) 152285169Scy#define SCI_YMAX_MASK (0xffff<<16) 153280849Scy#define SCI_XMAX_MASK (0xffff<<0) 154280849Scy#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 155285169Scy#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 156285169Scy#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 157285169Scy#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 158285169Scy#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 159285169Scy#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 160285169Scy#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 161285169Scy#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 162285169Scy#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 163285169Scy#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 164285169Scy#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 165285169Scy#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 166285169Scy#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 167285169Scy#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 168200576Sroberto#define BLT_DEPTH_8 (0<<24) 169200576Sroberto#define BLT_DEPTH_16_565 (1<<24) 170200576Sroberto#define BLT_DEPTH_16_1555 (2<<24) 171200576Sroberto#define BLT_DEPTH_32 (3<<24) 172200576Sroberto#define BLT_ROP_GXCOPY (0xcc<<16) 173200576Sroberto#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 174200576Sroberto#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 175200576Sroberto#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 176200576Sroberto#define ASYNC_FLIP (1<<22) 177200576Sroberto#define DISPLAY_PLANE_A (0<<20) 178200576Sroberto#define DISPLAY_PLANE_B (1<<20) 179200576Sroberto 180200576Sroberto/* 181200576Sroberto * Instruction and interrupt control regs 182200576Sroberto */ 183200576Sroberto 184200576Sroberto#define PRB0_TAIL 0x02030 185200576Sroberto#define PRB0_HEAD 0x02034 186200576Sroberto#define PRB0_START 0x02038 187200576Sroberto#define PRB0_CTL 0x0203c 188200576Sroberto#define TAIL_ADDR 0x001FFFF8 189285169Scy#define HEAD_WRAP_COUNT 0xFFE00000 190285169Scy#define HEAD_WRAP_ONE 0x00200000 191285169Scy#define HEAD_ADDR 0x001FFFFC 192285169Scy#define RING_NR_PAGES 0x001FF000 193285169Scy#define RING_REPORT_MASK 0x00000006 194285169Scy#define RING_REPORT_64K 0x00000002 195280849Scy#define RING_REPORT_128K 0x00000004 196280849Scy#define RING_NO_REPORT 0x00000000 197280849Scy#define RING_VALID_MASK 0x00000001 198280849Scy#define RING_VALID 0x00000001 199280849Scy#define RING_INVALID 0x00000000 200280849Scy#define PRB1_TAIL 0x02040 /* 915+ only */ 201280849Scy#define PRB1_HEAD 0x02044 /* 915+ only */ 202280849Scy#define PRB1_START 0x02048 /* 915+ only */ 203285169Scy#define PRB1_CTL 0x0204c /* 915+ only */ 204285169Scy#define ACTHD_I965 0x02074 205285169Scy#define HWS_PGA 0x02080 206285169Scy#define HWS_ADDRESS_MASK 0xfffff000 207285169Scy#define HWS_START_ADDRESS_SHIFT 4 208280849Scy#define IPEIR 0x02088 209285169Scy#define NOPID 0x02094 210285169Scy#define HWSTAM 0x02098 211285169Scy#define SCPD0 0x0209c /* 915+ only */ 212285169Scy#define IER 0x020a0 213285169Scy#define IIR 0x020a4 214285169Scy#define IMR 0x020a8 215285169Scy#define ISR 0x020ac 216285169Scy#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 217285169Scy#define I915_DISPLAY_PORT_INTERRUPT (1<<17) 218285169Scy#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 219285169Scy#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) 220285169Scy#define I915_HWB_OOM_INTERRUPT (1<<13) 221285169Scy#define I915_SYNC_STATUS_INTERRUPT (1<<12) 222285169Scy#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 223285169Scy#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 224285169Scy#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 225285169Scy#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 226280849Scy#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 227280849Scy#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 228280849Scy#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 229285169Scy#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 230285169Scy#define I915_DEBUG_INTERRUPT (1<<2) 231182007Sroberto#define I915_USER_INTERRUPT (1<<1) 232280849Scy#define I915_ASLE_INTERRUPT (1<<0) 233280849Scy#define EIR 0x020b0 234280849Scy#define EMR 0x020b4 235280849Scy#define ESR 0x020b8 236280849Scy#define INSTPM 0x020c0 237280849Scy#define ACTHD 0x020c8 238280849Scy#define FW_BLC 0x020d8 239280849Scy#define FW_BLC_SELF 0x020e0 /* 915+ only */ 240280849Scy#define MI_ARB_STATE 0x020e4 /* 915+ only */ 241280849Scy#define CACHE_MODE_0 0x02120 /* 915+ only */ 242280849Scy#define CM0_MASK_SHIFT 16 243280849Scy#define CM0_IZ_OPT_DISABLE (1<<6) 244280849Scy#define CM0_ZR_OPT_DISABLE (1<<5) 245280849Scy#define CM0_DEPTH_EVICT_DISABLE (1<<4) 246280849Scy#define CM0_COLOR_EVICT_DISABLE (1<<3) 247280849Scy#define CM0_DEPTH_WRITE_DISABLE (1<<1) 248280849Scy#define CM0_RC_OP_FLUSH_DISABLE (1<<0) 249280849Scy#define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 250280849Scy 251280849Scy/* 252280849Scy * Framebuffer compression (915+ only) 253280849Scy */ 254280849Scy 255280849Scy#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 256280849Scy#define FBC_LL_BASE 0x03204 /* 4k page aligned */ 257132451Sroberto#define FBC_CONTROL 0x03208 258280849Scy#define FBC_CTL_EN (1<<31) 25954359Sroberto#define FBC_CTL_PERIODIC (1<<30) 260280849Scy#define FBC_CTL_INTERVAL_SHIFT (16) 261182007Sroberto#define FBC_CTL_UNCOMPRESSIBLE (1<<14) 262132451Sroberto#define FBC_CTL_STRIDE_SHIFT (5) 263132451Sroberto#define FBC_CTL_FENCENO (1<<0) 264132451Sroberto#define FBC_COMMAND 0x0320c 26554359Sroberto#define FBC_CMD_COMPRESS (1<<0) 266289764Sglebius#define FBC_STATUS 0x03210 267280849Scy#define FBC_STAT_COMPRESSING (1<<31) 268280849Scy#define FBC_STAT_COMPRESSED (1<<30) 269280849Scy#define FBC_STAT_MODIFIED (1<<29) 270280849Scy#define FBC_STAT_CURRENT_LINE (1<<0) 271280849Scy#define FBC_CONTROL2 0x03214 27254359Sroberto#define FBC_CTL_FENCE_DBL (0<<4) 273132451Sroberto#define FBC_CTL_IDLE_IMM (0<<2) 27454359Sroberto#define FBC_CTL_IDLE_FULL (1<<2) 275289764Sglebius#define FBC_CTL_IDLE_LINE (2<<2) 276280849Scy#define FBC_CTL_IDLE_DEBUG (3<<2) 27754359Sroberto#define FBC_CTL_CPU_FENCE (1<<1) 278280849Scy#define FBC_CTL_PLANEA (0<<0) 27954359Sroberto#define FBC_CTL_PLANEB (1<<0) 280132451Sroberto#define FBC_FENCE_OFF 0x0321b 281280849Scy 282280849Scy#define FBC_LL_SIZE (1536) 283132451Sroberto 28454359Sroberto/* 285132451Sroberto * GPIO regs 28656746Sroberto */ 287280849Scy#define GPIOA 0x5010 288280849Scy#define GPIOB 0x5014 289280849Scy#define GPIOC 0x5018 290132451Sroberto#define GPIOD 0x501c 291132451Sroberto#define GPIOE 0x5020 292132451Sroberto#define GPIOF 0x5024 293280849Scy#define GPIOG 0x5028 294132451Sroberto#define GPIOH 0x502c 295106163Sroberto# define GPIO_CLOCK_DIR_MASK (1 << 0) 296280849Scy# define GPIO_CLOCK_DIR_IN (0 << 1) 297200576Sroberto# define GPIO_CLOCK_DIR_OUT (1 << 1) 298280849Scy# define GPIO_CLOCK_VAL_MASK (1 << 2) 299280849Scy# define GPIO_CLOCK_VAL_OUT (1 << 3) 300280849Scy# define GPIO_CLOCK_VAL_IN (1 << 4) 301280849Scy# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 302280849Scy# define GPIO_DATA_DIR_MASK (1 << 8) 303200576Sroberto# define GPIO_DATA_DIR_IN (0 << 9) 304285169Scy# define GPIO_DATA_DIR_OUT (1 << 9) 305280849Scy# define GPIO_DATA_VAL_MASK (1 << 10) 306280849Scy# define GPIO_DATA_VAL_OUT (1 << 11) 307200576Sroberto# define GPIO_DATA_VAL_IN (1 << 12) 308132451Sroberto# define GPIO_DATA_PULLUP_DISABLE (1 << 13) 309132451Sroberto 310132451Sroberto/* 31182498Sroberto * Clock control & power management 312280849Scy */ 313280849Scy 314280849Scy#define VGA0 0x6000 315280849Scy#define VGA1 0x6004 316280849Scy#define VGA_PD 0x6010 317280849Scy#define VGA0_PD_P2_DIV_4 (1 << 7) 31854359Sroberto#define VGA0_PD_P1_DIV_2 (1 << 5) 319280849Scy#define VGA0_PD_P1_SHIFT 0 320280849Scy#define VGA0_PD_P1_MASK (0x1f << 0) 321280849Scy#define VGA1_PD_P2_DIV_4 (1 << 15) 322132451Sroberto#define VGA1_PD_P1_DIV_2 (1 << 13) 323182007Sroberto#define VGA1_PD_P1_SHIFT 8 324182007Sroberto#define VGA1_PD_P1_MASK (0x1f << 8) 325182007Sroberto#define DPLL_A 0x06014 32654359Sroberto#define DPLL_B 0x06018 327132451Sroberto#define DPLL_VCO_ENABLE (1 << 31) 328182007Sroberto#define DPLL_DVO_HIGH_SPEED (1 << 30) 329280849Scy#define DPLL_SYNCLOCK_ENABLE (1 << 29) 330280849Scy#define DPLL_VGA_MODE_DIS (1 << 28) 33154359Sroberto#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 332200576Sroberto#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 333289764Sglebius#define DPLL_MODE_MASK (3 << 26) 334132451Sroberto#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 335316722Sdelphij#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 336132451Sroberto#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 33754359Sroberto#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 338182007Sroberto#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 33954359Sroberto#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 340132451Sroberto 34154359Sroberto#define I915_FIFO_UNDERRUN_STATUS (1UL<<31) 34254359Sroberto#define I915_CRC_ERROR_ENABLE (1UL<<29) 343132451Sroberto#define I915_CRC_DONE_ENABLE (1UL<<28) 344280849Scy#define I915_GMBUS_EVENT_ENABLE (1UL<<27) 34554359Sroberto#define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) 34654359Sroberto#define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 34754359Sroberto#define I915_DPST_EVENT_ENABLE (1UL<<23) 34882498Sroberto#define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 349280849Scy#define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 350280849Scy#define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 351200576Sroberto#define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 352280849Scy#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) 353280849Scy#define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) 354280849Scy#define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 355280849Scy#define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 356280849Scy#define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) 357280849Scy#define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) 358280849Scy#define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 359280849Scy#define I915_DPST_EVENT_STATUS (1UL<<7) 360280849Scy#define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) 361280849Scy#define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 362280849Scy#define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 363280849Scy#define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 364280849Scy#define I915_VBLANK_INTERRUPT_STATUS (1UL<<1) 365280849Scy#define I915_OVERLAY_UPDATED_STATUS (1UL<<0) 366280849Scy 367280849Scy#define SRX_INDEX 0x3c4 368280849Scy#define SRX_DATA 0x3c5 369280849Scy#define SR01 1 370280849Scy#define SR01_SCREEN_OFF (1<<5) 371280849Scy 372280849Scy#define PPCR 0x61204 373280849Scy#define PPCR_ON (1<<0) 374280849Scy 375280849Scy#define DVOB 0x61140 376280849Scy#define DVOB_ON (1<<31) 377280849Scy#define DVOC 0x61160 378280849Scy#define DVOC_ON (1<<31) 379280849Scy#define LVDS 0x61180 380280849Scy#define LVDS_ON (1<<31) 381280849Scy 382280849Scy#define ADPA 0x61100 383280849Scy#define ADPA_DPMS_MASK (~(3<<10)) 384280849Scy#define ADPA_DPMS_ON (0<<10) 385280849Scy#define ADPA_DPMS_SUSPEND (1<<10) 386280849Scy#define ADPA_DPMS_STANDBY (2<<10) 387280849Scy#define ADPA_DPMS_OFF (3<<10) 388280849Scy 389280849Scy#define RING_TAIL 0x00 390280849Scy#define TAIL_ADDR 0x001FFFF8 391280849Scy#define RING_HEAD 0x04 392280849Scy#define HEAD_WRAP_COUNT 0xFFE00000 393280849Scy#define HEAD_WRAP_ONE 0x00200000 394280849Scy#define HEAD_ADDR 0x001FFFFC 395280849Scy#define RING_START 0x08 396280849Scy#define START_ADDR 0xFFFFF000 397280849Scy#define RING_LEN 0x0C 398280849Scy#define RING_NR_PAGES 0x001FF000 399316722Sdelphij#define RING_REPORT_MASK 0x00000006 400316722Sdelphij#define RING_REPORT_64K 0x00000002 401316722Sdelphij#define RING_REPORT_128K 0x00000004 402280849Scy#define RING_NO_REPORT 0x00000000 403280849Scy#define RING_VALID_MASK 0x00000001 404280849Scy#define RING_VALID 0x00000001 405280849Scy#define RING_INVALID 0x00000000 406280849Scy 407280849Scy/* Scratch pad debug 0 reg: 408280849Scy */ 409280849Scy#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 410280849Scy/* 411280849Scy * The i830 generation, in LVDS mode, defines P1 as the bit number set within 412280849Scy * this field (only one bit may be set). 413280849Scy */ 414106163Sroberto#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 415280849Scy#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 416280849Scy/* i830, required in DVO non-gang */ 41754359Sroberto#define PLL_P2_DIVIDE_BY_4 (1 << 23) 418132451Sroberto#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 419132451Sroberto#define PLL_REF_INPUT_DREFCLK (0 << 13) 420132451Sroberto#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 421132451Sroberto#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 422200576Sroberto#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 423132451Sroberto#define PLL_REF_INPUT_MASK (3 << 13) 424280849Scy#define PLL_LOAD_PULSE_PHASE_SHIFT 9 42582498Sroberto/* 426285169Scy * Parallel to Serial Load Pulse phase selection. 427132451Sroberto * Selects the phase for the 10X DPLL clock for the PCIe 428280849Scy * digital display port. The range is 4 to 13; 10 or more 429280849Scy * is just a flip delay. The default is 6 430280849Scy */ 431280849Scy#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 43254359Sroberto#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 433280849Scy/* 43454359Sroberto * SDVO multiplier for 945G/GM. Not used on 965. 435280849Scy */ 436132451Sroberto#define SDVO_MULTIPLIER_MASK 0x000000ff 437132451Sroberto#define SDVO_MULTIPLIER_SHIFT_HIRES 4 438280849Scy#define SDVO_MULTIPLIER_SHIFT_VGA 0 439280849Scy#define DPLL_A_MD 0x0601c /* 965+ only */ 440280849Scy/* 441280849Scy * UDI pixel divider, controlling how many pixels are stuffed into a packet. 442280849Scy * 443280849Scy * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 444280849Scy */ 445280849Scy#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 446280849Scy#define DPLL_MD_UDI_DIVIDER_SHIFT 24 447280849Scy/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 448132451Sroberto#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 44954359Sroberto#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 450280849Scy/* 451280849Scy * SDVO/UDI pixel multiplier. 452280849Scy * 453280849Scy * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 454280849Scy * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 455280849Scy * modes, the bus rate would be below the limits, so SDVO allows for stuffing 456280849Scy * dummy bytes in the datastream at an increased clock rate, with both sides of 457280849Scy * the link knowing how many bytes are fill. 458280849Scy * 459280849Scy * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 460282408Scy * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 461282408Scy * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 462282408Scy * through an SDVO command. 463282408Scy * 464282408Scy * This register field has values of multiplication factor minus 1, with 46554359Sroberto * a maximum multiplier of 5 for SDVO. 466280849Scy */ 467280849Scy#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 468280849Scy#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 469200576Sroberto/* 470200576Sroberto * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 471200576Sroberto * This best be set to the default value (3) or the CRT won't work. No, 472200576Sroberto * I don't entirely understand what this does... 473280849Scy */ 474132451Sroberto#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 475280849Scy#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 476106163Sroberto#define DPLL_B_MD 0x06020 /* 965+ only */ 477132451Sroberto#define FPA0 0x06040 478106163Sroberto#define FPA1 0x06044 479182007Sroberto#define FPB0 0x06048 480182007Sroberto#define FPB1 0x0604c 481132451Sroberto#define FP_N_DIV_MASK 0x003f0000 482132451Sroberto#define FP_N_DIV_SHIFT 16 483132451Sroberto#define FP_M1_DIV_MASK 0x00003f00 484132451Sroberto#define FP_M1_DIV_SHIFT 8 485132451Sroberto#define FP_M2_DIV_MASK 0x0000003f 486132451Sroberto#define FP_M2_DIV_SHIFT 0 487200576Sroberto#define DPLL_TEST 0x606c 488132451Sroberto#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 489200576Sroberto#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 490200576Sroberto#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 491200576Sroberto#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 492132451Sroberto#define DPLLB_TEST_N_BYPASS (1 << 19) 493132451Sroberto#define DPLLB_TEST_M_BYPASS (1 << 18) 494132451Sroberto#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 495132451Sroberto#define DPLLA_TEST_N_BYPASS (1 << 3) 496132451Sroberto#define DPLLA_TEST_M_BYPASS (1 << 2) 497132451Sroberto#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 498200576Sroberto#define D_STATE 0x6104 499132451Sroberto#define CG_2D_DIS 0x6200 500132451Sroberto#define CG_3D_DIS 0x6204 50156746Sroberto 502132451Sroberto/* 503132451Sroberto * Palette regs 504200576Sroberto */ 505132451Sroberto 506132451Sroberto#define PALETTE_A 0x0a000 507182007Sroberto#define PALETTE_B 0x0a800 508132451Sroberto 509200576Sroberto/* MCH MMIO space */ 510132451Sroberto 511132451Sroberto/* 512200576Sroberto * MCHBAR mirror. 513132451Sroberto * 514132451Sroberto * This mirrors the MCHBAR MMIO space whose location is determined by 515200576Sroberto * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 516132451Sroberto * every way. It is not accessible from the CP register read instructions. 517132451Sroberto * 518132451Sroberto */ 519200576Sroberto#define MCHBAR_MIRROR_BASE 0x10000 520200576Sroberto 521200576Sroberto/** 915-945 and GM965 MCH register controlling DRAM channel access */ 522280849Scy#define DCC 0x10200 523280849Scy#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 524280849Scy#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 525280849Scy#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 526280849Scy#define DCC_ADDRESSING_MODE_MASK (3 << 0) 527280849Scy#define DCC_CHANNEL_XOR_DISABLE (1 << 10) 528280849Scy 529280849Scy/** 965 MCH register controlling DRAM channel configuration */ 530282408Scy#define C0DRB3 0x10206 531280849Scy#define C1DRB3 0x10606 53282498Sroberto 533280849Scy/* 534280849Scy * Overlay regs 535280849Scy */ 536280849Scy 537280849Scy#define OVADD 0x30000 53854359Sroberto#define DOVSTA 0x30008 539280849Scy#define OC_BUF (0x3<<20) 540280849Scy#define OGAMC5 0x30010 541280849Scy#define OGAMC4 0x30014 542280849Scy#define OGAMC3 0x30018 543280849Scy#define OGAMC2 0x3001c 544280849Scy#define OGAMC1 0x30020 545280849Scy#define OGAMC0 0x30024 546280849Scy 547280849Scy/* 548280849Scy * Display engine regs 549280849Scy */ 550280849Scy 551280849Scy/* Pipe A timing regs */ 552280849Scy#define HTOTAL_A 0x60000 553280849Scy#define HBLANK_A 0x60004 554280849Scy#define HSYNC_A 0x60008 555280849Scy#define VTOTAL_A 0x6000c 556280849Scy#define VBLANK_A 0x60010 557280849Scy#define VSYNC_A 0x60014 558280849Scy#define PIPEASRC 0x6001c 559280849Scy#define BCLRPAT_A 0x60020 560280849Scy 561280849Scy/* Pipe B timing regs */ 562280849Scy#define HTOTAL_B 0x61000 563280849Scy#define HBLANK_B 0x61004 564280849Scy#define HSYNC_B 0x61008 565280849Scy#define VTOTAL_B 0x6100c 566280849Scy#define VBLANK_B 0x61010 567280849Scy#define VSYNC_B 0x61014 568280849Scy#define PIPEBSRC 0x6101c 569280849Scy#define BCLRPAT_B 0x61020 570280849Scy 571280849Scy/* VGA port control */ 572280849Scy#define ADPA 0x61100 573280849Scy#define ADPA_DAC_ENABLE (1<<31) 574280849Scy#define ADPA_DAC_DISABLE 0 575280849Scy#define ADPA_PIPE_SELECT_MASK (1<<30) 576280849Scy#define ADPA_PIPE_A_SELECT 0 577280849Scy#define ADPA_PIPE_B_SELECT (1<<30) 578280849Scy#define ADPA_USE_VGA_HVPOLARITY (1<<15) 579280849Scy#define ADPA_SETS_HVPOLARITY 0 580280849Scy#define ADPA_VSYNC_CNTL_DISABLE (1<<11) 581280849Scy#define ADPA_VSYNC_CNTL_ENABLE 0 582280849Scy#define ADPA_HSYNC_CNTL_DISABLE (1<<10) 583280849Scy#define ADPA_HSYNC_CNTL_ENABLE 0 584280849Scy#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 585280849Scy#define ADPA_VSYNC_ACTIVE_LOW 0 586280849Scy#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 587280849Scy#define ADPA_HSYNC_ACTIVE_LOW 0 588280849Scy#define ADPA_DPMS_MASK (~(3<<10)) 589280849Scy#define ADPA_DPMS_ON (0<<10) 590280849Scy#define ADPA_DPMS_SUSPEND (1<<10) 591280849Scy#define ADPA_DPMS_STANDBY (2<<10) 592280849Scy#define ADPA_DPMS_OFF (3<<10) 593280849Scy 594280849Scy/* Hotplug control (945+ only) */ 595280849Scy#define PORT_HOTPLUG_EN 0x61110 596280849Scy#define SDVOB_HOTPLUG_INT_EN (1 << 26) 597280849Scy#define SDVOC_HOTPLUG_INT_EN (1 << 25) 598280849Scy#define TV_HOTPLUG_INT_EN (1 << 18) 599280849Scy#define CRT_HOTPLUG_INT_EN (1 << 9) 600280849Scy#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 601280849Scy 602280849Scy#define PORT_HOTPLUG_STAT 0x61114 603280849Scy#define CRT_HOTPLUG_INT_STATUS (1 << 11) 604280849Scy#define TV_HOTPLUG_INT_STATUS (1 << 10) 60554359Sroberto#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 606182007Sroberto#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 607182007Sroberto#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 608182007Sroberto#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 609182007Sroberto#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 610200576Sroberto#define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 611200576Sroberto 612182007Sroberto/* SDVO port control */ 613182007Sroberto#define SDVOB 0x61140 614182007Sroberto#define SDVOC 0x61160 615200576Sroberto#define SDVO_ENABLE (1 << 31) 616200576Sroberto#define SDVO_PIPE_B_SELECT (1 << 30) 617200576Sroberto#define SDVO_STALL_SELECT (1 << 29) 618182007Sroberto#define SDVO_INTERRUPT_ENABLE (1 << 26) 619182007Sroberto/** 620182007Sroberto * 915G/GM SDVO pixel multiplier. 621182007Sroberto * 622182007Sroberto * Programmed value is multiplier - 1, up to 5x. 623182007Sroberto * 624182007Sroberto * \sa DPLL_MD_UDI_MULTIPLIER_MASK 625182007Sroberto */ 626182007Sroberto#define SDVO_PORT_MULTIPLY_MASK (7 << 23) 627182007Sroberto#define SDVO_PORT_MULTIPLY_SHIFT 23 628182007Sroberto#define SDVO_PHASE_SELECT_MASK (15 << 19) 629182007Sroberto#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 630182007Sroberto#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 631182007Sroberto#define SDVOC_GANG_MODE (1 << 16) 632182007Sroberto#define SDVO_BORDER_ENABLE (1 << 7) 633182007Sroberto#define SDVOB_PCIE_CONCURRENCY (1 << 3) 634200576Sroberto#define SDVO_DETECTED (1 << 2) 635182007Sroberto/* Bits to be preserved when writing */ 636132451Sroberto#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) 637182007Sroberto#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) 638132451Sroberto 639182007Sroberto/* DVO port control */ 640182007Sroberto#define DVOA 0x61120 641280849Scy#define DVOB 0x61140 642280849Scy#define DVOC 0x61160 643280849Scy#define DVO_ENABLE (1 << 31) 644280849Scy#define DVO_PIPE_B_SELECT (1 << 30) 645280849Scy#define DVO_PIPE_STALL_UNUSED (0 << 28) 646280849Scy#define DVO_PIPE_STALL (1 << 28) 647280849Scy#define DVO_PIPE_STALL_TV (2 << 28) 64882498Sroberto#define DVO_PIPE_STALL_MASK (3 << 28) 649285169Scy#define DVO_USE_VGA_SYNC (1 << 15) 650285169Scy#define DVO_DATA_ORDER_I740 (0 << 14) 651285169Scy#define DVO_DATA_ORDER_FP (1 << 14) 652285169Scy#define DVO_VSYNC_DISABLE (1 << 11) 653285169Scy#define DVO_HSYNC_DISABLE (1 << 10) 654285169Scy#define DVO_VSYNC_TRISTATE (1 << 9) 655285169Scy#define DVO_HSYNC_TRISTATE (1 << 8) 656285169Scy#define DVO_BORDER_ENABLE (1 << 7) 657285169Scy#define DVO_DATA_ORDER_GBRG (1 << 6) 658285169Scy#define DVO_DATA_ORDER_RGGB (0 << 6) 659285169Scy#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 660285169Scy#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 661280849Scy#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 662280849Scy#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 663280849Scy#define DVO_BLANK_ACTIVE_HIGH (1 << 2) 664200576Sroberto#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 665280849Scy#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 666280849Scy#define DVO_PRESERVE_MASK (0x7<<24) 667280849Scy#define DVOA_SRCDIM 0x61124 668280849Scy#define DVOB_SRCDIM 0x61144 669280849Scy#define DVOC_SRCDIM 0x61164 670280849Scy#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 671280849Scy#define DVO_SRCDIM_VERTICAL_SHIFT 0 672280849Scy 673280849Scy/* LVDS port control */ 674280849Scy#define LVDS 0x61180 675280849Scy/* 676280849Scy * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 677280849Scy * the DPLL semantics change when the LVDS is assigned to that pipe. 678280849Scy */ 679280849Scy#define LVDS_PORT_EN (1 << 31) 68082498Sroberto/* Selects pipe B for LVDS data. Must be set on pre-965. */ 681280849Scy#define LVDS_PIPEB_SELECT (1 << 30) 68282498Sroberto/* 683280849Scy * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 684280849Scy * pixel. 685280849Scy */ 686280849Scy#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 687285169Scy#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 688280849Scy#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 689280849Scy/* 690285169Scy * Controls the A3 data pair, which contains the additional LSBs for 24 bit 691285169Scy * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 692285169Scy * on. 693285169Scy */ 694285169Scy#define LVDS_A3_POWER_MASK (3 << 6) 695285169Scy#define LVDS_A3_POWER_DOWN (0 << 6) 696285169Scy#define LVDS_A3_POWER_UP (3 << 6) 697285169Scy/* 698285169Scy * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 699285169Scy * is set. 700285169Scy */ 701285169Scy#define LVDS_CLKB_POWER_MASK (3 << 4) 702280849Scy#define LVDS_CLKB_POWER_DOWN (0 << 4) 703280849Scy#define LVDS_CLKB_POWER_UP (3 << 4) 704280849Scy/* 705280849Scy * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 706280849Scy * setting for whether we are in dual-channel mode. The B3 pair will 707280849Scy * additionally only be powered up when LVDS_A3_POWER_UP is set. 708280849Scy */ 709280849Scy#define LVDS_B0B3_POWER_MASK (3 << 2) 710280849Scy#define LVDS_B0B3_POWER_DOWN (0 << 2) 711280849Scy#define LVDS_B0B3_POWER_UP (3 << 2) 712280849Scy 713280849Scy/* Panel power sequencing */ 714280849Scy#define PP_STATUS 0x61200 715280849Scy#define PP_ON (1 << 31) 716280849Scy/* 717280849Scy * Indicates that all dependencies of the panel are on: 718280849Scy * 719280849Scy * - PLL enabled 720280849Scy * - pipe enabled 721182007Sroberto * - LVDS/DVOB/DVOC on 722280849Scy */ 723280849Scy#define PP_READY (1 << 30) 724280849Scy#define PP_SEQUENCE_NONE (0 << 28) 725280849Scy#define PP_SEQUENCE_ON (1 << 28) 726280849Scy#define PP_SEQUENCE_OFF (2 << 28) 727280849Scy#define PP_SEQUENCE_MASK 0x30000000 728285169Scy#define PP_CONTROL 0x61204 729182007Sroberto#define POWER_TARGET_ON (1 << 0) 730280849Scy#define PP_ON_DELAYS 0x61208 731285169Scy#define PP_OFF_DELAYS 0x6120c 732285169Scy#define PP_DIVISOR 0x61210 733285169Scy 734285169Scy/* Panel fitting */ 735285169Scy#define PFIT_CONTROL 0x61230 736285169Scy#define PFIT_ENABLE (1 << 31) 737285169Scy#define PFIT_PIPE_MASK (3 << 29) 738285169Scy#define PFIT_PIPE_SHIFT 29 739285169Scy#define VERT_INTERP_DISABLE (0 << 10) 740285169Scy#define VERT_INTERP_BILINEAR (1 << 10) 741285169Scy#define VERT_INTERP_MASK (3 << 10) 742285169Scy#define VERT_AUTO_SCALE (1 << 9) 743280849Scy#define HORIZ_INTERP_DISABLE (0 << 6) 744280849Scy#define HORIZ_INTERP_BILINEAR (1 << 6) 745285169Scy#define HORIZ_INTERP_MASK (3 << 6) 746285169Scy#define HORIZ_AUTO_SCALE (1 << 5) 747285169Scy#define PANEL_8TO6_DITHER_ENABLE (1 << 3) 748285169Scy#define PFIT_PGM_RATIOS 0x61234 749285169Scy#define PFIT_VERT_SCALE_MASK 0xfff00000 750280849Scy#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 751280849Scy#define PFIT_AUTO_RATIOS 0x61238 752280849Scy 753280849Scy/* Backlight control */ 754280849Scy#define BLC_PWM_CTL 0x61254 755280849Scy#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 756280849Scy#define BLC_PWM_CTL2 0x61250 /* 965+ only */ 757280849Scy#define BLM_COMBINATION_MODE (1 << 30) 758280849Scy/* 759280849Scy * This is the most significant 15 bits of the number of backlight cycles in a 760280849Scy * complete cycle of the modulated backlight control. 761280849Scy * 762280849Scy * The actual value is this field multiplied by two. 763280849Scy */ 764285169Scy#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 765285169Scy#define BLM_LEGACY_MODE (1 << 16) 766285169Scy/* 767285169Scy * This is the number of cycles out of the backlight modulation cycle for which 768280849Scy * the backlight is on. 769285169Scy * 770280849Scy * This field must be no greater than the number of cycles in the complete 771280849Scy * backlight modulation cycle. 772280849Scy */ 773280849Scy#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 774280849Scy#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 775280849Scy 776280849Scy/* TV port control */ 777280849Scy#define TV_CTL 0x68000 778280849Scy/** Enables the TV encoder */ 779280849Scy# define TV_ENC_ENABLE (1 << 31) 780280849Scy/** Sources the TV encoder input from pipe B instead of A. */ 781280849Scy# define TV_ENC_PIPEB_SELECT (1 << 30) 782280849Scy/** Outputs composite video (DAC A only) */ 783280849Scy# define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 784280849Scy/** Outputs SVideo video (DAC B/C) */ 785285169Scy# define TV_ENC_OUTPUT_SVIDEO (1 << 28) 786280849Scy/** Outputs Component video (DAC A/B/C) */ 787280849Scy# define TV_ENC_OUTPUT_COMPONENT (2 << 28) 788280849Scy/** Outputs Composite and SVideo (DAC A/B/C) */ 789280849Scy# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 790280849Scy# define TV_TRILEVEL_SYNC (1 << 21) 791280849Scy/** Enables slow sync generation (945GM only) */ 792280849Scy# define TV_SLOW_SYNC (1 << 20) 793280849Scy/** Selects 4x oversampling for 480i and 576p */ 794280849Scy# define TV_OVERSAMPLE_4X (0 << 18) 795280849Scy/** Selects 2x oversampling for 720p and 1080i */ 796280849Scy# define TV_OVERSAMPLE_2X (1 << 18) 797285169Scy/** Selects no oversampling for 1080p */ 798285169Scy# define TV_OVERSAMPLE_NONE (2 << 18) 799285169Scy/** Selects 8x oversampling */ 800285169Scy# define TV_OVERSAMPLE_8X (3 << 18) 801285169Scy/** Selects progressive mode rather than interlaced */ 802280849Scy# define TV_PROGRESSIVE (1 << 17) 803280849Scy/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 804280849Scy# define TV_PAL_BURST (1 << 16) 80554359Sroberto/** Field for setting delay of Y compared to C */ 806280849Scy# define TV_YC_SKEW_MASK (7 << 12) 807280849Scy/** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 808280849Scy# define TV_ENC_SDP_FIX (1 << 11) 809280849Scy/** 810285169Scy * Enables a fix for the 915GM only. 81154359Sroberto * 812285169Scy * Not sure what it does. 813285169Scy */ 814285169Scy# define TV_ENC_C0_FIX (1 << 10) 815285169Scy/** Bits that must be preserved by software */ 816285169Scy# define TV_CTL_SAVE ((3 << 8) | (3 << 6)) 817285169Scy# define TV_FUSE_STATE_MASK (3 << 4) 818285169Scy/** Read-only state that reports all features enabled */ 819285169Scy# define TV_FUSE_STATE_ENABLED (0 << 4) 820285169Scy/** Read-only state that reports that Macrovision is disabled in hardware*/ 821285169Scy# define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 822285169Scy/** Read-only state that reports that TV-out is disabled in hardware. */ 823285169Scy# define TV_FUSE_STATE_DISABLED (2 << 4) 824285169Scy/** Normal operation */ 825285169Scy# define TV_TEST_MODE_NORMAL (0 << 0) 826280849Scy/** Encoder test pattern 1 - combo pattern */ 827280849Scy# define TV_TEST_MODE_PATTERN_1 (1 << 0) 828280849Scy/** Encoder test pattern 2 - full screen vertical 75% color bars */ 82954359Sroberto# define TV_TEST_MODE_PATTERN_2 (2 << 0) 830200576Sroberto/** Encoder test pattern 3 - full screen horizontal 75% color bars */ 831200576Sroberto# define TV_TEST_MODE_PATTERN_3 (3 << 0) 832200576Sroberto/** Encoder test pattern 4 - random noise */ 833200576Sroberto# define TV_TEST_MODE_PATTERN_4 (4 << 0) 834200576Sroberto/** Encoder test pattern 5 - linear color ramps */ 835200576Sroberto# define TV_TEST_MODE_PATTERN_5 (5 << 0) 836200576Sroberto/** 837200576Sroberto * This test mode forces the DACs to 50% of full output. 838200576Sroberto * 839200576Sroberto * This is used for load detection in combination with TVDAC_SENSE_MASK 840200576Sroberto */ 841200576Sroberto# define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 842132451Sroberto# define TV_TEST_MODE_MASK (7 << 0) 84354359Sroberto 844200576Sroberto#define TV_DAC 0x68004 845200576Sroberto/** 846200576Sroberto * Reports that DAC state change logic has reported change (RO). 847200576Sroberto * 848132451Sroberto * This gets cleared when TV_DAC_STATE_EN is cleared 849200576Sroberto*/ 850200576Sroberto# define TVDAC_STATE_CHG (1 << 31) 851132451Sroberto# define TVDAC_SENSE_MASK (7 << 28) 852200576Sroberto/** Reports that DAC A voltage is above the detect threshold */ 85354359Sroberto# define TVDAC_A_SENSE (1 << 30) 854200576Sroberto/** Reports that DAC B voltage is above the detect threshold */ 855200576Sroberto# define TVDAC_B_SENSE (1 << 29) 85682498Sroberto/** Reports that DAC C voltage is above the detect threshold */ 85754359Sroberto# define TVDAC_C_SENSE (1 << 28) 85854359Sroberto/** 859280849Scy * Enables DAC state detection logic, for load-based TV detection. 860280849Scy * 861285169Scy * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 862285169Scy * to off, for load detection to work. 863285169Scy */ 864285169Scy# define TVDAC_STATE_CHG_EN (1 << 27) 865280849Scy/** Sets the DAC A sense value to high */ 866280849Scy# define TVDAC_A_SENSE_CTL (1 << 26) 867280849Scy/** Sets the DAC B sense value to high */ 868280849Scy# define TVDAC_B_SENSE_CTL (1 << 25) 869280849Scy/** Sets the DAC C sense value to high */ 870280849Scy# define TVDAC_C_SENSE_CTL (1 << 24) 871280849Scy/** Overrides the ENC_ENABLE and DAC voltage levels */ 872280849Scy# define DAC_CTL_OVERRIDE (1 << 7) 873280849Scy/** Sets the slew rate. Must be preserved in software */ 874280849Scy# define ENC_TVDAC_SLEW_FAST (1 << 6) 875280849Scy# define DAC_A_1_3_V (0 << 4) 876280849Scy# define DAC_A_1_1_V (1 << 4) 877280849Scy# define DAC_A_0_7_V (2 << 4) 878280849Scy# define DAC_A_OFF (3 << 4) 879280849Scy# define DAC_B_1_3_V (0 << 2) 880280849Scy# define DAC_B_1_1_V (1 << 2) 881280849Scy# define DAC_B_0_7_V (2 << 2) 882280849Scy# define DAC_B_OFF (3 << 2) 883280849Scy# define DAC_C_1_3_V (0 << 0) 88454359Sroberto# define DAC_C_1_1_V (1 << 0) 885280849Scy# define DAC_C_0_7_V (2 << 0) 886280849Scy# define DAC_C_OFF (3 << 0) 887280849Scy 888280849Scy/** 889280849Scy * CSC coefficients are stored in a floating point format with 9 bits of 890200576Sroberto * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 891182007Sroberto * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 892280849Scy * -1 (0x3) being the only legal negative value. 893280849Scy */ 894280849Scy#define TV_CSC_Y 0x68010 895280849Scy# define TV_RY_MASK 0x07ff0000 89654359Sroberto# define TV_RY_SHIFT 16 89754359Sroberto# define TV_GY_MASK 0x00000fff 89854359Sroberto# define TV_GY_SHIFT 0 89982498Sroberto 900280849Scy#define TV_CSC_Y2 0x68014 90154359Sroberto# define TV_BY_MASK 0x07ff0000 902285169Scy# define TV_BY_SHIFT 16 903285169Scy/** 904285169Scy * Y attenuation for component video. 905285169Scy * 906285169Scy * Stored in 1.9 fixed point. 907285169Scy */ 908285169Scy# define TV_AY_MASK 0x000003ff 909285169Scy# define TV_AY_SHIFT 0 910285169Scy 91154359Sroberto#define TV_CSC_U 0x68018 91254359Sroberto# define TV_RU_MASK 0x07ff0000 91354359Sroberto# define TV_RU_SHIFT 16 91454359Sroberto# define TV_GU_MASK 0x000007ff 91554359Sroberto# define TV_GU_SHIFT 0 916182007Sroberto 917200576Sroberto#define TV_CSC_U2 0x6801c 918280849Scy# define TV_BU_MASK 0x07ff0000 91954359Sroberto# define TV_BU_SHIFT 16 92054359Sroberto/** 92182498Sroberto * U attenuation for component video. 92282498Sroberto * 923280849Scy * Stored in 1.9 fixed point. 92454359Sroberto */ 925182007Sroberto# define TV_AU_MASK 0x000003ff 92654359Sroberto# define TV_AU_SHIFT 0 927280849Scy 928132451Sroberto#define TV_CSC_V 0x68020 929280849Scy# define TV_RV_MASK 0x0fff0000 93054359Sroberto# define TV_RV_SHIFT 16 931280849Scy# define TV_GV_MASK 0x000007ff 93254359Sroberto# define TV_GV_SHIFT 0 93382498Sroberto 93454359Sroberto#define TV_CSC_V2 0x68024 935280849Scy# define TV_BV_MASK 0x07ff0000 936182007Sroberto# define TV_BV_SHIFT 16 937200576Sroberto/** 938200576Sroberto * V attenuation for component video. 939280849Scy * 94054359Sroberto * Stored in 1.9 fixed point. 94182498Sroberto */ 94282498Sroberto# define TV_AV_MASK 0x000007ff 943280849Scy# define TV_AV_SHIFT 0 94482498Sroberto 945280849Scy#define TV_CLR_KNOBS 0x68028 946200576Sroberto/** 2s-complement brightness adjustment */ 947200576Sroberto# define TV_BRIGHTNESS_MASK 0xff000000 948200576Sroberto# define TV_BRIGHTNESS_SHIFT 24 949280849Scy/** Contrast adjustment, as a 2.6 unsigned floating point number */ 95082498Sroberto# define TV_CONTRAST_MASK 0x00ff0000 951280849Scy# define TV_CONTRAST_SHIFT 16 952200576Sroberto/** Saturation adjustment, as a 2.6 unsigned floating point number */ 953200576Sroberto# define TV_SATURATION_MASK 0x0000ff00 954200576Sroberto# define TV_SATURATION_SHIFT 8 955280849Scy/** Hue adjustment, as an integer phase angle in degrees */ 95682498Sroberto# define TV_HUE_MASK 0x000000ff 957200576Sroberto# define TV_HUE_SHIFT 0 958200576Sroberto 959280849Scy#define TV_CLR_LEVEL 0x6802c 96082498Sroberto/** Controls the DAC level for black */ 961280849Scy# define TV_BLACK_LEVEL_MASK 0x01ff0000 962200576Sroberto# define TV_BLACK_LEVEL_SHIFT 16 963200576Sroberto/** Controls the DAC level for blanking */ 964200576Sroberto# define TV_BLANK_LEVEL_MASK 0x000001ff 965280849Scy# define TV_BLANK_LEVEL_SHIFT 0 966200576Sroberto 967200576Sroberto#define TV_H_CTL_1 0x68030 968200576Sroberto/** Number of pixels in the hsync. */ 96982498Sroberto# define TV_HSYNC_END_MASK 0x1fff0000 97082498Sroberto# define TV_HSYNC_END_SHIFT 16 971280849Scy/** Total number of pixels minus one in the line (display and blanking). */ 972132451Sroberto# define TV_HTOTAL_MASK 0x00001fff 97382498Sroberto# define TV_HTOTAL_SHIFT 0 97454359Sroberto 975280849Scy#define TV_H_CTL_2 0x68034 97654359Sroberto/** Enables the colorburst (needed for non-component color) */ 977182007Sroberto# define TV_BURST_ENA (1 << 31) 97882498Sroberto/** Offset of the colorburst from the start of hsync, in pixels minus one. */ 979280849Scy# define TV_HBURST_START_SHIFT 16 980132451Sroberto# define TV_HBURST_START_MASK 0x1fff0000 981132451Sroberto/** Length of the colorburst */ 982132451Sroberto# define TV_HBURST_LEN_SHIFT 0 983280849Scy# define TV_HBURST_LEN_MASK 0x0001fff 984132451Sroberto 985132451Sroberto#define TV_H_CTL_3 0x68038 986132451Sroberto/** End of hblank, measured in pixels minus one from start of hsync */ 987280849Scy# define TV_HBLANK_END_SHIFT 16 98882498Sroberto# define TV_HBLANK_END_MASK 0x1fff0000 989280849Scy/** Start of hblank, measured in pixels minus one from start of hsync */ 990200576Sroberto# define TV_HBLANK_START_SHIFT 0 991285169Scy# define TV_HBLANK_START_MASK 0x0001fff 99282498Sroberto 993285169Scy#define TV_V_CTL_1 0x6803c 994285169Scy/** XXX */ 995285169Scy# define TV_NBR_END_SHIFT 16 996285169Scy# define TV_NBR_END_MASK 0x07ff0000 997285169Scy/** XXX */ 998285169Scy# define TV_VI_END_F1_SHIFT 8 999285169Scy# define TV_VI_END_F1_MASK 0x00003f00 1000285169Scy/** XXX */ 1001285169Scy# define TV_VI_END_F2_SHIFT 0 1002285169Scy# define TV_VI_END_F2_MASK 0x0000003f 1003285169Scy 1004285169Scy#define TV_V_CTL_2 0x68040 1005285169Scy/** Length of vsync, in half lines */ 1006285169Scy# define TV_VSYNC_LEN_MASK 0x07ff0000 1007200576Sroberto# define TV_VSYNC_LEN_SHIFT 16 1008285169Scy/** Offset of the start of vsync in field 1, measured in one less than the 1009280849Scy * number of half lines. 1010285169Scy */ 1011280849Scy# define TV_VSYNC_START_F1_MASK 0x00007f00 1012280849Scy# define TV_VSYNC_START_F1_SHIFT 8 1013280849Scy/** 1014280849Scy * Offset of the start of vsync in field 2, measured in one less than the 1015280849Scy * number of half lines. 1016280849Scy */ 1017280849Scy# define TV_VSYNC_START_F2_MASK 0x0000007f 1018280849Scy# define TV_VSYNC_START_F2_SHIFT 0 1019280849Scy 1020280849Scy#define TV_V_CTL_3 0x68044 1021280849Scy/** Enables generation of the equalization signal */ 1022280849Scy# define TV_EQUAL_ENA (1 << 31) 1023280849Scy/** Length of vsync, in half lines */ 1024280849Scy# define TV_VEQ_LEN_MASK 0x007f0000 1025280849Scy# define TV_VEQ_LEN_SHIFT 16 1026280849Scy/** Offset of the start of equalization in field 1, measured in one less than 1027280849Scy * the number of half lines. 1028280849Scy */ 1029280849Scy# define TV_VEQ_START_F1_MASK 0x0007f00 1030280849Scy# define TV_VEQ_START_F1_SHIFT 8 1031280849Scy/** 1032280849Scy * Offset of the start of equalization in field 2, measured in one less than 1033280849Scy * the number of half lines. 1034280849Scy */ 1035280849Scy# define TV_VEQ_START_F2_MASK 0x000007f 1036280849Scy# define TV_VEQ_START_F2_SHIFT 0 1037280849Scy 1038280849Scy#define TV_V_CTL_4 0x68048 1039280849Scy/** 1040280849Scy * Offset to start of vertical colorburst, measured in one less than the 1041280849Scy * number of lines from vertical start. 1042280849Scy */ 1043280849Scy# define TV_VBURST_START_F1_MASK 0x003f0000 1044280849Scy# define TV_VBURST_START_F1_SHIFT 16 1045280849Scy/** 1046280849Scy * Offset to the end of vertical colorburst, measured in one less than the 1047280849Scy * number of lines from the start of NBR. 1048280849Scy */ 1049280849Scy# define TV_VBURST_END_F1_MASK 0x000000ff 1050280849Scy# define TV_VBURST_END_F1_SHIFT 0 1051280849Scy 1052280849Scy#define TV_V_CTL_5 0x6804c 1053280849Scy/** 1054280849Scy * Offset to start of vertical colorburst, measured in one less than the 1055280849Scy * number of lines from vertical start. 1056280849Scy */ 1057280849Scy# define TV_VBURST_START_F2_MASK 0x003f0000 1058280849Scy# define TV_VBURST_START_F2_SHIFT 16 1059280849Scy/** 1060280849Scy * Offset to the end of vertical colorburst, measured in one less than the 1061280849Scy * number of lines from the start of NBR. 1062280849Scy */ 1063280849Scy# define TV_VBURST_END_F2_MASK 0x000000ff 1064280849Scy# define TV_VBURST_END_F2_SHIFT 0 1065280849Scy 1066280849Scy#define TV_V_CTL_6 0x68050 1067280849Scy/** 1068280849Scy * Offset to start of vertical colorburst, measured in one less than the 1069280849Scy * number of lines from vertical start. 1070280849Scy */ 1071280849Scy# define TV_VBURST_START_F3_MASK 0x003f0000 1072280849Scy# define TV_VBURST_START_F3_SHIFT 16 1073280849Scy/** 1074280849Scy * Offset to the end of vertical colorburst, measured in one less than the 1075280849Scy * number of lines from the start of NBR. 1076280849Scy */ 1077280849Scy# define TV_VBURST_END_F3_MASK 0x000000ff 1078280849Scy# define TV_VBURST_END_F3_SHIFT 0 1079280849Scy 1080280849Scy#define TV_V_CTL_7 0x68054 1081280849Scy/** 1082280849Scy * Offset to start of vertical colorburst, measured in one less than the 1083280849Scy * number of lines from vertical start. 1084280849Scy */ 1085280849Scy# define TV_VBURST_START_F4_MASK 0x003f0000 1086280849Scy# define TV_VBURST_START_F4_SHIFT 16 1087280849Scy/** 1088280849Scy * Offset to the end of vertical colorburst, measured in one less than the 1089280849Scy * number of lines from the start of NBR. 1090280849Scy */ 1091280849Scy# define TV_VBURST_END_F4_MASK 0x000000ff 1092280849Scy# define TV_VBURST_END_F4_SHIFT 0 1093280849Scy 1094280849Scy#define TV_SC_CTL_1 0x68060 1095280849Scy/** Turns on the first subcarrier phase generation DDA */ 1096280849Scy# define TV_SC_DDA1_EN (1 << 31) 1097280849Scy/** Turns on the first subcarrier phase generation DDA */ 1098280849Scy# define TV_SC_DDA2_EN (1 << 30) 109954359Sroberto/** Turns on the first subcarrier phase generation DDA */ 110054359Sroberto# define TV_SC_DDA3_EN (1 << 29) 110154359Sroberto/** Sets the subcarrier DDA to reset frequency every other field */ 1102# define TV_SC_RESET_EVERY_2 (0 << 24) 1103/** Sets the subcarrier DDA to reset frequency every fourth field */ 1104# define TV_SC_RESET_EVERY_4 (1 << 24) 1105/** Sets the subcarrier DDA to reset frequency every eighth field */ 1106# define TV_SC_RESET_EVERY_8 (2 << 24) 1107/** Sets the subcarrier DDA to never reset the frequency */ 1108# define TV_SC_RESET_NEVER (3 << 24) 1109/** Sets the peak amplitude of the colorburst.*/ 1110# define TV_BURST_LEVEL_MASK 0x00ff0000 1111# define TV_BURST_LEVEL_SHIFT 16 1112/** Sets the increment of the first subcarrier phase generation DDA */ 1113# define TV_SCDDA1_INC_MASK 0x00000fff 1114# define TV_SCDDA1_INC_SHIFT 0 1115 1116#define TV_SC_CTL_2 0x68064 1117/** Sets the rollover for the second subcarrier phase generation DDA */ 1118# define TV_SCDDA2_SIZE_MASK 0x7fff0000 1119# define TV_SCDDA2_SIZE_SHIFT 16 1120/** Sets the increent of the second subcarrier phase generation DDA */ 1121# define TV_SCDDA2_INC_MASK 0x00007fff 1122# define TV_SCDDA2_INC_SHIFT 0 1123 1124#define TV_SC_CTL_3 0x68068 1125/** Sets the rollover for the third subcarrier phase generation DDA */ 1126# define TV_SCDDA3_SIZE_MASK 0x7fff0000 1127# define TV_SCDDA3_SIZE_SHIFT 16 1128/** Sets the increent of the third subcarrier phase generation DDA */ 1129# define TV_SCDDA3_INC_MASK 0x00007fff 1130# define TV_SCDDA3_INC_SHIFT 0 1131 1132#define TV_WIN_POS 0x68070 1133/** X coordinate of the display from the start of horizontal active */ 1134# define TV_XPOS_MASK 0x1fff0000 1135# define TV_XPOS_SHIFT 16 1136/** Y coordinate of the display from the start of vertical active (NBR) */ 1137# define TV_YPOS_MASK 0x00000fff 1138# define TV_YPOS_SHIFT 0 1139 1140#define TV_WIN_SIZE 0x68074 1141/** Horizontal size of the display window, measured in pixels*/ 1142# define TV_XSIZE_MASK 0x1fff0000 1143# define TV_XSIZE_SHIFT 16 1144/** 1145 * Vertical size of the display window, measured in pixels. 1146 * 1147 * Must be even for interlaced modes. 1148 */ 1149# define TV_YSIZE_MASK 0x00000fff 1150# define TV_YSIZE_SHIFT 0 1151 1152#define TV_FILTER_CTL_1 0x68080 1153/** 1154 * Enables automatic scaling calculation. 1155 * 1156 * If set, the rest of the registers are ignored, and the calculated values can 1157 * be read back from the register. 1158 */ 1159# define TV_AUTO_SCALE (1 << 31) 1160/** 1161 * Disables the vertical filter. 1162 * 1163 * This is required on modes more than 1024 pixels wide */ 1164# define TV_V_FILTER_BYPASS (1 << 29) 1165/** Enables adaptive vertical filtering */ 1166# define TV_VADAPT (1 << 28) 1167# define TV_VADAPT_MODE_MASK (3 << 26) 1168/** Selects the least adaptive vertical filtering mode */ 1169# define TV_VADAPT_MODE_LEAST (0 << 26) 1170/** Selects the moderately adaptive vertical filtering mode */ 1171# define TV_VADAPT_MODE_MODERATE (1 << 26) 1172/** Selects the most adaptive vertical filtering mode */ 1173# define TV_VADAPT_MODE_MOST (3 << 26) 1174/** 1175 * Sets the horizontal scaling factor. 1176 * 1177 * This should be the fractional part of the horizontal scaling factor divided 1178 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 1179 * 1180 * (src width - 1) / ((oversample * dest width) - 1) 1181 */ 1182# define TV_HSCALE_FRAC_MASK 0x00003fff 1183# define TV_HSCALE_FRAC_SHIFT 0 1184 1185#define TV_FILTER_CTL_2 0x68084 1186/** 1187 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1188 * 1189 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 1190 */ 1191# define TV_VSCALE_INT_MASK 0x00038000 1192# define TV_VSCALE_INT_SHIFT 15 1193/** 1194 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1195 * 1196 * \sa TV_VSCALE_INT_MASK 1197 */ 1198# define TV_VSCALE_FRAC_MASK 0x00007fff 1199# define TV_VSCALE_FRAC_SHIFT 0 1200 1201#define TV_FILTER_CTL_3 0x68088 1202/** 1203 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1204 * 1205 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 1206 * 1207 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 1208 */ 1209# define TV_VSCALE_IP_INT_MASK 0x00038000 1210# define TV_VSCALE_IP_INT_SHIFT 15 1211/** 1212 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1213 * 1214 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 1215 * 1216 * \sa TV_VSCALE_IP_INT_MASK 1217 */ 1218# define TV_VSCALE_IP_FRAC_MASK 0x00007fff 1219# define TV_VSCALE_IP_FRAC_SHIFT 0 1220 1221#define TV_CC_CONTROL 0x68090 1222# define TV_CC_ENABLE (1 << 31) 1223/** 1224 * Specifies which field to send the CC data in. 1225 * 1226 * CC data is usually sent in field 0. 1227 */ 1228# define TV_CC_FID_MASK (1 << 27) 1229# define TV_CC_FID_SHIFT 27 1230/** Sets the horizontal position of the CC data. Usually 135. */ 1231# define TV_CC_HOFF_MASK 0x03ff0000 1232# define TV_CC_HOFF_SHIFT 16 1233/** Sets the vertical position of the CC data. Usually 21 */ 1234# define TV_CC_LINE_MASK 0x0000003f 1235# define TV_CC_LINE_SHIFT 0 1236 1237#define TV_CC_DATA 0x68094 1238# define TV_CC_RDY (1 << 31) 1239/** Second word of CC data to be transmitted. */ 1240# define TV_CC_DATA_2_MASK 0x007f0000 1241# define TV_CC_DATA_2_SHIFT 16 1242/** First word of CC data to be transmitted. */ 1243# define TV_CC_DATA_1_MASK 0x0000007f 1244# define TV_CC_DATA_1_SHIFT 0 1245 1246#define TV_H_LUMA_0 0x68100 1247#define TV_H_LUMA_59 0x681ec 1248#define TV_H_CHROMA_0 0x68200 1249#define TV_H_CHROMA_59 0x682ec 1250#define TV_V_LUMA_0 0x68300 1251#define TV_V_LUMA_42 0x683a8 1252#define TV_V_CHROMA_0 0x68400 1253#define TV_V_CHROMA_42 0x684a8 1254 1255/* Display & cursor control */ 1256 1257/* Pipe A */ 1258#define PIPEADSL 0x70000 1259#define PIPEACONF 0x70008 1260#define PIPEACONF_ENABLE (1<<31) 1261#define PIPEACONF_DISABLE 0 1262#define PIPEACONF_DOUBLE_WIDE (1<<30) 1263#define I965_PIPECONF_ACTIVE (1<<30) 1264#define PIPEACONF_SINGLE_WIDE 0 1265#define PIPEACONF_PIPE_UNLOCKED 0 1266#define PIPEACONF_PIPE_LOCKED (1<<25) 1267#define PIPEACONF_PALETTE 0 1268#define PIPEACONF_GAMMA (1<<24) 1269#define PIPECONF_FORCE_BORDER (1<<25) 1270#define PIPECONF_PROGRESSIVE (0 << 21) 1271#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 1272#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 1273#define PIPEASTAT 0x70024 1274#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 1275#define PIPE_CRC_ERROR_ENABLE (1UL<<29) 1276#define PIPE_CRC_DONE_ENABLE (1UL<<28) 1277#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 1278#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 1279#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 1280#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 1281#define PIPE_DPST_EVENT_ENABLE (1UL<<23) 1282#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 1283#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 1284#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 1285#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 1286#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 1287#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 1288#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 1289#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 1290#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 1291#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 1292#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 1293#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 1294#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 1295#define PIPE_DPST_EVENT_STATUS (1UL<<7) 1296#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 1297#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 1298#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 1299#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 1300#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 1301#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 1302#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 1303 1304#define DSPARB 0x70030 1305#define DSPARB_CSTART_MASK (0x7f << 7) 1306#define DSPARB_CSTART_SHIFT 7 1307#define DSPARB_BSTART_MASK (0x7f) 1308#define DSPARB_BSTART_SHIFT 0 1309/* 1310 * The two pipe frame counter registers are not synchronized, so 1311 * reading a stable value is somewhat tricky. The following code 1312 * should work: 1313 * 1314 * do { 1315 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 1316 * PIPE_FRAME_HIGH_SHIFT; 1317 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 1318 * PIPE_FRAME_LOW_SHIFT); 1319 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 1320 * PIPE_FRAME_HIGH_SHIFT); 1321 * } while (high1 != high2); 1322 * frame = (high1 << 8) | low1; 1323 */ 1324#define PIPEAFRAMEHIGH 0x70040 1325#define PIPE_FRAME_HIGH_MASK 0x0000ffff 1326#define PIPE_FRAME_HIGH_SHIFT 0 1327#define PIPEAFRAMEPIXEL 0x70044 1328#define PIPE_FRAME_LOW_MASK 0xff000000 1329#define PIPE_FRAME_LOW_SHIFT 24 1330#define PIPE_PIXEL_MASK 0x00ffffff 1331#define PIPE_PIXEL_SHIFT 0 1332/* GM45+ just has to be different */ 1333#define PIPEA_FRMCOUNT_GM45 0x70040 1334#define PIPEA_FLIPCOUNT_GM45 0x70044 1335 1336/* Cursor A & B regs */ 1337#define CURACNTR 0x70080 1338#define CURSOR_MODE_DISABLE 0x00 1339#define CURSOR_MODE_64_32B_AX 0x07 1340#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 1341#define MCURSOR_GAMMA_ENABLE (1 << 26) 1342#define CURABASE 0x70084 1343#define CURAPOS 0x70088 1344#define CURSOR_POS_MASK 0x007FF 1345#define CURSOR_POS_SIGN 0x8000 1346#define CURSOR_X_SHIFT 0 1347#define CURSOR_Y_SHIFT 16 1348#define CURBCNTR 0x700c0 1349#define CURBBASE 0x700c4 1350#define CURBPOS 0x700c8 1351 1352/* Display A control */ 1353#define DSPACNTR 0x70180 1354#define DISPLAY_PLANE_ENABLE (1<<31) 1355#define DISPLAY_PLANE_DISABLE 0 1356#define DISPPLANE_GAMMA_ENABLE (1<<30) 1357#define DISPPLANE_GAMMA_DISABLE 0 1358#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 1359#define DISPPLANE_8BPP (0x2<<26) 1360#define DISPPLANE_15_16BPP (0x4<<26) 1361#define DISPPLANE_16BPP (0x5<<26) 1362#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 1363#define DISPPLANE_32BPP (0x7<<26) 1364#define DISPPLANE_STEREO_ENABLE (1<<25) 1365#define DISPPLANE_STEREO_DISABLE 0 1366#define DISPPLANE_SEL_PIPE_MASK (1<<24) 1367#define DISPPLANE_SEL_PIPE_A 0 1368#define DISPPLANE_SEL_PIPE_B (1<<24) 1369#define DISPPLANE_SRC_KEY_ENABLE (1<<22) 1370#define DISPPLANE_SRC_KEY_DISABLE 0 1371#define DISPPLANE_LINE_DOUBLE (1<<20) 1372#define DISPPLANE_NO_LINE_DOUBLE 0 1373#define DISPPLANE_STEREO_POLARITY_FIRST 0 1374#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 1375#define DSPAADDR 0x70184 1376#define DSPASTRIDE 0x70188 1377#define DSPAPOS 0x7018C /* reserved */ 1378#define DSPASIZE 0x70190 1379#define DSPASURF 0x7019C /* 965+ only */ 1380#define DSPATILEOFF 0x701A4 /* 965+ only */ 1381 1382/* VBIOS flags */ 1383#define SWF00 0x71410 1384#define SWF01 0x71414 1385#define SWF02 0x71418 1386#define SWF03 0x7141c 1387#define SWF04 0x71420 1388#define SWF05 0x71424 1389#define SWF06 0x71428 1390#define SWF10 0x70410 1391#define SWF11 0x70414 1392#define SWF14 0x71420 1393#define SWF30 0x72414 1394#define SWF31 0x72418 1395#define SWF32 0x7241c 1396 1397/* Pipe B */ 1398#define PIPEBDSL 0x71000 1399#define PIPEBCONF 0x71008 1400#define PIPEBSTAT 0x71024 1401#define PIPEBFRAMEHIGH 0x71040 1402#define PIPEBFRAMEPIXEL 0x71044 1403#define PIPEB_FRMCOUNT_GM45 0x71040 1404#define PIPEB_FLIPCOUNT_GM45 0x71044 1405 1406/* Display B control */ 1407#define DSPBCNTR 0x71180 1408#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 1409#define DISPPLANE_ALPHA_TRANS_DISABLE 0 1410#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 1411#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 1412#define DSPBADDR 0x71184 1413#define DSPBSTRIDE 0x71188 1414#define DSPBPOS 0x7118C 1415#define DSPBSIZE 0x71190 1416#define DSPBSURF 0x7119C 1417#define DSPBTILEOFF 0x711A4 1418 1419/* VBIOS regs */ 1420#define VGACNTRL 0x71400 1421# define VGA_DISP_DISABLE (1 << 31) 1422# define VGA_2X_MODE (1 << 30) 1423# define VGA_PIPE_B_SELECT (1 << 29) 1424 1425#endif /* _I915_REG_H_ */ 1426