1189049Srnoland/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2189049Srnoland * All Rights Reserved. 3189049Srnoland * 4189049Srnoland * Permission is hereby granted, free of charge, to any person obtaining a 5189049Srnoland * copy of this software and associated documentation files (the 6189049Srnoland * "Software"), to deal in the Software without restriction, including 7189049Srnoland * without limitation the rights to use, copy, modify, merge, publish, 8189049Srnoland * distribute, sub license, and/or sell copies of the Software, and to 9189049Srnoland * permit persons to whom the Software is furnished to do so, subject to 10189049Srnoland * the following conditions: 11189049Srnoland * 12189049Srnoland * The above copyright notice and this permission notice (including the 13189049Srnoland * next paragraph) shall be included in all copies or substantial portions 14189049Srnoland * of the Software. 15189049Srnoland * 16189049Srnoland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17189049Srnoland * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18189049Srnoland * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19189049Srnoland * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20189049Srnoland * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21189049Srnoland * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22189049Srnoland * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23189049Srnoland */ 24189049Srnoland 25189049Srnoland#include <sys/cdefs.h> 26189049Srnoland__FBSDID("$FreeBSD$"); 27189049Srnoland 28189049Srnoland#ifndef _I915_REG_H_ 29189049Srnoland#define _I915_REG_H_ 30189049Srnoland 31189049Srnoland/* 32189049Srnoland * The Bridge device's PCI config space has information about the 33189049Srnoland * fb aperture size and the amount of pre-reserved memory. 34189049Srnoland */ 35189049Srnoland#define INTEL_GMCH_CTRL 0x52 36189049Srnoland#define INTEL_GMCH_ENABLED 0x4 37189049Srnoland#define INTEL_GMCH_MEM_MASK 0x1 38189049Srnoland#define INTEL_GMCH_MEM_64M 0x1 39189049Srnoland#define INTEL_GMCH_MEM_128M 0 40189049Srnoland 41190020Srnoland#define INTEL_GMCH_GMS_MASK (0xf << 4) 42189049Srnoland#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) 43189049Srnoland#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) 44189049Srnoland#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) 45189049Srnoland#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4) 46189049Srnoland#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4) 47189049Srnoland#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4) 48189049Srnoland 49189049Srnoland#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4) 50189049Srnoland#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4) 51190020Srnoland#define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4) 52190020Srnoland#define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4) 53190020Srnoland#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 54190020Srnoland#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 55190020Srnoland#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 56190020Srnoland#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 57189049Srnoland 58189049Srnoland/* PCI config space */ 59189049Srnoland 60189049Srnoland#define HPLLCC 0xc0 /* 855 only */ 61189049Srnoland#define GC_CLOCK_CONTROL_MASK (3 << 0) 62189049Srnoland#define GC_CLOCK_133_200 (0 << 0) 63189049Srnoland#define GC_CLOCK_100_200 (1 << 0) 64189049Srnoland#define GC_CLOCK_100_133 (2 << 0) 65189049Srnoland#define GC_CLOCK_166_250 (3 << 0) 66189049Srnoland#define GCFGC 0xf0 /* 915+ only */ 67189049Srnoland#define GC_LOW_FREQUENCY_ENABLE (1 << 7) 68189049Srnoland#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 69189049Srnoland#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 70189049Srnoland#define GC_DISPLAY_CLOCK_MASK (7 << 4) 71189049Srnoland#define LBB 0xf4 72189049Srnoland 73189049Srnoland/* VGA stuff */ 74189049Srnoland 75189049Srnoland#define VGA_ST01_MDA 0x3ba 76189049Srnoland#define VGA_ST01_CGA 0x3da 77189049Srnoland 78189049Srnoland#define VGA_MSR_WRITE 0x3c2 79189049Srnoland#define VGA_MSR_READ 0x3cc 80189049Srnoland#define VGA_MSR_MEM_EN (1<<1) 81189049Srnoland#define VGA_MSR_CGA_MODE (1<<0) 82189049Srnoland 83189049Srnoland#define VGA_SR_INDEX 0x3c4 84189049Srnoland#define VGA_SR_DATA 0x3c5 85189049Srnoland 86189049Srnoland#define VGA_AR_INDEX 0x3c0 87189049Srnoland#define VGA_AR_VID_EN (1<<5) 88189049Srnoland#define VGA_AR_DATA_WRITE 0x3c0 89189049Srnoland#define VGA_AR_DATA_READ 0x3c1 90189049Srnoland 91189049Srnoland#define VGA_GR_INDEX 0x3ce 92189049Srnoland#define VGA_GR_DATA 0x3cf 93189049Srnoland/* GR05 */ 94189049Srnoland#define VGA_GR_MEM_READ_MODE_SHIFT 3 95189049Srnoland#define VGA_GR_MEM_READ_MODE_PLANE 1 96189049Srnoland/* GR06 */ 97189049Srnoland#define VGA_GR_MEM_MODE_MASK 0xc 98189049Srnoland#define VGA_GR_MEM_MODE_SHIFT 2 99189049Srnoland#define VGA_GR_MEM_A0000_AFFFF 0 100189049Srnoland#define VGA_GR_MEM_A0000_BFFFF 1 101189049Srnoland#define VGA_GR_MEM_B0000_B7FFF 2 102189049Srnoland#define VGA_GR_MEM_B0000_BFFFF 3 103189049Srnoland 104189049Srnoland#define VGA_DACMASK 0x3c6 105189049Srnoland#define VGA_DACRX 0x3c7 106189049Srnoland#define VGA_DACWX 0x3c8 107189049Srnoland#define VGA_DACDATA 0x3c9 108189049Srnoland 109189049Srnoland#define VGA_CR_INDEX_MDA 0x3b4 110189049Srnoland#define VGA_CR_DATA_MDA 0x3b5 111189049Srnoland#define VGA_CR_INDEX_CGA 0x3d4 112189049Srnoland#define VGA_CR_DATA_CGA 0x3d5 113189049Srnoland 114189049Srnoland/* 115189049Srnoland * Memory interface instructions used by the kernel 116189049Srnoland */ 117189049Srnoland#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 118189049Srnoland 119189049Srnoland#define MI_NOOP MI_INSTR(0, 0) 120189049Srnoland#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 121189049Srnoland#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 122189049Srnoland#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 123189049Srnoland#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 124189049Srnoland#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 125189049Srnoland#define MI_FLUSH MI_INSTR(0x04, 0) 126189049Srnoland#define MI_READ_FLUSH (1 << 0) 127189049Srnoland#define MI_EXE_FLUSH (1 << 1) 128189049Srnoland#define MI_NO_WRITE_FLUSH (1 << 2) 129189049Srnoland#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 130189049Srnoland#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 131189049Srnoland#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 132189049Srnoland#define MI_REPORT_HEAD MI_INSTR(0x07, 0) 133189049Srnoland#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 134189049Srnoland#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 135189049Srnoland#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 136189049Srnoland#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 137189049Srnoland#define MI_STORE_DWORD_INDEX_SHIFT 2 138189049Srnoland#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1) 139189049Srnoland#define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 140189049Srnoland#define MI_BATCH_NON_SECURE (1) 141189049Srnoland#define MI_BATCH_NON_SECURE_I965 (1<<8) 142189049Srnoland#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 143189049Srnoland 144189049Srnoland/* 145189049Srnoland * 3D instructions used by the kernel 146189049Srnoland */ 147189049Srnoland#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 148189049Srnoland 149189049Srnoland#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 150189049Srnoland#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 151189049Srnoland#define SC_UPDATE_SCISSOR (0x1<<1) 152189049Srnoland#define SC_ENABLE_MASK (0x1<<0) 153189049Srnoland#define SC_ENABLE (0x1<<0) 154189049Srnoland#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 155189049Srnoland#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 156189049Srnoland#define SCI_YMIN_MASK (0xffff<<16) 157189049Srnoland#define SCI_XMIN_MASK (0xffff<<0) 158189049Srnoland#define SCI_YMAX_MASK (0xffff<<16) 159189049Srnoland#define SCI_XMAX_MASK (0xffff<<0) 160189049Srnoland#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 161189049Srnoland#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 162189049Srnoland#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 163189049Srnoland#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 164189049Srnoland#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 165189049Srnoland#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 166189049Srnoland#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 167189049Srnoland#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 168189049Srnoland#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 169189049Srnoland#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 170189049Srnoland#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 171189049Srnoland#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 172189049Srnoland#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 173189049Srnoland#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 174189049Srnoland#define BLT_DEPTH_8 (0<<24) 175189049Srnoland#define BLT_DEPTH_16_565 (1<<24) 176189049Srnoland#define BLT_DEPTH_16_1555 (2<<24) 177189049Srnoland#define BLT_DEPTH_32 (3<<24) 178189049Srnoland#define BLT_ROP_GXCOPY (0xcc<<16) 179189049Srnoland#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 180189049Srnoland#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 181189049Srnoland#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 182189049Srnoland#define ASYNC_FLIP (1<<22) 183189049Srnoland#define DISPLAY_PLANE_A (0<<20) 184189049Srnoland#define DISPLAY_PLANE_B (1<<20) 185189049Srnoland 186189049Srnoland/* 187190020Srnoland * Fence registers 188190020Srnoland */ 189190020Srnoland#define FENCE_REG_830_0 0x2000 190190020Srnoland#define FENCE_REG_945_8 0x3000 191190020Srnoland#define I830_FENCE_START_MASK 0x07f80000 192190020Srnoland#define I830_FENCE_TILING_Y_SHIFT 12 193190020Srnoland#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 194190020Srnoland#define I830_FENCE_PITCH_SHIFT 4 195190020Srnoland#define I830_FENCE_REG_VALID (1<<0) 196190020Srnoland 197190020Srnoland#define I915_FENCE_START_MASK 0x0ff00000 198190020Srnoland#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 199190020Srnoland 200190020Srnoland#define FENCE_REG_965_0 0x03000 201190020Srnoland#define I965_FENCE_PITCH_SHIFT 2 202190020Srnoland#define I965_FENCE_TILING_Y_SHIFT 1 203190020Srnoland#define I965_FENCE_REG_VALID (1<<0) 204190020Srnoland 205190020Srnoland/* 206189049Srnoland * Instruction and interrupt control regs 207189049Srnoland */ 208189049Srnoland#define PRB0_TAIL 0x02030 209189049Srnoland#define PRB0_HEAD 0x02034 210189049Srnoland#define PRB0_START 0x02038 211189049Srnoland#define PRB0_CTL 0x0203c 212189049Srnoland#define TAIL_ADDR 0x001FFFF8 213189049Srnoland#define HEAD_WRAP_COUNT 0xFFE00000 214189049Srnoland#define HEAD_WRAP_ONE 0x00200000 215189049Srnoland#define HEAD_ADDR 0x001FFFFC 216189049Srnoland#define RING_NR_PAGES 0x001FF000 217189049Srnoland#define RING_REPORT_MASK 0x00000006 218189049Srnoland#define RING_REPORT_64K 0x00000002 219189049Srnoland#define RING_REPORT_128K 0x00000004 220189049Srnoland#define RING_NO_REPORT 0x00000000 221189049Srnoland#define RING_VALID_MASK 0x00000001 222189049Srnoland#define RING_VALID 0x00000001 223189049Srnoland#define RING_INVALID 0x00000000 224189049Srnoland#define PRB1_TAIL 0x02040 /* 915+ only */ 225189049Srnoland#define PRB1_HEAD 0x02044 /* 915+ only */ 226189049Srnoland#define PRB1_START 0x02048 /* 915+ only */ 227189049Srnoland#define PRB1_CTL 0x0204c /* 915+ only */ 228189049Srnoland#define ACTHD_I965 0x02074 229189049Srnoland#define HWS_PGA 0x02080 230189049Srnoland#define HWS_ADDRESS_MASK 0xfffff000 231189049Srnoland#define HWS_START_ADDRESS_SHIFT 4 232189049Srnoland#define IPEIR 0x02088 233189049Srnoland#define NOPID 0x02094 234189049Srnoland#define HWSTAM 0x02098 235189049Srnoland#define SCPD0 0x0209c /* 915+ only */ 236189049Srnoland#define IER 0x020a0 237189049Srnoland#define IIR 0x020a4 238189049Srnoland#define IMR 0x020a8 239189049Srnoland#define ISR 0x020ac 240189049Srnoland#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 241189049Srnoland#define I915_DISPLAY_PORT_INTERRUPT (1<<17) 242189049Srnoland#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 243189049Srnoland#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) 244189049Srnoland#define I915_HWB_OOM_INTERRUPT (1<<13) 245189049Srnoland#define I915_SYNC_STATUS_INTERRUPT (1<<12) 246189049Srnoland#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 247189049Srnoland#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 248189049Srnoland#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 249189049Srnoland#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 250189049Srnoland#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 251189049Srnoland#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 252189049Srnoland#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 253189049Srnoland#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 254189049Srnoland#define I915_DEBUG_INTERRUPT (1<<2) 255189049Srnoland#define I915_USER_INTERRUPT (1<<1) 256189049Srnoland#define I915_ASLE_INTERRUPT (1<<0) 257189049Srnoland#define EIR 0x020b0 258189049Srnoland#define EMR 0x020b4 259189049Srnoland#define ESR 0x020b8 260189049Srnoland#define INSTPM 0x020c0 261189049Srnoland#define ACTHD 0x020c8 262189049Srnoland#define FW_BLC 0x020d8 263189049Srnoland#define FW_BLC_SELF 0x020e0 /* 915+ only */ 264189049Srnoland#define MI_ARB_STATE 0x020e4 /* 915+ only */ 265189049Srnoland#define CACHE_MODE_0 0x02120 /* 915+ only */ 266189049Srnoland#define CM0_MASK_SHIFT 16 267189049Srnoland#define CM0_IZ_OPT_DISABLE (1<<6) 268189049Srnoland#define CM0_ZR_OPT_DISABLE (1<<5) 269189049Srnoland#define CM0_DEPTH_EVICT_DISABLE (1<<4) 270189049Srnoland#define CM0_COLOR_EVICT_DISABLE (1<<3) 271189049Srnoland#define CM0_DEPTH_WRITE_DISABLE (1<<1) 272189049Srnoland#define CM0_RC_OP_FLUSH_DISABLE (1<<0) 273189049Srnoland#define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 274189049Srnoland 275190020Srnoland 276189049Srnoland/* 277189049Srnoland * Framebuffer compression (915+ only) 278189049Srnoland */ 279189049Srnoland 280189049Srnoland#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 281189049Srnoland#define FBC_LL_BASE 0x03204 /* 4k page aligned */ 282189049Srnoland#define FBC_CONTROL 0x03208 283189049Srnoland#define FBC_CTL_EN (1<<31) 284189049Srnoland#define FBC_CTL_PERIODIC (1<<30) 285189049Srnoland#define FBC_CTL_INTERVAL_SHIFT (16) 286189049Srnoland#define FBC_CTL_UNCOMPRESSIBLE (1<<14) 287189049Srnoland#define FBC_CTL_STRIDE_SHIFT (5) 288189049Srnoland#define FBC_CTL_FENCENO (1<<0) 289189049Srnoland#define FBC_COMMAND 0x0320c 290189049Srnoland#define FBC_CMD_COMPRESS (1<<0) 291189049Srnoland#define FBC_STATUS 0x03210 292189049Srnoland#define FBC_STAT_COMPRESSING (1<<31) 293189049Srnoland#define FBC_STAT_COMPRESSED (1<<30) 294189049Srnoland#define FBC_STAT_MODIFIED (1<<29) 295189049Srnoland#define FBC_STAT_CURRENT_LINE (1<<0) 296189049Srnoland#define FBC_CONTROL2 0x03214 297189049Srnoland#define FBC_CTL_FENCE_DBL (0<<4) 298189049Srnoland#define FBC_CTL_IDLE_IMM (0<<2) 299189049Srnoland#define FBC_CTL_IDLE_FULL (1<<2) 300189049Srnoland#define FBC_CTL_IDLE_LINE (2<<2) 301189049Srnoland#define FBC_CTL_IDLE_DEBUG (3<<2) 302189049Srnoland#define FBC_CTL_CPU_FENCE (1<<1) 303189049Srnoland#define FBC_CTL_PLANEA (0<<0) 304189049Srnoland#define FBC_CTL_PLANEB (1<<0) 305189049Srnoland#define FBC_FENCE_OFF 0x0321b 306189049Srnoland 307189049Srnoland#define FBC_LL_SIZE (1536) 308189049Srnoland 309189049Srnoland/* 310189049Srnoland * GPIO regs 311189049Srnoland */ 312189049Srnoland#define GPIOA 0x5010 313189049Srnoland#define GPIOB 0x5014 314189049Srnoland#define GPIOC 0x5018 315189049Srnoland#define GPIOD 0x501c 316189049Srnoland#define GPIOE 0x5020 317189049Srnoland#define GPIOF 0x5024 318189049Srnoland#define GPIOG 0x5028 319189049Srnoland#define GPIOH 0x502c 320189049Srnoland# define GPIO_CLOCK_DIR_MASK (1 << 0) 321189049Srnoland# define GPIO_CLOCK_DIR_IN (0 << 1) 322189049Srnoland# define GPIO_CLOCK_DIR_OUT (1 << 1) 323189049Srnoland# define GPIO_CLOCK_VAL_MASK (1 << 2) 324189049Srnoland# define GPIO_CLOCK_VAL_OUT (1 << 3) 325189049Srnoland# define GPIO_CLOCK_VAL_IN (1 << 4) 326189049Srnoland# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 327189049Srnoland# define GPIO_DATA_DIR_MASK (1 << 8) 328189049Srnoland# define GPIO_DATA_DIR_IN (0 << 9) 329189049Srnoland# define GPIO_DATA_DIR_OUT (1 << 9) 330189049Srnoland# define GPIO_DATA_VAL_MASK (1 << 10) 331189049Srnoland# define GPIO_DATA_VAL_OUT (1 << 11) 332189049Srnoland# define GPIO_DATA_VAL_IN (1 << 12) 333189049Srnoland# define GPIO_DATA_PULLUP_DISABLE (1 << 13) 334189049Srnoland 335189049Srnoland/* 336189049Srnoland * Clock control & power management 337189049Srnoland */ 338189049Srnoland 339189049Srnoland#define VGA0 0x6000 340189049Srnoland#define VGA1 0x6004 341189049Srnoland#define VGA_PD 0x6010 342189049Srnoland#define VGA0_PD_P2_DIV_4 (1 << 7) 343189049Srnoland#define VGA0_PD_P1_DIV_2 (1 << 5) 344189049Srnoland#define VGA0_PD_P1_SHIFT 0 345189049Srnoland#define VGA0_PD_P1_MASK (0x1f << 0) 346189049Srnoland#define VGA1_PD_P2_DIV_4 (1 << 15) 347189049Srnoland#define VGA1_PD_P1_DIV_2 (1 << 13) 348189049Srnoland#define VGA1_PD_P1_SHIFT 8 349189049Srnoland#define VGA1_PD_P1_MASK (0x1f << 8) 350189049Srnoland#define DPLL_A 0x06014 351189049Srnoland#define DPLL_B 0x06018 352189049Srnoland#define DPLL_VCO_ENABLE (1 << 31) 353189049Srnoland#define DPLL_DVO_HIGH_SPEED (1 << 30) 354189049Srnoland#define DPLL_SYNCLOCK_ENABLE (1 << 29) 355189049Srnoland#define DPLL_VGA_MODE_DIS (1 << 28) 356189049Srnoland#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 357189049Srnoland#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 358189049Srnoland#define DPLL_MODE_MASK (3 << 26) 359189049Srnoland#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 360189049Srnoland#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 361189049Srnoland#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 362189049Srnoland#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 363189049Srnoland#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 364189049Srnoland#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 365205120Srnoland#define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */ 366189049Srnoland 367189049Srnoland#define I915_FIFO_UNDERRUN_STATUS (1UL<<31) 368189049Srnoland#define I915_CRC_ERROR_ENABLE (1UL<<29) 369189049Srnoland#define I915_CRC_DONE_ENABLE (1UL<<28) 370189049Srnoland#define I915_GMBUS_EVENT_ENABLE (1UL<<27) 371189049Srnoland#define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) 372189049Srnoland#define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 373189049Srnoland#define I915_DPST_EVENT_ENABLE (1UL<<23) 374189049Srnoland#define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 375189049Srnoland#define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 376189049Srnoland#define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 377189049Srnoland#define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 378189049Srnoland#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) 379189049Srnoland#define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) 380189049Srnoland#define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 381189049Srnoland#define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 382189049Srnoland#define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) 383189049Srnoland#define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) 384189049Srnoland#define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 385189049Srnoland#define I915_DPST_EVENT_STATUS (1UL<<7) 386189049Srnoland#define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) 387189049Srnoland#define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 388189049Srnoland#define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 389189049Srnoland#define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 390189049Srnoland#define I915_VBLANK_INTERRUPT_STATUS (1UL<<1) 391189049Srnoland#define I915_OVERLAY_UPDATED_STATUS (1UL<<0) 392189049Srnoland 393189049Srnoland#define SRX_INDEX 0x3c4 394189049Srnoland#define SRX_DATA 0x3c5 395189049Srnoland#define SR01 1 396189049Srnoland#define SR01_SCREEN_OFF (1<<5) 397189049Srnoland 398189049Srnoland#define PPCR 0x61204 399189049Srnoland#define PPCR_ON (1<<0) 400189049Srnoland 401189049Srnoland#define DVOB 0x61140 402189049Srnoland#define DVOB_ON (1<<31) 403189049Srnoland#define DVOC 0x61160 404189049Srnoland#define DVOC_ON (1<<31) 405189049Srnoland#define LVDS 0x61180 406189049Srnoland#define LVDS_ON (1<<31) 407189049Srnoland 408189049Srnoland#define ADPA 0x61100 409189049Srnoland#define ADPA_DPMS_MASK (~(3<<10)) 410189049Srnoland#define ADPA_DPMS_ON (0<<10) 411189049Srnoland#define ADPA_DPMS_SUSPEND (1<<10) 412189049Srnoland#define ADPA_DPMS_STANDBY (2<<10) 413189049Srnoland#define ADPA_DPMS_OFF (3<<10) 414189049Srnoland 415189049Srnoland#define RING_TAIL 0x00 416189049Srnoland#define TAIL_ADDR 0x001FFFF8 417189049Srnoland#define RING_HEAD 0x04 418189049Srnoland#define HEAD_WRAP_COUNT 0xFFE00000 419189049Srnoland#define HEAD_WRAP_ONE 0x00200000 420189049Srnoland#define HEAD_ADDR 0x001FFFFC 421189049Srnoland#define RING_START 0x08 422189049Srnoland#define START_ADDR 0xFFFFF000 423189049Srnoland#define RING_LEN 0x0C 424189049Srnoland#define RING_NR_PAGES 0x001FF000 425189049Srnoland#define RING_REPORT_MASK 0x00000006 426189049Srnoland#define RING_REPORT_64K 0x00000002 427189049Srnoland#define RING_REPORT_128K 0x00000004 428189049Srnoland#define RING_NO_REPORT 0x00000000 429189049Srnoland#define RING_VALID_MASK 0x00000001 430189049Srnoland#define RING_VALID 0x00000001 431189049Srnoland#define RING_INVALID 0x00000000 432189049Srnoland 433189049Srnoland/* Scratch pad debug 0 reg: 434189049Srnoland */ 435189049Srnoland#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 436189049Srnoland/* 437189049Srnoland * The i830 generation, in LVDS mode, defines P1 as the bit number set within 438189049Srnoland * this field (only one bit may be set). 439189049Srnoland */ 440189049Srnoland#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 441189049Srnoland#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 442205120Srnoland#define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15 443189049Srnoland/* i830, required in DVO non-gang */ 444189049Srnoland#define PLL_P2_DIVIDE_BY_4 (1 << 23) 445189049Srnoland#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 446189049Srnoland#define PLL_REF_INPUT_DREFCLK (0 << 13) 447189049Srnoland#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 448189049Srnoland#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 449189049Srnoland#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 450189049Srnoland#define PLL_REF_INPUT_MASK (3 << 13) 451189049Srnoland#define PLL_LOAD_PULSE_PHASE_SHIFT 9 452189049Srnoland/* 453189049Srnoland * Parallel to Serial Load Pulse phase selection. 454189049Srnoland * Selects the phase for the 10X DPLL clock for the PCIe 455189049Srnoland * digital display port. The range is 4 to 13; 10 or more 456189049Srnoland * is just a flip delay. The default is 6 457189049Srnoland */ 458189049Srnoland#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 459189049Srnoland#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 460189049Srnoland/* 461189049Srnoland * SDVO multiplier for 945G/GM. Not used on 965. 462189049Srnoland */ 463189049Srnoland#define SDVO_MULTIPLIER_MASK 0x000000ff 464189049Srnoland#define SDVO_MULTIPLIER_SHIFT_HIRES 4 465189049Srnoland#define SDVO_MULTIPLIER_SHIFT_VGA 0 466189049Srnoland#define DPLL_A_MD 0x0601c /* 965+ only */ 467189049Srnoland/* 468189049Srnoland * UDI pixel divider, controlling how many pixels are stuffed into a packet. 469189049Srnoland * 470189049Srnoland * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 471189049Srnoland */ 472189049Srnoland#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 473189049Srnoland#define DPLL_MD_UDI_DIVIDER_SHIFT 24 474189049Srnoland/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 475189049Srnoland#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 476189049Srnoland#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 477189049Srnoland/* 478189049Srnoland * SDVO/UDI pixel multiplier. 479189049Srnoland * 480189049Srnoland * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 481189049Srnoland * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 482189049Srnoland * modes, the bus rate would be below the limits, so SDVO allows for stuffing 483189049Srnoland * dummy bytes in the datastream at an increased clock rate, with both sides of 484189049Srnoland * the link knowing how many bytes are fill. 485189049Srnoland * 486189049Srnoland * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 487189049Srnoland * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 488189049Srnoland * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 489189049Srnoland * through an SDVO command. 490189049Srnoland * 491189049Srnoland * This register field has values of multiplication factor minus 1, with 492189049Srnoland * a maximum multiplier of 5 for SDVO. 493189049Srnoland */ 494189049Srnoland#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 495189049Srnoland#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 496189049Srnoland/* 497189049Srnoland * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 498189049Srnoland * This best be set to the default value (3) or the CRT won't work. No, 499189049Srnoland * I don't entirely understand what this does... 500189049Srnoland */ 501189049Srnoland#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 502189049Srnoland#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 503189049Srnoland#define DPLL_B_MD 0x06020 /* 965+ only */ 504189049Srnoland#define FPA0 0x06040 505189049Srnoland#define FPA1 0x06044 506189049Srnoland#define FPB0 0x06048 507189049Srnoland#define FPB1 0x0604c 508189049Srnoland#define FP_N_DIV_MASK 0x003f0000 509205120Srnoland#define FP_N_IGD_DIV_MASK 0x00ff0000 510189049Srnoland#define FP_N_DIV_SHIFT 16 511189049Srnoland#define FP_M1_DIV_MASK 0x00003f00 512189049Srnoland#define FP_M1_DIV_SHIFT 8 513189049Srnoland#define FP_M2_DIV_MASK 0x0000003f 514205120Srnoland#define FP_M2_IGD_DIV_MASK 0x000000ff 515189049Srnoland#define FP_M2_DIV_SHIFT 0 516189049Srnoland#define DPLL_TEST 0x606c 517189049Srnoland#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 518189049Srnoland#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 519189049Srnoland#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 520189049Srnoland#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 521189049Srnoland#define DPLLB_TEST_N_BYPASS (1 << 19) 522189049Srnoland#define DPLLB_TEST_M_BYPASS (1 << 18) 523189049Srnoland#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 524189049Srnoland#define DPLLA_TEST_N_BYPASS (1 << 3) 525189049Srnoland#define DPLLA_TEST_M_BYPASS (1 << 2) 526189049Srnoland#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 527189049Srnoland#define D_STATE 0x6104 528189049Srnoland#define CG_2D_DIS 0x6200 529189049Srnoland#define CG_3D_DIS 0x6204 530189049Srnoland 531189049Srnoland/* 532189049Srnoland * Palette regs 533189049Srnoland */ 534189049Srnoland 535189049Srnoland#define PALETTE_A 0x0a000 536189049Srnoland#define PALETTE_B 0x0a800 537189049Srnoland 538189049Srnoland/* MCH MMIO space */ 539189049Srnoland 540189049Srnoland/* 541189049Srnoland * MCHBAR mirror. 542189049Srnoland * 543189049Srnoland * This mirrors the MCHBAR MMIO space whose location is determined by 544189049Srnoland * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 545189049Srnoland * every way. It is not accessible from the CP register read instructions. 546189049Srnoland * 547189049Srnoland */ 548189049Srnoland#define MCHBAR_MIRROR_BASE 0x10000 549189049Srnoland 550189049Srnoland/** 915-945 and GM965 MCH register controlling DRAM channel access */ 551189049Srnoland#define DCC 0x10200 552189049Srnoland#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 553189049Srnoland#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 554189049Srnoland#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 555189049Srnoland#define DCC_ADDRESSING_MODE_MASK (3 << 0) 556189049Srnoland#define DCC_CHANNEL_XOR_DISABLE (1 << 10) 557190020Srnoland#define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 558189049Srnoland 559189049Srnoland/** 965 MCH register controlling DRAM channel configuration */ 560189049Srnoland#define C0DRB3 0x10206 561189049Srnoland#define C1DRB3 0x10606 562189049Srnoland 563190020Srnoland/** GM965 GM45 render standby register */ 564190020Srnoland#define MCHBAR_RENDER_STANDBY 0x111B8 565190020Srnoland 566190020Srnoland#define PEG_BAND_GAP_DATA 0x14d68 567190020Srnoland 568189049Srnoland/* 569189049Srnoland * Overlay regs 570189049Srnoland */ 571189049Srnoland 572189049Srnoland#define OVADD 0x30000 573189049Srnoland#define DOVSTA 0x30008 574189049Srnoland#define OC_BUF (0x3<<20) 575189049Srnoland#define OGAMC5 0x30010 576189049Srnoland#define OGAMC4 0x30014 577189049Srnoland#define OGAMC3 0x30018 578189049Srnoland#define OGAMC2 0x3001c 579189049Srnoland#define OGAMC1 0x30020 580189049Srnoland#define OGAMC0 0x30024 581189049Srnoland 582189049Srnoland/* 583189049Srnoland * Display engine regs 584189049Srnoland */ 585189049Srnoland 586189049Srnoland/* Pipe A timing regs */ 587189049Srnoland#define HTOTAL_A 0x60000 588189049Srnoland#define HBLANK_A 0x60004 589189049Srnoland#define HSYNC_A 0x60008 590189049Srnoland#define VTOTAL_A 0x6000c 591189049Srnoland#define VBLANK_A 0x60010 592189049Srnoland#define VSYNC_A 0x60014 593189049Srnoland#define PIPEASRC 0x6001c 594189049Srnoland#define BCLRPAT_A 0x60020 595189049Srnoland 596189049Srnoland/* Pipe B timing regs */ 597189049Srnoland#define HTOTAL_B 0x61000 598189049Srnoland#define HBLANK_B 0x61004 599189049Srnoland#define HSYNC_B 0x61008 600189049Srnoland#define VTOTAL_B 0x6100c 601189049Srnoland#define VBLANK_B 0x61010 602189049Srnoland#define VSYNC_B 0x61014 603189049Srnoland#define PIPEBSRC 0x6101c 604189049Srnoland#define BCLRPAT_B 0x61020 605189049Srnoland 606189049Srnoland/* VGA port control */ 607189049Srnoland#define ADPA 0x61100 608189049Srnoland#define ADPA_DAC_ENABLE (1<<31) 609189049Srnoland#define ADPA_DAC_DISABLE 0 610189049Srnoland#define ADPA_PIPE_SELECT_MASK (1<<30) 611189049Srnoland#define ADPA_PIPE_A_SELECT 0 612189049Srnoland#define ADPA_PIPE_B_SELECT (1<<30) 613189049Srnoland#define ADPA_USE_VGA_HVPOLARITY (1<<15) 614189049Srnoland#define ADPA_SETS_HVPOLARITY 0 615189049Srnoland#define ADPA_VSYNC_CNTL_DISABLE (1<<11) 616189049Srnoland#define ADPA_VSYNC_CNTL_ENABLE 0 617189049Srnoland#define ADPA_HSYNC_CNTL_DISABLE (1<<10) 618189049Srnoland#define ADPA_HSYNC_CNTL_ENABLE 0 619189049Srnoland#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 620189049Srnoland#define ADPA_VSYNC_ACTIVE_LOW 0 621189049Srnoland#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 622189049Srnoland#define ADPA_HSYNC_ACTIVE_LOW 0 623189049Srnoland#define ADPA_DPMS_MASK (~(3<<10)) 624189049Srnoland#define ADPA_DPMS_ON (0<<10) 625189049Srnoland#define ADPA_DPMS_SUSPEND (1<<10) 626189049Srnoland#define ADPA_DPMS_STANDBY (2<<10) 627189049Srnoland#define ADPA_DPMS_OFF (3<<10) 628189049Srnoland 629189049Srnoland/* Hotplug control (945+ only) */ 630189049Srnoland#define PORT_HOTPLUG_EN 0x61110 631190020Srnoland#define HDMIB_HOTPLUG_INT_EN (1 << 29) 632190020Srnoland#define HDMIC_HOTPLUG_INT_EN (1 << 28) 633190020Srnoland#define HDMID_HOTPLUG_INT_EN (1 << 27) 634189049Srnoland#define SDVOB_HOTPLUG_INT_EN (1 << 26) 635189049Srnoland#define SDVOC_HOTPLUG_INT_EN (1 << 25) 636189049Srnoland#define TV_HOTPLUG_INT_EN (1 << 18) 637189049Srnoland#define CRT_HOTPLUG_INT_EN (1 << 9) 638189049Srnoland#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 639189049Srnoland 640189049Srnoland#define PORT_HOTPLUG_STAT 0x61114 641190020Srnoland#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) 642190020Srnoland#define HDMIC_HOTPLUG_INT_STATUS (1 << 28) 643190020Srnoland#define HDMID_HOTPLUG_INT_STATUS (1 << 27) 644189049Srnoland#define CRT_HOTPLUG_INT_STATUS (1 << 11) 645189049Srnoland#define TV_HOTPLUG_INT_STATUS (1 << 10) 646189049Srnoland#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 647189049Srnoland#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 648189049Srnoland#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 649189049Srnoland#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 650189049Srnoland#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 651189049Srnoland#define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 652189049Srnoland 653189049Srnoland/* SDVO port control */ 654189049Srnoland#define SDVOB 0x61140 655189049Srnoland#define SDVOC 0x61160 656189049Srnoland#define SDVO_ENABLE (1 << 31) 657189049Srnoland#define SDVO_PIPE_B_SELECT (1 << 30) 658189049Srnoland#define SDVO_STALL_SELECT (1 << 29) 659189049Srnoland#define SDVO_INTERRUPT_ENABLE (1 << 26) 660189049Srnoland/** 661189049Srnoland * 915G/GM SDVO pixel multiplier. 662189049Srnoland * 663189049Srnoland * Programmed value is multiplier - 1, up to 5x. 664189049Srnoland * 665189049Srnoland * \sa DPLL_MD_UDI_MULTIPLIER_MASK 666189049Srnoland */ 667189049Srnoland#define SDVO_PORT_MULTIPLY_MASK (7 << 23) 668189049Srnoland#define SDVO_PORT_MULTIPLY_SHIFT 23 669189049Srnoland#define SDVO_PHASE_SELECT_MASK (15 << 19) 670189049Srnoland#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 671189049Srnoland#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 672189049Srnoland#define SDVOC_GANG_MODE (1 << 16) 673190020Srnoland#define SDVO_ENCODING_SDVO (0x0 << 10) 674190020Srnoland#define SDVO_ENCODING_HDMI (0x2 << 10) 675190020Srnoland/** Requird for HDMI operation */ 676190020Srnoland#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) 677189049Srnoland#define SDVO_BORDER_ENABLE (1 << 7) 678190020Srnoland#define SDVO_AUDIO_ENABLE (1 << 6) 679190020Srnoland/** New with 965, default is to be set */ 680190020Srnoland#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 681190020Srnoland/** New with 965, default is to be set */ 682190020Srnoland#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 683189049Srnoland#define SDVOB_PCIE_CONCURRENCY (1 << 3) 684189049Srnoland#define SDVO_DETECTED (1 << 2) 685189049Srnoland/* Bits to be preserved when writing */ 686189049Srnoland#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) 687189049Srnoland#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) 688189049Srnoland 689189049Srnoland/* DVO port control */ 690189049Srnoland#define DVOA 0x61120 691189049Srnoland#define DVOB 0x61140 692189049Srnoland#define DVOC 0x61160 693189049Srnoland#define DVO_ENABLE (1 << 31) 694189049Srnoland#define DVO_PIPE_B_SELECT (1 << 30) 695189049Srnoland#define DVO_PIPE_STALL_UNUSED (0 << 28) 696189049Srnoland#define DVO_PIPE_STALL (1 << 28) 697189049Srnoland#define DVO_PIPE_STALL_TV (2 << 28) 698189049Srnoland#define DVO_PIPE_STALL_MASK (3 << 28) 699189049Srnoland#define DVO_USE_VGA_SYNC (1 << 15) 700189049Srnoland#define DVO_DATA_ORDER_I740 (0 << 14) 701189049Srnoland#define DVO_DATA_ORDER_FP (1 << 14) 702189049Srnoland#define DVO_VSYNC_DISABLE (1 << 11) 703189049Srnoland#define DVO_HSYNC_DISABLE (1 << 10) 704189049Srnoland#define DVO_VSYNC_TRISTATE (1 << 9) 705189049Srnoland#define DVO_HSYNC_TRISTATE (1 << 8) 706189049Srnoland#define DVO_BORDER_ENABLE (1 << 7) 707189049Srnoland#define DVO_DATA_ORDER_GBRG (1 << 6) 708189049Srnoland#define DVO_DATA_ORDER_RGGB (0 << 6) 709189049Srnoland#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 710189049Srnoland#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 711189049Srnoland#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 712189049Srnoland#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 713189049Srnoland#define DVO_BLANK_ACTIVE_HIGH (1 << 2) 714189049Srnoland#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 715189049Srnoland#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 716189049Srnoland#define DVO_PRESERVE_MASK (0x7<<24) 717189049Srnoland#define DVOA_SRCDIM 0x61124 718189049Srnoland#define DVOB_SRCDIM 0x61144 719189049Srnoland#define DVOC_SRCDIM 0x61164 720189049Srnoland#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 721189049Srnoland#define DVO_SRCDIM_VERTICAL_SHIFT 0 722189049Srnoland 723189049Srnoland/* LVDS port control */ 724189049Srnoland#define LVDS 0x61180 725189049Srnoland/* 726189049Srnoland * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 727189049Srnoland * the DPLL semantics change when the LVDS is assigned to that pipe. 728189049Srnoland */ 729189049Srnoland#define LVDS_PORT_EN (1 << 31) 730189049Srnoland/* Selects pipe B for LVDS data. Must be set on pre-965. */ 731189049Srnoland#define LVDS_PIPEB_SELECT (1 << 30) 732189049Srnoland/* 733189049Srnoland * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 734189049Srnoland * pixel. 735189049Srnoland */ 736189049Srnoland#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 737189049Srnoland#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 738189049Srnoland#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 739189049Srnoland/* 740189049Srnoland * Controls the A3 data pair, which contains the additional LSBs for 24 bit 741189049Srnoland * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 742189049Srnoland * on. 743189049Srnoland */ 744189049Srnoland#define LVDS_A3_POWER_MASK (3 << 6) 745189049Srnoland#define LVDS_A3_POWER_DOWN (0 << 6) 746189049Srnoland#define LVDS_A3_POWER_UP (3 << 6) 747189049Srnoland/* 748189049Srnoland * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 749189049Srnoland * is set. 750189049Srnoland */ 751189049Srnoland#define LVDS_CLKB_POWER_MASK (3 << 4) 752189049Srnoland#define LVDS_CLKB_POWER_DOWN (0 << 4) 753189049Srnoland#define LVDS_CLKB_POWER_UP (3 << 4) 754189049Srnoland/* 755189049Srnoland * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 756189049Srnoland * setting for whether we are in dual-channel mode. The B3 pair will 757189049Srnoland * additionally only be powered up when LVDS_A3_POWER_UP is set. 758189049Srnoland */ 759189049Srnoland#define LVDS_B0B3_POWER_MASK (3 << 2) 760189049Srnoland#define LVDS_B0B3_POWER_DOWN (0 << 2) 761189049Srnoland#define LVDS_B0B3_POWER_UP (3 << 2) 762189049Srnoland 763189049Srnoland/* Panel power sequencing */ 764189049Srnoland#define PP_STATUS 0x61200 765189049Srnoland#define PP_ON (1 << 31) 766189049Srnoland/* 767189049Srnoland * Indicates that all dependencies of the panel are on: 768189049Srnoland * 769189049Srnoland * - PLL enabled 770189049Srnoland * - pipe enabled 771189049Srnoland * - LVDS/DVOB/DVOC on 772189049Srnoland */ 773189049Srnoland#define PP_READY (1 << 30) 774189049Srnoland#define PP_SEQUENCE_NONE (0 << 28) 775189049Srnoland#define PP_SEQUENCE_ON (1 << 28) 776189049Srnoland#define PP_SEQUENCE_OFF (2 << 28) 777189049Srnoland#define PP_SEQUENCE_MASK 0x30000000 778189049Srnoland#define PP_CONTROL 0x61204 779189049Srnoland#define POWER_TARGET_ON (1 << 0) 780189049Srnoland#define PP_ON_DELAYS 0x61208 781189049Srnoland#define PP_OFF_DELAYS 0x6120c 782189049Srnoland#define PP_DIVISOR 0x61210 783189049Srnoland 784189049Srnoland/* Panel fitting */ 785189049Srnoland#define PFIT_CONTROL 0x61230 786189049Srnoland#define PFIT_ENABLE (1 << 31) 787189049Srnoland#define PFIT_PIPE_MASK (3 << 29) 788189049Srnoland#define PFIT_PIPE_SHIFT 29 789189049Srnoland#define VERT_INTERP_DISABLE (0 << 10) 790189049Srnoland#define VERT_INTERP_BILINEAR (1 << 10) 791189049Srnoland#define VERT_INTERP_MASK (3 << 10) 792189049Srnoland#define VERT_AUTO_SCALE (1 << 9) 793189049Srnoland#define HORIZ_INTERP_DISABLE (0 << 6) 794189049Srnoland#define HORIZ_INTERP_BILINEAR (1 << 6) 795189049Srnoland#define HORIZ_INTERP_MASK (3 << 6) 796189049Srnoland#define HORIZ_AUTO_SCALE (1 << 5) 797189049Srnoland#define PANEL_8TO6_DITHER_ENABLE (1 << 3) 798189049Srnoland#define PFIT_PGM_RATIOS 0x61234 799189049Srnoland#define PFIT_VERT_SCALE_MASK 0xfff00000 800189049Srnoland#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 801189049Srnoland#define PFIT_AUTO_RATIOS 0x61238 802189049Srnoland 803189049Srnoland/* Backlight control */ 804189049Srnoland#define BLC_PWM_CTL 0x61254 805189049Srnoland#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 806189049Srnoland#define BLC_PWM_CTL2 0x61250 /* 965+ only */ 807189049Srnoland#define BLM_COMBINATION_MODE (1 << 30) 808189049Srnoland/* 809189049Srnoland * This is the most significant 15 bits of the number of backlight cycles in a 810189049Srnoland * complete cycle of the modulated backlight control. 811189049Srnoland * 812189049Srnoland * The actual value is this field multiplied by two. 813189049Srnoland */ 814189049Srnoland#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 815189049Srnoland#define BLM_LEGACY_MODE (1 << 16) 816189049Srnoland/* 817189049Srnoland * This is the number of cycles out of the backlight modulation cycle for which 818189049Srnoland * the backlight is on. 819189049Srnoland * 820189049Srnoland * This field must be no greater than the number of cycles in the complete 821189049Srnoland * backlight modulation cycle. 822189049Srnoland */ 823189049Srnoland#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 824189049Srnoland#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 825189049Srnoland 826189049Srnoland/* TV port control */ 827189049Srnoland#define TV_CTL 0x68000 828189049Srnoland/** Enables the TV encoder */ 829189049Srnoland# define TV_ENC_ENABLE (1 << 31) 830189049Srnoland/** Sources the TV encoder input from pipe B instead of A. */ 831189049Srnoland# define TV_ENC_PIPEB_SELECT (1 << 30) 832189049Srnoland/** Outputs composite video (DAC A only) */ 833189049Srnoland# define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 834189049Srnoland/** Outputs SVideo video (DAC B/C) */ 835189049Srnoland# define TV_ENC_OUTPUT_SVIDEO (1 << 28) 836189049Srnoland/** Outputs Component video (DAC A/B/C) */ 837189049Srnoland# define TV_ENC_OUTPUT_COMPONENT (2 << 28) 838189049Srnoland/** Outputs Composite and SVideo (DAC A/B/C) */ 839189049Srnoland# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 840189049Srnoland# define TV_TRILEVEL_SYNC (1 << 21) 841189049Srnoland/** Enables slow sync generation (945GM only) */ 842189049Srnoland# define TV_SLOW_SYNC (1 << 20) 843189049Srnoland/** Selects 4x oversampling for 480i and 576p */ 844189049Srnoland# define TV_OVERSAMPLE_4X (0 << 18) 845189049Srnoland/** Selects 2x oversampling for 720p and 1080i */ 846189049Srnoland# define TV_OVERSAMPLE_2X (1 << 18) 847189049Srnoland/** Selects no oversampling for 1080p */ 848189049Srnoland# define TV_OVERSAMPLE_NONE (2 << 18) 849189049Srnoland/** Selects 8x oversampling */ 850189049Srnoland# define TV_OVERSAMPLE_8X (3 << 18) 851189049Srnoland/** Selects progressive mode rather than interlaced */ 852189049Srnoland# define TV_PROGRESSIVE (1 << 17) 853189049Srnoland/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 854189049Srnoland# define TV_PAL_BURST (1 << 16) 855189049Srnoland/** Field for setting delay of Y compared to C */ 856189049Srnoland# define TV_YC_SKEW_MASK (7 << 12) 857189049Srnoland/** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 858189049Srnoland# define TV_ENC_SDP_FIX (1 << 11) 859189049Srnoland/** 860189049Srnoland * Enables a fix for the 915GM only. 861189049Srnoland * 862189049Srnoland * Not sure what it does. 863189049Srnoland */ 864189049Srnoland# define TV_ENC_C0_FIX (1 << 10) 865189049Srnoland/** Bits that must be preserved by software */ 866189049Srnoland# define TV_CTL_SAVE ((3 << 8) | (3 << 6)) 867189049Srnoland# define TV_FUSE_STATE_MASK (3 << 4) 868189049Srnoland/** Read-only state that reports all features enabled */ 869189049Srnoland# define TV_FUSE_STATE_ENABLED (0 << 4) 870189049Srnoland/** Read-only state that reports that Macrovision is disabled in hardware*/ 871189049Srnoland# define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 872189049Srnoland/** Read-only state that reports that TV-out is disabled in hardware. */ 873189049Srnoland# define TV_FUSE_STATE_DISABLED (2 << 4) 874189049Srnoland/** Normal operation */ 875189049Srnoland# define TV_TEST_MODE_NORMAL (0 << 0) 876189049Srnoland/** Encoder test pattern 1 - combo pattern */ 877189049Srnoland# define TV_TEST_MODE_PATTERN_1 (1 << 0) 878189049Srnoland/** Encoder test pattern 2 - full screen vertical 75% color bars */ 879189049Srnoland# define TV_TEST_MODE_PATTERN_2 (2 << 0) 880189049Srnoland/** Encoder test pattern 3 - full screen horizontal 75% color bars */ 881189049Srnoland# define TV_TEST_MODE_PATTERN_3 (3 << 0) 882189049Srnoland/** Encoder test pattern 4 - random noise */ 883189049Srnoland# define TV_TEST_MODE_PATTERN_4 (4 << 0) 884189049Srnoland/** Encoder test pattern 5 - linear color ramps */ 885189049Srnoland# define TV_TEST_MODE_PATTERN_5 (5 << 0) 886189049Srnoland/** 887189049Srnoland * This test mode forces the DACs to 50% of full output. 888189049Srnoland * 889189049Srnoland * This is used for load detection in combination with TVDAC_SENSE_MASK 890189049Srnoland */ 891189049Srnoland# define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 892189049Srnoland# define TV_TEST_MODE_MASK (7 << 0) 893189049Srnoland 894189049Srnoland#define TV_DAC 0x68004 895189049Srnoland/** 896189049Srnoland * Reports that DAC state change logic has reported change (RO). 897189049Srnoland * 898189049Srnoland * This gets cleared when TV_DAC_STATE_EN is cleared 899189049Srnoland*/ 900189049Srnoland# define TVDAC_STATE_CHG (1 << 31) 901189049Srnoland# define TVDAC_SENSE_MASK (7 << 28) 902189049Srnoland/** Reports that DAC A voltage is above the detect threshold */ 903189049Srnoland# define TVDAC_A_SENSE (1 << 30) 904189049Srnoland/** Reports that DAC B voltage is above the detect threshold */ 905189049Srnoland# define TVDAC_B_SENSE (1 << 29) 906189049Srnoland/** Reports that DAC C voltage is above the detect threshold */ 907189049Srnoland# define TVDAC_C_SENSE (1 << 28) 908189049Srnoland/** 909189049Srnoland * Enables DAC state detection logic, for load-based TV detection. 910189049Srnoland * 911189049Srnoland * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 912189049Srnoland * to off, for load detection to work. 913189049Srnoland */ 914189049Srnoland# define TVDAC_STATE_CHG_EN (1 << 27) 915189049Srnoland/** Sets the DAC A sense value to high */ 916189049Srnoland# define TVDAC_A_SENSE_CTL (1 << 26) 917189049Srnoland/** Sets the DAC B sense value to high */ 918189049Srnoland# define TVDAC_B_SENSE_CTL (1 << 25) 919189049Srnoland/** Sets the DAC C sense value to high */ 920189049Srnoland# define TVDAC_C_SENSE_CTL (1 << 24) 921189049Srnoland/** Overrides the ENC_ENABLE and DAC voltage levels */ 922189049Srnoland# define DAC_CTL_OVERRIDE (1 << 7) 923189049Srnoland/** Sets the slew rate. Must be preserved in software */ 924189049Srnoland# define ENC_TVDAC_SLEW_FAST (1 << 6) 925189049Srnoland# define DAC_A_1_3_V (0 << 4) 926189049Srnoland# define DAC_A_1_1_V (1 << 4) 927189049Srnoland# define DAC_A_0_7_V (2 << 4) 928189049Srnoland# define DAC_A_OFF (3 << 4) 929189049Srnoland# define DAC_B_1_3_V (0 << 2) 930189049Srnoland# define DAC_B_1_1_V (1 << 2) 931189049Srnoland# define DAC_B_0_7_V (2 << 2) 932189049Srnoland# define DAC_B_OFF (3 << 2) 933189049Srnoland# define DAC_C_1_3_V (0 << 0) 934189049Srnoland# define DAC_C_1_1_V (1 << 0) 935189049Srnoland# define DAC_C_0_7_V (2 << 0) 936189049Srnoland# define DAC_C_OFF (3 << 0) 937189049Srnoland 938189049Srnoland/** 939189049Srnoland * CSC coefficients are stored in a floating point format with 9 bits of 940189049Srnoland * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 941189049Srnoland * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 942189049Srnoland * -1 (0x3) being the only legal negative value. 943189049Srnoland */ 944189049Srnoland#define TV_CSC_Y 0x68010 945189049Srnoland# define TV_RY_MASK 0x07ff0000 946189049Srnoland# define TV_RY_SHIFT 16 947189049Srnoland# define TV_GY_MASK 0x00000fff 948189049Srnoland# define TV_GY_SHIFT 0 949189049Srnoland 950189049Srnoland#define TV_CSC_Y2 0x68014 951189049Srnoland# define TV_BY_MASK 0x07ff0000 952189049Srnoland# define TV_BY_SHIFT 16 953189049Srnoland/** 954189049Srnoland * Y attenuation for component video. 955189049Srnoland * 956189049Srnoland * Stored in 1.9 fixed point. 957189049Srnoland */ 958189049Srnoland# define TV_AY_MASK 0x000003ff 959189049Srnoland# define TV_AY_SHIFT 0 960189049Srnoland 961189049Srnoland#define TV_CSC_U 0x68018 962189049Srnoland# define TV_RU_MASK 0x07ff0000 963189049Srnoland# define TV_RU_SHIFT 16 964189049Srnoland# define TV_GU_MASK 0x000007ff 965189049Srnoland# define TV_GU_SHIFT 0 966189049Srnoland 967189049Srnoland#define TV_CSC_U2 0x6801c 968189049Srnoland# define TV_BU_MASK 0x07ff0000 969189049Srnoland# define TV_BU_SHIFT 16 970189049Srnoland/** 971189049Srnoland * U attenuation for component video. 972189049Srnoland * 973189049Srnoland * Stored in 1.9 fixed point. 974189049Srnoland */ 975189049Srnoland# define TV_AU_MASK 0x000003ff 976189049Srnoland# define TV_AU_SHIFT 0 977189049Srnoland 978189049Srnoland#define TV_CSC_V 0x68020 979189049Srnoland# define TV_RV_MASK 0x0fff0000 980189049Srnoland# define TV_RV_SHIFT 16 981189049Srnoland# define TV_GV_MASK 0x000007ff 982189049Srnoland# define TV_GV_SHIFT 0 983189049Srnoland 984189049Srnoland#define TV_CSC_V2 0x68024 985189049Srnoland# define TV_BV_MASK 0x07ff0000 986189049Srnoland# define TV_BV_SHIFT 16 987189049Srnoland/** 988189049Srnoland * V attenuation for component video. 989189049Srnoland * 990189049Srnoland * Stored in 1.9 fixed point. 991189049Srnoland */ 992189049Srnoland# define TV_AV_MASK 0x000007ff 993189049Srnoland# define TV_AV_SHIFT 0 994189049Srnoland 995189049Srnoland#define TV_CLR_KNOBS 0x68028 996189049Srnoland/** 2s-complement brightness adjustment */ 997189049Srnoland# define TV_BRIGHTNESS_MASK 0xff000000 998189049Srnoland# define TV_BRIGHTNESS_SHIFT 24 999189049Srnoland/** Contrast adjustment, as a 2.6 unsigned floating point number */ 1000189049Srnoland# define TV_CONTRAST_MASK 0x00ff0000 1001189049Srnoland# define TV_CONTRAST_SHIFT 16 1002189049Srnoland/** Saturation adjustment, as a 2.6 unsigned floating point number */ 1003189049Srnoland# define TV_SATURATION_MASK 0x0000ff00 1004189049Srnoland# define TV_SATURATION_SHIFT 8 1005189049Srnoland/** Hue adjustment, as an integer phase angle in degrees */ 1006189049Srnoland# define TV_HUE_MASK 0x000000ff 1007189049Srnoland# define TV_HUE_SHIFT 0 1008189049Srnoland 1009189049Srnoland#define TV_CLR_LEVEL 0x6802c 1010189049Srnoland/** Controls the DAC level for black */ 1011189049Srnoland# define TV_BLACK_LEVEL_MASK 0x01ff0000 1012189049Srnoland# define TV_BLACK_LEVEL_SHIFT 16 1013189049Srnoland/** Controls the DAC level for blanking */ 1014189049Srnoland# define TV_BLANK_LEVEL_MASK 0x000001ff 1015189049Srnoland# define TV_BLANK_LEVEL_SHIFT 0 1016189049Srnoland 1017189049Srnoland#define TV_H_CTL_1 0x68030 1018189049Srnoland/** Number of pixels in the hsync. */ 1019189049Srnoland# define TV_HSYNC_END_MASK 0x1fff0000 1020189049Srnoland# define TV_HSYNC_END_SHIFT 16 1021189049Srnoland/** Total number of pixels minus one in the line (display and blanking). */ 1022189049Srnoland# define TV_HTOTAL_MASK 0x00001fff 1023189049Srnoland# define TV_HTOTAL_SHIFT 0 1024189049Srnoland 1025189049Srnoland#define TV_H_CTL_2 0x68034 1026189049Srnoland/** Enables the colorburst (needed for non-component color) */ 1027189049Srnoland# define TV_BURST_ENA (1 << 31) 1028189049Srnoland/** Offset of the colorburst from the start of hsync, in pixels minus one. */ 1029189049Srnoland# define TV_HBURST_START_SHIFT 16 1030189049Srnoland# define TV_HBURST_START_MASK 0x1fff0000 1031189049Srnoland/** Length of the colorburst */ 1032189049Srnoland# define TV_HBURST_LEN_SHIFT 0 1033189049Srnoland# define TV_HBURST_LEN_MASK 0x0001fff 1034189049Srnoland 1035189049Srnoland#define TV_H_CTL_3 0x68038 1036189049Srnoland/** End of hblank, measured in pixels minus one from start of hsync */ 1037189049Srnoland# define TV_HBLANK_END_SHIFT 16 1038189049Srnoland# define TV_HBLANK_END_MASK 0x1fff0000 1039189049Srnoland/** Start of hblank, measured in pixels minus one from start of hsync */ 1040189049Srnoland# define TV_HBLANK_START_SHIFT 0 1041189049Srnoland# define TV_HBLANK_START_MASK 0x0001fff 1042189049Srnoland 1043189049Srnoland#define TV_V_CTL_1 0x6803c 1044189049Srnoland/** XXX */ 1045189049Srnoland# define TV_NBR_END_SHIFT 16 1046189049Srnoland# define TV_NBR_END_MASK 0x07ff0000 1047189049Srnoland/** XXX */ 1048189049Srnoland# define TV_VI_END_F1_SHIFT 8 1049189049Srnoland# define TV_VI_END_F1_MASK 0x00003f00 1050189049Srnoland/** XXX */ 1051189049Srnoland# define TV_VI_END_F2_SHIFT 0 1052189049Srnoland# define TV_VI_END_F2_MASK 0x0000003f 1053189049Srnoland 1054189049Srnoland#define TV_V_CTL_2 0x68040 1055189049Srnoland/** Length of vsync, in half lines */ 1056189049Srnoland# define TV_VSYNC_LEN_MASK 0x07ff0000 1057189049Srnoland# define TV_VSYNC_LEN_SHIFT 16 1058189049Srnoland/** Offset of the start of vsync in field 1, measured in one less than the 1059189049Srnoland * number of half lines. 1060189049Srnoland */ 1061189049Srnoland# define TV_VSYNC_START_F1_MASK 0x00007f00 1062189049Srnoland# define TV_VSYNC_START_F1_SHIFT 8 1063189049Srnoland/** 1064189049Srnoland * Offset of the start of vsync in field 2, measured in one less than the 1065189049Srnoland * number of half lines. 1066189049Srnoland */ 1067189049Srnoland# define TV_VSYNC_START_F2_MASK 0x0000007f 1068189049Srnoland# define TV_VSYNC_START_F2_SHIFT 0 1069189049Srnoland 1070189049Srnoland#define TV_V_CTL_3 0x68044 1071189049Srnoland/** Enables generation of the equalization signal */ 1072189049Srnoland# define TV_EQUAL_ENA (1 << 31) 1073189049Srnoland/** Length of vsync, in half lines */ 1074189049Srnoland# define TV_VEQ_LEN_MASK 0x007f0000 1075189049Srnoland# define TV_VEQ_LEN_SHIFT 16 1076189049Srnoland/** Offset of the start of equalization in field 1, measured in one less than 1077189049Srnoland * the number of half lines. 1078189049Srnoland */ 1079189049Srnoland# define TV_VEQ_START_F1_MASK 0x0007f00 1080189049Srnoland# define TV_VEQ_START_F1_SHIFT 8 1081189049Srnoland/** 1082189049Srnoland * Offset of the start of equalization in field 2, measured in one less than 1083189049Srnoland * the number of half lines. 1084189049Srnoland */ 1085189049Srnoland# define TV_VEQ_START_F2_MASK 0x000007f 1086189049Srnoland# define TV_VEQ_START_F2_SHIFT 0 1087189049Srnoland 1088189049Srnoland#define TV_V_CTL_4 0x68048 1089189049Srnoland/** 1090189049Srnoland * Offset to start of vertical colorburst, measured in one less than the 1091189049Srnoland * number of lines from vertical start. 1092189049Srnoland */ 1093189049Srnoland# define TV_VBURST_START_F1_MASK 0x003f0000 1094189049Srnoland# define TV_VBURST_START_F1_SHIFT 16 1095189049Srnoland/** 1096189049Srnoland * Offset to the end of vertical colorburst, measured in one less than the 1097189049Srnoland * number of lines from the start of NBR. 1098189049Srnoland */ 1099189049Srnoland# define TV_VBURST_END_F1_MASK 0x000000ff 1100189049Srnoland# define TV_VBURST_END_F1_SHIFT 0 1101189049Srnoland 1102189049Srnoland#define TV_V_CTL_5 0x6804c 1103189049Srnoland/** 1104189049Srnoland * Offset to start of vertical colorburst, measured in one less than the 1105189049Srnoland * number of lines from vertical start. 1106189049Srnoland */ 1107189049Srnoland# define TV_VBURST_START_F2_MASK 0x003f0000 1108189049Srnoland# define TV_VBURST_START_F2_SHIFT 16 1109189049Srnoland/** 1110189049Srnoland * Offset to the end of vertical colorburst, measured in one less than the 1111189049Srnoland * number of lines from the start of NBR. 1112189049Srnoland */ 1113189049Srnoland# define TV_VBURST_END_F2_MASK 0x000000ff 1114189049Srnoland# define TV_VBURST_END_F2_SHIFT 0 1115189049Srnoland 1116189049Srnoland#define TV_V_CTL_6 0x68050 1117189049Srnoland/** 1118189049Srnoland * Offset to start of vertical colorburst, measured in one less than the 1119189049Srnoland * number of lines from vertical start. 1120189049Srnoland */ 1121189049Srnoland# define TV_VBURST_START_F3_MASK 0x003f0000 1122189049Srnoland# define TV_VBURST_START_F3_SHIFT 16 1123189049Srnoland/** 1124189049Srnoland * Offset to the end of vertical colorburst, measured in one less than the 1125189049Srnoland * number of lines from the start of NBR. 1126189049Srnoland */ 1127189049Srnoland# define TV_VBURST_END_F3_MASK 0x000000ff 1128189049Srnoland# define TV_VBURST_END_F3_SHIFT 0 1129189049Srnoland 1130189049Srnoland#define TV_V_CTL_7 0x68054 1131189049Srnoland/** 1132189049Srnoland * Offset to start of vertical colorburst, measured in one less than the 1133189049Srnoland * number of lines from vertical start. 1134189049Srnoland */ 1135189049Srnoland# define TV_VBURST_START_F4_MASK 0x003f0000 1136189049Srnoland# define TV_VBURST_START_F4_SHIFT 16 1137189049Srnoland/** 1138189049Srnoland * Offset to the end of vertical colorburst, measured in one less than the 1139189049Srnoland * number of lines from the start of NBR. 1140189049Srnoland */ 1141189049Srnoland# define TV_VBURST_END_F4_MASK 0x000000ff 1142189049Srnoland# define TV_VBURST_END_F4_SHIFT 0 1143189049Srnoland 1144189049Srnoland#define TV_SC_CTL_1 0x68060 1145189049Srnoland/** Turns on the first subcarrier phase generation DDA */ 1146189049Srnoland# define TV_SC_DDA1_EN (1 << 31) 1147189049Srnoland/** Turns on the first subcarrier phase generation DDA */ 1148189049Srnoland# define TV_SC_DDA2_EN (1 << 30) 1149189049Srnoland/** Turns on the first subcarrier phase generation DDA */ 1150189049Srnoland# define TV_SC_DDA3_EN (1 << 29) 1151189049Srnoland/** Sets the subcarrier DDA to reset frequency every other field */ 1152189049Srnoland# define TV_SC_RESET_EVERY_2 (0 << 24) 1153189049Srnoland/** Sets the subcarrier DDA to reset frequency every fourth field */ 1154189049Srnoland# define TV_SC_RESET_EVERY_4 (1 << 24) 1155189049Srnoland/** Sets the subcarrier DDA to reset frequency every eighth field */ 1156189049Srnoland# define TV_SC_RESET_EVERY_8 (2 << 24) 1157189049Srnoland/** Sets the subcarrier DDA to never reset the frequency */ 1158189049Srnoland# define TV_SC_RESET_NEVER (3 << 24) 1159189049Srnoland/** Sets the peak amplitude of the colorburst.*/ 1160189049Srnoland# define TV_BURST_LEVEL_MASK 0x00ff0000 1161189049Srnoland# define TV_BURST_LEVEL_SHIFT 16 1162189049Srnoland/** Sets the increment of the first subcarrier phase generation DDA */ 1163189049Srnoland# define TV_SCDDA1_INC_MASK 0x00000fff 1164189049Srnoland# define TV_SCDDA1_INC_SHIFT 0 1165189049Srnoland 1166189049Srnoland#define TV_SC_CTL_2 0x68064 1167189049Srnoland/** Sets the rollover for the second subcarrier phase generation DDA */ 1168189049Srnoland# define TV_SCDDA2_SIZE_MASK 0x7fff0000 1169189049Srnoland# define TV_SCDDA2_SIZE_SHIFT 16 1170189049Srnoland/** Sets the increent of the second subcarrier phase generation DDA */ 1171189049Srnoland# define TV_SCDDA2_INC_MASK 0x00007fff 1172189049Srnoland# define TV_SCDDA2_INC_SHIFT 0 1173189049Srnoland 1174189049Srnoland#define TV_SC_CTL_3 0x68068 1175189049Srnoland/** Sets the rollover for the third subcarrier phase generation DDA */ 1176189049Srnoland# define TV_SCDDA3_SIZE_MASK 0x7fff0000 1177189049Srnoland# define TV_SCDDA3_SIZE_SHIFT 16 1178189049Srnoland/** Sets the increent of the third subcarrier phase generation DDA */ 1179189049Srnoland# define TV_SCDDA3_INC_MASK 0x00007fff 1180189049Srnoland# define TV_SCDDA3_INC_SHIFT 0 1181189049Srnoland 1182189049Srnoland#define TV_WIN_POS 0x68070 1183189049Srnoland/** X coordinate of the display from the start of horizontal active */ 1184189049Srnoland# define TV_XPOS_MASK 0x1fff0000 1185189049Srnoland# define TV_XPOS_SHIFT 16 1186189049Srnoland/** Y coordinate of the display from the start of vertical active (NBR) */ 1187189049Srnoland# define TV_YPOS_MASK 0x00000fff 1188189049Srnoland# define TV_YPOS_SHIFT 0 1189189049Srnoland 1190189049Srnoland#define TV_WIN_SIZE 0x68074 1191189049Srnoland/** Horizontal size of the display window, measured in pixels*/ 1192189049Srnoland# define TV_XSIZE_MASK 0x1fff0000 1193189049Srnoland# define TV_XSIZE_SHIFT 16 1194189049Srnoland/** 1195189049Srnoland * Vertical size of the display window, measured in pixels. 1196189049Srnoland * 1197189049Srnoland * Must be even for interlaced modes. 1198189049Srnoland */ 1199189049Srnoland# define TV_YSIZE_MASK 0x00000fff 1200189049Srnoland# define TV_YSIZE_SHIFT 0 1201189049Srnoland 1202189049Srnoland#define TV_FILTER_CTL_1 0x68080 1203189049Srnoland/** 1204189049Srnoland * Enables automatic scaling calculation. 1205189049Srnoland * 1206189049Srnoland * If set, the rest of the registers are ignored, and the calculated values can 1207189049Srnoland * be read back from the register. 1208189049Srnoland */ 1209189049Srnoland# define TV_AUTO_SCALE (1 << 31) 1210189049Srnoland/** 1211189049Srnoland * Disables the vertical filter. 1212189049Srnoland * 1213189049Srnoland * This is required on modes more than 1024 pixels wide */ 1214189049Srnoland# define TV_V_FILTER_BYPASS (1 << 29) 1215189049Srnoland/** Enables adaptive vertical filtering */ 1216189049Srnoland# define TV_VADAPT (1 << 28) 1217189049Srnoland# define TV_VADAPT_MODE_MASK (3 << 26) 1218189049Srnoland/** Selects the least adaptive vertical filtering mode */ 1219189049Srnoland# define TV_VADAPT_MODE_LEAST (0 << 26) 1220189049Srnoland/** Selects the moderately adaptive vertical filtering mode */ 1221189049Srnoland# define TV_VADAPT_MODE_MODERATE (1 << 26) 1222189049Srnoland/** Selects the most adaptive vertical filtering mode */ 1223189049Srnoland# define TV_VADAPT_MODE_MOST (3 << 26) 1224189049Srnoland/** 1225189049Srnoland * Sets the horizontal scaling factor. 1226189049Srnoland * 1227189049Srnoland * This should be the fractional part of the horizontal scaling factor divided 1228189049Srnoland * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 1229189049Srnoland * 1230189049Srnoland * (src width - 1) / ((oversample * dest width) - 1) 1231189049Srnoland */ 1232189049Srnoland# define TV_HSCALE_FRAC_MASK 0x00003fff 1233189049Srnoland# define TV_HSCALE_FRAC_SHIFT 0 1234189049Srnoland 1235189049Srnoland#define TV_FILTER_CTL_2 0x68084 1236189049Srnoland/** 1237189049Srnoland * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1238189049Srnoland * 1239189049Srnoland * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 1240189049Srnoland */ 1241189049Srnoland# define TV_VSCALE_INT_MASK 0x00038000 1242189049Srnoland# define TV_VSCALE_INT_SHIFT 15 1243189049Srnoland/** 1244189049Srnoland * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1245189049Srnoland * 1246189049Srnoland * \sa TV_VSCALE_INT_MASK 1247189049Srnoland */ 1248189049Srnoland# define TV_VSCALE_FRAC_MASK 0x00007fff 1249189049Srnoland# define TV_VSCALE_FRAC_SHIFT 0 1250189049Srnoland 1251189049Srnoland#define TV_FILTER_CTL_3 0x68088 1252189049Srnoland/** 1253189049Srnoland * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1254189049Srnoland * 1255189049Srnoland * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 1256189049Srnoland * 1257189049Srnoland * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 1258189049Srnoland */ 1259189049Srnoland# define TV_VSCALE_IP_INT_MASK 0x00038000 1260189049Srnoland# define TV_VSCALE_IP_INT_SHIFT 15 1261189049Srnoland/** 1262189049Srnoland * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1263189049Srnoland * 1264189049Srnoland * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 1265189049Srnoland * 1266189049Srnoland * \sa TV_VSCALE_IP_INT_MASK 1267189049Srnoland */ 1268189049Srnoland# define TV_VSCALE_IP_FRAC_MASK 0x00007fff 1269189049Srnoland# define TV_VSCALE_IP_FRAC_SHIFT 0 1270189049Srnoland 1271189049Srnoland#define TV_CC_CONTROL 0x68090 1272189049Srnoland# define TV_CC_ENABLE (1 << 31) 1273189049Srnoland/** 1274189049Srnoland * Specifies which field to send the CC data in. 1275189049Srnoland * 1276189049Srnoland * CC data is usually sent in field 0. 1277189049Srnoland */ 1278189049Srnoland# define TV_CC_FID_MASK (1 << 27) 1279189049Srnoland# define TV_CC_FID_SHIFT 27 1280189049Srnoland/** Sets the horizontal position of the CC data. Usually 135. */ 1281189049Srnoland# define TV_CC_HOFF_MASK 0x03ff0000 1282189049Srnoland# define TV_CC_HOFF_SHIFT 16 1283189049Srnoland/** Sets the vertical position of the CC data. Usually 21 */ 1284189049Srnoland# define TV_CC_LINE_MASK 0x0000003f 1285189049Srnoland# define TV_CC_LINE_SHIFT 0 1286189049Srnoland 1287189049Srnoland#define TV_CC_DATA 0x68094 1288189049Srnoland# define TV_CC_RDY (1 << 31) 1289189049Srnoland/** Second word of CC data to be transmitted. */ 1290189049Srnoland# define TV_CC_DATA_2_MASK 0x007f0000 1291189049Srnoland# define TV_CC_DATA_2_SHIFT 16 1292189049Srnoland/** First word of CC data to be transmitted. */ 1293189049Srnoland# define TV_CC_DATA_1_MASK 0x0000007f 1294189049Srnoland# define TV_CC_DATA_1_SHIFT 0 1295189049Srnoland 1296189049Srnoland#define TV_H_LUMA_0 0x68100 1297189049Srnoland#define TV_H_LUMA_59 0x681ec 1298189049Srnoland#define TV_H_CHROMA_0 0x68200 1299189049Srnoland#define TV_H_CHROMA_59 0x682ec 1300189049Srnoland#define TV_V_LUMA_0 0x68300 1301189049Srnoland#define TV_V_LUMA_42 0x683a8 1302189049Srnoland#define TV_V_CHROMA_0 0x68400 1303189049Srnoland#define TV_V_CHROMA_42 0x684a8 1304189049Srnoland 1305189049Srnoland/* Display & cursor control */ 1306189049Srnoland 1307189049Srnoland/* Pipe A */ 1308189049Srnoland#define PIPEADSL 0x70000 1309189049Srnoland#define PIPEACONF 0x70008 1310189049Srnoland#define PIPEACONF_ENABLE (1<<31) 1311189049Srnoland#define PIPEACONF_DISABLE 0 1312189049Srnoland#define PIPEACONF_DOUBLE_WIDE (1<<30) 1313189049Srnoland#define I965_PIPECONF_ACTIVE (1<<30) 1314189049Srnoland#define PIPEACONF_SINGLE_WIDE 0 1315189049Srnoland#define PIPEACONF_PIPE_UNLOCKED 0 1316189049Srnoland#define PIPEACONF_PIPE_LOCKED (1<<25) 1317189049Srnoland#define PIPEACONF_PALETTE 0 1318189049Srnoland#define PIPEACONF_GAMMA (1<<24) 1319189049Srnoland#define PIPECONF_FORCE_BORDER (1<<25) 1320189049Srnoland#define PIPECONF_PROGRESSIVE (0 << 21) 1321189049Srnoland#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 1322189049Srnoland#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 1323189049Srnoland#define PIPEASTAT 0x70024 1324189049Srnoland#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 1325189049Srnoland#define PIPE_CRC_ERROR_ENABLE (1UL<<29) 1326189049Srnoland#define PIPE_CRC_DONE_ENABLE (1UL<<28) 1327189049Srnoland#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 1328189049Srnoland#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 1329189049Srnoland#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 1330189049Srnoland#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 1331189049Srnoland#define PIPE_DPST_EVENT_ENABLE (1UL<<23) 1332189049Srnoland#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 1333189049Srnoland#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 1334189049Srnoland#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 1335189049Srnoland#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 1336189049Srnoland#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 1337189049Srnoland#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 1338189049Srnoland#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 1339189049Srnoland#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 1340189049Srnoland#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 1341189049Srnoland#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 1342189049Srnoland#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 1343189049Srnoland#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 1344189049Srnoland#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 1345189049Srnoland#define PIPE_DPST_EVENT_STATUS (1UL<<7) 1346189049Srnoland#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 1347189049Srnoland#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 1348189049Srnoland#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 1349189049Srnoland#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 1350189049Srnoland#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 1351189049Srnoland#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 1352189049Srnoland#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 1353189049Srnoland 1354189049Srnoland#define DSPARB 0x70030 1355189049Srnoland#define DSPARB_CSTART_MASK (0x7f << 7) 1356189049Srnoland#define DSPARB_CSTART_SHIFT 7 1357189049Srnoland#define DSPARB_BSTART_MASK (0x7f) 1358189049Srnoland#define DSPARB_BSTART_SHIFT 0 1359189049Srnoland/* 1360189049Srnoland * The two pipe frame counter registers are not synchronized, so 1361189049Srnoland * reading a stable value is somewhat tricky. The following code 1362189049Srnoland * should work: 1363189049Srnoland * 1364189049Srnoland * do { 1365189049Srnoland * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 1366189049Srnoland * PIPE_FRAME_HIGH_SHIFT; 1367189049Srnoland * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 1368189049Srnoland * PIPE_FRAME_LOW_SHIFT); 1369189049Srnoland * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 1370189049Srnoland * PIPE_FRAME_HIGH_SHIFT); 1371189049Srnoland * } while (high1 != high2); 1372189049Srnoland * frame = (high1 << 8) | low1; 1373189049Srnoland */ 1374189049Srnoland#define PIPEAFRAMEHIGH 0x70040 1375189049Srnoland#define PIPE_FRAME_HIGH_MASK 0x0000ffff 1376189049Srnoland#define PIPE_FRAME_HIGH_SHIFT 0 1377189049Srnoland#define PIPEAFRAMEPIXEL 0x70044 1378189049Srnoland#define PIPE_FRAME_LOW_MASK 0xff000000 1379189049Srnoland#define PIPE_FRAME_LOW_SHIFT 24 1380189049Srnoland#define PIPE_PIXEL_MASK 0x00ffffff 1381189049Srnoland#define PIPE_PIXEL_SHIFT 0 1382189054Srnoland/* GM45+ just has to be different */ 1383189054Srnoland#define PIPEA_FRMCOUNT_GM45 0x70040 1384189054Srnoland#define PIPEA_FLIPCOUNT_GM45 0x70044 1385189049Srnoland 1386189049Srnoland/* Cursor A & B regs */ 1387189049Srnoland#define CURACNTR 0x70080 1388189049Srnoland#define CURSOR_MODE_DISABLE 0x00 1389189049Srnoland#define CURSOR_MODE_64_32B_AX 0x07 1390189049Srnoland#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 1391189049Srnoland#define MCURSOR_GAMMA_ENABLE (1 << 26) 1392189049Srnoland#define CURABASE 0x70084 1393189049Srnoland#define CURAPOS 0x70088 1394189049Srnoland#define CURSOR_POS_MASK 0x007FF 1395189049Srnoland#define CURSOR_POS_SIGN 0x8000 1396189049Srnoland#define CURSOR_X_SHIFT 0 1397189049Srnoland#define CURSOR_Y_SHIFT 16 1398189049Srnoland#define CURBCNTR 0x700c0 1399189049Srnoland#define CURBBASE 0x700c4 1400189049Srnoland#define CURBPOS 0x700c8 1401189049Srnoland 1402189049Srnoland/* Display A control */ 1403189049Srnoland#define DSPACNTR 0x70180 1404189049Srnoland#define DISPLAY_PLANE_ENABLE (1<<31) 1405189049Srnoland#define DISPLAY_PLANE_DISABLE 0 1406189049Srnoland#define DISPPLANE_GAMMA_ENABLE (1<<30) 1407189049Srnoland#define DISPPLANE_GAMMA_DISABLE 0 1408189049Srnoland#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 1409189049Srnoland#define DISPPLANE_8BPP (0x2<<26) 1410189049Srnoland#define DISPPLANE_15_16BPP (0x4<<26) 1411189049Srnoland#define DISPPLANE_16BPP (0x5<<26) 1412189049Srnoland#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 1413189049Srnoland#define DISPPLANE_32BPP (0x7<<26) 1414189049Srnoland#define DISPPLANE_STEREO_ENABLE (1<<25) 1415189049Srnoland#define DISPPLANE_STEREO_DISABLE 0 1416189049Srnoland#define DISPPLANE_SEL_PIPE_MASK (1<<24) 1417189049Srnoland#define DISPPLANE_SEL_PIPE_A 0 1418189049Srnoland#define DISPPLANE_SEL_PIPE_B (1<<24) 1419189049Srnoland#define DISPPLANE_SRC_KEY_ENABLE (1<<22) 1420189049Srnoland#define DISPPLANE_SRC_KEY_DISABLE 0 1421189049Srnoland#define DISPPLANE_LINE_DOUBLE (1<<20) 1422189049Srnoland#define DISPPLANE_NO_LINE_DOUBLE 0 1423189049Srnoland#define DISPPLANE_STEREO_POLARITY_FIRST 0 1424189049Srnoland#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 1425189049Srnoland#define DSPAADDR 0x70184 1426189049Srnoland#define DSPASTRIDE 0x70188 1427189049Srnoland#define DSPAPOS 0x7018C /* reserved */ 1428189049Srnoland#define DSPASIZE 0x70190 1429189049Srnoland#define DSPASURF 0x7019C /* 965+ only */ 1430189049Srnoland#define DSPATILEOFF 0x701A4 /* 965+ only */ 1431189049Srnoland 1432189049Srnoland/* VBIOS flags */ 1433189049Srnoland#define SWF00 0x71410 1434189049Srnoland#define SWF01 0x71414 1435189049Srnoland#define SWF02 0x71418 1436189049Srnoland#define SWF03 0x7141c 1437189049Srnoland#define SWF04 0x71420 1438189049Srnoland#define SWF05 0x71424 1439189049Srnoland#define SWF06 0x71428 1440189049Srnoland#define SWF10 0x70410 1441189049Srnoland#define SWF11 0x70414 1442189049Srnoland#define SWF14 0x71420 1443189049Srnoland#define SWF30 0x72414 1444189049Srnoland#define SWF31 0x72418 1445189049Srnoland#define SWF32 0x7241c 1446189049Srnoland 1447189049Srnoland/* Pipe B */ 1448189049Srnoland#define PIPEBDSL 0x71000 1449189049Srnoland#define PIPEBCONF 0x71008 1450189049Srnoland#define PIPEBSTAT 0x71024 1451189049Srnoland#define PIPEBFRAMEHIGH 0x71040 1452189049Srnoland#define PIPEBFRAMEPIXEL 0x71044 1453189054Srnoland#define PIPEB_FRMCOUNT_GM45 0x71040 1454189054Srnoland#define PIPEB_FLIPCOUNT_GM45 0x71044 1455189049Srnoland 1456190020Srnoland 1457189049Srnoland/* Display B control */ 1458189049Srnoland#define DSPBCNTR 0x71180 1459189049Srnoland#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 1460189049Srnoland#define DISPPLANE_ALPHA_TRANS_DISABLE 0 1461189049Srnoland#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 1462189049Srnoland#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 1463189049Srnoland#define DSPBADDR 0x71184 1464189049Srnoland#define DSPBSTRIDE 0x71188 1465189049Srnoland#define DSPBPOS 0x7118C 1466189049Srnoland#define DSPBSIZE 0x71190 1467189049Srnoland#define DSPBSURF 0x7119C 1468189049Srnoland#define DSPBTILEOFF 0x711A4 1469189049Srnoland 1470189049Srnoland/* VBIOS regs */ 1471189049Srnoland#define VGACNTRL 0x71400 1472189049Srnoland# define VGA_DISP_DISABLE (1 << 31) 1473189049Srnoland# define VGA_2X_MODE (1 << 30) 1474189049Srnoland# define VGA_PIPE_B_SELECT (1 << 29) 1475189049Srnoland 1476189049Srnoland#endif /* _I915_REG_H_ */ 1477