if_dcreg.h revision 82978
154134Swpaul/* 254134Swpaul * Copyright (c) 1997, 1998, 1999 354134Swpaul * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 454134Swpaul * 554134Swpaul * Redistribution and use in source and binary forms, with or without 654134Swpaul * modification, are permitted provided that the following conditions 754134Swpaul * are met: 854134Swpaul * 1. Redistributions of source code must retain the above copyright 954134Swpaul * notice, this list of conditions and the following disclaimer. 1054134Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1154134Swpaul * notice, this list of conditions and the following disclaimer in the 1254134Swpaul * documentation and/or other materials provided with the distribution. 1354134Swpaul * 3. All advertising materials mentioning features or use of this software 1454134Swpaul * must display the following acknowledgement: 1554134Swpaul * This product includes software developed by Bill Paul. 1654134Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1754134Swpaul * may be used to endorse or promote products derived from this software 1854134Swpaul * without specific prior written permission. 1954134Swpaul * 2054134Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2154134Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2254134Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2354134Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2454134Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2554134Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2654134Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2754134Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2854134Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2954134Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3054134Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3154134Swpaul * 3254134Swpaul * $FreeBSD: head/sys/dev/dc/if_dcreg.h 82978 2001-09-04 17:10:11Z wpaul $ 3354134Swpaul */ 3454134Swpaul 3554134Swpaul/* 3654134Swpaul * 21143 and clone common register definitions. 3754134Swpaul */ 3854134Swpaul 3954134Swpaul#define DC_BUSCTL 0x00 /* bus control */ 4054134Swpaul#define DC_TXSTART 0x08 /* tx start demand */ 4154134Swpaul#define DC_RXSTART 0x10 /* rx start demand */ 4254134Swpaul#define DC_RXADDR 0x18 /* rx descriptor list start addr */ 4354134Swpaul#define DC_TXADDR 0x20 /* tx descriptor list start addr */ 4454134Swpaul#define DC_ISR 0x28 /* interrupt status register */ 4554134Swpaul#define DC_NETCFG 0x30 /* network config register */ 4654134Swpaul#define DC_IMR 0x38 /* interrupt mask */ 4754134Swpaul#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ 4854134Swpaul#define DC_SIO 0x48 /* MII and ROM/EEPROM access */ 4954134Swpaul#define DC_ROM 0x50 /* ROM programming address */ 5054134Swpaul#define DC_TIMER 0x58 /* general timer */ 5154134Swpaul#define DC_10BTSTAT 0x60 /* SIA status */ 5254134Swpaul#define DC_SIARESET 0x68 /* SIA connectivity */ 5354134Swpaul#define DC_10BTCTRL 0x70 /* SIA transmit and receive */ 5454134Swpaul#define DC_WATCHDOG 0x78 /* SIA and general purpose port */ 5567314Sjon#define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */ 5654134Swpaul 5754134Swpaul/* 5854134Swpaul * There are two general 'types' of MX chips that we need to be 5954134Swpaul * concerned with. One is the original 98713, which has its internal 6054134Swpaul * NWAY support controlled via the MDIO bits in the serial I/O 6154134Swpaul * register. The other is everything else (from the 98713A on up), 6254134Swpaul * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, 6354134Swpaul * just like the 21143. This type setting also governs which of the 6454134Swpaul * 'magic' numbers we write to CSR16. The PNIC II falls into the 6554134Swpaul * 98713A/98715/98715A/98725 category. 6654134Swpaul */ 6754134Swpaul#define DC_TYPE_98713 0x1 6854134Swpaul#define DC_TYPE_98713A 0x2 6954134Swpaul#define DC_TYPE_987x5 0x3 7054134Swpaul 7154134Swpaul/* Other type of supported chips. */ 7254134Swpaul#define DC_TYPE_21143 0x4 /* Intel 21143 */ 7354134Swpaul#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ 7454134Swpaul#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ 7554134Swpaul#define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */ 7654134Swpaul#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ 7754134Swpaul#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ 7854134Swpaul#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ 7967314Sjon#define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */ 8082978Swpaul#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */ 8154134Swpaul 8254134Swpaul#define DC_IS_MACRONIX(x) \ 8354134Swpaul (x->dc_type == DC_TYPE_98713 || \ 8454134Swpaul x->dc_type == DC_TYPE_98713A || \ 8554134Swpaul x->dc_type == DC_TYPE_987x5) 8654134Swpaul 8754134Swpaul#define DC_IS_ADMTEK(x) \ 8854134Swpaul (x->dc_type == DC_TYPE_AL981 || \ 8954134Swpaul x->dc_type == DC_TYPE_AN985) 9054134Swpaul 9154134Swpaul#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) 9254134Swpaul#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) 9354134Swpaul#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) 9454134Swpaul#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985) 9554134Swpaul#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) 9654134Swpaul#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) 9754134Swpaul#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) 9867314Sjon#define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM) 9982978Swpaul#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT) 10054134Swpaul 10154134Swpaul/* MII/symbol mode port types */ 10254134Swpaul#define DC_PMODE_MII 0x1 10354134Swpaul#define DC_PMODE_SYM 0x2 10466681Swpaul#define DC_PMODE_SIA 0x3 10554134Swpaul 10654134Swpaul/* 10754134Swpaul * Bus control bits. 10854134Swpaul */ 10954134Swpaul#define DC_BUSCTL_RESET 0x00000001 11054134Swpaul#define DC_BUSCTL_ARBITRATION 0x00000002 11154134Swpaul#define DC_BUSCTL_SKIPLEN 0x0000007C 11254134Swpaul#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 11354134Swpaul#define DC_BUSCTL_BURSTLEN 0x00003F00 11454134Swpaul#define DC_BUSCTL_CACHEALIGN 0x0000C000 11554134Swpaul#define DC_BUSCTL_TXPOLL 0x000E0000 11654134Swpaul#define DC_BUSCTL_DBO 0x00100000 11754134Swpaul#define DC_BUSCTL_MRME 0x00200000 11854134Swpaul#define DC_BUSCTL_MRLE 0x00800000 11954134Swpaul#define DC_BUSCTL_MWIE 0x01000000 12054134Swpaul#define DC_BUSCTL_ONNOW_ENB 0x04000000 12154134Swpaul 12254134Swpaul#define DC_SKIPLEN_1LONG 0x00000004 12354134Swpaul#define DC_SKIPLEN_2LONG 0x00000008 12454134Swpaul#define DC_SKIPLEN_3LONG 0x00000010 12554134Swpaul#define DC_SKIPLEN_4LONG 0x00000020 12654134Swpaul#define DC_SKIPLEN_5LONG 0x00000040 12754134Swpaul 12854134Swpaul#define DC_CACHEALIGN_NONE 0x00000000 12954134Swpaul#define DC_CACHEALIGN_8LONG 0x00004000 13054134Swpaul#define DC_CACHEALIGN_16LONG 0x00008000 13154134Swpaul#define DC_CACHEALIGN_32LONG 0x0000C000 13254134Swpaul 13354134Swpaul#define DC_BURSTLEN_USECA 0x00000000 13454134Swpaul#define DC_BURSTLEN_1LONG 0x00000100 13554134Swpaul#define DC_BURSTLEN_2LONG 0x00000200 13654134Swpaul#define DC_BURSTLEN_4LONG 0x00000400 13754134Swpaul#define DC_BURSTLEN_8LONG 0x00000800 13854134Swpaul#define DC_BURSTLEN_16LONG 0x00001000 13954134Swpaul#define DC_BURSTLEN_32LONG 0x00002000 14054134Swpaul 14154134Swpaul#define DC_TXPOLL_OFF 0x00000000 14254134Swpaul#define DC_TXPOLL_1 0x00020000 14354134Swpaul#define DC_TXPOLL_2 0x00040000 14454134Swpaul#define DC_TXPOLL_3 0x00060000 14554134Swpaul#define DC_TXPOLL_4 0x00080000 14654134Swpaul#define DC_TXPOLL_5 0x000A0000 14754134Swpaul#define DC_TXPOLL_6 0x000C0000 14854134Swpaul#define DC_TXPOLL_7 0x000E0000 14954134Swpaul 15054134Swpaul/* 15154134Swpaul * Interrupt status bits. 15254134Swpaul */ 15354134Swpaul#define DC_ISR_TX_OK 0x00000001 15454134Swpaul#define DC_ISR_TX_IDLE 0x00000002 15554134Swpaul#define DC_ISR_TX_NOBUF 0x00000004 15654134Swpaul#define DC_ISR_TX_JABBERTIMEO 0x00000008 15754134Swpaul#define DC_ISR_LINKGOOD 0x00000010 15854134Swpaul#define DC_ISR_TX_UNDERRUN 0x00000020 15954134Swpaul#define DC_ISR_RX_OK 0x00000040 16054134Swpaul#define DC_ISR_RX_NOBUF 0x00000080 16154134Swpaul#define DC_ISR_RX_READ 0x00000100 16254134Swpaul#define DC_ISR_RX_WATDOGTIMEO 0x00000200 16354134Swpaul#define DC_ISR_TX_EARLY 0x00000400 16454134Swpaul#define DC_ISR_TIMER_EXPIRED 0x00000800 16554134Swpaul#define DC_ISR_LINKFAIL 0x00001000 16654134Swpaul#define DC_ISR_BUS_ERR 0x00002000 16754134Swpaul#define DC_ISR_RX_EARLY 0x00004000 16854134Swpaul#define DC_ISR_ABNORMAL 0x00008000 16954134Swpaul#define DC_ISR_NORMAL 0x00010000 17054134Swpaul#define DC_ISR_RX_STATE 0x000E0000 17154134Swpaul#define DC_ISR_TX_STATE 0x00700000 17254134Swpaul#define DC_ISR_BUSERRTYPE 0x03800000 17354134Swpaul#define DC_ISR_100MBPSLINK 0x08000000 17454134Swpaul#define DC_ISR_MAGICKPACK 0x10000000 17554134Swpaul 17654134Swpaul#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 17754134Swpaul#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 17854134Swpaul#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 17954134Swpaul#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 18054134Swpaul#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 18154134Swpaul#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 18254134Swpaul#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 18354134Swpaul#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 18454134Swpaul 18554134Swpaul#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ 18654134Swpaul#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 18754134Swpaul#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 18854134Swpaul#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 18954134Swpaul#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 19054134Swpaul#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 19154134Swpaul#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 19254134Swpaul#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 19354134Swpaul 19454134Swpaul/* 19554134Swpaul * Network config bits. 19654134Swpaul */ 19754134Swpaul#define DC_NETCFG_RX_HASHPERF 0x00000001 19854134Swpaul#define DC_NETCFG_RX_ON 0x00000002 19954134Swpaul#define DC_NETCFG_RX_HASHONLY 0x00000004 20054134Swpaul#define DC_NETCFG_RX_BADFRAMES 0x00000008 20154134Swpaul#define DC_NETCFG_RX_INVFILT 0x00000010 20254134Swpaul#define DC_NETCFG_BACKOFFCNT 0x00000020 20354134Swpaul#define DC_NETCFG_RX_PROMISC 0x00000040 20454134Swpaul#define DC_NETCFG_RX_ALLMULTI 0x00000080 20554134Swpaul#define DC_NETCFG_FULLDUPLEX 0x00000200 20654134Swpaul#define DC_NETCFG_LOOPBACK 0x00000C00 20754134Swpaul#define DC_NETCFG_FORCECOLL 0x00001000 20854134Swpaul#define DC_NETCFG_TX_ON 0x00002000 20954134Swpaul#define DC_NETCFG_TX_THRESH 0x0000C000 21054134Swpaul#define DC_NETCFG_TX_BACKOFF 0x00020000 21154134Swpaul#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ 21254134Swpaul#define DC_NETCFG_HEARTBEAT 0x00080000 21354134Swpaul#define DC_NETCFG_STORENFWD 0x00200000 21454134Swpaul#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ 21554134Swpaul#define DC_NETCFG_PCS 0x00800000 21654134Swpaul#define DC_NETCFG_SCRAMBLER 0x01000000 21754134Swpaul#define DC_NETCFG_NO_RXCRC 0x02000000 21854134Swpaul#define DC_NETCFG_RX_ALL 0x40000000 21954134Swpaul#define DC_NETCFG_CAPEFFECT 0x80000000 22054134Swpaul 22154134Swpaul#define DC_OPMODE_NORM 0x00000000 22254134Swpaul#define DC_OPMODE_INTLOOP 0x00000400 22354134Swpaul#define DC_OPMODE_EXTLOOP 0x00000800 22454134Swpaul 22572915Swpaul#if 0 22654134Swpaul#define DC_TXTHRESH_72BYTES 0x00000000 22754134Swpaul#define DC_TXTHRESH_96BYTES 0x00004000 22854134Swpaul#define DC_TXTHRESH_128BYTES 0x00008000 22954134Swpaul#define DC_TXTHRESH_160BYTES 0x0000C000 23072915Swpaul#endif 23154134Swpaul 23272915Swpaul#define DC_TXTHRESH_MIN 0x00000000 23372915Swpaul#define DC_TXTHRESH_INC 0x00004000 23472915Swpaul#define DC_TXTHRESH_MAX 0x0000C000 23554134Swpaul 23672915Swpaul 23754134Swpaul/* 23854134Swpaul * Interrupt mask bits. 23954134Swpaul */ 24054134Swpaul#define DC_IMR_TX_OK 0x00000001 24154134Swpaul#define DC_IMR_TX_IDLE 0x00000002 24254134Swpaul#define DC_IMR_TX_NOBUF 0x00000004 24354134Swpaul#define DC_IMR_TX_JABBERTIMEO 0x00000008 24454134Swpaul#define DC_IMR_LINKGOOD 0x00000010 24554134Swpaul#define DC_IMR_TX_UNDERRUN 0x00000020 24654134Swpaul#define DC_IMR_RX_OK 0x00000040 24754134Swpaul#define DC_IMR_RX_NOBUF 0x00000080 24854134Swpaul#define DC_IMR_RX_READ 0x00000100 24954134Swpaul#define DC_IMR_RX_WATDOGTIMEO 0x00000200 25054134Swpaul#define DC_IMR_TX_EARLY 0x00000400 25154134Swpaul#define DC_IMR_TIMER_EXPIRED 0x00000800 25254134Swpaul#define DC_IMR_LINKFAIL 0x00001000 25354134Swpaul#define DC_IMR_BUS_ERR 0x00002000 25454134Swpaul#define DC_IMR_RX_EARLY 0x00004000 25554134Swpaul#define DC_IMR_ABNORMAL 0x00008000 25654134Swpaul#define DC_IMR_NORMAL 0x00010000 25754134Swpaul#define DC_IMR_100MBPSLINK 0x08000000 25854134Swpaul#define DC_IMR_MAGICKPACK 0x10000000 25954134Swpaul 26054134Swpaul#define DC_INTRS \ 26154134Swpaul (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ 26254134Swpaul DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ 26354134Swpaul DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) 26454134Swpaul/* 26554134Swpaul * Serial I/O (EEPROM/ROM) bits. 26654134Swpaul */ 26754134Swpaul#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 26854134Swpaul#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 26954134Swpaul#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 27054134Swpaul#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 27154134Swpaul#define DC_SIO_ROMDATA4 0x00000010 27254134Swpaul#define DC_SIO_ROMDATA5 0x00000020 27354134Swpaul#define DC_SIO_ROMDATA6 0x00000040 27454134Swpaul#define DC_SIO_ROMDATA7 0x00000080 27554134Swpaul#define DC_SIO_EESEL 0x00000800 27654134Swpaul#define DC_SIO_ROMSEL 0x00001000 27754134Swpaul#define DC_SIO_ROMCTL_WRITE 0x00002000 27854134Swpaul#define DC_SIO_ROMCTL_READ 0x00004000 27954134Swpaul#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ 28054134Swpaul#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ 28154134Swpaul#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ 28254134Swpaul#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ 28354134Swpaul 28454134Swpaul#define DC_EECMD_WRITE 0x140 28554134Swpaul#define DC_EECMD_READ 0x180 28654134Swpaul#define DC_EECMD_ERASE 0x1c0 28754134Swpaul 28854134Swpaul#define DC_EE_NODEADDR_OFFSET 0x70 28954134Swpaul#define DC_EE_NODEADDR 10 29054134Swpaul 29154134Swpaul/* 29254134Swpaul * General purpose timer register 29354134Swpaul */ 29454134Swpaul#define DC_TIMER_VALUE 0x0000FFFF 29554134Swpaul#define DC_TIMER_CONTINUOUS 0x00010000 29654134Swpaul 29754134Swpaul/* 29854134Swpaul * 10baseT status register 29954134Swpaul */ 30054134Swpaul#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ 30154134Swpaul#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ 30254134Swpaul#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ 30354134Swpaul#define DC_TSTAT_AUTOPOLARITY 0x00000008 30454134Swpaul#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ 30554134Swpaul#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ 30654134Swpaul#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ 30754134Swpaul#define DC_TSTAT_REMFAULT 0x00000800 30854134Swpaul#define DC_TSTAT_ANEGSTAT 0x00007000 30954134Swpaul#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ 31054134Swpaul#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ 31154134Swpaul 31254134Swpaul#define DC_ASTAT_DISABLE 0x00000000 31354134Swpaul#define DC_ASTAT_TXDISABLE 0x00001000 31454134Swpaul#define DC_ASTAT_ABDETECT 0x00002000 31554134Swpaul#define DC_ASTAT_ACKDETECT 0x00003000 31654134Swpaul#define DC_ASTAT_CMPACKDETECT 0x00004000 31754134Swpaul#define DC_ASTAT_AUTONEGCMP 0x00005000 31854134Swpaul#define DC_ASTAT_LINKCHECK 0x00006000 31954134Swpaul 32054134Swpaul/* 32154134Swpaul * PHY reset register 32254134Swpaul */ 32354134Swpaul#define DC_SIA_RESET 0x00000001 32454134Swpaul#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ 32554134Swpaul 32654134Swpaul/* 32754134Swpaul * 10baseT control register 32854134Swpaul */ 32954134Swpaul#define DC_TCTL_ENCODER_ENB 0x00000001 33054134Swpaul#define DC_TCTL_LOOPBACK 0x00000002 33154134Swpaul#define DC_TCTL_DRIVER_ENB 0x00000004 33254134Swpaul#define DC_TCTL_LNKPULSE_ENB 0x00000008 33354134Swpaul#define DC_TCTL_HALFDUPLEX 0x00000040 33454134Swpaul#define DC_TCTL_AUTONEGENBL 0x00000080 33554134Swpaul#define DC_TCTL_RX_SQUELCH 0x00000100 33654134Swpaul#define DC_TCTL_COLL_SQUELCH 0x00000200 33754134Swpaul#define DC_TCTL_COLL_DETECT 0x00000400 33854134Swpaul#define DC_TCTL_SQE_ENB 0x00000800 33954134Swpaul#define DC_TCTL_LINKTEST 0x00001000 34054134Swpaul#define DC_TCTL_AUTOPOLARITY 0x00002000 34154134Swpaul#define DC_TCTL_SET_POL_PLUS 0x00004000 34254134Swpaul#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ 34354134Swpaul#define DC_TCTL_100BTXHALF 0x00010000 34454134Swpaul#define DC_TCTL_100BTXFULL 0x00020000 34554134Swpaul#define DC_TCTL_100BT4 0x00040000 34654134Swpaul 34754134Swpaul/* 34854134Swpaul * Watchdog timer register 34954134Swpaul */ 35054134Swpaul#define DC_WDOG_JABBERDIS 0x00000001 35154134Swpaul#define DC_WDOG_HOSTUNJAB 0x00000002 35254134Swpaul#define DC_WDOG_JABBERCLK 0x00000004 35354134Swpaul#define DC_WDOG_RXWDOGDIS 0x00000010 35454134Swpaul#define DC_WDOG_RXWDOGCLK 0x00000020 35554134Swpaul#define DC_WDOG_MUSTBEZERO 0x00000100 35665350Swpaul#define DC_WDOG_AUIBNC 0x00100000 35765350Swpaul#define DC_WDOG_ACTIVITY 0x00200000 35865350Swpaul#define DC_WDOG_RX_MATCH 0x00400000 35965350Swpaul#define DC_WDOG_LINK 0x00800000 36064134Swpaul#define DC_WDOG_CTLWREN 0x08000000 36154134Swpaul 36254134Swpaul/* 36367314Sjon * SIA and General Purpose Port register (X3201) 36467314Sjon */ 36567314Sjon#define DC_SIAGP_RXMATCH 0x40000000 36667314Sjon#define DC_SIAGP_INT1 0x20000000 36767314Sjon#define DC_SIAGP_INT0 0x10000000 36867314Sjon#define DC_SIAGP_WRITE_EN 0x08000000 36967314Sjon#define DC_SIAGP_RXMATCH_EN 0x04000000 37067314Sjon#define DC_SIAGP_INT1_EN 0x02000000 37167314Sjon#define DC_SIAGP_INT0_EN 0x01000000 37267314Sjon#define DC_SIAGP_LED3 0x00800000 37367314Sjon#define DC_SIAGP_LED2 0x00400000 37467314Sjon#define DC_SIAGP_LED1 0x00200000 37567314Sjon#define DC_SIAGP_LED0 0x00100000 37667314Sjon#define DC_SIAGP_MD_GP3_OUTPUT 0x00080000 37767314Sjon#define DC_SIAGP_MD_GP2_OUTPUT 0x00040000 37867314Sjon#define DC_SIAGP_MD_GP1_OUTPUT 0x00020000 37967314Sjon#define DC_SIAGP_MD_GP0_OUTPUT 0x00010000 38067314Sjon 38167314Sjon/* 38254134Swpaul * Size of a setup frame. 38354134Swpaul */ 38454134Swpaul#define DC_SFRAME_LEN 192 38554134Swpaul 38654134Swpaul/* 38754134Swpaul * 21x4x TX/RX list structure. 38854134Swpaul */ 38954134Swpaul 39054134Swpaulstruct dc_desc { 39154134Swpaul u_int32_t dc_status; 39254134Swpaul u_int32_t dc_ctl; 39354134Swpaul u_int32_t dc_ptr1; 39454134Swpaul u_int32_t dc_ptr2; 39554134Swpaul}; 39654134Swpaul 39754134Swpaul#define dc_data dc_ptr1 39854134Swpaul#define dc_next dc_ptr2 39954134Swpaul 40054134Swpaul#define DC_RXSTAT_FIFOOFLOW 0x00000001 40154134Swpaul#define DC_RXSTAT_CRCERR 0x00000002 40254134Swpaul#define DC_RXSTAT_DRIBBLE 0x00000004 40354134Swpaul#define DC_RXSTAT_WATCHDOG 0x00000010 40454134Swpaul#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ 40554134Swpaul#define DC_RXSTAT_COLLSEEN 0x00000040 40654134Swpaul#define DC_RXSTAT_GIANT 0x00000080 40754134Swpaul#define DC_RXSTAT_LASTFRAG 0x00000100 40854134Swpaul#define DC_RXSTAT_FIRSTFRAG 0x00000200 40954134Swpaul#define DC_RXSTAT_MULTICAST 0x00000400 41054134Swpaul#define DC_RXSTAT_RUNT 0x00000800 41154134Swpaul#define DC_RXSTAT_RXTYPE 0x00003000 41254134Swpaul#define DC_RXSTAT_RXERR 0x00008000 41354134Swpaul#define DC_RXSTAT_RXLEN 0x3FFF0000 41454134Swpaul#define DC_RXSTAT_OWN 0x80000000 41554134Swpaul 41654134Swpaul#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) 41754134Swpaul#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) 41854134Swpaul 41954134Swpaul#define DC_RXCTL_BUFLEN1 0x00000FFF 42054134Swpaul#define DC_RXCTL_BUFLEN2 0x00FFF000 42154134Swpaul#define DC_RXCTL_RLINK 0x01000000 42254134Swpaul#define DC_RXCTL_RLAST 0x02000000 42354134Swpaul 42454134Swpaul#define DC_TXSTAT_DEFER 0x00000001 42554134Swpaul#define DC_TXSTAT_UNDERRUN 0x00000002 42654134Swpaul#define DC_TXSTAT_LINKFAIL 0x00000003 42754134Swpaul#define DC_TXSTAT_COLLCNT 0x00000078 42854134Swpaul#define DC_TXSTAT_SQE 0x00000080 42954134Swpaul#define DC_TXSTAT_EXCESSCOLL 0x00000100 43054134Swpaul#define DC_TXSTAT_LATECOLL 0x00000200 43154134Swpaul#define DC_TXSTAT_NOCARRIER 0x00000400 43254134Swpaul#define DC_TXSTAT_CARRLOST 0x00000800 43354134Swpaul#define DC_TXSTAT_JABTIMEO 0x00004000 43454134Swpaul#define DC_TXSTAT_ERRSUM 0x00008000 43554134Swpaul#define DC_TXSTAT_OWN 0x80000000 43654134Swpaul 43754134Swpaul#define DC_TXCTL_BUFLEN1 0x000007FF 43854134Swpaul#define DC_TXCTL_BUFLEN2 0x003FF800 43954134Swpaul#define DC_TXCTL_FILTTYPE0 0x00400000 44054134Swpaul#define DC_TXCTL_PAD 0x00800000 44154134Swpaul#define DC_TXCTL_TLINK 0x01000000 44254134Swpaul#define DC_TXCTL_TLAST 0x02000000 44354134Swpaul#define DC_TXCTL_NOCRC 0x04000000 44454134Swpaul#define DC_TXCTL_SETUP 0x08000000 44554134Swpaul#define DC_TXCTL_FILTTYPE1 0x10000000 44654134Swpaul#define DC_TXCTL_FIRSTFRAG 0x20000000 44754134Swpaul#define DC_TXCTL_LASTFRAG 0x40000000 44854134Swpaul#define DC_TXCTL_FINT 0x80000000 44954134Swpaul 45054134Swpaul#define DC_FILTER_PERFECT 0x00000000 45154134Swpaul#define DC_FILTER_HASHPERF 0x00400000 45254134Swpaul#define DC_FILTER_INVERSE 0x10000000 45354134Swpaul#define DC_FILTER_HASHONLY 0x10400000 45454134Swpaul 45554134Swpaul#define DC_MAXFRAGS 16 45654134Swpaul#define DC_RX_LIST_CNT 64 45754134Swpaul#define DC_TX_LIST_CNT 256 45854134Swpaul#define DC_MIN_FRAMELEN 60 45954134Swpaul#define DC_RXLEN 1536 46054134Swpaul 46154134Swpaul#define DC_INC(x, y) (x) = (x + 1) % y 46254134Swpaul 46354134Swpaulstruct dc_list_data { 46454134Swpaul struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; 46554134Swpaul struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; 46654134Swpaul}; 46754134Swpaul 46854134Swpaulstruct dc_chain_data { 46954134Swpaul struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; 47054134Swpaul struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; 47154134Swpaul u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)]; 47254134Swpaul u_int8_t dc_pad[DC_MIN_FRAMELEN]; 47354134Swpaul int dc_tx_prod; 47454134Swpaul int dc_tx_cons; 47554134Swpaul int dc_tx_cnt; 47654134Swpaul int dc_rx_prod; 47754134Swpaul}; 47854134Swpaul 47966681Swpaulstruct dc_mediainfo { 48066681Swpaul int dc_media; 48166681Swpaul u_int8_t *dc_gp_ptr; 48266681Swpaul u_int8_t dc_gp_len; 48366681Swpaul u_int8_t *dc_reset_ptr; 48466681Swpaul u_int8_t dc_reset_len; 48566681Swpaul struct dc_mediainfo *dc_next; 48666681Swpaul}; 48766681Swpaul 48866681Swpaul 48954134Swpaulstruct dc_type { 49054134Swpaul u_int16_t dc_vid; 49154134Swpaul u_int16_t dc_did; 49254134Swpaul char *dc_name; 49354134Swpaul}; 49454134Swpaul 49554134Swpaulstruct dc_mii_frame { 49654134Swpaul u_int8_t mii_stdelim; 49754134Swpaul u_int8_t mii_opcode; 49854134Swpaul u_int8_t mii_phyaddr; 49954134Swpaul u_int8_t mii_regaddr; 50054134Swpaul u_int8_t mii_turnaround; 50154134Swpaul u_int16_t mii_data; 50254134Swpaul}; 50354134Swpaul 50454134Swpaul/* 50554134Swpaul * MII constants 50654134Swpaul */ 50754134Swpaul#define DC_MII_STARTDELIM 0x01 50854134Swpaul#define DC_MII_READOP 0x02 50954134Swpaul#define DC_MII_WRITEOP 0x01 51054134Swpaul#define DC_MII_TURNAROUND 0x02 51154134Swpaul 51254134Swpaul 51354134Swpaul/* 51454134Swpaul * Registers specific to clone devices. 51554134Swpaul * This mainly relates to RX filter programming: not all 21x4x clones 51654134Swpaul * use the standard DEC filter programming mechanism. 51754134Swpaul */ 51854134Swpaul 51954134Swpaul/* 52054134Swpaul * ADMtek specific registers and constants for the AL981 and AN985. 52154134Swpaul * The AN985 doesn't use the magic PHY registers. 52254134Swpaul */ 52354134Swpaul#define DC_AL_PAR0 0xA4 /* station address */ 52454134Swpaul#define DC_AL_PAR1 0xA8 /* station address */ 52554134Swpaul#define DC_AL_MAR0 0xAC /* multicast hash filter */ 52654134Swpaul#define DC_AL_MAR1 0xB0 /* multicast hash filter */ 52754134Swpaul#define DC_AL_BMCR 0xB4 /* built in PHY control */ 52854134Swpaul#define DC_AL_BMSR 0xB8 /* built in PHY status */ 52954134Swpaul#define DC_AL_VENID 0xBC /* built in PHY ID0 */ 53054134Swpaul#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ 53154134Swpaul#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ 53254134Swpaul#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ 53354134Swpaul#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ 53454134Swpaul 53554134Swpaul#define DC_ADMTEK_PHYADDR 0x1 53654134Swpaul#define DC_AL_EE_NODEADDR 4 53754134Swpaul/* End of ADMtek specific registers */ 53854134Swpaul 53954134Swpaul/* 54054134Swpaul * ASIX specific registers. 54154134Swpaul */ 54254134Swpaul#define DC_AX_FILTIDX 0x68 /* RX filter index */ 54354134Swpaul#define DC_AX_FILTDATA 0x70 /* RX filter data */ 54454134Swpaul 54554134Swpaul/* 54654134Swpaul * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). 54754134Swpaul */ 54854134Swpaul#define DC_AX_NETCFG_RX_BROAD 0x00000100 54954134Swpaul 55054134Swpaul/* 55154134Swpaul * RX Filter Index Register values 55254134Swpaul */ 55354134Swpaul#define DC_AX_FILTIDX_PAR0 0x00000000 55454134Swpaul#define DC_AX_FILTIDX_PAR1 0x00000001 55554134Swpaul#define DC_AX_FILTIDX_MAR0 0x00000002 55654134Swpaul#define DC_AX_FILTIDX_MAR1 0x00000003 55754134Swpaul/* End of ASIX specific registers */ 55854134Swpaul 55954134Swpaul/* 56054134Swpaul * Macronix specific registers. The Macronix chips have a special 56154134Swpaul * register for reading the NWAY status, which we don't use, plus 56254134Swpaul * a magic packet register, which we need to tweak a bit per the 56354134Swpaul * Macronix application notes. 56454134Swpaul */ 56554134Swpaul#define DC_MX_MAGICPACKET 0x80 56654134Swpaul#define DC_MX_NWAYSTAT 0xA0 56754134Swpaul 56854134Swpaul/* 56954134Swpaul * Magic packet register 57054134Swpaul */ 57154134Swpaul#define DC_MX_MPACK_DISABLE 0x00400000 57254134Swpaul 57354134Swpaul/* 57454134Swpaul * NWAY status register. 57554134Swpaul */ 57654134Swpaul#define DC_MX_NWAY_10BTHALF 0x08000000 57754134Swpaul#define DC_MX_NWAY_10BTFULL 0x10000000 57854134Swpaul#define DC_MX_NWAY_100BTHALF 0x20000000 57954134Swpaul#define DC_MX_NWAY_100BTFULL 0x40000000 58054134Swpaul#define DC_MX_NWAY_100BT4 0x80000000 58154134Swpaul 58254134Swpaul/* 58354134Swpaul * These are magic values that must be written into CSR16 58454134Swpaul * (DC_MX_MAGICPACKET) in order to put the chip into proper 58554134Swpaul * operating mode. The magic numbers are documented in the 58654134Swpaul * Macronix 98715 application notes. 58754134Swpaul */ 58854134Swpaul#define DC_MX_MAGIC_98713 0x0F370000 58954134Swpaul#define DC_MX_MAGIC_98713A 0x0B3C0000 59054134Swpaul#define DC_MX_MAGIC_98715 0x0B3C0000 59154134Swpaul#define DC_MX_MAGIC_98725 0x0B3C0000 59254134Swpaul/* End of Macronix specific registers */ 59354134Swpaul 59454134Swpaul/* 59554134Swpaul * PNIC 82c168/82c169 specific registers. 59654134Swpaul * The PNIC has its own special NWAY support, which doesn't work, 59754134Swpaul * and shortcut ways of reading the EEPROM and MII bus. 59854134Swpaul */ 59954134Swpaul#define DC_PN_GPIO 0x60 /* general purpose pins control */ 60054134Swpaul#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ 60154134Swpaul#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ 60254134Swpaul#define DC_PN_MII 0xA0 /* MII access register */ 60354134Swpaul#define DC_PN_NWAY 0xB8 /* Internal NWAY register */ 60454134Swpaul 60554134Swpaul/* Serial I/O EEPROM register */ 60654134Swpaul#define DC_PN_SIOCTL_DATA 0x0000003F 60754134Swpaul#define DC_PN_SIOCTL_OPCODE 0x00000300 60854134Swpaul#define DC_PN_SIOCTL_BUSY 0x80000000 60954134Swpaul 61054134Swpaul#define DC_PN_EEOPCODE_ERASE 0x00000300 61154134Swpaul#define DC_PN_EEOPCODE_READ 0x00000600 61254134Swpaul#define DC_PN_EEOPCODE_WRITE 0x00000100 61354134Swpaul 61454134Swpaul/* 61554134Swpaul * The first two general purpose pins control speed selection and 61654134Swpaul * 100Mbps loopback on the 82c168 chip. The control bits should always 61754134Swpaul * be set (to make the data pins outputs) and the speed selction and 61854134Swpaul * loopback bits set accordingly when changing media. Physically, this 61954134Swpaul * will set the state of a relay mounted on the card. 62054134Swpaul */ 62154134Swpaul#define DC_PN_GPIO_DATA0 0x000000001 62254134Swpaul#define DC_PN_GPIO_DATA1 0x000000002 62354134Swpaul#define DC_PN_GPIO_DATA2 0x000000004 62454134Swpaul#define DC_PN_GPIO_DATA3 0x000000008 62554134Swpaul#define DC_PN_GPIO_CTL0 0x000000010 62654134Swpaul#define DC_PN_GPIO_CTL1 0x000000020 62754134Swpaul#define DC_PN_GPIO_CTL2 0x000000040 62854134Swpaul#define DC_PN_GPIO_CTL3 0x000000080 62954134Swpaul#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ 63054134Swpaul#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ 63154134Swpaul#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 63254134Swpaul#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 63354134Swpaul#define DC_PN_GPIO_SETBIT(sc, r) \ 63454134Swpaul DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) 63554134Swpaul#define DC_PN_GPIO_CLRBIT(sc, r) \ 63654134Swpaul { \ 63754134Swpaul DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ 63854134Swpaul DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ 63954134Swpaul } 64054134Swpaul 64154134Swpaul/* shortcut MII access register */ 64254134Swpaul#define DC_PN_MII_DATA 0x0000FFFF 64354134Swpaul#define DC_PN_MII_RESERVER 0x00020000 64454134Swpaul#define DC_PN_MII_REGADDR 0x007C0000 64554134Swpaul#define DC_PN_MII_PHYADDR 0x0F800000 64654134Swpaul#define DC_PN_MII_OPCODE 0x30000000 64754134Swpaul#define DC_PN_MII_BUSY 0x80000000 64854134Swpaul 64954134Swpaul#define DC_PN_MIIOPCODE_READ 0x60020000 65054134Swpaul#define DC_PN_MIIOPCODE_WRITE 0x50020000 65154134Swpaul 65254134Swpaul/* Internal NWAY bits */ 65354134Swpaul#define DC_PN_NWAY_RESET 0x00000001 /* reset */ 65454134Swpaul#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ 65554134Swpaul#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ 65654134Swpaul#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ 65754134Swpaul#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ 65854134Swpaul#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ 65954134Swpaul#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ 66054134Swpaul#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ 66154134Swpaul#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ 66254134Swpaul#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ 66354134Swpaul#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ 66454134Swpaul#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ 66554134Swpaul#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ 66654134Swpaul#define DC_PN_NWAY_CAP10HDX 0x00002000 66754134Swpaul#define DC_PN_NWAY_CAP10FDX 0x00004000 66854134Swpaul#define DC_PN_NWAY_CAP100FDX 0x00008000 66954134Swpaul#define DC_PN_NWAY_CAP100HDX 0x00010000 67054134Swpaul#define DC_PN_NWAY_CAP100T4 0x00020000 67154134Swpaul#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ 67254134Swpaul#define DC_PN_NWAY_REMFAULT 0x04000000 67354134Swpaul#define DC_PN_NWAY_LPAR10HDX 0x08000000 67454134Swpaul#define DC_PN_NWAY_LPAR10FDX 0x10000000 67554134Swpaul#define DC_PN_NWAY_LPAR100FDX 0x20000000 67654134Swpaul#define DC_PN_NWAY_LPAR100HDX 0x40000000 67754134Swpaul#define DC_PN_NWAY_LPAR100T4 0x80000000 67854134Swpaul 67954134Swpaul/* End of PNIC specific registers */ 68054134Swpaul 68182978Swpaul/* 68282978Swpaul * CONEXANT specific registers. 68382978Swpaul */ 68482978Swpaul 68582978Swpaul#define DC_CONEXANT_PHYADDR 0x1 68682978Swpaul#define DC_CONEXANT_EE_NODEADDR 0x19A 68782978Swpaul 68882978Swpaul/* End of CONEXANT specific registers */ 68982978Swpaul 69082978Swpaul 69154134Swpaulstruct dc_softc { 69254134Swpaul struct arpcom arpcom; /* interface info */ 69354134Swpaul bus_space_handle_t dc_bhandle; /* bus space handle */ 69454134Swpaul bus_space_tag_t dc_btag; /* bus space tag */ 69554134Swpaul void *dc_intrhand; 69654134Swpaul struct resource *dc_irq; 69754134Swpaul struct resource *dc_res; 69854134Swpaul struct dc_type *dc_info; /* adapter info */ 69954134Swpaul device_t dc_miibus; 70054134Swpaul u_int8_t dc_unit; /* interface number */ 70154134Swpaul u_int8_t dc_type; 70254134Swpaul u_int8_t dc_pmode; 70354134Swpaul u_int8_t dc_link; 70454134Swpaul u_int8_t dc_cachesize; 70554134Swpaul int dc_pnic_rx_bug_save; 70654134Swpaul unsigned char *dc_pnic_rx_buf; 70754134Swpaul int dc_if_flags; 70854134Swpaul int dc_if_media; 70954134Swpaul u_int32_t dc_flags; 71054134Swpaul u_int32_t dc_txthresh; 71166681Swpaul u_int8_t dc_srom[1024]; 71266681Swpaul struct dc_mediainfo *dc_mi; 71354134Swpaul struct dc_list_data *dc_ldata; 71454134Swpaul struct dc_chain_data dc_cdata; 71569154Sjlemon struct callout dc_stat_ch; 71666681Swpaul#ifdef SRM_MEDIA 71757901Smsmith int dc_srm_media; 71857901Smsmith#endif 71967087Swpaul struct mtx dc_mtx; 72054134Swpaul}; 72154134Swpaul 72267087Swpaul 72372200Sbmilekic#define DC_LOCK(_sc) mtx_lock(&(_sc)->dc_mtx) 72472200Sbmilekic#define DC_UNLOCK(_sc) mtx_unlock(&(_sc)->dc_mtx) 72567087Swpaul 72654134Swpaul#define DC_TX_POLL 0x00000001 72754134Swpaul#define DC_TX_COALESCE 0x00000002 72854134Swpaul#define DC_TX_ADMTEK_WAR 0x00000004 72954134Swpaul#define DC_TX_USE_TX_INTR 0x00000008 73054134Swpaul#define DC_RX_FILTER_TULIP 0x00000010 73154134Swpaul#define DC_TX_INTR_FIRSTFRAG 0x00000020 73254134Swpaul#define DC_PNIC_RX_BUG_WAR 0x00000040 73354134Swpaul#define DC_TX_FIXED_RING 0x00000080 73454134Swpaul#define DC_TX_STORENFWD 0x00000100 73554134Swpaul#define DC_REDUCED_MII_POLL 0x00000200 73654577Swpaul#define DC_TX_INTR_ALWAYS 0x00000400 73761110Swpaul#define DC_21143_NWAY 0x00000800 73863229Swpaul#define DC_128BIT_HASH 0x00001000 73963229Swpaul#define DC_64BIT_HASH 0x00002000 74065584Swpaul#define DC_TULIP_LEDS 0x00004000 74166681Swpaul#define DC_TX_ONE 0x00008000 74254134Swpaul 74354134Swpaul/* 74454134Swpaul * register space access macros 74554134Swpaul */ 74654134Swpaul#define CSR_WRITE_4(sc, reg, val) \ 74754134Swpaul bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) 74854134Swpaul 74954134Swpaul#define CSR_READ_4(sc, reg) \ 75054134Swpaul bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) 75154134Swpaul 75254134Swpaul#define DC_TIMEOUT 1000 75354134Swpaul#define ETHER_ALIGN 2 75454134Swpaul 75554134Swpaul/* 75654134Swpaul * General constants that are fun to know. 75754134Swpaul */ 75854134Swpaul 75954134Swpaul/* 76054134Swpaul * DEC PCI vendor ID 76154134Swpaul */ 76254134Swpaul#define DC_VENDORID_DEC 0x1011 76354134Swpaul 76454134Swpaul/* 76554134Swpaul * DEC/Intel 21143 PCI device ID 76654134Swpaul */ 76754134Swpaul#define DC_DEVICEID_21143 0x0019 76854134Swpaul 76954134Swpaul/* 77054134Swpaul * Macronix PCI vendor ID 77154134Swpaul */ 77254134Swpaul#define DC_VENDORID_MX 0x10D9 77354134Swpaul 77454134Swpaul/* 77554134Swpaul * Macronix PMAC device IDs. 77654134Swpaul */ 77754134Swpaul#define DC_DEVICEID_98713 0x0512 77854134Swpaul#define DC_DEVICEID_987x5 0x0531 77963326Swpaul#define DC_DEVICEID_98727 0x0532 78063326Swpaul#define DC_DEVICEID_98732 0x0532 78154134Swpaul 78254134Swpaul/* Macronix PCI revision codes. */ 78354134Swpaul#define DC_REVISION_98713 0x00 78454134Swpaul#define DC_REVISION_98713A 0x10 78554134Swpaul#define DC_REVISION_98715 0x20 78663229Swpaul#define DC_REVISION_98715AEC_C 0x25 78754134Swpaul#define DC_REVISION_98725 0x30 78854134Swpaul 78954134Swpaul/* 79054134Swpaul * Compex PCI vendor ID. 79154134Swpaul */ 79254134Swpaul#define DC_VENDORID_CP 0x11F6 79354134Swpaul 79454134Swpaul/* 79554134Swpaul * Compex PMAC PCI device IDs. 79654134Swpaul */ 79754134Swpaul#define DC_DEVICEID_98713_CP 0x9881 79854134Swpaul 79954134Swpaul/* 80054134Swpaul * Lite-On PNIC PCI vendor ID 80154134Swpaul */ 80254134Swpaul#define DC_VENDORID_LO 0x11AD 80354134Swpaul 80454134Swpaul/* 80554134Swpaul * 82c168/82c169 PNIC device IDs. Both chips have the same device 80654134Swpaul * ID but different revisions. Revision 0x10 is the 82c168, and 80754134Swpaul * 0x20 is the 82c169. 80854134Swpaul */ 80954134Swpaul#define DC_DEVICEID_82C168 0x0002 81054134Swpaul 81154134Swpaul#define DC_REVISION_82C168 0x10 81254134Swpaul#define DC_REVISION_82C169 0x20 81354134Swpaul 81454134Swpaul/* 81554134Swpaul * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A 81654134Swpaul * with wake on lan/magic packet support. 81754134Swpaul */ 81854134Swpaul#define DC_DEVICEID_82C115 0xc115 81954134Swpaul 82054134Swpaul/* 82154134Swpaul * Davicom vendor ID. 82254134Swpaul */ 82354134Swpaul#define DC_VENDORID_DAVICOM 0x1282 82454134Swpaul 82554134Swpaul/* 82654134Swpaul * Davicom device IDs. 82754134Swpaul */ 82854134Swpaul#define DC_DEVICEID_DM9100 0x9100 82954134Swpaul#define DC_DEVICEID_DM9102 0x9102 83054134Swpaul 83154134Swpaul/* 83256295Swpaul * The DM9102A has the same PCI device ID as the DM9102, 83356295Swpaul * but a higher revision code. 83456295Swpaul */ 83556295Swpaul#define DC_REVISION_DM9102 0x10 83656295Swpaul#define DC_REVISION_DM9102A 0x30 83756295Swpaul 83856295Swpaul/* 83954134Swpaul * ADMtek vendor ID. 84054134Swpaul */ 84154134Swpaul#define DC_VENDORID_ADMTEK 0x1317 84254134Swpaul 84354134Swpaul/* 84454134Swpaul * ADMtek device IDs. 84554134Swpaul */ 84654134Swpaul#define DC_DEVICEID_AL981 0x0981 84754134Swpaul#define DC_DEVICEID_AN985 0x0985 84854134Swpaul 84954134Swpaul/* 85054134Swpaul * ASIX vendor ID. 85154134Swpaul */ 85254134Swpaul#define DC_VENDORID_ASIX 0x125B 85354134Swpaul 85454134Swpaul/* 85554134Swpaul * ASIX device IDs. 85654134Swpaul */ 85754134Swpaul#define DC_DEVICEID_AX88140A 0x1400 85854134Swpaul 85954134Swpaul/* 86054134Swpaul * The ASIX AX88140 and ASIX AX88141 have the same vendor and 86154134Swpaul * device IDs but different revision values. 86254134Swpaul */ 86354134Swpaul#define DC_REVISION_88140 0x00 86454134Swpaul#define DC_REVISION_88141 0x10 86554134Swpaul 86654134Swpaul/* 86761545Sasmodai * Accton vendor ID. 86861545Sasmodai */ 86961545Sasmodai#define DC_VENDORID_ACCTON 0x1113 87061545Sasmodai 87161545Sasmodai/* 87261545Sasmodai * Accton device IDs. 87361545Sasmodai */ 87461545Sasmodai#define DC_DEVICEID_EN1217 0x1217 87568725Swpaul#define DC_DEVICEID_EN2242 0x1216 87661545Sasmodai 87761545Sasmodai/* 87867314Sjon * Xircom vendor ID 87967314Sjon */ 88067314Sjon#define DC_VENDORID_XIRCOM 0x115d 88167314Sjon 88267314Sjon/* 88367314Sjon * Xircom device IDs. 88467314Sjon */ 88567314Sjon#define DC_DEVICEID_X3201 0x0003 88667314Sjon 88767771Swpaul/* 88867771Swpaul * Abocom vendor ID 88967771Swpaul */ 89067771Swpaul#define DC_VENDORID_ABOCOM 0x13d1 89167314Sjon 89267314Sjon/* 89367771Swpaul * Abocom device IDs. 89467771Swpaul */ 89567771Swpaul#define DC_DEVICEID_FE2500 0xAB02 89667771Swpaul 89767771Swpaul/* 89882978Swpaul * Conexant vendor ID. 89982978Swpaul */ 90082978Swpaul#define DC_VENDORID_CONEXANT 0x14f1 90182978Swpaul 90282978Swpaul/* 90382978Swpaul * Conexant device IDs. 90482978Swpaul */ 90582978Swpaul#define DC_DEVICEID_RS7112 0x1803 90682978Swpaul 90782978Swpaul/* 90854134Swpaul * PCI low memory base and low I/O base register, and 90954134Swpaul * other PCI registers. 91054134Swpaul */ 91154134Swpaul 91254134Swpaul#define DC_PCI_CFID 0x00 /* Id */ 91354134Swpaul#define DC_PCI_CFCS 0x04 /* Command and status */ 91454134Swpaul#define DC_PCI_CFRV 0x08 /* Revision */ 91554134Swpaul#define DC_PCI_CFLT 0x0C /* Latency timer */ 91654134Swpaul#define DC_PCI_CFBIO 0x10 /* Base I/O address */ 91754134Swpaul#define DC_PCI_CFBMA 0x14 /* Base memory address */ 91854134Swpaul#define DC_PCI_CCIS 0x28 /* Card info struct */ 91954134Swpaul#define DC_PCI_CSID 0x2C /* Subsystem ID */ 92054134Swpaul#define DC_PCI_CBER 0x30 /* Expansion ROM base address */ 92154134Swpaul#define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */ 92254134Swpaul#define DC_PCI_CFIT 0x3C /* Interrupt */ 92354134Swpaul#define DC_PCI_CFDD 0x40 /* Device and driver area */ 92454134Swpaul#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ 92554134Swpaul#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ 92654134Swpaul#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ 92754134Swpaul#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ 92854134Swpaul#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ 92954134Swpaul#define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */ 93054134Swpaul#define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */ 93154134Swpaul 93254134Swpaul/* PCI ID register */ 93354134Swpaul#define DC_CFID_VENDOR 0x0000FFFF 93454134Swpaul#define DC_CFID_DEVICE 0xFFFF0000 93554134Swpaul 93654134Swpaul/* PCI command/status register */ 93754134Swpaul#define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */ 93854134Swpaul#define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */ 93954134Swpaul#define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */ 94054134Swpaul#define DC_CFCS_MWI_ENB 0x00000008 /* mem write and inval enable */ 94154134Swpaul#define DC_CFCS_PARITYERR_ENB 0x00000020 /* parity error enable */ 94254134Swpaul#define DC_CFCS_SYSERR_ENB 0x00000080 /* system error enable */ 94354134Swpaul#define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */ 94454134Swpaul#define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */ 94554134Swpaul#define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */ 94654134Swpaul#define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */ 94754134Swpaul#define DC_CFCS_TGTABRT 0x10000000 /* received target abort */ 94854134Swpaul#define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */ 94954134Swpaul#define DC_CFCS_SYSERR 0x40000000 /* asserted system error */ 95054134Swpaul#define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */ 95154134Swpaul 95254134Swpaul/* PCI revision register */ 95354134Swpaul#define DC_CFRV_STEPPING 0x0000000F 95454134Swpaul#define DC_CFRV_REVISION 0x000000F0 95554134Swpaul#define DC_CFRV_SUBCLASS 0x00FF0000 95654134Swpaul#define DC_CFRV_BASECLASS 0xFF000000 95754134Swpaul 95854134Swpaul#define DC_21143_PB_REV 0x00000030 95954134Swpaul#define DC_21143_TB_REV 0x00000030 96054134Swpaul#define DC_21143_PC_REV 0x00000030 96154134Swpaul#define DC_21143_TC_REV 0x00000030 96254134Swpaul#define DC_21143_PD_REV 0x00000041 96354134Swpaul#define DC_21143_TD_REV 0x00000041 96454134Swpaul 96554134Swpaul/* PCI latency timer register */ 96654134Swpaul#define DC_CFLT_CACHELINESIZE 0x000000FF 96754134Swpaul#define DC_CFLT_LATENCYTIMER 0x0000FF00 96854134Swpaul 96954134Swpaul/* PCI subsystem ID register */ 97054134Swpaul#define DC_CSID_VENDOR 0x0000FFFF 97154134Swpaul#define DC_CSID_DEVICE 0xFFFF0000 97254134Swpaul 97354134Swpaul/* PCI cababilities pointer */ 97454134Swpaul#define DC_CCAP_OFFSET 0x000000FF 97554134Swpaul 97654134Swpaul/* PCI interrupt config register */ 97754134Swpaul#define DC_CFIT_INTLINE 0x000000FF 97854134Swpaul#define DC_CFIT_INTPIN 0x0000FF00 97954134Swpaul#define DC_CFIT_MIN_GNT 0x00FF0000 98054134Swpaul#define DC_CFIT_MAX_LAT 0xFF000000 98154134Swpaul 98254134Swpaul/* PCI capability register */ 98354134Swpaul#define DC_CCID_CAPID 0x000000FF 98454134Swpaul#define DC_CCID_NEXTPTR 0x0000FF00 98554134Swpaul#define DC_CCID_PM_VERS 0x00070000 98654134Swpaul#define DC_CCID_PME_CLK 0x00080000 98754134Swpaul#define DC_CCID_DVSPEC_INT 0x00200000 98854134Swpaul#define DC_CCID_STATE_D1 0x02000000 98954134Swpaul#define DC_CCID_STATE_D2 0x04000000 99054134Swpaul#define DC_CCID_PME_D0 0x08000000 99154134Swpaul#define DC_CCID_PME_D1 0x10000000 99254134Swpaul#define DC_CCID_PME_D2 0x20000000 99354134Swpaul#define DC_CCID_PME_D3HOT 0x40000000 99454134Swpaul#define DC_CCID_PME_D3COLD 0x80000000 99554134Swpaul 99654134Swpaul/* PCI power management control/status register */ 99754134Swpaul#define DC_CPMC_STATE 0x00000003 99854134Swpaul#define DC_CPMC_PME_ENB 0x00000100 99954134Swpaul#define DC_CPMC_PME_STS 0x00008000 100054134Swpaul 100154134Swpaul#define DC_PSTATE_D0 0x0 100254134Swpaul#define DC_PSTATE_D1 0x1 100354134Swpaul#define DC_PSTATE_D2 0x2 100454134Swpaul#define DC_PSTATE_D3 0x3 100554134Swpaul 100654134Swpaul/* Device specific region */ 100754134Swpaul/* Configuration and driver area */ 100854134Swpaul#define DC_CFDD_DRVUSE 0x0000FFFF 100954134Swpaul#define DC_CFDD_SNOOZE_MODE 0x40000000 101054134Swpaul#define DC_CFDD_SLEEP_MODE 0x80000000 101154134Swpaul 101254134Swpaul/* Configuration wake-up command register */ 101354134Swpaul#define DC_CWUC_MUST_BE_ZERO 0x00000001 101454134Swpaul#define DC_CWUC_SECUREON_ENB 0x00000002 101554134Swpaul#define DC_CWUC_FORCE_WUL 0x00000004 101654134Swpaul#define DC_CWUC_BNC_ABILITY 0x00000008 101754134Swpaul#define DC_CWUC_AUI_ABILITY 0x00000010 101854134Swpaul#define DC_CWUC_TP10_ABILITY 0x00000020 101954134Swpaul#define DC_CWUC_MII_ABILITY 0x00000040 102054134Swpaul#define DC_CWUC_SYM_ABILITY 0x00000080 102154134Swpaul#define DC_CWUC_LOCK 0x00000100 102254134Swpaul 102366681Swpaul/* 102466681Swpaul * SROM nonsense. 102566681Swpaul */ 102666681Swpaul 102766681Swpaul#define DC_IB_CTLRCNT 0x13 102866681Swpaul#define DC_IB_LEAF0_CNUM 0x1A 102966681Swpaul#define DC_IB_LEAF0_OFFSET 0x1B 103066681Swpaul 103166681Swpaulstruct dc_info_leaf { 103266681Swpaul u_int16_t dc_conntype; 103366681Swpaul u_int8_t dc_blkcnt; 103466681Swpaul u_int8_t dc_rsvd; 103566681Swpaul u_int16_t dc_infoblk; 103666681Swpaul}; 103766681Swpaul 103866681Swpaul#define DC_CTYPE_10BT 0x0000 103966681Swpaul#define DC_CTYPE_10BT_NWAY 0x0100 104066681Swpaul#define DC_CTYPE_10BT_FDX 0x0204 104166681Swpaul#define DC_CTYPE_10B2 0x0001 104266681Swpaul#define DC_CTYPE_10B5 0x0002 104366681Swpaul#define DC_CTYPE_100BT 0x0003 104466681Swpaul#define DC_CTYPE_100BT_FDX 0x0205 104566681Swpaul#define DC_CTYPE_100T4 0x0006 104666681Swpaul#define DC_CTYPE_100FX 0x0007 104766681Swpaul#define DC_CTYPE_100FX_FDX 0x0208 104866681Swpaul#define DC_CTYPE_MII_10BT 0x0009 104966681Swpaul#define DC_CTYPE_MII_10BT_FDX 0x020A 105066681Swpaul#define DC_CTYPE_MII_100BT 0x000D 105166681Swpaul#define DC_CTYPE_MII_100BT_FDX 0x020E 105266681Swpaul#define DC_CTYPE_MII_100T4 0x000F 105366681Swpaul#define DC_CTYPE_MII_100FX 0x0010 105466681Swpaul#define DC_CTYPE_MII_100FX_FDX 0x0211 105566681Swpaul#define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 105666681Swpaul#define DC_CTYPE_PUP_AUTOSENSe 0x8800 105766681Swpaul#define DC_CTYPE_NOMEDIA 0xFFFF 105866681Swpaul 105966681Swpaul#define DC_EBLOCK_SIA 0x0002 106066681Swpaul#define DC_EBLOCK_MII 0x0003 106166681Swpaul#define DC_EBLOCK_SYM 0x0004 106266681Swpaul#define DC_EBLOCK_RESET 0x0005 106366681Swpaul#define DC_EBLOCK_PHY_SHUTDOWN 0x0006 106466681Swpaul 106566681Swpaulstruct dc_leaf_hdr { 106666681Swpaul u_int16_t dc_mtype; 106766681Swpaul u_int8_t dc_mcnt; 106866681Swpaul u_int8_t dc_rsvd; 106966681Swpaul}; 107066681Swpaul 107166681Swpaulstruct dc_eblock_hdr { 107266681Swpaul u_int8_t dc_len; 107366681Swpaul u_int8_t dc_type; 107466681Swpaul}; 107566681Swpaul 107666681Swpaulstruct dc_eblock_sia { 107766681Swpaul struct dc_eblock_hdr dc_sia_hdr; 107866681Swpaul u_int8_t dc_sia_code; 107966681Swpaul u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ 108066681Swpaul u_int8_t dc_sia_gpio_ctl[2]; 108166681Swpaul u_int8_t dc_sia_gpio_dat[2]; 108266681Swpaul}; 108366681Swpaul 108466681Swpaul#define DC_SIA_CODE_10BT 0x00 108566681Swpaul#define DC_SIA_CODE_10B2 0x01 108666681Swpaul#define DC_SIA_CODE_10B5 0x02 108766681Swpaul#define DC_SIA_CODE_10BT_FDX 0x04 108866681Swpaul#define DC_SIA_CODE_EXT 0x40 108966681Swpaul 109066681Swpaul/* 109166681Swpaul * Note that the first word in the gpr and reset 109266681Swpaul * sequences is always a control word. 109366681Swpaul */ 109466681Swpaulstruct dc_eblock_mii { 109566681Swpaul struct dc_eblock_hdr dc_mii_hdr; 109666681Swpaul u_int8_t dc_mii_phynum; 109766681Swpaul u_int8_t dc_gpr_len; 109866681Swpaul/* u_int16_t dc_gpr_dat[n]; */ 109966681Swpaul/* u_int8_t dc_reset_len; */ 110066681Swpaul/* u_int16_t dc_reset_dat[n]; */ 110166681Swpaul/* There are other fields after these, but we don't 110266681Swpaul * care about them since they can be determined by looking 110366681Swpaul * at the PHY. 110466681Swpaul */ 110566681Swpaul}; 110666681Swpaul 110766681Swpaulstruct dc_eblock_sym { 110866681Swpaul struct dc_eblock_hdr dc_sym_hdr; 110966681Swpaul u_int8_t dc_sym_code; 111066681Swpaul u_int8_t dc_sym_gpio_ctl[2]; 111166681Swpaul u_int8_t dc_sym_gpio_dat[2]; 111266681Swpaul u_int8_t dc_sym_cmd[2]; 111366681Swpaul}; 111466681Swpaul 111566681Swpaul#define DC_SYM_CODE_100BT 0x03 111666681Swpaul#define DC_SYM_CODE_100BT_FDX 0x05 111766681Swpaul#define DC_SYM_CODE_100T4 0x06 111866681Swpaul#define DC_SYM_CODE_100FX 0x07 111966681Swpaul#define DC_SYM_CODE_100FX_FDX 0x08 112066681Swpaul 112166681Swpaulstruct dc_eblock_reset { 112266681Swpaul struct dc_eblock_hdr dc_reset_hdr; 112366681Swpaul u_int8_t dc_reset_len; 112466681Swpaul/* u_int16_t dc_reset_dat[n]; */ 112566681Swpaul}; 112666681Swpaul 112754134Swpaul#ifdef __alpha__ 112854134Swpaul#undef vtophys 112954134Swpaul#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 113054134Swpaul#endif 1131