if_dcreg.h revision 56295
154134Swpaul/* 254134Swpaul * Copyright (c) 1997, 1998, 1999 354134Swpaul * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 454134Swpaul * 554134Swpaul * Redistribution and use in source and binary forms, with or without 654134Swpaul * modification, are permitted provided that the following conditions 754134Swpaul * are met: 854134Swpaul * 1. Redistributions of source code must retain the above copyright 954134Swpaul * notice, this list of conditions and the following disclaimer. 1054134Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1154134Swpaul * notice, this list of conditions and the following disclaimer in the 1254134Swpaul * documentation and/or other materials provided with the distribution. 1354134Swpaul * 3. All advertising materials mentioning features or use of this software 1454134Swpaul * must display the following acknowledgement: 1554134Swpaul * This product includes software developed by Bill Paul. 1654134Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1754134Swpaul * may be used to endorse or promote products derived from this software 1854134Swpaul * without specific prior written permission. 1954134Swpaul * 2054134Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2154134Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2254134Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2354134Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2454134Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2554134Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2654134Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2754134Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2854134Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2954134Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3054134Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3154134Swpaul * 3254134Swpaul * $FreeBSD: head/sys/dev/dc/if_dcreg.h 56295 2000-01-19 19:03:08Z wpaul $ 3354134Swpaul */ 3454134Swpaul 3554134Swpaul/* 3654134Swpaul * 21143 and clone common register definitions. 3754134Swpaul */ 3854134Swpaul 3954134Swpaul#define DC_BUSCTL 0x00 /* bus control */ 4054134Swpaul#define DC_TXSTART 0x08 /* tx start demand */ 4154134Swpaul#define DC_RXSTART 0x10 /* rx start demand */ 4254134Swpaul#define DC_RXADDR 0x18 /* rx descriptor list start addr */ 4354134Swpaul#define DC_TXADDR 0x20 /* tx descriptor list start addr */ 4454134Swpaul#define DC_ISR 0x28 /* interrupt status register */ 4554134Swpaul#define DC_NETCFG 0x30 /* network config register */ 4654134Swpaul#define DC_IMR 0x38 /* interrupt mask */ 4754134Swpaul#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ 4854134Swpaul#define DC_SIO 0x48 /* MII and ROM/EEPROM access */ 4954134Swpaul#define DC_ROM 0x50 /* ROM programming address */ 5054134Swpaul#define DC_TIMER 0x58 /* general timer */ 5154134Swpaul#define DC_10BTSTAT 0x60 /* SIA status */ 5254134Swpaul#define DC_SIARESET 0x68 /* SIA connectivity */ 5354134Swpaul#define DC_10BTCTRL 0x70 /* SIA transmit and receive */ 5454134Swpaul#define DC_WATCHDOG 0x78 /* SIA and general purpose port */ 5554134Swpaul 5654134Swpaul/* 5754134Swpaul * There are two general 'types' of MX chips that we need to be 5854134Swpaul * concerned with. One is the original 98713, which has its internal 5954134Swpaul * NWAY support controlled via the MDIO bits in the serial I/O 6054134Swpaul * register. The other is everything else (from the 98713A on up), 6154134Swpaul * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, 6254134Swpaul * just like the 21143. This type setting also governs which of the 6354134Swpaul * 'magic' numbers we write to CSR16. The PNIC II falls into the 6454134Swpaul * 98713A/98715/98715A/98725 category. 6554134Swpaul */ 6654134Swpaul#define DC_TYPE_98713 0x1 6754134Swpaul#define DC_TYPE_98713A 0x2 6854134Swpaul#define DC_TYPE_987x5 0x3 6954134Swpaul 7054134Swpaul/* Other type of supported chips. */ 7154134Swpaul#define DC_TYPE_21143 0x4 /* Intel 21143 */ 7254134Swpaul#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ 7354134Swpaul#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ 7454134Swpaul#define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */ 7554134Swpaul#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ 7654134Swpaul#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ 7754134Swpaul#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ 7854134Swpaul 7954134Swpaul#define DC_IS_MACRONIX(x) \ 8054134Swpaul (x->dc_type == DC_TYPE_98713 || \ 8154134Swpaul x->dc_type == DC_TYPE_98713A || \ 8254134Swpaul x->dc_type == DC_TYPE_987x5) 8354134Swpaul 8454134Swpaul#define DC_IS_ADMTEK(x) \ 8554134Swpaul (x->dc_type == DC_TYPE_AL981 || \ 8654134Swpaul x->dc_type == DC_TYPE_AN985) 8754134Swpaul 8854134Swpaul#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) 8954134Swpaul#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) 9054134Swpaul#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) 9154134Swpaul#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985) 9254134Swpaul#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) 9354134Swpaul#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) 9454134Swpaul#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) 9554134Swpaul 9654134Swpaul/* MII/symbol mode port types */ 9754134Swpaul#define DC_PMODE_MII 0x1 9854134Swpaul#define DC_PMODE_SYM 0x2 9954134Swpaul 10054134Swpaul/* 10154134Swpaul * Bus control bits. 10254134Swpaul */ 10354134Swpaul#define DC_BUSCTL_RESET 0x00000001 10454134Swpaul#define DC_BUSCTL_ARBITRATION 0x00000002 10554134Swpaul#define DC_BUSCTL_SKIPLEN 0x0000007C 10654134Swpaul#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 10754134Swpaul#define DC_BUSCTL_BURSTLEN 0x00003F00 10854134Swpaul#define DC_BUSCTL_CACHEALIGN 0x0000C000 10954134Swpaul#define DC_BUSCTL_TXPOLL 0x000E0000 11054134Swpaul#define DC_BUSCTL_DBO 0x00100000 11154134Swpaul#define DC_BUSCTL_MRME 0x00200000 11254134Swpaul#define DC_BUSCTL_MRLE 0x00800000 11354134Swpaul#define DC_BUSCTL_MWIE 0x01000000 11454134Swpaul#define DC_BUSCTL_ONNOW_ENB 0x04000000 11554134Swpaul 11654134Swpaul#define DC_SKIPLEN_1LONG 0x00000004 11754134Swpaul#define DC_SKIPLEN_2LONG 0x00000008 11854134Swpaul#define DC_SKIPLEN_3LONG 0x00000010 11954134Swpaul#define DC_SKIPLEN_4LONG 0x00000020 12054134Swpaul#define DC_SKIPLEN_5LONG 0x00000040 12154134Swpaul 12254134Swpaul#define DC_CACHEALIGN_NONE 0x00000000 12354134Swpaul#define DC_CACHEALIGN_8LONG 0x00004000 12454134Swpaul#define DC_CACHEALIGN_16LONG 0x00008000 12554134Swpaul#define DC_CACHEALIGN_32LONG 0x0000C000 12654134Swpaul 12754134Swpaul#define DC_BURSTLEN_USECA 0x00000000 12854134Swpaul#define DC_BURSTLEN_1LONG 0x00000100 12954134Swpaul#define DC_BURSTLEN_2LONG 0x00000200 13054134Swpaul#define DC_BURSTLEN_4LONG 0x00000400 13154134Swpaul#define DC_BURSTLEN_8LONG 0x00000800 13254134Swpaul#define DC_BURSTLEN_16LONG 0x00001000 13354134Swpaul#define DC_BURSTLEN_32LONG 0x00002000 13454134Swpaul 13554134Swpaul#define DC_TXPOLL_OFF 0x00000000 13654134Swpaul#define DC_TXPOLL_1 0x00020000 13754134Swpaul#define DC_TXPOLL_2 0x00040000 13854134Swpaul#define DC_TXPOLL_3 0x00060000 13954134Swpaul#define DC_TXPOLL_4 0x00080000 14054134Swpaul#define DC_TXPOLL_5 0x000A0000 14154134Swpaul#define DC_TXPOLL_6 0x000C0000 14254134Swpaul#define DC_TXPOLL_7 0x000E0000 14354134Swpaul 14454134Swpaul/* 14554134Swpaul * Interrupt status bits. 14654134Swpaul */ 14754134Swpaul#define DC_ISR_TX_OK 0x00000001 14854134Swpaul#define DC_ISR_TX_IDLE 0x00000002 14954134Swpaul#define DC_ISR_TX_NOBUF 0x00000004 15054134Swpaul#define DC_ISR_TX_JABBERTIMEO 0x00000008 15154134Swpaul#define DC_ISR_LINKGOOD 0x00000010 15254134Swpaul#define DC_ISR_TX_UNDERRUN 0x00000020 15354134Swpaul#define DC_ISR_RX_OK 0x00000040 15454134Swpaul#define DC_ISR_RX_NOBUF 0x00000080 15554134Swpaul#define DC_ISR_RX_READ 0x00000100 15654134Swpaul#define DC_ISR_RX_WATDOGTIMEO 0x00000200 15754134Swpaul#define DC_ISR_TX_EARLY 0x00000400 15854134Swpaul#define DC_ISR_TIMER_EXPIRED 0x00000800 15954134Swpaul#define DC_ISR_LINKFAIL 0x00001000 16054134Swpaul#define DC_ISR_BUS_ERR 0x00002000 16154134Swpaul#define DC_ISR_RX_EARLY 0x00004000 16254134Swpaul#define DC_ISR_ABNORMAL 0x00008000 16354134Swpaul#define DC_ISR_NORMAL 0x00010000 16454134Swpaul#define DC_ISR_RX_STATE 0x000E0000 16554134Swpaul#define DC_ISR_TX_STATE 0x00700000 16654134Swpaul#define DC_ISR_BUSERRTYPE 0x03800000 16754134Swpaul#define DC_ISR_100MBPSLINK 0x08000000 16854134Swpaul#define DC_ISR_MAGICKPACK 0x10000000 16954134Swpaul 17054134Swpaul#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 17154134Swpaul#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 17254134Swpaul#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 17354134Swpaul#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 17454134Swpaul#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 17554134Swpaul#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 17654134Swpaul#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 17754134Swpaul#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 17854134Swpaul 17954134Swpaul#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ 18054134Swpaul#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 18154134Swpaul#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 18254134Swpaul#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 18354134Swpaul#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 18454134Swpaul#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 18554134Swpaul#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 18654134Swpaul#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 18754134Swpaul 18854134Swpaul/* 18954134Swpaul * Network config bits. 19054134Swpaul */ 19154134Swpaul#define DC_NETCFG_RX_HASHPERF 0x00000001 19254134Swpaul#define DC_NETCFG_RX_ON 0x00000002 19354134Swpaul#define DC_NETCFG_RX_HASHONLY 0x00000004 19454134Swpaul#define DC_NETCFG_RX_BADFRAMES 0x00000008 19554134Swpaul#define DC_NETCFG_RX_INVFILT 0x00000010 19654134Swpaul#define DC_NETCFG_BACKOFFCNT 0x00000020 19754134Swpaul#define DC_NETCFG_RX_PROMISC 0x00000040 19854134Swpaul#define DC_NETCFG_RX_ALLMULTI 0x00000080 19954134Swpaul#define DC_NETCFG_FULLDUPLEX 0x00000200 20054134Swpaul#define DC_NETCFG_LOOPBACK 0x00000C00 20154134Swpaul#define DC_NETCFG_FORCECOLL 0x00001000 20254134Swpaul#define DC_NETCFG_TX_ON 0x00002000 20354134Swpaul#define DC_NETCFG_TX_THRESH 0x0000C000 20454134Swpaul#define DC_NETCFG_TX_BACKOFF 0x00020000 20554134Swpaul#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ 20654134Swpaul#define DC_NETCFG_HEARTBEAT 0x00080000 20754134Swpaul#define DC_NETCFG_STORENFWD 0x00200000 20854134Swpaul#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ 20954134Swpaul#define DC_NETCFG_PCS 0x00800000 21054134Swpaul#define DC_NETCFG_SCRAMBLER 0x01000000 21154134Swpaul#define DC_NETCFG_NO_RXCRC 0x02000000 21254134Swpaul#define DC_NETCFG_RX_ALL 0x40000000 21354134Swpaul#define DC_NETCFG_CAPEFFECT 0x80000000 21454134Swpaul 21554134Swpaul#define DC_OPMODE_NORM 0x00000000 21654134Swpaul#define DC_OPMODE_INTLOOP 0x00000400 21754134Swpaul#define DC_OPMODE_EXTLOOP 0x00000800 21854134Swpaul 21954134Swpaul#define DC_TXTHRESH_72BYTES 0x00000000 22054134Swpaul#define DC_TXTHRESH_96BYTES 0x00004000 22154134Swpaul#define DC_TXTHRESH_128BYTES 0x00008000 22254134Swpaul#define DC_TXTHRESH_160BYTES 0x0000C000 22354134Swpaul 22454134Swpaul 22554134Swpaul/* 22654134Swpaul * Interrupt mask bits. 22754134Swpaul */ 22854134Swpaul#define DC_IMR_TX_OK 0x00000001 22954134Swpaul#define DC_IMR_TX_IDLE 0x00000002 23054134Swpaul#define DC_IMR_TX_NOBUF 0x00000004 23154134Swpaul#define DC_IMR_TX_JABBERTIMEO 0x00000008 23254134Swpaul#define DC_IMR_LINKGOOD 0x00000010 23354134Swpaul#define DC_IMR_TX_UNDERRUN 0x00000020 23454134Swpaul#define DC_IMR_RX_OK 0x00000040 23554134Swpaul#define DC_IMR_RX_NOBUF 0x00000080 23654134Swpaul#define DC_IMR_RX_READ 0x00000100 23754134Swpaul#define DC_IMR_RX_WATDOGTIMEO 0x00000200 23854134Swpaul#define DC_IMR_TX_EARLY 0x00000400 23954134Swpaul#define DC_IMR_TIMER_EXPIRED 0x00000800 24054134Swpaul#define DC_IMR_LINKFAIL 0x00001000 24154134Swpaul#define DC_IMR_BUS_ERR 0x00002000 24254134Swpaul#define DC_IMR_RX_EARLY 0x00004000 24354134Swpaul#define DC_IMR_ABNORMAL 0x00008000 24454134Swpaul#define DC_IMR_NORMAL 0x00010000 24554134Swpaul#define DC_IMR_100MBPSLINK 0x08000000 24654134Swpaul#define DC_IMR_MAGICKPACK 0x10000000 24754134Swpaul 24854134Swpaul#define DC_INTRS \ 24954134Swpaul (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ 25054134Swpaul DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ 25154134Swpaul DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) 25254134Swpaul/* 25354134Swpaul * Serial I/O (EEPROM/ROM) bits. 25454134Swpaul */ 25554134Swpaul#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 25654134Swpaul#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 25754134Swpaul#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 25854134Swpaul#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 25954134Swpaul#define DC_SIO_ROMDATA4 0x00000010 26054134Swpaul#define DC_SIO_ROMDATA5 0x00000020 26154134Swpaul#define DC_SIO_ROMDATA6 0x00000040 26254134Swpaul#define DC_SIO_ROMDATA7 0x00000080 26354134Swpaul#define DC_SIO_EESEL 0x00000800 26454134Swpaul#define DC_SIO_ROMSEL 0x00001000 26554134Swpaul#define DC_SIO_ROMCTL_WRITE 0x00002000 26654134Swpaul#define DC_SIO_ROMCTL_READ 0x00004000 26754134Swpaul#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ 26854134Swpaul#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ 26954134Swpaul#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ 27054134Swpaul#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ 27154134Swpaul 27254134Swpaul#define DC_EECMD_WRITE 0x140 27354134Swpaul#define DC_EECMD_READ 0x180 27454134Swpaul#define DC_EECMD_ERASE 0x1c0 27554134Swpaul 27654134Swpaul#define DC_EE_NODEADDR_OFFSET 0x70 27754134Swpaul#define DC_EE_NODEADDR 10 27854134Swpaul 27954134Swpaul/* 28054134Swpaul * General purpose timer register 28154134Swpaul */ 28254134Swpaul#define DC_TIMER_VALUE 0x0000FFFF 28354134Swpaul#define DC_TIMER_CONTINUOUS 0x00010000 28454134Swpaul 28554134Swpaul/* 28654134Swpaul * 10baseT status register 28754134Swpaul */ 28854134Swpaul#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ 28954134Swpaul#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ 29054134Swpaul#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ 29154134Swpaul#define DC_TSTAT_AUTOPOLARITY 0x00000008 29254134Swpaul#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ 29354134Swpaul#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ 29454134Swpaul#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ 29554134Swpaul#define DC_TSTAT_REMFAULT 0x00000800 29654134Swpaul#define DC_TSTAT_ANEGSTAT 0x00007000 29754134Swpaul#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ 29854134Swpaul#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ 29954134Swpaul 30054134Swpaul#define DC_ASTAT_DISABLE 0x00000000 30154134Swpaul#define DC_ASTAT_TXDISABLE 0x00001000 30254134Swpaul#define DC_ASTAT_ABDETECT 0x00002000 30354134Swpaul#define DC_ASTAT_ACKDETECT 0x00003000 30454134Swpaul#define DC_ASTAT_CMPACKDETECT 0x00004000 30554134Swpaul#define DC_ASTAT_AUTONEGCMP 0x00005000 30654134Swpaul#define DC_ASTAT_LINKCHECK 0x00006000 30754134Swpaul 30854134Swpaul/* 30954134Swpaul * PHY reset register 31054134Swpaul */ 31154134Swpaul#define DC_SIA_RESET 0x00000001 31254134Swpaul#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ 31354134Swpaul 31454134Swpaul/* 31554134Swpaul * 10baseT control register 31654134Swpaul */ 31754134Swpaul#define DC_TCTL_ENCODER_ENB 0x00000001 31854134Swpaul#define DC_TCTL_LOOPBACK 0x00000002 31954134Swpaul#define DC_TCTL_DRIVER_ENB 0x00000004 32054134Swpaul#define DC_TCTL_LNKPULSE_ENB 0x00000008 32154134Swpaul#define DC_TCTL_HALFDUPLEX 0x00000040 32254134Swpaul#define DC_TCTL_AUTONEGENBL 0x00000080 32354134Swpaul#define DC_TCTL_RX_SQUELCH 0x00000100 32454134Swpaul#define DC_TCTL_COLL_SQUELCH 0x00000200 32554134Swpaul#define DC_TCTL_COLL_DETECT 0x00000400 32654134Swpaul#define DC_TCTL_SQE_ENB 0x00000800 32754134Swpaul#define DC_TCTL_LINKTEST 0x00001000 32854134Swpaul#define DC_TCTL_AUTOPOLARITY 0x00002000 32954134Swpaul#define DC_TCTL_SET_POL_PLUS 0x00004000 33054134Swpaul#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ 33154134Swpaul#define DC_TCTL_100BTXHALF 0x00010000 33254134Swpaul#define DC_TCTL_100BTXFULL 0x00020000 33354134Swpaul#define DC_TCTL_100BT4 0x00040000 33454134Swpaul 33554134Swpaul/* 33654134Swpaul * Watchdog timer register 33754134Swpaul */ 33854134Swpaul#define DC_WDOG_JABBERDIS 0x00000001 33954134Swpaul#define DC_WDOG_HOSTUNJAB 0x00000002 34054134Swpaul#define DC_WDOG_JABBERCLK 0x00000004 34154134Swpaul#define DC_WDOG_RXWDOGDIS 0x00000010 34254134Swpaul#define DC_WDOG_RXWDOGCLK 0x00000020 34354134Swpaul#define DC_WDOG_MUSTBEZERO 0x00000100 34454134Swpaul 34554134Swpaul/* 34654134Swpaul * Size of a setup frame. 34754134Swpaul */ 34854134Swpaul#define DC_SFRAME_LEN 192 34954134Swpaul 35054134Swpaul/* 35154134Swpaul * 21x4x TX/RX list structure. 35254134Swpaul */ 35354134Swpaul 35454134Swpaulstruct dc_desc { 35554134Swpaul u_int32_t dc_status; 35654134Swpaul u_int32_t dc_ctl; 35754134Swpaul u_int32_t dc_ptr1; 35854134Swpaul u_int32_t dc_ptr2; 35954134Swpaul}; 36054134Swpaul 36154134Swpaul#define dc_data dc_ptr1 36254134Swpaul#define dc_next dc_ptr2 36354134Swpaul 36454134Swpaul#define DC_RXSTAT_FIFOOFLOW 0x00000001 36554134Swpaul#define DC_RXSTAT_CRCERR 0x00000002 36654134Swpaul#define DC_RXSTAT_DRIBBLE 0x00000004 36754134Swpaul#define DC_RXSTAT_WATCHDOG 0x00000010 36854134Swpaul#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ 36954134Swpaul#define DC_RXSTAT_COLLSEEN 0x00000040 37054134Swpaul#define DC_RXSTAT_GIANT 0x00000080 37154134Swpaul#define DC_RXSTAT_LASTFRAG 0x00000100 37254134Swpaul#define DC_RXSTAT_FIRSTFRAG 0x00000200 37354134Swpaul#define DC_RXSTAT_MULTICAST 0x00000400 37454134Swpaul#define DC_RXSTAT_RUNT 0x00000800 37554134Swpaul#define DC_RXSTAT_RXTYPE 0x00003000 37654134Swpaul#define DC_RXSTAT_RXERR 0x00008000 37754134Swpaul#define DC_RXSTAT_RXLEN 0x3FFF0000 37854134Swpaul#define DC_RXSTAT_OWN 0x80000000 37954134Swpaul 38054134Swpaul#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) 38154134Swpaul#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) 38254134Swpaul 38354134Swpaul#define DC_RXCTL_BUFLEN1 0x00000FFF 38454134Swpaul#define DC_RXCTL_BUFLEN2 0x00FFF000 38554134Swpaul#define DC_RXCTL_RLINK 0x01000000 38654134Swpaul#define DC_RXCTL_RLAST 0x02000000 38754134Swpaul 38854134Swpaul#define DC_TXSTAT_DEFER 0x00000001 38954134Swpaul#define DC_TXSTAT_UNDERRUN 0x00000002 39054134Swpaul#define DC_TXSTAT_LINKFAIL 0x00000003 39154134Swpaul#define DC_TXSTAT_COLLCNT 0x00000078 39254134Swpaul#define DC_TXSTAT_SQE 0x00000080 39354134Swpaul#define DC_TXSTAT_EXCESSCOLL 0x00000100 39454134Swpaul#define DC_TXSTAT_LATECOLL 0x00000200 39554134Swpaul#define DC_TXSTAT_NOCARRIER 0x00000400 39654134Swpaul#define DC_TXSTAT_CARRLOST 0x00000800 39754134Swpaul#define DC_TXSTAT_JABTIMEO 0x00004000 39854134Swpaul#define DC_TXSTAT_ERRSUM 0x00008000 39954134Swpaul#define DC_TXSTAT_OWN 0x80000000 40054134Swpaul 40154134Swpaul#define DC_TXCTL_BUFLEN1 0x000007FF 40254134Swpaul#define DC_TXCTL_BUFLEN2 0x003FF800 40354134Swpaul#define DC_TXCTL_FILTTYPE0 0x00400000 40454134Swpaul#define DC_TXCTL_PAD 0x00800000 40554134Swpaul#define DC_TXCTL_TLINK 0x01000000 40654134Swpaul#define DC_TXCTL_TLAST 0x02000000 40754134Swpaul#define DC_TXCTL_NOCRC 0x04000000 40854134Swpaul#define DC_TXCTL_SETUP 0x08000000 40954134Swpaul#define DC_TXCTL_FILTTYPE1 0x10000000 41054134Swpaul#define DC_TXCTL_FIRSTFRAG 0x20000000 41154134Swpaul#define DC_TXCTL_LASTFRAG 0x40000000 41254134Swpaul#define DC_TXCTL_FINT 0x80000000 41354134Swpaul 41454134Swpaul#define DC_FILTER_PERFECT 0x00000000 41554134Swpaul#define DC_FILTER_HASHPERF 0x00400000 41654134Swpaul#define DC_FILTER_INVERSE 0x10000000 41754134Swpaul#define DC_FILTER_HASHONLY 0x10400000 41854134Swpaul 41954134Swpaul#define DC_MAXFRAGS 16 42054134Swpaul#define DC_RX_LIST_CNT 64 42154134Swpaul#define DC_TX_LIST_CNT 256 42254134Swpaul#define DC_MIN_FRAMELEN 60 42354134Swpaul#define DC_RXLEN 1536 42454134Swpaul 42554134Swpaul#define DC_INC(x, y) (x) = (x + 1) % y 42654134Swpaul 42754134Swpaulstruct dc_list_data { 42854134Swpaul struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; 42954134Swpaul struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; 43054134Swpaul}; 43154134Swpaul 43254134Swpaulstruct dc_chain_data { 43354134Swpaul struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; 43454134Swpaul struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; 43554134Swpaul u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)]; 43654134Swpaul u_int8_t dc_pad[DC_MIN_FRAMELEN]; 43754134Swpaul int dc_tx_prod; 43854134Swpaul int dc_tx_cons; 43954134Swpaul int dc_tx_cnt; 44054134Swpaul int dc_rx_prod; 44154134Swpaul}; 44254134Swpaul 44354134Swpaulstruct dc_type { 44454134Swpaul u_int16_t dc_vid; 44554134Swpaul u_int16_t dc_did; 44654134Swpaul char *dc_name; 44754134Swpaul}; 44854134Swpaul 44954134Swpaulstruct dc_mii_frame { 45054134Swpaul u_int8_t mii_stdelim; 45154134Swpaul u_int8_t mii_opcode; 45254134Swpaul u_int8_t mii_phyaddr; 45354134Swpaul u_int8_t mii_regaddr; 45454134Swpaul u_int8_t mii_turnaround; 45554134Swpaul u_int16_t mii_data; 45654134Swpaul}; 45754134Swpaul 45854134Swpaul/* 45954134Swpaul * MII constants 46054134Swpaul */ 46154134Swpaul#define DC_MII_STARTDELIM 0x01 46254134Swpaul#define DC_MII_READOP 0x02 46354134Swpaul#define DC_MII_WRITEOP 0x01 46454134Swpaul#define DC_MII_TURNAROUND 0x02 46554134Swpaul 46654134Swpaul 46754134Swpaul/* 46854134Swpaul * Registers specific to clone devices. 46954134Swpaul * This mainly relates to RX filter programming: not all 21x4x clones 47054134Swpaul * use the standard DEC filter programming mechanism. 47154134Swpaul */ 47254134Swpaul 47354134Swpaul/* 47454134Swpaul * ADMtek specific registers and constants for the AL981 and AN985. 47554134Swpaul * The AN985 doesn't use the magic PHY registers. 47654134Swpaul */ 47754134Swpaul#define DC_AL_PAR0 0xA4 /* station address */ 47854134Swpaul#define DC_AL_PAR1 0xA8 /* station address */ 47954134Swpaul#define DC_AL_MAR0 0xAC /* multicast hash filter */ 48054134Swpaul#define DC_AL_MAR1 0xB0 /* multicast hash filter */ 48154134Swpaul#define DC_AL_BMCR 0xB4 /* built in PHY control */ 48254134Swpaul#define DC_AL_BMSR 0xB8 /* built in PHY status */ 48354134Swpaul#define DC_AL_VENID 0xBC /* built in PHY ID0 */ 48454134Swpaul#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ 48554134Swpaul#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ 48654134Swpaul#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ 48754134Swpaul#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ 48854134Swpaul 48954134Swpaul#define DC_ADMTEK_PHYADDR 0x1 49054134Swpaul#define DC_AL_EE_NODEADDR 4 49154134Swpaul/* End of ADMtek specific registers */ 49254134Swpaul 49354134Swpaul/* 49454134Swpaul * ASIX specific registers. 49554134Swpaul */ 49654134Swpaul#define DC_AX_FILTIDX 0x68 /* RX filter index */ 49754134Swpaul#define DC_AX_FILTDATA 0x70 /* RX filter data */ 49854134Swpaul 49954134Swpaul/* 50054134Swpaul * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). 50154134Swpaul */ 50254134Swpaul#define DC_AX_NETCFG_RX_BROAD 0x00000100 50354134Swpaul 50454134Swpaul/* 50554134Swpaul * RX Filter Index Register values 50654134Swpaul */ 50754134Swpaul#define DC_AX_FILTIDX_PAR0 0x00000000 50854134Swpaul#define DC_AX_FILTIDX_PAR1 0x00000001 50954134Swpaul#define DC_AX_FILTIDX_MAR0 0x00000002 51054134Swpaul#define DC_AX_FILTIDX_MAR1 0x00000003 51154134Swpaul/* End of ASIX specific registers */ 51254134Swpaul 51354134Swpaul/* 51454134Swpaul * Macronix specific registers. The Macronix chips have a special 51554134Swpaul * register for reading the NWAY status, which we don't use, plus 51654134Swpaul * a magic packet register, which we need to tweak a bit per the 51754134Swpaul * Macronix application notes. 51854134Swpaul */ 51954134Swpaul#define DC_MX_MAGICPACKET 0x80 52054134Swpaul#define DC_MX_NWAYSTAT 0xA0 52154134Swpaul 52254134Swpaul/* 52354134Swpaul * Magic packet register 52454134Swpaul */ 52554134Swpaul#define DC_MX_MPACK_DISABLE 0x00400000 52654134Swpaul 52754134Swpaul/* 52854134Swpaul * NWAY status register. 52954134Swpaul */ 53054134Swpaul#define DC_MX_NWAY_10BTHALF 0x08000000 53154134Swpaul#define DC_MX_NWAY_10BTFULL 0x10000000 53254134Swpaul#define DC_MX_NWAY_100BTHALF 0x20000000 53354134Swpaul#define DC_MX_NWAY_100BTFULL 0x40000000 53454134Swpaul#define DC_MX_NWAY_100BT4 0x80000000 53554134Swpaul 53654134Swpaul/* 53754134Swpaul * These are magic values that must be written into CSR16 53854134Swpaul * (DC_MX_MAGICPACKET) in order to put the chip into proper 53954134Swpaul * operating mode. The magic numbers are documented in the 54054134Swpaul * Macronix 98715 application notes. 54154134Swpaul */ 54254134Swpaul#define DC_MX_MAGIC_98713 0x0F370000 54354134Swpaul#define DC_MX_MAGIC_98713A 0x0B3C0000 54454134Swpaul#define DC_MX_MAGIC_98715 0x0B3C0000 54554134Swpaul#define DC_MX_MAGIC_98725 0x0B3C0000 54654134Swpaul/* End of Macronix specific registers */ 54754134Swpaul 54854134Swpaul/* 54954134Swpaul * PNIC 82c168/82c169 specific registers. 55054134Swpaul * The PNIC has its own special NWAY support, which doesn't work, 55154134Swpaul * and shortcut ways of reading the EEPROM and MII bus. 55254134Swpaul */ 55354134Swpaul#define DC_PN_GPIO 0x60 /* general purpose pins control */ 55454134Swpaul#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ 55554134Swpaul#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ 55654134Swpaul#define DC_PN_MII 0xA0 /* MII access register */ 55754134Swpaul#define DC_PN_NWAY 0xB8 /* Internal NWAY register */ 55854134Swpaul 55954134Swpaul/* Serial I/O EEPROM register */ 56054134Swpaul#define DC_PN_SIOCTL_DATA 0x0000003F 56154134Swpaul#define DC_PN_SIOCTL_OPCODE 0x00000300 56254134Swpaul#define DC_PN_SIOCTL_BUSY 0x80000000 56354134Swpaul 56454134Swpaul#define DC_PN_EEOPCODE_ERASE 0x00000300 56554134Swpaul#define DC_PN_EEOPCODE_READ 0x00000600 56654134Swpaul#define DC_PN_EEOPCODE_WRITE 0x00000100 56754134Swpaul 56854134Swpaul/* 56954134Swpaul * The first two general purpose pins control speed selection and 57054134Swpaul * 100Mbps loopback on the 82c168 chip. The control bits should always 57154134Swpaul * be set (to make the data pins outputs) and the speed selction and 57254134Swpaul * loopback bits set accordingly when changing media. Physically, this 57354134Swpaul * will set the state of a relay mounted on the card. 57454134Swpaul */ 57554134Swpaul#define DC_PN_GPIO_DATA0 0x000000001 57654134Swpaul#define DC_PN_GPIO_DATA1 0x000000002 57754134Swpaul#define DC_PN_GPIO_DATA2 0x000000004 57854134Swpaul#define DC_PN_GPIO_DATA3 0x000000008 57954134Swpaul#define DC_PN_GPIO_CTL0 0x000000010 58054134Swpaul#define DC_PN_GPIO_CTL1 0x000000020 58154134Swpaul#define DC_PN_GPIO_CTL2 0x000000040 58254134Swpaul#define DC_PN_GPIO_CTL3 0x000000080 58354134Swpaul#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ 58454134Swpaul#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ 58554134Swpaul#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 58654134Swpaul#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 58754134Swpaul#define DC_PN_GPIO_SETBIT(sc, r) \ 58854134Swpaul DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) 58954134Swpaul#define DC_PN_GPIO_CLRBIT(sc, r) \ 59054134Swpaul { \ 59154134Swpaul DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ 59254134Swpaul DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ 59354134Swpaul } 59454134Swpaul 59554134Swpaul/* shortcut MII access register */ 59654134Swpaul#define DC_PN_MII_DATA 0x0000FFFF 59754134Swpaul#define DC_PN_MII_RESERVER 0x00020000 59854134Swpaul#define DC_PN_MII_REGADDR 0x007C0000 59954134Swpaul#define DC_PN_MII_PHYADDR 0x0F800000 60054134Swpaul#define DC_PN_MII_OPCODE 0x30000000 60154134Swpaul#define DC_PN_MII_BUSY 0x80000000 60254134Swpaul 60354134Swpaul#define DC_PN_MIIOPCODE_READ 0x60020000 60454134Swpaul#define DC_PN_MIIOPCODE_WRITE 0x50020000 60554134Swpaul 60654134Swpaul/* Internal NWAY bits */ 60754134Swpaul#define DC_PN_NWAY_RESET 0x00000001 /* reset */ 60854134Swpaul#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ 60954134Swpaul#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ 61054134Swpaul#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ 61154134Swpaul#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ 61254134Swpaul#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ 61354134Swpaul#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ 61454134Swpaul#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ 61554134Swpaul#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ 61654134Swpaul#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ 61754134Swpaul#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ 61854134Swpaul#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ 61954134Swpaul#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ 62054134Swpaul#define DC_PN_NWAY_CAP10HDX 0x00002000 62154134Swpaul#define DC_PN_NWAY_CAP10FDX 0x00004000 62254134Swpaul#define DC_PN_NWAY_CAP100FDX 0x00008000 62354134Swpaul#define DC_PN_NWAY_CAP100HDX 0x00010000 62454134Swpaul#define DC_PN_NWAY_CAP100T4 0x00020000 62554134Swpaul#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ 62654134Swpaul#define DC_PN_NWAY_REMFAULT 0x04000000 62754134Swpaul#define DC_PN_NWAY_LPAR10HDX 0x08000000 62854134Swpaul#define DC_PN_NWAY_LPAR10FDX 0x10000000 62954134Swpaul#define DC_PN_NWAY_LPAR100FDX 0x20000000 63054134Swpaul#define DC_PN_NWAY_LPAR100HDX 0x40000000 63154134Swpaul#define DC_PN_NWAY_LPAR100T4 0x80000000 63254134Swpaul 63354134Swpaul/* End of PNIC specific registers */ 63454134Swpaul 63554134Swpaulstruct dc_softc { 63654134Swpaul struct arpcom arpcom; /* interface info */ 63754134Swpaul bus_space_handle_t dc_bhandle; /* bus space handle */ 63854134Swpaul bus_space_tag_t dc_btag; /* bus space tag */ 63954134Swpaul void *dc_intrhand; 64054134Swpaul struct resource *dc_irq; 64154134Swpaul struct resource *dc_res; 64254134Swpaul struct dc_type *dc_info; /* adapter info */ 64354134Swpaul device_t dc_miibus; 64454134Swpaul u_int8_t dc_unit; /* interface number */ 64554134Swpaul u_int8_t dc_type; 64654134Swpaul u_int8_t dc_pmode; 64754134Swpaul u_int8_t dc_link; 64854134Swpaul u_int8_t dc_cachesize; 64954134Swpaul int dc_pnic_rx_bug_save; 65054134Swpaul unsigned char *dc_pnic_rx_buf; 65154134Swpaul int dc_if_flags; 65254134Swpaul int dc_if_media; 65354134Swpaul u_int32_t dc_flags; 65454134Swpaul u_int32_t dc_txthresh; 65554134Swpaul struct dc_list_data *dc_ldata; 65654134Swpaul struct dc_chain_data dc_cdata; 65754134Swpaul struct callout_handle dc_stat_ch; 65854134Swpaul}; 65954134Swpaul 66054134Swpaul#define DC_TX_POLL 0x00000001 66154134Swpaul#define DC_TX_COALESCE 0x00000002 66254134Swpaul#define DC_TX_ADMTEK_WAR 0x00000004 66354134Swpaul#define DC_TX_USE_TX_INTR 0x00000008 66454134Swpaul#define DC_RX_FILTER_TULIP 0x00000010 66554134Swpaul#define DC_TX_INTR_FIRSTFRAG 0x00000020 66654134Swpaul#define DC_PNIC_RX_BUG_WAR 0x00000040 66754134Swpaul#define DC_TX_FIXED_RING 0x00000080 66854134Swpaul#define DC_TX_STORENFWD 0x00000100 66954134Swpaul#define DC_REDUCED_MII_POLL 0x00000200 67054577Swpaul#define DC_TX_INTR_ALWAYS 0x00000400 67154134Swpaul 67254134Swpaul/* 67354134Swpaul * register space access macros 67454134Swpaul */ 67554134Swpaul#define CSR_WRITE_4(sc, reg, val) \ 67654134Swpaul bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) 67754134Swpaul 67854134Swpaul#define CSR_READ_4(sc, reg) \ 67954134Swpaul bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) 68054134Swpaul 68154134Swpaul#define DC_TIMEOUT 1000 68254134Swpaul#define ETHER_ALIGN 2 68354134Swpaul 68454134Swpaul/* 68554134Swpaul * General constants that are fun to know. 68654134Swpaul */ 68754134Swpaul 68854134Swpaul/* 68954134Swpaul * DEC PCI vendor ID 69054134Swpaul */ 69154134Swpaul#define DC_VENDORID_DEC 0x1011 69254134Swpaul 69354134Swpaul/* 69454134Swpaul * DEC/Intel 21143 PCI device ID 69554134Swpaul */ 69654134Swpaul#define DC_DEVICEID_21143 0x0019 69754134Swpaul 69854134Swpaul/* 69954134Swpaul * Macronix PCI vendor ID 70054134Swpaul */ 70154134Swpaul#define DC_VENDORID_MX 0x10D9 70254134Swpaul 70354134Swpaul/* 70454134Swpaul * Macronix PMAC device IDs. 70554134Swpaul */ 70654134Swpaul#define DC_DEVICEID_98713 0x0512 70754134Swpaul#define DC_DEVICEID_987x5 0x0531 70854134Swpaul 70954134Swpaul/* Macronix PCI revision codes. */ 71054134Swpaul#define DC_REVISION_98713 0x00 71154134Swpaul#define DC_REVISION_98713A 0x10 71254134Swpaul#define DC_REVISION_98715 0x20 71354134Swpaul#define DC_REVISION_98725 0x30 71454134Swpaul 71554134Swpaul/* 71654134Swpaul * Compex PCI vendor ID. 71754134Swpaul */ 71854134Swpaul#define DC_VENDORID_CP 0x11F6 71954134Swpaul 72054134Swpaul/* 72154134Swpaul * Compex PMAC PCI device IDs. 72254134Swpaul */ 72354134Swpaul#define DC_DEVICEID_98713_CP 0x9881 72454134Swpaul 72554134Swpaul/* 72654134Swpaul * Lite-On PNIC PCI vendor ID 72754134Swpaul */ 72854134Swpaul#define DC_VENDORID_LO 0x11AD 72954134Swpaul 73054134Swpaul/* 73154134Swpaul * 82c168/82c169 PNIC device IDs. Both chips have the same device 73254134Swpaul * ID but different revisions. Revision 0x10 is the 82c168, and 73354134Swpaul * 0x20 is the 82c169. 73454134Swpaul */ 73554134Swpaul#define DC_DEVICEID_82C168 0x0002 73654134Swpaul 73754134Swpaul#define DC_REVISION_82C168 0x10 73854134Swpaul#define DC_REVISION_82C169 0x20 73954134Swpaul 74054134Swpaul/* 74154134Swpaul * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A 74254134Swpaul * with wake on lan/magic packet support. 74354134Swpaul */ 74454134Swpaul#define DC_DEVICEID_82C115 0xc115 74554134Swpaul 74654134Swpaul/* 74754134Swpaul * Davicom vendor ID. 74854134Swpaul */ 74954134Swpaul#define DC_VENDORID_DAVICOM 0x1282 75054134Swpaul 75154134Swpaul/* 75254134Swpaul * Davicom device IDs. 75354134Swpaul */ 75454134Swpaul#define DC_DEVICEID_DM9100 0x9100 75554134Swpaul#define DC_DEVICEID_DM9102 0x9102 75654134Swpaul 75754134Swpaul/* 75856295Swpaul * The DM9102A has the same PCI device ID as the DM9102, 75956295Swpaul * but a higher revision code. 76056295Swpaul */ 76156295Swpaul#define DC_REVISION_DM9102 0x10 76256295Swpaul#define DC_REVISION_DM9102A 0x30 76356295Swpaul 76456295Swpaul/* 76554134Swpaul * ADMtek vendor ID. 76654134Swpaul */ 76754134Swpaul#define DC_VENDORID_ADMTEK 0x1317 76854134Swpaul 76954134Swpaul/* 77054134Swpaul * ADMtek device IDs. 77154134Swpaul */ 77254134Swpaul#define DC_DEVICEID_AL981 0x0981 77354134Swpaul#define DC_DEVICEID_AN985 0x0985 77454134Swpaul 77554134Swpaul/* 77654134Swpaul * ASIX vendor ID. 77754134Swpaul */ 77854134Swpaul#define DC_VENDORID_ASIX 0x125B 77954134Swpaul 78054134Swpaul/* 78154134Swpaul * ASIX device IDs. 78254134Swpaul */ 78354134Swpaul#define DC_DEVICEID_AX88140A 0x1400 78454134Swpaul 78554134Swpaul/* 78654134Swpaul * The ASIX AX88140 and ASIX AX88141 have the same vendor and 78754134Swpaul * device IDs but different revision values. 78854134Swpaul */ 78954134Swpaul#define DC_REVISION_88140 0x00 79054134Swpaul#define DC_REVISION_88141 0x10 79154134Swpaul 79254134Swpaul/* 79354134Swpaul * PCI low memory base and low I/O base register, and 79454134Swpaul * other PCI registers. 79554134Swpaul */ 79654134Swpaul 79754134Swpaul#define DC_PCI_CFID 0x00 /* Id */ 79854134Swpaul#define DC_PCI_CFCS 0x04 /* Command and status */ 79954134Swpaul#define DC_PCI_CFRV 0x08 /* Revision */ 80054134Swpaul#define DC_PCI_CFLT 0x0C /* Latency timer */ 80154134Swpaul#define DC_PCI_CFBIO 0x10 /* Base I/O address */ 80254134Swpaul#define DC_PCI_CFBMA 0x14 /* Base memory address */ 80354134Swpaul#define DC_PCI_CCIS 0x28 /* Card info struct */ 80454134Swpaul#define DC_PCI_CSID 0x2C /* Subsystem ID */ 80554134Swpaul#define DC_PCI_CBER 0x30 /* Expansion ROM base address */ 80654134Swpaul#define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */ 80754134Swpaul#define DC_PCI_CFIT 0x3C /* Interrupt */ 80854134Swpaul#define DC_PCI_CFDD 0x40 /* Device and driver area */ 80954134Swpaul#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ 81054134Swpaul#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ 81154134Swpaul#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ 81254134Swpaul#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ 81354134Swpaul#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ 81454134Swpaul#define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */ 81554134Swpaul#define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */ 81654134Swpaul 81754134Swpaul/* PCI ID register */ 81854134Swpaul#define DC_CFID_VENDOR 0x0000FFFF 81954134Swpaul#define DC_CFID_DEVICE 0xFFFF0000 82054134Swpaul 82154134Swpaul/* PCI command/status register */ 82254134Swpaul#define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */ 82354134Swpaul#define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */ 82454134Swpaul#define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */ 82554134Swpaul#define DC_CFCS_MWI_ENB 0x00000008 /* mem write and inval enable */ 82654134Swpaul#define DC_CFCS_PARITYERR_ENB 0x00000020 /* parity error enable */ 82754134Swpaul#define DC_CFCS_SYSERR_ENB 0x00000080 /* system error enable */ 82854134Swpaul#define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */ 82954134Swpaul#define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */ 83054134Swpaul#define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */ 83154134Swpaul#define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */ 83254134Swpaul#define DC_CFCS_TGTABRT 0x10000000 /* received target abort */ 83354134Swpaul#define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */ 83454134Swpaul#define DC_CFCS_SYSERR 0x40000000 /* asserted system error */ 83554134Swpaul#define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */ 83654134Swpaul 83754134Swpaul/* PCI revision register */ 83854134Swpaul#define DC_CFRV_STEPPING 0x0000000F 83954134Swpaul#define DC_CFRV_REVISION 0x000000F0 84054134Swpaul#define DC_CFRV_SUBCLASS 0x00FF0000 84154134Swpaul#define DC_CFRV_BASECLASS 0xFF000000 84254134Swpaul 84354134Swpaul#define DC_21143_PB_REV 0x00000030 84454134Swpaul#define DC_21143_TB_REV 0x00000030 84554134Swpaul#define DC_21143_PC_REV 0x00000030 84654134Swpaul#define DC_21143_TC_REV 0x00000030 84754134Swpaul#define DC_21143_PD_REV 0x00000041 84854134Swpaul#define DC_21143_TD_REV 0x00000041 84954134Swpaul 85054134Swpaul/* PCI latency timer register */ 85154134Swpaul#define DC_CFLT_CACHELINESIZE 0x000000FF 85254134Swpaul#define DC_CFLT_LATENCYTIMER 0x0000FF00 85354134Swpaul 85454134Swpaul/* PCI subsystem ID register */ 85554134Swpaul#define DC_CSID_VENDOR 0x0000FFFF 85654134Swpaul#define DC_CSID_DEVICE 0xFFFF0000 85754134Swpaul 85854134Swpaul/* PCI cababilities pointer */ 85954134Swpaul#define DC_CCAP_OFFSET 0x000000FF 86054134Swpaul 86154134Swpaul/* PCI interrupt config register */ 86254134Swpaul#define DC_CFIT_INTLINE 0x000000FF 86354134Swpaul#define DC_CFIT_INTPIN 0x0000FF00 86454134Swpaul#define DC_CFIT_MIN_GNT 0x00FF0000 86554134Swpaul#define DC_CFIT_MAX_LAT 0xFF000000 86654134Swpaul 86754134Swpaul/* PCI capability register */ 86854134Swpaul#define DC_CCID_CAPID 0x000000FF 86954134Swpaul#define DC_CCID_NEXTPTR 0x0000FF00 87054134Swpaul#define DC_CCID_PM_VERS 0x00070000 87154134Swpaul#define DC_CCID_PME_CLK 0x00080000 87254134Swpaul#define DC_CCID_DVSPEC_INT 0x00200000 87354134Swpaul#define DC_CCID_STATE_D1 0x02000000 87454134Swpaul#define DC_CCID_STATE_D2 0x04000000 87554134Swpaul#define DC_CCID_PME_D0 0x08000000 87654134Swpaul#define DC_CCID_PME_D1 0x10000000 87754134Swpaul#define DC_CCID_PME_D2 0x20000000 87854134Swpaul#define DC_CCID_PME_D3HOT 0x40000000 87954134Swpaul#define DC_CCID_PME_D3COLD 0x80000000 88054134Swpaul 88154134Swpaul/* PCI power management control/status register */ 88254134Swpaul#define DC_CPMC_STATE 0x00000003 88354134Swpaul#define DC_CPMC_PME_ENB 0x00000100 88454134Swpaul#define DC_CPMC_PME_STS 0x00008000 88554134Swpaul 88654134Swpaul#define DC_PSTATE_D0 0x0 88754134Swpaul#define DC_PSTATE_D1 0x1 88854134Swpaul#define DC_PSTATE_D2 0x2 88954134Swpaul#define DC_PSTATE_D3 0x3 89054134Swpaul 89154134Swpaul/* Device specific region */ 89254134Swpaul/* Configuration and driver area */ 89354134Swpaul#define DC_CFDD_DRVUSE 0x0000FFFF 89454134Swpaul#define DC_CFDD_SNOOZE_MODE 0x40000000 89554134Swpaul#define DC_CFDD_SLEEP_MODE 0x80000000 89654134Swpaul 89754134Swpaul/* Configuration wake-up command register */ 89854134Swpaul#define DC_CWUC_MUST_BE_ZERO 0x00000001 89954134Swpaul#define DC_CWUC_SECUREON_ENB 0x00000002 90054134Swpaul#define DC_CWUC_FORCE_WUL 0x00000004 90154134Swpaul#define DC_CWUC_BNC_ABILITY 0x00000008 90254134Swpaul#define DC_CWUC_AUI_ABILITY 0x00000010 90354134Swpaul#define DC_CWUC_TP10_ABILITY 0x00000020 90454134Swpaul#define DC_CWUC_MII_ABILITY 0x00000040 90554134Swpaul#define DC_CWUC_SYM_ABILITY 0x00000080 90654134Swpaul#define DC_CWUC_LOCK 0x00000100 90754134Swpaul 90854134Swpaul#ifdef __alpha__ 90954134Swpaul#undef vtophys 91054134Swpaul#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 91154134Swpaul#endif 912