if_dcreg.h revision 54577
168349Sobrien/* 268349Sobrien * Copyright (c) 1997, 1998, 1999 368349Sobrien * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 468349Sobrien * 568349Sobrien * Redistribution and use in source and binary forms, with or without 668349Sobrien * modification, are permitted provided that the following conditions 768349Sobrien * are met: 868349Sobrien * 1. Redistributions of source code must retain the above copyright 968349Sobrien * notice, this list of conditions and the following disclaimer. 1068349Sobrien * 2. Redistributions in binary form must reproduce the above copyright 1168349Sobrien * notice, this list of conditions and the following disclaimer in the 1268349Sobrien * documentation and/or other materials provided with the distribution. 1368349Sobrien * 3. All advertising materials mentioning features or use of this software 1468349Sobrien * must display the following acknowledgement: 1568349Sobrien * This product includes software developed by Bill Paul. 1668349Sobrien * 4. Neither the name of the author nor the names of any co-contributors 1768349Sobrien * may be used to endorse or promote products derived from this software 1868349Sobrien * without specific prior written permission. 1968349Sobrien * 2068349Sobrien * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2168349Sobrien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2268349Sobrien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2368349Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2468349Sobrien * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2568349Sobrien * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2668349Sobrien * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2768349Sobrien * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2868349Sobrien * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2968349Sobrien * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3068349Sobrien * THE POSSIBILITY OF SUCH DAMAGE. 3168349Sobrien * 3268349Sobrien * $FreeBSD: head/sys/dev/dc/if_dcreg.h 54577 1999-12-13 21:45:13Z wpaul $ 3368349Sobrien */ 3468349Sobrien 3568349Sobrien/* 3668349Sobrien * 21143 and clone common register definitions. 3768349Sobrien */ 3868349Sobrien 3968349Sobrien#define DC_BUSCTL 0x00 /* bus control */ 4068349Sobrien#define DC_TXSTART 0x08 /* tx start demand */ 4168349Sobrien#define DC_RXSTART 0x10 /* rx start demand */ 4268349Sobrien#define DC_RXADDR 0x18 /* rx descriptor list start addr */ 4368349Sobrien#define DC_TXADDR 0x20 /* tx descriptor list start addr */ 4468349Sobrien#define DC_ISR 0x28 /* interrupt status register */ 4568349Sobrien#define DC_NETCFG 0x30 /* network config register */ 4668349Sobrien#define DC_IMR 0x38 /* interrupt mask */ 4768349Sobrien#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ 4868349Sobrien#define DC_SIO 0x48 /* MII and ROM/EEPROM access */ 4968349Sobrien#define DC_ROM 0x50 /* ROM programming address */ 5068349Sobrien#define DC_TIMER 0x58 /* general timer */ 5168349Sobrien#define DC_10BTSTAT 0x60 /* SIA status */ 5268349Sobrien#define DC_SIARESET 0x68 /* SIA connectivity */ 5368349Sobrien#define DC_10BTCTRL 0x70 /* SIA transmit and receive */ 5468349Sobrien#define DC_WATCHDOG 0x78 /* SIA and general purpose port */ 5568349Sobrien 5668349Sobrien/* 5768349Sobrien * There are two general 'types' of MX chips that we need to be 5868349Sobrien * concerned with. One is the original 98713, which has its internal 5968349Sobrien * NWAY support controlled via the MDIO bits in the serial I/O 6068349Sobrien * register. The other is everything else (from the 98713A on up), 6168349Sobrien * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, 6268349Sobrien * just like the 21143. This type setting also governs which of the 6368349Sobrien * 'magic' numbers we write to CSR16. The PNIC II falls into the 6468349Sobrien * 98713A/98715/98715A/98725 category. 6568349Sobrien */ 6668349Sobrien#define DC_TYPE_98713 0x1 6768349Sobrien#define DC_TYPE_98713A 0x2 6868349Sobrien#define DC_TYPE_987x5 0x3 6968349Sobrien 7068349Sobrien/* Other type of supported chips. */ 7168349Sobrien#define DC_TYPE_21143 0x4 /* Intel 21143 */ 7268349Sobrien#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ 7368349Sobrien#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ 7468349Sobrien#define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */ 7568349Sobrien#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ 7668349Sobrien#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ 7768349Sobrien#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ 7868349Sobrien 7968349Sobrien#define DC_IS_MACRONIX(x) \ 8068349Sobrien (x->dc_type == DC_TYPE_98713 || \ 8168349Sobrien x->dc_type == DC_TYPE_98713A || \ 8268349Sobrien x->dc_type == DC_TYPE_987x5) 8368349Sobrien 8468349Sobrien#define DC_IS_ADMTEK(x) \ 8568349Sobrien (x->dc_type == DC_TYPE_AL981 || \ 8668349Sobrien x->dc_type == DC_TYPE_AN985) 8768349Sobrien 8868349Sobrien#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) 8968349Sobrien#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) 9068349Sobrien#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) 9168349Sobrien#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985) 9268349Sobrien#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) 9368349Sobrien#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) 9468349Sobrien#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) 9568349Sobrien 9668349Sobrien/* MII/symbol mode port types */ 9768349Sobrien#define DC_PMODE_MII 0x1 9868349Sobrien#define DC_PMODE_SYM 0x2 9968349Sobrien 10068349Sobrien/* 10168349Sobrien * Bus control bits. 10268349Sobrien */ 10368349Sobrien#define DC_BUSCTL_RESET 0x00000001 10468349Sobrien#define DC_BUSCTL_ARBITRATION 0x00000002 10568349Sobrien#define DC_BUSCTL_SKIPLEN 0x0000007C 10668349Sobrien#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 10768349Sobrien#define DC_BUSCTL_BURSTLEN 0x00003F00 10868349Sobrien#define DC_BUSCTL_CACHEALIGN 0x0000C000 10968349Sobrien#define DC_BUSCTL_TXPOLL 0x000E0000 11068349Sobrien#define DC_BUSCTL_DBO 0x00100000 11168349Sobrien#define DC_BUSCTL_MRME 0x00200000 11268349Sobrien#define DC_BUSCTL_MRLE 0x00800000 11368349Sobrien#define DC_BUSCTL_MWIE 0x01000000 11468349Sobrien#define DC_BUSCTL_ONNOW_ENB 0x04000000 11568349Sobrien 11668349Sobrien#define DC_SKIPLEN_1LONG 0x00000004 11768349Sobrien#define DC_SKIPLEN_2LONG 0x00000008 11868349Sobrien#define DC_SKIPLEN_3LONG 0x00000010 11968349Sobrien#define DC_SKIPLEN_4LONG 0x00000020 12068349Sobrien#define DC_SKIPLEN_5LONG 0x00000040 12168349Sobrien 12268349Sobrien#define DC_CACHEALIGN_NONE 0x00000000 12368349Sobrien#define DC_CACHEALIGN_8LONG 0x00004000 12468349Sobrien#define DC_CACHEALIGN_16LONG 0x00008000 12568349Sobrien#define DC_CACHEALIGN_32LONG 0x0000C000 12668349Sobrien 12768349Sobrien#define DC_BURSTLEN_USECA 0x00000000 12868349Sobrien#define DC_BURSTLEN_1LONG 0x00000100 12968349Sobrien#define DC_BURSTLEN_2LONG 0x00000200 13068349Sobrien#define DC_BURSTLEN_4LONG 0x00000400 13168349Sobrien#define DC_BURSTLEN_8LONG 0x00000800 13268349Sobrien#define DC_BURSTLEN_16LONG 0x00001000 13368349Sobrien#define DC_BURSTLEN_32LONG 0x00002000 13468349Sobrien 13568349Sobrien#define DC_TXPOLL_OFF 0x00000000 13668349Sobrien#define DC_TXPOLL_1 0x00020000 13768349Sobrien#define DC_TXPOLL_2 0x00040000 13868349Sobrien#define DC_TXPOLL_3 0x00060000 13968349Sobrien#define DC_TXPOLL_4 0x00080000 14068349Sobrien#define DC_TXPOLL_5 0x000A0000 14168349Sobrien#define DC_TXPOLL_6 0x000C0000 14268349Sobrien#define DC_TXPOLL_7 0x000E0000 14368349Sobrien 14468349Sobrien/* 14568349Sobrien * Interrupt status bits. 14668349Sobrien */ 14768349Sobrien#define DC_ISR_TX_OK 0x00000001 14868349Sobrien#define DC_ISR_TX_IDLE 0x00000002 14968349Sobrien#define DC_ISR_TX_NOBUF 0x00000004 15068349Sobrien#define DC_ISR_TX_JABBERTIMEO 0x00000008 15168349Sobrien#define DC_ISR_LINKGOOD 0x00000010 15268349Sobrien#define DC_ISR_TX_UNDERRUN 0x00000020 15368349Sobrien#define DC_ISR_RX_OK 0x00000040 15468349Sobrien#define DC_ISR_RX_NOBUF 0x00000080 15568349Sobrien#define DC_ISR_RX_READ 0x00000100 15668349Sobrien#define DC_ISR_RX_WATDOGTIMEO 0x00000200 15768349Sobrien#define DC_ISR_TX_EARLY 0x00000400 15868349Sobrien#define DC_ISR_TIMER_EXPIRED 0x00000800 15968349Sobrien#define DC_ISR_LINKFAIL 0x00001000 16068349Sobrien#define DC_ISR_BUS_ERR 0x00002000 16168349Sobrien#define DC_ISR_RX_EARLY 0x00004000 16268349Sobrien#define DC_ISR_ABNORMAL 0x00008000 16368349Sobrien#define DC_ISR_NORMAL 0x00010000 16468349Sobrien#define DC_ISR_RX_STATE 0x000E0000 16568349Sobrien#define DC_ISR_TX_STATE 0x00700000 16668349Sobrien#define DC_ISR_BUSERRTYPE 0x03800000 16768349Sobrien#define DC_ISR_100MBPSLINK 0x08000000 16868349Sobrien#define DC_ISR_MAGICKPACK 0x10000000 16968349Sobrien 17068349Sobrien#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 17168349Sobrien#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 17268349Sobrien#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 17368349Sobrien#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 17468349Sobrien#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 17568349Sobrien#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 17668349Sobrien#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 17768349Sobrien#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 17868349Sobrien 17968349Sobrien#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ 18068349Sobrien#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 18168349Sobrien#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 18268349Sobrien#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 18368349Sobrien#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 18468349Sobrien#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 18568349Sobrien#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 18668349Sobrien#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 18768349Sobrien 18868349Sobrien/* 18968349Sobrien * Network config bits. 19068349Sobrien */ 19168349Sobrien#define DC_NETCFG_RX_HASHPERF 0x00000001 19268349Sobrien#define DC_NETCFG_RX_ON 0x00000002 19368349Sobrien#define DC_NETCFG_RX_HASHONLY 0x00000004 19468349Sobrien#define DC_NETCFG_RX_BADFRAMES 0x00000008 19568349Sobrien#define DC_NETCFG_RX_INVFILT 0x00000010 19668349Sobrien#define DC_NETCFG_BACKOFFCNT 0x00000020 19768349Sobrien#define DC_NETCFG_RX_PROMISC 0x00000040 19868349Sobrien#define DC_NETCFG_RX_ALLMULTI 0x00000080 19968349Sobrien#define DC_NETCFG_FULLDUPLEX 0x00000200 20068349Sobrien#define DC_NETCFG_LOOPBACK 0x00000C00 20168349Sobrien#define DC_NETCFG_FORCECOLL 0x00001000 20268349Sobrien#define DC_NETCFG_TX_ON 0x00002000 20368349Sobrien#define DC_NETCFG_TX_THRESH 0x0000C000 20468349Sobrien#define DC_NETCFG_TX_BACKOFF 0x00020000 20568349Sobrien#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ 20668349Sobrien#define DC_NETCFG_HEARTBEAT 0x00080000 20768349Sobrien#define DC_NETCFG_STORENFWD 0x00200000 20868349Sobrien#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ 20968349Sobrien#define DC_NETCFG_PCS 0x00800000 21068349Sobrien#define DC_NETCFG_SCRAMBLER 0x01000000 21168349Sobrien#define DC_NETCFG_NO_RXCRC 0x02000000 21268349Sobrien#define DC_NETCFG_RX_ALL 0x40000000 21368349Sobrien#define DC_NETCFG_CAPEFFECT 0x80000000 21468349Sobrien 21568349Sobrien#define DC_OPMODE_NORM 0x00000000 21668349Sobrien#define DC_OPMODE_INTLOOP 0x00000400 21768349Sobrien#define DC_OPMODE_EXTLOOP 0x00000800 21868349Sobrien 21968349Sobrien#define DC_TXTHRESH_72BYTES 0x00000000 22068349Sobrien#define DC_TXTHRESH_96BYTES 0x00004000 22168349Sobrien#define DC_TXTHRESH_128BYTES 0x00008000 22268349Sobrien#define DC_TXTHRESH_160BYTES 0x0000C000 22368349Sobrien 22468349Sobrien 22568349Sobrien/* 22668349Sobrien * Interrupt mask bits. 22768349Sobrien */ 22868349Sobrien#define DC_IMR_TX_OK 0x00000001 22968349Sobrien#define DC_IMR_TX_IDLE 0x00000002 23068349Sobrien#define DC_IMR_TX_NOBUF 0x00000004 23168349Sobrien#define DC_IMR_TX_JABBERTIMEO 0x00000008 23268349Sobrien#define DC_IMR_LINKGOOD 0x00000010 23368349Sobrien#define DC_IMR_TX_UNDERRUN 0x00000020 23468349Sobrien#define DC_IMR_RX_OK 0x00000040 23568349Sobrien#define DC_IMR_RX_NOBUF 0x00000080 23668349Sobrien#define DC_IMR_RX_READ 0x00000100 23768349Sobrien#define DC_IMR_RX_WATDOGTIMEO 0x00000200 23868349Sobrien#define DC_IMR_TX_EARLY 0x00000400 239#define DC_IMR_TIMER_EXPIRED 0x00000800 240#define DC_IMR_LINKFAIL 0x00001000 241#define DC_IMR_BUS_ERR 0x00002000 242#define DC_IMR_RX_EARLY 0x00004000 243#define DC_IMR_ABNORMAL 0x00008000 244#define DC_IMR_NORMAL 0x00010000 245#define DC_IMR_100MBPSLINK 0x08000000 246#define DC_IMR_MAGICKPACK 0x10000000 247 248#define DC_INTRS \ 249 (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ 250 DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ 251 DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) 252/* 253 * Serial I/O (EEPROM/ROM) bits. 254 */ 255#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 256#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 257#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 258#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 259#define DC_SIO_ROMDATA4 0x00000010 260#define DC_SIO_ROMDATA5 0x00000020 261#define DC_SIO_ROMDATA6 0x00000040 262#define DC_SIO_ROMDATA7 0x00000080 263#define DC_SIO_EESEL 0x00000800 264#define DC_SIO_ROMSEL 0x00001000 265#define DC_SIO_ROMCTL_WRITE 0x00002000 266#define DC_SIO_ROMCTL_READ 0x00004000 267#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ 268#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ 269#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ 270#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ 271 272#define DC_EECMD_WRITE 0x140 273#define DC_EECMD_READ 0x180 274#define DC_EECMD_ERASE 0x1c0 275 276#define DC_EE_NODEADDR_OFFSET 0x70 277#define DC_EE_NODEADDR 10 278 279/* 280 * General purpose timer register 281 */ 282#define DC_TIMER_VALUE 0x0000FFFF 283#define DC_TIMER_CONTINUOUS 0x00010000 284 285/* 286 * 10baseT status register 287 */ 288#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ 289#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ 290#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ 291#define DC_TSTAT_AUTOPOLARITY 0x00000008 292#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ 293#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ 294#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ 295#define DC_TSTAT_REMFAULT 0x00000800 296#define DC_TSTAT_ANEGSTAT 0x00007000 297#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ 298#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ 299 300#define DC_ASTAT_DISABLE 0x00000000 301#define DC_ASTAT_TXDISABLE 0x00001000 302#define DC_ASTAT_ABDETECT 0x00002000 303#define DC_ASTAT_ACKDETECT 0x00003000 304#define DC_ASTAT_CMPACKDETECT 0x00004000 305#define DC_ASTAT_AUTONEGCMP 0x00005000 306#define DC_ASTAT_LINKCHECK 0x00006000 307 308/* 309 * PHY reset register 310 */ 311#define DC_SIA_RESET 0x00000001 312#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ 313 314/* 315 * 10baseT control register 316 */ 317#define DC_TCTL_ENCODER_ENB 0x00000001 318#define DC_TCTL_LOOPBACK 0x00000002 319#define DC_TCTL_DRIVER_ENB 0x00000004 320#define DC_TCTL_LNKPULSE_ENB 0x00000008 321#define DC_TCTL_HALFDUPLEX 0x00000040 322#define DC_TCTL_AUTONEGENBL 0x00000080 323#define DC_TCTL_RX_SQUELCH 0x00000100 324#define DC_TCTL_COLL_SQUELCH 0x00000200 325#define DC_TCTL_COLL_DETECT 0x00000400 326#define DC_TCTL_SQE_ENB 0x00000800 327#define DC_TCTL_LINKTEST 0x00001000 328#define DC_TCTL_AUTOPOLARITY 0x00002000 329#define DC_TCTL_SET_POL_PLUS 0x00004000 330#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ 331#define DC_TCTL_100BTXHALF 0x00010000 332#define DC_TCTL_100BTXFULL 0x00020000 333#define DC_TCTL_100BT4 0x00040000 334 335/* 336 * Watchdog timer register 337 */ 338#define DC_WDOG_JABBERDIS 0x00000001 339#define DC_WDOG_HOSTUNJAB 0x00000002 340#define DC_WDOG_JABBERCLK 0x00000004 341#define DC_WDOG_RXWDOGDIS 0x00000010 342#define DC_WDOG_RXWDOGCLK 0x00000020 343#define DC_WDOG_MUSTBEZERO 0x00000100 344 345/* 346 * Size of a setup frame. 347 */ 348#define DC_SFRAME_LEN 192 349 350/* 351 * 21x4x TX/RX list structure. 352 */ 353 354struct dc_desc { 355 u_int32_t dc_status; 356 u_int32_t dc_ctl; 357 u_int32_t dc_ptr1; 358 u_int32_t dc_ptr2; 359}; 360 361#define dc_data dc_ptr1 362#define dc_next dc_ptr2 363 364#define DC_RXSTAT_FIFOOFLOW 0x00000001 365#define DC_RXSTAT_CRCERR 0x00000002 366#define DC_RXSTAT_DRIBBLE 0x00000004 367#define DC_RXSTAT_WATCHDOG 0x00000010 368#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ 369#define DC_RXSTAT_COLLSEEN 0x00000040 370#define DC_RXSTAT_GIANT 0x00000080 371#define DC_RXSTAT_LASTFRAG 0x00000100 372#define DC_RXSTAT_FIRSTFRAG 0x00000200 373#define DC_RXSTAT_MULTICAST 0x00000400 374#define DC_RXSTAT_RUNT 0x00000800 375#define DC_RXSTAT_RXTYPE 0x00003000 376#define DC_RXSTAT_RXERR 0x00008000 377#define DC_RXSTAT_RXLEN 0x3FFF0000 378#define DC_RXSTAT_OWN 0x80000000 379 380#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) 381#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) 382 383#define DC_RXCTL_BUFLEN1 0x00000FFF 384#define DC_RXCTL_BUFLEN2 0x00FFF000 385#define DC_RXCTL_RLINK 0x01000000 386#define DC_RXCTL_RLAST 0x02000000 387 388#define DC_TXSTAT_DEFER 0x00000001 389#define DC_TXSTAT_UNDERRUN 0x00000002 390#define DC_TXSTAT_LINKFAIL 0x00000003 391#define DC_TXSTAT_COLLCNT 0x00000078 392#define DC_TXSTAT_SQE 0x00000080 393#define DC_TXSTAT_EXCESSCOLL 0x00000100 394#define DC_TXSTAT_LATECOLL 0x00000200 395#define DC_TXSTAT_NOCARRIER 0x00000400 396#define DC_TXSTAT_CARRLOST 0x00000800 397#define DC_TXSTAT_JABTIMEO 0x00004000 398#define DC_TXSTAT_ERRSUM 0x00008000 399#define DC_TXSTAT_OWN 0x80000000 400 401#define DC_TXCTL_BUFLEN1 0x000007FF 402#define DC_TXCTL_BUFLEN2 0x003FF800 403#define DC_TXCTL_FILTTYPE0 0x00400000 404#define DC_TXCTL_PAD 0x00800000 405#define DC_TXCTL_TLINK 0x01000000 406#define DC_TXCTL_TLAST 0x02000000 407#define DC_TXCTL_NOCRC 0x04000000 408#define DC_TXCTL_SETUP 0x08000000 409#define DC_TXCTL_FILTTYPE1 0x10000000 410#define DC_TXCTL_FIRSTFRAG 0x20000000 411#define DC_TXCTL_LASTFRAG 0x40000000 412#define DC_TXCTL_FINT 0x80000000 413 414#define DC_FILTER_PERFECT 0x00000000 415#define DC_FILTER_HASHPERF 0x00400000 416#define DC_FILTER_INVERSE 0x10000000 417#define DC_FILTER_HASHONLY 0x10400000 418 419#define DC_MAXFRAGS 16 420#define DC_RX_LIST_CNT 64 421#define DC_TX_LIST_CNT 256 422#define DC_MIN_FRAMELEN 60 423#define DC_RXLEN 1536 424 425#define DC_INC(x, y) (x) = (x + 1) % y 426 427struct dc_list_data { 428 struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; 429 struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; 430}; 431 432struct dc_chain_data { 433 struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; 434 struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; 435 u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)]; 436 u_int8_t dc_pad[DC_MIN_FRAMELEN]; 437 int dc_tx_prod; 438 int dc_tx_cons; 439 int dc_tx_cnt; 440 int dc_rx_prod; 441}; 442 443struct dc_type { 444 u_int16_t dc_vid; 445 u_int16_t dc_did; 446 char *dc_name; 447}; 448 449struct dc_mii_frame { 450 u_int8_t mii_stdelim; 451 u_int8_t mii_opcode; 452 u_int8_t mii_phyaddr; 453 u_int8_t mii_regaddr; 454 u_int8_t mii_turnaround; 455 u_int16_t mii_data; 456}; 457 458/* 459 * MII constants 460 */ 461#define DC_MII_STARTDELIM 0x01 462#define DC_MII_READOP 0x02 463#define DC_MII_WRITEOP 0x01 464#define DC_MII_TURNAROUND 0x02 465 466 467/* 468 * Registers specific to clone devices. 469 * This mainly relates to RX filter programming: not all 21x4x clones 470 * use the standard DEC filter programming mechanism. 471 */ 472 473/* 474 * ADMtek specific registers and constants for the AL981 and AN985. 475 * The AN985 doesn't use the magic PHY registers. 476 */ 477#define DC_AL_PAR0 0xA4 /* station address */ 478#define DC_AL_PAR1 0xA8 /* station address */ 479#define DC_AL_MAR0 0xAC /* multicast hash filter */ 480#define DC_AL_MAR1 0xB0 /* multicast hash filter */ 481#define DC_AL_BMCR 0xB4 /* built in PHY control */ 482#define DC_AL_BMSR 0xB8 /* built in PHY status */ 483#define DC_AL_VENID 0xBC /* built in PHY ID0 */ 484#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ 485#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ 486#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ 487#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ 488 489#define DC_ADMTEK_PHYADDR 0x1 490#define DC_AL_EE_NODEADDR 4 491/* End of ADMtek specific registers */ 492 493/* 494 * ASIX specific registers. 495 */ 496#define DC_AX_FILTIDX 0x68 /* RX filter index */ 497#define DC_AX_FILTDATA 0x70 /* RX filter data */ 498 499/* 500 * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). 501 */ 502#define DC_AX_NETCFG_RX_BROAD 0x00000100 503 504/* 505 * RX Filter Index Register values 506 */ 507#define DC_AX_FILTIDX_PAR0 0x00000000 508#define DC_AX_FILTIDX_PAR1 0x00000001 509#define DC_AX_FILTIDX_MAR0 0x00000002 510#define DC_AX_FILTIDX_MAR1 0x00000003 511/* End of ASIX specific registers */ 512 513/* 514 * Macronix specific registers. The Macronix chips have a special 515 * register for reading the NWAY status, which we don't use, plus 516 * a magic packet register, which we need to tweak a bit per the 517 * Macronix application notes. 518 */ 519#define DC_MX_MAGICPACKET 0x80 520#define DC_MX_NWAYSTAT 0xA0 521 522/* 523 * Magic packet register 524 */ 525#define DC_MX_MPACK_DISABLE 0x00400000 526 527/* 528 * NWAY status register. 529 */ 530#define DC_MX_NWAY_10BTHALF 0x08000000 531#define DC_MX_NWAY_10BTFULL 0x10000000 532#define DC_MX_NWAY_100BTHALF 0x20000000 533#define DC_MX_NWAY_100BTFULL 0x40000000 534#define DC_MX_NWAY_100BT4 0x80000000 535 536/* 537 * These are magic values that must be written into CSR16 538 * (DC_MX_MAGICPACKET) in order to put the chip into proper 539 * operating mode. The magic numbers are documented in the 540 * Macronix 98715 application notes. 541 */ 542#define DC_MX_MAGIC_98713 0x0F370000 543#define DC_MX_MAGIC_98713A 0x0B3C0000 544#define DC_MX_MAGIC_98715 0x0B3C0000 545#define DC_MX_MAGIC_98725 0x0B3C0000 546/* End of Macronix specific registers */ 547 548/* 549 * PNIC 82c168/82c169 specific registers. 550 * The PNIC has its own special NWAY support, which doesn't work, 551 * and shortcut ways of reading the EEPROM and MII bus. 552 */ 553#define DC_PN_GPIO 0x60 /* general purpose pins control */ 554#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ 555#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ 556#define DC_PN_MII 0xA0 /* MII access register */ 557#define DC_PN_NWAY 0xB8 /* Internal NWAY register */ 558 559/* Serial I/O EEPROM register */ 560#define DC_PN_SIOCTL_DATA 0x0000003F 561#define DC_PN_SIOCTL_OPCODE 0x00000300 562#define DC_PN_SIOCTL_BUSY 0x80000000 563 564#define DC_PN_EEOPCODE_ERASE 0x00000300 565#define DC_PN_EEOPCODE_READ 0x00000600 566#define DC_PN_EEOPCODE_WRITE 0x00000100 567 568/* 569 * The first two general purpose pins control speed selection and 570 * 100Mbps loopback on the 82c168 chip. The control bits should always 571 * be set (to make the data pins outputs) and the speed selction and 572 * loopback bits set accordingly when changing media. Physically, this 573 * will set the state of a relay mounted on the card. 574 */ 575#define DC_PN_GPIO_DATA0 0x000000001 576#define DC_PN_GPIO_DATA1 0x000000002 577#define DC_PN_GPIO_DATA2 0x000000004 578#define DC_PN_GPIO_DATA3 0x000000008 579#define DC_PN_GPIO_CTL0 0x000000010 580#define DC_PN_GPIO_CTL1 0x000000020 581#define DC_PN_GPIO_CTL2 0x000000040 582#define DC_PN_GPIO_CTL3 0x000000080 583#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ 584#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ 585#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 586#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 587#define DC_PN_GPIO_SETBIT(sc, r) \ 588 DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) 589#define DC_PN_GPIO_CLRBIT(sc, r) \ 590 { \ 591 DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ 592 DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ 593 } 594 595/* shortcut MII access register */ 596#define DC_PN_MII_DATA 0x0000FFFF 597#define DC_PN_MII_RESERVER 0x00020000 598#define DC_PN_MII_REGADDR 0x007C0000 599#define DC_PN_MII_PHYADDR 0x0F800000 600#define DC_PN_MII_OPCODE 0x30000000 601#define DC_PN_MII_BUSY 0x80000000 602 603#define DC_PN_MIIOPCODE_READ 0x60020000 604#define DC_PN_MIIOPCODE_WRITE 0x50020000 605 606/* Internal NWAY bits */ 607#define DC_PN_NWAY_RESET 0x00000001 /* reset */ 608#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ 609#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ 610#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ 611#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ 612#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ 613#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ 614#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ 615#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ 616#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ 617#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ 618#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ 619#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ 620#define DC_PN_NWAY_CAP10HDX 0x00002000 621#define DC_PN_NWAY_CAP10FDX 0x00004000 622#define DC_PN_NWAY_CAP100FDX 0x00008000 623#define DC_PN_NWAY_CAP100HDX 0x00010000 624#define DC_PN_NWAY_CAP100T4 0x00020000 625#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ 626#define DC_PN_NWAY_REMFAULT 0x04000000 627#define DC_PN_NWAY_LPAR10HDX 0x08000000 628#define DC_PN_NWAY_LPAR10FDX 0x10000000 629#define DC_PN_NWAY_LPAR100FDX 0x20000000 630#define DC_PN_NWAY_LPAR100HDX 0x40000000 631#define DC_PN_NWAY_LPAR100T4 0x80000000 632 633/* End of PNIC specific registers */ 634 635struct dc_softc { 636 struct arpcom arpcom; /* interface info */ 637 bus_space_handle_t dc_bhandle; /* bus space handle */ 638 bus_space_tag_t dc_btag; /* bus space tag */ 639 void *dc_intrhand; 640 struct resource *dc_irq; 641 struct resource *dc_res; 642 struct dc_type *dc_info; /* adapter info */ 643 device_t dc_miibus; 644 u_int8_t dc_unit; /* interface number */ 645 u_int8_t dc_type; 646 u_int8_t dc_pmode; 647 u_int8_t dc_link; 648 u_int8_t dc_cachesize; 649 int dc_pnic_rx_bug_save; 650 unsigned char *dc_pnic_rx_buf; 651 int dc_if_flags; 652 int dc_if_media; 653 u_int32_t dc_flags; 654 u_int32_t dc_txthresh; 655 struct dc_list_data *dc_ldata; 656 struct dc_chain_data dc_cdata; 657 struct callout_handle dc_stat_ch; 658}; 659 660#define DC_TX_POLL 0x00000001 661#define DC_TX_COALESCE 0x00000002 662#define DC_TX_ADMTEK_WAR 0x00000004 663#define DC_TX_USE_TX_INTR 0x00000008 664#define DC_RX_FILTER_TULIP 0x00000010 665#define DC_TX_INTR_FIRSTFRAG 0x00000020 666#define DC_PNIC_RX_BUG_WAR 0x00000040 667#define DC_TX_FIXED_RING 0x00000080 668#define DC_TX_STORENFWD 0x00000100 669#define DC_REDUCED_MII_POLL 0x00000200 670#define DC_TX_INTR_ALWAYS 0x00000400 671 672/* 673 * register space access macros 674 */ 675#define CSR_WRITE_4(sc, reg, val) \ 676 bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) 677 678#define CSR_READ_4(sc, reg) \ 679 bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) 680 681#define DC_TIMEOUT 1000 682#define ETHER_ALIGN 2 683 684/* 685 * General constants that are fun to know. 686 */ 687 688/* 689 * DEC PCI vendor ID 690 */ 691#define DC_VENDORID_DEC 0x1011 692 693/* 694 * DEC/Intel 21143 PCI device ID 695 */ 696#define DC_DEVICEID_21143 0x0019 697 698/* 699 * Macronix PCI vendor ID 700 */ 701#define DC_VENDORID_MX 0x10D9 702 703/* 704 * Macronix PMAC device IDs. 705 */ 706#define DC_DEVICEID_98713 0x0512 707#define DC_DEVICEID_987x5 0x0531 708 709/* Macronix PCI revision codes. */ 710#define DC_REVISION_98713 0x00 711#define DC_REVISION_98713A 0x10 712#define DC_REVISION_98715 0x20 713#define DC_REVISION_98725 0x30 714 715/* 716 * Compex PCI vendor ID. 717 */ 718#define DC_VENDORID_CP 0x11F6 719 720/* 721 * Compex PMAC PCI device IDs. 722 */ 723#define DC_DEVICEID_98713_CP 0x9881 724 725/* 726 * Lite-On PNIC PCI vendor ID 727 */ 728#define DC_VENDORID_LO 0x11AD 729 730/* 731 * 82c168/82c169 PNIC device IDs. Both chips have the same device 732 * ID but different revisions. Revision 0x10 is the 82c168, and 733 * 0x20 is the 82c169. 734 */ 735#define DC_DEVICEID_82C168 0x0002 736 737#define DC_REVISION_82C168 0x10 738#define DC_REVISION_82C169 0x20 739 740/* 741 * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A 742 * with wake on lan/magic packet support. 743 */ 744#define DC_DEVICEID_82C115 0xc115 745 746/* 747 * Davicom vendor ID. 748 */ 749#define DC_VENDORID_DAVICOM 0x1282 750 751/* 752 * Davicom device IDs. 753 */ 754#define DC_DEVICEID_DM9100 0x9100 755#define DC_DEVICEID_DM9102 0x9102 756 757/* 758 * ADMtek vendor ID. 759 */ 760#define DC_VENDORID_ADMTEK 0x1317 761 762/* 763 * ADMtek device IDs. 764 */ 765#define DC_DEVICEID_AL981 0x0981 766#define DC_DEVICEID_AN985 0x0985 767 768/* 769 * ASIX vendor ID. 770 */ 771#define DC_VENDORID_ASIX 0x125B 772 773/* 774 * ASIX device IDs. 775 */ 776#define DC_DEVICEID_AX88140A 0x1400 777 778/* 779 * The ASIX AX88140 and ASIX AX88141 have the same vendor and 780 * device IDs but different revision values. 781 */ 782#define DC_REVISION_88140 0x00 783#define DC_REVISION_88141 0x10 784 785/* 786 * PCI low memory base and low I/O base register, and 787 * other PCI registers. 788 */ 789 790#define DC_PCI_CFID 0x00 /* Id */ 791#define DC_PCI_CFCS 0x04 /* Command and status */ 792#define DC_PCI_CFRV 0x08 /* Revision */ 793#define DC_PCI_CFLT 0x0C /* Latency timer */ 794#define DC_PCI_CFBIO 0x10 /* Base I/O address */ 795#define DC_PCI_CFBMA 0x14 /* Base memory address */ 796#define DC_PCI_CCIS 0x28 /* Card info struct */ 797#define DC_PCI_CSID 0x2C /* Subsystem ID */ 798#define DC_PCI_CBER 0x30 /* Expansion ROM base address */ 799#define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */ 800#define DC_PCI_CFIT 0x3C /* Interrupt */ 801#define DC_PCI_CFDD 0x40 /* Device and driver area */ 802#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ 803#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ 804#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ 805#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ 806#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ 807#define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */ 808#define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */ 809 810/* PCI ID register */ 811#define DC_CFID_VENDOR 0x0000FFFF 812#define DC_CFID_DEVICE 0xFFFF0000 813 814/* PCI command/status register */ 815#define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */ 816#define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */ 817#define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */ 818#define DC_CFCS_MWI_ENB 0x00000008 /* mem write and inval enable */ 819#define DC_CFCS_PARITYERR_ENB 0x00000020 /* parity error enable */ 820#define DC_CFCS_SYSERR_ENB 0x00000080 /* system error enable */ 821#define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */ 822#define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */ 823#define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */ 824#define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */ 825#define DC_CFCS_TGTABRT 0x10000000 /* received target abort */ 826#define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */ 827#define DC_CFCS_SYSERR 0x40000000 /* asserted system error */ 828#define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */ 829 830/* PCI revision register */ 831#define DC_CFRV_STEPPING 0x0000000F 832#define DC_CFRV_REVISION 0x000000F0 833#define DC_CFRV_SUBCLASS 0x00FF0000 834#define DC_CFRV_BASECLASS 0xFF000000 835 836#define DC_21143_PB_REV 0x00000030 837#define DC_21143_TB_REV 0x00000030 838#define DC_21143_PC_REV 0x00000030 839#define DC_21143_TC_REV 0x00000030 840#define DC_21143_PD_REV 0x00000041 841#define DC_21143_TD_REV 0x00000041 842 843/* PCI latency timer register */ 844#define DC_CFLT_CACHELINESIZE 0x000000FF 845#define DC_CFLT_LATENCYTIMER 0x0000FF00 846 847/* PCI subsystem ID register */ 848#define DC_CSID_VENDOR 0x0000FFFF 849#define DC_CSID_DEVICE 0xFFFF0000 850 851/* PCI cababilities pointer */ 852#define DC_CCAP_OFFSET 0x000000FF 853 854/* PCI interrupt config register */ 855#define DC_CFIT_INTLINE 0x000000FF 856#define DC_CFIT_INTPIN 0x0000FF00 857#define DC_CFIT_MIN_GNT 0x00FF0000 858#define DC_CFIT_MAX_LAT 0xFF000000 859 860/* PCI capability register */ 861#define DC_CCID_CAPID 0x000000FF 862#define DC_CCID_NEXTPTR 0x0000FF00 863#define DC_CCID_PM_VERS 0x00070000 864#define DC_CCID_PME_CLK 0x00080000 865#define DC_CCID_DVSPEC_INT 0x00200000 866#define DC_CCID_STATE_D1 0x02000000 867#define DC_CCID_STATE_D2 0x04000000 868#define DC_CCID_PME_D0 0x08000000 869#define DC_CCID_PME_D1 0x10000000 870#define DC_CCID_PME_D2 0x20000000 871#define DC_CCID_PME_D3HOT 0x40000000 872#define DC_CCID_PME_D3COLD 0x80000000 873 874/* PCI power management control/status register */ 875#define DC_CPMC_STATE 0x00000003 876#define DC_CPMC_PME_ENB 0x00000100 877#define DC_CPMC_PME_STS 0x00008000 878 879#define DC_PSTATE_D0 0x0 880#define DC_PSTATE_D1 0x1 881#define DC_PSTATE_D2 0x2 882#define DC_PSTATE_D3 0x3 883 884/* Device specific region */ 885/* Configuration and driver area */ 886#define DC_CFDD_DRVUSE 0x0000FFFF 887#define DC_CFDD_SNOOZE_MODE 0x40000000 888#define DC_CFDD_SLEEP_MODE 0x80000000 889 890/* Configuration wake-up command register */ 891#define DC_CWUC_MUST_BE_ZERO 0x00000001 892#define DC_CWUC_SECUREON_ENB 0x00000002 893#define DC_CWUC_FORCE_WUL 0x00000004 894#define DC_CWUC_BNC_ABILITY 0x00000008 895#define DC_CWUC_AUI_ABILITY 0x00000010 896#define DC_CWUC_TP10_ABILITY 0x00000020 897#define DC_CWUC_MII_ABILITY 0x00000040 898#define DC_CWUC_SYM_ABILITY 0x00000080 899#define DC_CWUC_LOCK 0x00000100 900 901#ifdef __alpha__ 902#undef vtophys 903#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 904#endif 905