if_dcreg.h revision 218832
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/dc/if_dcreg.h 218832 2011-02-19 02:47:10Z yongari $ 33 */ 34 35/* 36 * 21143 and clone common register definitions. 37 */ 38 39#define DC_BUSCTL 0x00 /* bus control */ 40#define DC_TXSTART 0x08 /* tx start demand */ 41#define DC_RXSTART 0x10 /* rx start demand */ 42#define DC_RXADDR 0x18 /* rx descriptor list start addr */ 43#define DC_TXADDR 0x20 /* tx descriptor list start addr */ 44#define DC_ISR 0x28 /* interrupt status register */ 45#define DC_NETCFG 0x30 /* network config register */ 46#define DC_IMR 0x38 /* interrupt mask */ 47#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ 48#define DC_SIO 0x48 /* MII and ROM/EEPROM access */ 49#define DC_ROM 0x50 /* ROM programming address */ 50#define DC_TIMER 0x58 /* general timer */ 51#define DC_10BTSTAT 0x60 /* SIA status */ 52#define DC_SIARESET 0x68 /* SIA connectivity */ 53#define DC_10BTCTRL 0x70 /* SIA transmit and receive */ 54#define DC_WATCHDOG 0x78 /* SIA and general purpose port */ 55#define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */ 56 57/* 58 * There are two general 'types' of MX chips that we need to be 59 * concerned with. One is the original 98713, which has its internal 60 * NWAY support controlled via the MDIO bits in the serial I/O 61 * register. The other is everything else (from the 98713A on up), 62 * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, 63 * just like the 21143. This type setting also governs which of the 64 * 'magic' numbers we write to CSR16. The PNIC II falls into the 65 * 98713A/98715/98715A/98725 category. 66 */ 67#define DC_TYPE_98713 0x1 68#define DC_TYPE_98713A 0x2 69#define DC_TYPE_987x5 0x3 70 71/* Other type of supported chips. */ 72#define DC_TYPE_21143 0x4 /* Intel 21143 */ 73#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ 74#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ 75#define DC_TYPE_AN983 0x7 /* ADMtek AN983 Centaur */ 76#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ 77#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ 78#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ 79#define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */ 80#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */ 81 82#define DC_IS_MACRONIX(x) \ 83 (x->dc_type == DC_TYPE_98713 || \ 84 x->dc_type == DC_TYPE_98713A || \ 85 x->dc_type == DC_TYPE_987x5) 86 87#define DC_IS_ADMTEK(x) \ 88 (x->dc_type == DC_TYPE_AL981 || \ 89 x->dc_type == DC_TYPE_AN983) 90 91#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) 92#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) 93#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) 94#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN983) 95#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) 96#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) 97#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) 98#define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM) 99#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT) 100 101/* MII/symbol mode port types */ 102#define DC_PMODE_MII 0x1 103#define DC_PMODE_SYM 0x2 104#define DC_PMODE_SIA 0x3 105 106/* 107 * Bus control bits. 108 */ 109#define DC_BUSCTL_RESET 0x00000001 110#define DC_BUSCTL_ARBITRATION 0x00000002 111#define DC_BUSCTL_SKIPLEN 0x0000007C 112#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 113#define DC_BUSCTL_BURSTLEN 0x00003F00 114#define DC_BUSCTL_CACHEALIGN 0x0000C000 115#define DC_BUSCTL_TXPOLL 0x000E0000 116#define DC_BUSCTL_DBO 0x00100000 117#define DC_BUSCTL_MRME 0x00200000 118#define DC_BUSCTL_MRLE 0x00800000 119#define DC_BUSCTL_MWIE 0x01000000 120#define DC_BUSCTL_ONNOW_ENB 0x04000000 121 122#define DC_SKIPLEN_1LONG 0x00000004 123#define DC_SKIPLEN_2LONG 0x00000008 124#define DC_SKIPLEN_3LONG 0x00000010 125#define DC_SKIPLEN_4LONG 0x00000020 126#define DC_SKIPLEN_5LONG 0x00000040 127 128#define DC_CACHEALIGN_NONE 0x00000000 129#define DC_CACHEALIGN_8LONG 0x00004000 130#define DC_CACHEALIGN_16LONG 0x00008000 131#define DC_CACHEALIGN_32LONG 0x0000C000 132 133#define DC_BURSTLEN_USECA 0x00000000 134#define DC_BURSTLEN_1LONG 0x00000100 135#define DC_BURSTLEN_2LONG 0x00000200 136#define DC_BURSTLEN_4LONG 0x00000400 137#define DC_BURSTLEN_8LONG 0x00000800 138#define DC_BURSTLEN_16LONG 0x00001000 139#define DC_BURSTLEN_32LONG 0x00002000 140 141#define DC_TXPOLL_OFF 0x00000000 142#define DC_TXPOLL_1 0x00020000 143#define DC_TXPOLL_2 0x00040000 144#define DC_TXPOLL_3 0x00060000 145#define DC_TXPOLL_4 0x00080000 146#define DC_TXPOLL_5 0x000A0000 147#define DC_TXPOLL_6 0x000C0000 148#define DC_TXPOLL_7 0x000E0000 149 150/* 151 * Interrupt status bits. 152 */ 153#define DC_ISR_TX_OK 0x00000001 154#define DC_ISR_TX_IDLE 0x00000002 155#define DC_ISR_TX_NOBUF 0x00000004 156#define DC_ISR_TX_JABBERTIMEO 0x00000008 157#define DC_ISR_LINKGOOD 0x00000010 158#define DC_ISR_TX_UNDERRUN 0x00000020 159#define DC_ISR_RX_OK 0x00000040 160#define DC_ISR_RX_NOBUF 0x00000080 161#define DC_ISR_RX_READ 0x00000100 162#define DC_ISR_RX_WATDOGTIMEO 0x00000200 163#define DC_ISR_TX_EARLY 0x00000400 164#define DC_ISR_TIMER_EXPIRED 0x00000800 165#define DC_ISR_LINKFAIL 0x00001000 166#define DC_ISR_BUS_ERR 0x00002000 167#define DC_ISR_RX_EARLY 0x00004000 168#define DC_ISR_ABNORMAL 0x00008000 169#define DC_ISR_NORMAL 0x00010000 170#define DC_ISR_RX_STATE 0x000E0000 171#define DC_ISR_TX_STATE 0x00700000 172#define DC_ISR_BUSERRTYPE 0x03800000 173#define DC_ISR_100MBPSLINK 0x08000000 174#define DC_ISR_MAGICKPACK 0x10000000 175 176#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 177#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 178#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 179#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 180#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 181#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 182#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 183#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 184 185#define DC_HAS_BROKEN_RXSTATE(x) \ 186 (DC_IS_CENTAUR(x) || DC_IS_CONEXANT(x) || (DC_IS_DAVICOM(x) && \ 187 pci_get_revid((x)->dc_dev) >= DC_REVISION_DM9102A)) 188 189#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ 190#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 191#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 192#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 193#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 194#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 195#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 196#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 197 198/* 199 * Network config bits. 200 */ 201#define DC_NETCFG_RX_HASHPERF 0x00000001 202#define DC_NETCFG_RX_ON 0x00000002 203#define DC_NETCFG_RX_HASHONLY 0x00000004 204#define DC_NETCFG_RX_BADFRAMES 0x00000008 205#define DC_NETCFG_RX_INVFILT 0x00000010 206#define DC_NETCFG_BACKOFFCNT 0x00000020 207#define DC_NETCFG_RX_PROMISC 0x00000040 208#define DC_NETCFG_RX_ALLMULTI 0x00000080 209#define DC_NETCFG_FULLDUPLEX 0x00000200 210#define DC_NETCFG_LOOPBACK 0x00000C00 211#define DC_NETCFG_FORCECOLL 0x00001000 212#define DC_NETCFG_TX_ON 0x00002000 213#define DC_NETCFG_TX_THRESH 0x0000C000 214#define DC_NETCFG_TX_BACKOFF 0x00020000 215#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ 216#define DC_NETCFG_HEARTBEAT 0x00080000 217#define DC_NETCFG_STORENFWD 0x00200000 218#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ 219#define DC_NETCFG_PCS 0x00800000 220#define DC_NETCFG_SCRAMBLER 0x01000000 221#define DC_NETCFG_NO_RXCRC 0x02000000 222#define DC_NETCFG_RX_ALL 0x40000000 223#define DC_NETCFG_CAPEFFECT 0x80000000 224 225#define DC_OPMODE_NORM 0x00000000 226#define DC_OPMODE_INTLOOP 0x00000400 227#define DC_OPMODE_EXTLOOP 0x00000800 228 229#if 0 230#define DC_TXTHRESH_72BYTES 0x00000000 231#define DC_TXTHRESH_96BYTES 0x00004000 232#define DC_TXTHRESH_128BYTES 0x00008000 233#define DC_TXTHRESH_160BYTES 0x0000C000 234#endif 235 236#define DC_TXTHRESH_MIN 0x00000000 237#define DC_TXTHRESH_INC 0x00004000 238#define DC_TXTHRESH_MAX 0x0000C000 239 240 241/* 242 * Interrupt mask bits. 243 */ 244#define DC_IMR_TX_OK 0x00000001 245#define DC_IMR_TX_IDLE 0x00000002 246#define DC_IMR_TX_NOBUF 0x00000004 247#define DC_IMR_TX_JABBERTIMEO 0x00000008 248#define DC_IMR_LINKGOOD 0x00000010 249#define DC_IMR_TX_UNDERRUN 0x00000020 250#define DC_IMR_RX_OK 0x00000040 251#define DC_IMR_RX_NOBUF 0x00000080 252#define DC_IMR_RX_READ 0x00000100 253#define DC_IMR_RX_WATDOGTIMEO 0x00000200 254#define DC_IMR_TX_EARLY 0x00000400 255#define DC_IMR_TIMER_EXPIRED 0x00000800 256#define DC_IMR_LINKFAIL 0x00001000 257#define DC_IMR_BUS_ERR 0x00002000 258#define DC_IMR_RX_EARLY 0x00004000 259#define DC_IMR_ABNORMAL 0x00008000 260#define DC_IMR_NORMAL 0x00010000 261#define DC_IMR_100MBPSLINK 0x08000000 262#define DC_IMR_MAGICKPACK 0x10000000 263 264#define DC_INTRS \ 265 (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ 266 DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ 267 DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) 268/* 269 * Serial I/O (EEPROM/ROM) bits. 270 */ 271#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 272#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 273#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 274#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 275#define DC_SIO_ROMDATA4 0x00000010 276#define DC_SIO_ROMDATA5 0x00000020 277#define DC_SIO_ROMDATA6 0x00000040 278#define DC_SIO_ROMDATA7 0x00000080 279#define DC_SIO_EESEL 0x00000800 280#define DC_SIO_ROMSEL 0x00001000 281#define DC_SIO_ROMCTL_WRITE 0x00002000 282#define DC_SIO_ROMCTL_READ 0x00004000 283#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ 284#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ 285#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ 286#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ 287 288#define DC_EECMD_WRITE 0x140 289#define DC_EECMD_READ 0x180 290#define DC_EECMD_ERASE 0x1c0 291 292#define DC_EE_NODEADDR_OFFSET 0x70 293#define DC_EE_NODEADDR 10 294 295/* 296 * General purpose timer register 297 */ 298#define DC_TIMER_VALUE 0x0000FFFF 299#define DC_TIMER_CONTINUOUS 0x00010000 300 301/* 302 * 10baseT status register 303 */ 304#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ 305#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ 306#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ 307#define DC_TSTAT_AUTOPOLARITY 0x00000008 308#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ 309#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ 310#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ 311#define DC_TSTAT_REMFAULT 0x00000800 312#define DC_TSTAT_ANEGSTAT 0x00007000 313#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ 314#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ 315 316#define DC_ASTAT_DISABLE 0x00000000 317#define DC_ASTAT_TXDISABLE 0x00001000 318#define DC_ASTAT_ABDETECT 0x00002000 319#define DC_ASTAT_ACKDETECT 0x00003000 320#define DC_ASTAT_CMPACKDETECT 0x00004000 321#define DC_ASTAT_AUTONEGCMP 0x00005000 322#define DC_ASTAT_LINKCHECK 0x00006000 323 324/* 325 * PHY reset register 326 */ 327#define DC_SIA_RESET 0x00000001 328#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ 329 330/* 331 * 10baseT control register 332 */ 333#define DC_TCTL_ENCODER_ENB 0x00000001 334#define DC_TCTL_LOOPBACK 0x00000002 335#define DC_TCTL_DRIVER_ENB 0x00000004 336#define DC_TCTL_LNKPULSE_ENB 0x00000008 337#define DC_TCTL_HALFDUPLEX 0x00000040 338#define DC_TCTL_AUTONEGENBL 0x00000080 339#define DC_TCTL_RX_SQUELCH 0x00000100 340#define DC_TCTL_COLL_SQUELCH 0x00000200 341#define DC_TCTL_COLL_DETECT 0x00000400 342#define DC_TCTL_SQE_ENB 0x00000800 343#define DC_TCTL_LINKTEST 0x00001000 344#define DC_TCTL_AUTOPOLARITY 0x00002000 345#define DC_TCTL_SET_POL_PLUS 0x00004000 346#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ 347#define DC_TCTL_100BTXHALF 0x00010000 348#define DC_TCTL_100BTXFULL 0x00020000 349#define DC_TCTL_100BT4 0x00040000 350 351/* 352 * Watchdog timer register 353 */ 354#define DC_WDOG_JABBERDIS 0x00000001 355#define DC_WDOG_HOSTUNJAB 0x00000002 356#define DC_WDOG_JABBERCLK 0x00000004 357#define DC_WDOG_RXWDOGDIS 0x00000010 358#define DC_WDOG_RXWDOGCLK 0x00000020 359#define DC_WDOG_MUSTBEZERO 0x00000100 360#define DC_WDOG_AUIBNC 0x00100000 361#define DC_WDOG_ACTIVITY 0x00200000 362#define DC_WDOG_RX_MATCH 0x00400000 363#define DC_WDOG_LINK 0x00800000 364#define DC_WDOG_CTLWREN 0x08000000 365 366/* 367 * SIA and General Purpose Port register (X3201) 368 */ 369#define DC_SIAGP_RXMATCH 0x40000000 370#define DC_SIAGP_INT1 0x20000000 371#define DC_SIAGP_INT0 0x10000000 372#define DC_SIAGP_WRITE_EN 0x08000000 373#define DC_SIAGP_RXMATCH_EN 0x04000000 374#define DC_SIAGP_INT1_EN 0x02000000 375#define DC_SIAGP_INT0_EN 0x01000000 376#define DC_SIAGP_LED3 0x00800000 377#define DC_SIAGP_LED2 0x00400000 378#define DC_SIAGP_LED1 0x00200000 379#define DC_SIAGP_LED0 0x00100000 380#define DC_SIAGP_MD_GP3_OUTPUT 0x00080000 381#define DC_SIAGP_MD_GP2_OUTPUT 0x00040000 382#define DC_SIAGP_MD_GP1_OUTPUT 0x00020000 383#define DC_SIAGP_MD_GP0_OUTPUT 0x00010000 384 385/* 386 * Size of a setup frame. 387 */ 388#define DC_SFRAME_LEN 192 389 390/* 391 * 21x4x TX/RX list structure. 392 */ 393 394struct dc_desc { 395 u_int32_t dc_status; 396 u_int32_t dc_ctl; 397 u_int32_t dc_ptr1; 398 u_int32_t dc_ptr2; 399}; 400 401#define dc_data dc_ptr1 402#define dc_next dc_ptr2 403 404#define DC_RXSTAT_FIFOOFLOW 0x00000001 405#define DC_RXSTAT_CRCERR 0x00000002 406#define DC_RXSTAT_DRIBBLE 0x00000004 407#define DC_RXSTAT_MIIERE 0x00000008 408#define DC_RXSTAT_WATCHDOG 0x00000010 409#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ 410#define DC_RXSTAT_COLLSEEN 0x00000040 411#define DC_RXSTAT_GIANT 0x00000080 412#define DC_RXSTAT_LASTFRAG 0x00000100 413#define DC_RXSTAT_FIRSTFRAG 0x00000200 414#define DC_RXSTAT_MULTICAST 0x00000400 415#define DC_RXSTAT_RUNT 0x00000800 416#define DC_RXSTAT_RXTYPE 0x00003000 417#define DC_RXSTAT_DE 0x00004000 418#define DC_RXSTAT_RXERR 0x00008000 419#define DC_RXSTAT_RXLEN 0x3FFF0000 420#define DC_RXSTAT_OWN 0x80000000 421 422#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) 423#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) 424 425#define DC_RXCTL_BUFLEN1 0x00000FFF 426#define DC_RXCTL_BUFLEN2 0x00FFF000 427#define DC_RXCTL_RLINK 0x01000000 428#define DC_RXCTL_RLAST 0x02000000 429 430#define DC_TXSTAT_DEFER 0x00000001 431#define DC_TXSTAT_UNDERRUN 0x00000002 432#define DC_TXSTAT_LINKFAIL 0x00000003 433#define DC_TXSTAT_COLLCNT 0x00000078 434#define DC_TXSTAT_SQE 0x00000080 435#define DC_TXSTAT_EXCESSCOLL 0x00000100 436#define DC_TXSTAT_LATECOLL 0x00000200 437#define DC_TXSTAT_NOCARRIER 0x00000400 438#define DC_TXSTAT_CARRLOST 0x00000800 439#define DC_TXSTAT_JABTIMEO 0x00004000 440#define DC_TXSTAT_ERRSUM 0x00008000 441#define DC_TXSTAT_OWN 0x80000000 442 443#define DC_TXCTL_BUFLEN1 0x000007FF 444#define DC_TXCTL_BUFLEN2 0x003FF800 445#define DC_TXCTL_FILTTYPE0 0x00400000 446#define DC_TXCTL_PAD 0x00800000 447#define DC_TXCTL_TLINK 0x01000000 448#define DC_TXCTL_TLAST 0x02000000 449#define DC_TXCTL_NOCRC 0x04000000 450#define DC_TXCTL_SETUP 0x08000000 451#define DC_TXCTL_FILTTYPE1 0x10000000 452#define DC_TXCTL_FIRSTFRAG 0x20000000 453#define DC_TXCTL_LASTFRAG 0x40000000 454#define DC_TXCTL_FINT 0x80000000 455 456#define DC_FILTER_PERFECT 0x00000000 457#define DC_FILTER_HASHPERF 0x00400000 458#define DC_FILTER_INVERSE 0x10000000 459#define DC_FILTER_HASHONLY 0x10400000 460 461#define DC_MAXFRAGS 16 462#ifdef DEVICE_POLLING 463#define DC_RX_LIST_CNT 192 464#else 465#define DC_RX_LIST_CNT 64 466#endif 467#define DC_TX_LIST_CNT 256 468#define DC_TX_LIST_RSVD 5 469#define DC_MIN_FRAMELEN 60 470#define DC_RXLEN 1536 471 472#define DC_INC(x, y) (x) = (x + 1) % y 473 474#define DC_LIST_ALIGN (sizeof(struct dc_desc)) 475#define DC_RXBUF_ALIGN 4 476 477/* Macros to easily get the DMA address of a descriptor. */ 478#define DC_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF) 479#define DC_RXDESC(sc, i) \ 480 (DC_ADDR_LO(sc->dc_ldata.dc_rx_list_paddr + (sizeof(struct dc_desc) * i))) 481#define DC_TXDESC(sc, i) \ 482 (DC_ADDR_LO(sc->dc_ldata.dc_tx_list_paddr + (sizeof(struct dc_desc) * i))) 483 484#if BYTE_ORDER == BIG_ENDIAN 485#define DC_SP_MAC(x) ((x) << 16) 486#else 487#define DC_SP_MAC(x) (x) 488#endif 489 490struct dc_list_data { 491 struct dc_desc *dc_rx_list; 492 bus_addr_t dc_rx_list_paddr; 493 struct dc_desc *dc_tx_list; 494 bus_addr_t dc_tx_list_paddr; 495}; 496 497#define DC_RX_LIST_SZ ((sizeof(struct dc_desc) * DC_RX_LIST_CNT)) 498#define DC_TX_LIST_SZ ((sizeof(struct dc_desc) * DC_TX_LIST_CNT)) 499 500struct dc_chain_data { 501 struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; 502 struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; 503 bus_dmamap_t dc_rx_map[DC_RX_LIST_CNT]; 504 bus_dmamap_t dc_tx_map[DC_TX_LIST_CNT]; 505 u_int32_t *dc_sbuf; 506 u_int8_t dc_pad[DC_MIN_FRAMELEN]; 507 int dc_tx_pkts; 508 int dc_tx_first; 509 int dc_tx_prod; 510 int dc_tx_cons; 511 int dc_tx_cnt; 512 int dc_rx_prod; 513}; 514 515struct dc_mediainfo { 516 int dc_media; 517 u_int8_t *dc_gp_ptr; 518 u_int8_t dc_gp_len; 519 u_int8_t *dc_reset_ptr; 520 u_int8_t dc_reset_len; 521 struct dc_mediainfo *dc_next; 522}; 523 524 525struct dc_type { 526 u_int32_t dc_devid; 527 u_int8_t dc_minrev; 528 char *dc_name; 529}; 530 531struct dc_mii_frame { 532 u_int8_t mii_stdelim; 533 u_int8_t mii_opcode; 534 u_int8_t mii_phyaddr; 535 u_int8_t mii_regaddr; 536 u_int8_t mii_turnaround; 537 u_int16_t mii_data; 538}; 539 540/* 541 * MII constants 542 */ 543#define DC_MII_STARTDELIM 0x01 544#define DC_MII_READOP 0x02 545#define DC_MII_WRITEOP 0x01 546#define DC_MII_TURNAROUND 0x02 547 548 549/* 550 * Registers specific to clone devices. 551 * This mainly relates to RX filter programming: not all 21x4x clones 552 * use the standard DEC filter programming mechanism. 553 */ 554 555/* 556 * ADMtek specific registers and constants for the AL981 and AN983. 557 * The AN983 doesn't use the magic PHY registers. 558 */ 559#define DC_AL_CR 0x88 /* command register */ 560#define DC_AL_PAR0 0xA4 /* station address */ 561#define DC_AL_PAR1 0xA8 /* station address */ 562#define DC_AL_MAR0 0xAC /* multicast hash filter */ 563#define DC_AL_MAR1 0xB0 /* multicast hash filter */ 564#define DC_AL_BMCR 0xB4 /* built in PHY control */ 565#define DC_AL_BMSR 0xB8 /* built in PHY status */ 566#define DC_AL_VENID 0xBC /* built in PHY ID0 */ 567#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ 568#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ 569#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ 570#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ 571 572#define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */ 573#define DC_ADMTEK_PHYADDR 0x1 574#define DC_AL_EE_NODEADDR 4 575/* End of ADMtek specific registers */ 576 577/* 578 * ASIX specific registers. 579 */ 580#define DC_AX_FILTIDX 0x68 /* RX filter index */ 581#define DC_AX_FILTDATA 0x70 /* RX filter data */ 582 583/* 584 * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). 585 */ 586#define DC_AX_NETCFG_RX_BROAD 0x00000100 587 588/* 589 * RX Filter Index Register values 590 */ 591#define DC_AX_FILTIDX_PAR0 0x00000000 592#define DC_AX_FILTIDX_PAR1 0x00000001 593#define DC_AX_FILTIDX_MAR0 0x00000002 594#define DC_AX_FILTIDX_MAR1 0x00000003 595/* End of ASIX specific registers */ 596 597/* 598 * Macronix specific registers. The Macronix chips have a special 599 * register for reading the NWAY status, which we don't use, plus 600 * a magic packet register, which we need to tweak a bit per the 601 * Macronix application notes. 602 */ 603#define DC_MX_MAGICPACKET 0x80 604#define DC_MX_NWAYSTAT 0xA0 605 606/* 607 * Magic packet register 608 */ 609#define DC_MX_MPACK_DISABLE 0x00400000 610 611/* 612 * NWAY status register. 613 */ 614#define DC_MX_NWAY_10BTHALF 0x08000000 615#define DC_MX_NWAY_10BTFULL 0x10000000 616#define DC_MX_NWAY_100BTHALF 0x20000000 617#define DC_MX_NWAY_100BTFULL 0x40000000 618#define DC_MX_NWAY_100BT4 0x80000000 619 620/* 621 * These are magic values that must be written into CSR16 622 * (DC_MX_MAGICPACKET) in order to put the chip into proper 623 * operating mode. The magic numbers are documented in the 624 * Macronix 98715 application notes. 625 */ 626#define DC_MX_MAGIC_98713 0x0F370000 627#define DC_MX_MAGIC_98713A 0x0B3C0000 628#define DC_MX_MAGIC_98715 0x0B3C0000 629#define DC_MX_MAGIC_98725 0x0B3C0000 630/* End of Macronix specific registers */ 631 632/* 633 * PNIC 82c168/82c169 specific registers. 634 * The PNIC has its own special NWAY support, which doesn't work, 635 * and shortcut ways of reading the EEPROM and MII bus. 636 */ 637#define DC_PN_GPIO 0x60 /* general purpose pins control */ 638#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ 639#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ 640#define DC_PN_MII 0xA0 /* MII access register */ 641#define DC_PN_NWAY 0xB8 /* Internal NWAY register */ 642 643/* Serial I/O EEPROM register */ 644#define DC_PN_SIOCTL_DATA 0x0000003F 645#define DC_PN_SIOCTL_OPCODE 0x00000300 646#define DC_PN_SIOCTL_BUSY 0x80000000 647 648#define DC_PN_EEOPCODE_ERASE 0x00000300 649#define DC_PN_EEOPCODE_READ 0x00000600 650#define DC_PN_EEOPCODE_WRITE 0x00000100 651 652/* 653 * The first two general purpose pins control speed selection and 654 * 100Mbps loopback on the 82c168 chip. The control bits should always 655 * be set (to make the data pins outputs) and the speed selction and 656 * loopback bits set accordingly when changing media. Physically, this 657 * will set the state of a relay mounted on the card. 658 */ 659#define DC_PN_GPIO_DATA0 0x000000001 660#define DC_PN_GPIO_DATA1 0x000000002 661#define DC_PN_GPIO_DATA2 0x000000004 662#define DC_PN_GPIO_DATA3 0x000000008 663#define DC_PN_GPIO_CTL0 0x000000010 664#define DC_PN_GPIO_CTL1 0x000000020 665#define DC_PN_GPIO_CTL2 0x000000040 666#define DC_PN_GPIO_CTL3 0x000000080 667#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ 668#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ 669#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 670#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 671#define DC_PN_GPIO_SETBIT(sc, r) \ 672 DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) 673#define DC_PN_GPIO_CLRBIT(sc, r) \ 674 { \ 675 DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ 676 DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ 677 } 678 679/* shortcut MII access register */ 680#define DC_PN_MII_DATA 0x0000FFFF 681#define DC_PN_MII_RESERVER 0x00020000 682#define DC_PN_MII_REGADDR 0x007C0000 683#define DC_PN_MII_PHYADDR 0x0F800000 684#define DC_PN_MII_OPCODE 0x30000000 685#define DC_PN_MII_BUSY 0x80000000 686 687#define DC_PN_MIIOPCODE_READ 0x60020000 688#define DC_PN_MIIOPCODE_WRITE 0x50020000 689 690/* Internal NWAY bits */ 691#define DC_PN_NWAY_RESET 0x00000001 /* reset */ 692#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ 693#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ 694#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ 695#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ 696#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ 697#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ 698#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ 699#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ 700#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ 701#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ 702#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ 703#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ 704#define DC_PN_NWAY_CAP10HDX 0x00002000 705#define DC_PN_NWAY_CAP10FDX 0x00004000 706#define DC_PN_NWAY_CAP100FDX 0x00008000 707#define DC_PN_NWAY_CAP100HDX 0x00010000 708#define DC_PN_NWAY_CAP100T4 0x00020000 709#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ 710#define DC_PN_NWAY_REMFAULT 0x04000000 711#define DC_PN_NWAY_LPAR10HDX 0x08000000 712#define DC_PN_NWAY_LPAR10FDX 0x10000000 713#define DC_PN_NWAY_LPAR100FDX 0x20000000 714#define DC_PN_NWAY_LPAR100HDX 0x40000000 715#define DC_PN_NWAY_LPAR100T4 0x80000000 716 717/* End of PNIC specific registers */ 718 719/* 720 * CONEXANT specific registers. 721 */ 722 723#define DC_CONEXANT_PHYADDR 0x1 724#define DC_CONEXANT_EE_NODEADDR 0x19A 725 726/* End of CONEXANT specific registers */ 727 728 729struct dc_softc { 730 struct ifnet *dc_ifp; /* interface info */ 731 device_t dc_dev; /* device info */ 732 bus_space_handle_t dc_bhandle; /* bus space handle */ 733 bus_space_tag_t dc_btag; /* bus space tag */ 734 bus_dma_tag_t dc_ptag; /* parent DMA tag */ 735 bus_dmamap_t dc_sparemap; 736 bus_dma_tag_t dc_rx_ltag; /* tag for RX descriptors */ 737 bus_dmamap_t dc_rx_lmap; 738 bus_dma_tag_t dc_tx_ltag; /* tag for TX descriptors */ 739 bus_dmamap_t dc_tx_lmap; 740 bus_dma_tag_t dc_stag; /* tag for the setup frame */ 741 bus_dmamap_t dc_smap; /* map for the setup frame */ 742 bus_addr_t dc_saddr; /* DMA address of setup frame */ 743 bus_dma_tag_t dc_rx_mtag; /* tag for RX mbufs */ 744 bus_dma_tag_t dc_tx_mtag; /* tag for TX mbufs */ 745 void *dc_intrhand; 746 struct resource *dc_irq; 747 struct resource *dc_res; 748 const struct dc_type *dc_info; /* adapter info */ 749 device_t dc_miibus; 750 u_int8_t dc_type; 751 u_int8_t dc_pmode; 752 u_int8_t dc_link; 753 u_int8_t dc_cachesize; 754 int dc_romwidth; 755 int dc_pnic_rx_bug_save; 756 unsigned char *dc_pnic_rx_buf; 757 int dc_if_flags; 758 int dc_if_media; 759 u_int32_t dc_flags; 760 u_int32_t dc_txthresh; 761 u_int32_t dc_eaddr[2]; 762 u_int8_t *dc_srom; 763 struct dc_mediainfo *dc_mi; 764 struct dc_list_data dc_ldata; 765 struct dc_chain_data dc_cdata; 766 struct callout dc_stat_ch; 767 struct callout dc_wdog_ch; 768 int dc_wdog_timer; 769 struct mtx dc_mtx; 770#ifdef DEVICE_POLLING 771 int rxcycles; /* ... when polling */ 772#endif 773 int suspended; /* 0 = normal 1 = suspended */ 774}; 775 776 777#define DC_LOCK(_sc) mtx_lock(&(_sc)->dc_mtx) 778#define DC_UNLOCK(_sc) mtx_unlock(&(_sc)->dc_mtx) 779#define DC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->dc_mtx, MA_OWNED) 780 781#define DC_TX_POLL 0x00000001 782#define DC_TX_COALESCE 0x00000002 783#define DC_TX_ADMTEK_WAR 0x00000004 784#define DC_TX_USE_TX_INTR 0x00000008 785#define DC_RX_FILTER_TULIP 0x00000010 786#define DC_TX_INTR_FIRSTFRAG 0x00000020 787#define DC_PNIC_RX_BUG_WAR 0x00000040 788#define DC_TX_FIXED_RING 0x00000080 789#define DC_TX_STORENFWD 0x00000100 790#define DC_REDUCED_MII_POLL 0x00000200 791#define DC_TX_INTR_ALWAYS 0x00000400 792#define DC_21143_NWAY 0x00000800 793#define DC_128BIT_HASH 0x00001000 794#define DC_64BIT_HASH 0x00002000 795#define DC_TULIP_LEDS 0x00004000 796#define DC_TX_ALIGN 0x00010000 /* align mbuf on tx */ 797 798/* 799 * register space access macros 800 */ 801#define CSR_WRITE_4(sc, reg, val) \ 802 bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) 803 804#define CSR_READ_4(sc, reg) \ 805 bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) 806 807#define CSR_BARRIER_4(sc, reg, flags) \ 808 bus_space_barrier(sc->dc_btag, sc->dc_bhandle, reg, 4, flags) 809 810#define DC_TIMEOUT 1000 811 812/* 813 * General constants that are fun to know. 814 */ 815 816/* 817 * DEC PCI vendor ID 818 */ 819#define DC_VENDORID_DEC 0x1011 820 821/* 822 * DEC/Intel 21143 PCI device ID 823 */ 824#define DC_DEVICEID_21143 0x0019 825 826/* 827 * Macronix PCI vendor ID 828 */ 829#define DC_VENDORID_MX 0x10D9 830 831/* 832 * Macronix PMAC device IDs. 833 */ 834#define DC_DEVICEID_98713 0x0512 835#define DC_DEVICEID_987x5 0x0531 836#define DC_DEVICEID_98727 0x0532 837#define DC_DEVICEID_98732 0x0532 838 839/* Macronix PCI revision codes. */ 840#define DC_REVISION_98713 0x00 841#define DC_REVISION_98713A 0x10 842#define DC_REVISION_98715 0x20 843#define DC_REVISION_98715AEC_C 0x25 844#define DC_REVISION_98725 0x30 845 846/* 847 * Compex PCI vendor ID. 848 */ 849#define DC_VENDORID_CP 0x11F6 850 851/* 852 * Compex PMAC PCI device IDs. 853 */ 854#define DC_DEVICEID_98713_CP 0x9881 855 856/* 857 * Lite-On PNIC PCI vendor ID 858 */ 859#define DC_VENDORID_LO 0x11AD 860 861/* 862 * 82c168/82c169 PNIC device IDs. Both chips have the same device 863 * ID but different revisions. Revision 0x10 is the 82c168, and 864 * 0x20 is the 82c169. 865 */ 866#define DC_DEVICEID_82C168 0x0002 867 868#define DC_REVISION_82C168 0x10 869#define DC_REVISION_82C169 0x20 870 871/* 872 * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A 873 * with wake on lan/magic packet support. 874 */ 875#define DC_DEVICEID_82C115 0xc115 876 877/* 878 * Davicom vendor ID. 879 */ 880#define DC_VENDORID_DAVICOM 0x1282 881 882/* 883 * Davicom device IDs. 884 */ 885#define DC_DEVICEID_DM9009 0x9009 886#define DC_DEVICEID_DM9100 0x9100 887#define DC_DEVICEID_DM9102 0x9102 888 889/* 890 * The DM9102A has the same PCI device ID as the DM9102, 891 * but a higher revision code. 892 */ 893#define DC_REVISION_DM9102 0x10 894#define DC_REVISION_DM9102A 0x30 895 896/* 897 * ADMtek vendor ID. 898 */ 899#define DC_VENDORID_ADMTEK 0x1317 900 901/* 902 * ADMtek device IDs. 903 */ 904#define DC_DEVICEID_AL981 0x0981 905#define DC_DEVICEID_AN983 0x0985 906#define DC_DEVICEID_AN985 0x1985 907#define DC_DEVICEID_ADM9511 0x9511 908#define DC_DEVICEID_ADM9513 0x9513 909 910/* 911 * 3COM PCI vendor ID 912 */ 913#define DC_VENDORID_3COM 0x10b7 914 915/* 916 * 3COM OfficeConnect 10/100B (3CSOHO100B-TX) 917 */ 918#define DC_DEVICEID_3CSOHOB 0x9300 919 920/* 921 * ASIX vendor ID. 922 */ 923#define DC_VENDORID_ASIX 0x125B 924 925/* 926 * ASIX device IDs. 927 */ 928#define DC_DEVICEID_AX88140A 0x1400 929 930/* 931 * The ASIX AX88140 and ASIX AX88141 have the same vendor and 932 * device IDs but different revision values. 933 */ 934#define DC_REVISION_88140 0x00 935#define DC_REVISION_88141 0x10 936 937/* 938 * Accton vendor ID. 939 */ 940#define DC_VENDORID_ACCTON 0x1113 941 942/* 943 * Accton device IDs. 944 */ 945#define DC_DEVICEID_EN1217 0x1217 946#define DC_DEVICEID_EN2242 0x1216 947 948/* 949 * Xircom vendor ID 950 */ 951#define DC_VENDORID_XIRCOM 0x115d 952 953/* 954 * Xircom device IDs. 955 */ 956#define DC_DEVICEID_X3201 0x0003 957 958/* 959 * D-Link vendor ID 960 */ 961#define DC_VENDORID_DLINK 0x1186 962 963/* 964 * D-Link device IDs. 965 */ 966#define DC_DEVICEID_DRP32TXD 0x1561 967 968/* 969 * Abocom vendor ID 970 */ 971#define DC_VENDORID_ABOCOM 0x13d1 972 973/* 974 * Abocom device IDs. 975 */ 976#define DC_DEVICEID_FE2500 0xAB02 977#define DC_DEVICEID_FE2500MX 0xab08 978 979/* 980 * Conexant vendor ID. 981 */ 982#define DC_VENDORID_CONEXANT 0x14f1 983 984/* 985 * Conexant device IDs. 986 */ 987#define DC_DEVICEID_RS7112 0x1803 988 989/* 990 * Planex vendor ID 991 */ 992#define DC_VENDORID_PLANEX 0x14ea 993 994/* 995 * Planex device IDs. 996 */ 997#define DC_DEVICEID_FNW3602T 0xab08 998 999/* 1000 * Not sure who this vendor should be, so we'll go with HAWKING until 1001 * I can locate the right one. 1002 */ 1003#define DC_VENDORID_HAWKING 0x17b3 1004 1005/* 1006 * Sure looks like an abocom device ID, but it found on my hawking PN672TX 1007 * card. Use that for now, and upgrade later. 1008 */ 1009#define DC_DEVICEID_HAWKING_PN672TX 0xab08 1010 1011/* 1012 * Microsoft device ID. 1013 */ 1014#define DC_VENDORID_MICROSOFT 0x1414 1015 1016/* 1017 * Supported Microsoft PCI and CardBus NICs. These are really 1018 * ADMtek parts in disguise. 1019 */ 1020 1021#define DC_DEVICEID_MSMN120 0x0001 1022#define DC_DEVICEID_MSMN130 0x0002 1023 1024/* 1025 * Linksys vendor ID. 1026 */ 1027#define DC_VENDORID_LINKSYS 0x1737 1028 1029/* 1030 * Linksys device IDs. 1031 */ 1032#define DC_DEVICEID_PCMPC200_AB08 0xab08 1033#define DC_DEVICEID_PCMPC200_AB09 0xab09 1034 1035#define DC_DEVID(vendor, device) ((device) << 16 | (vendor)) 1036 1037/* 1038 * PCI low memory base and low I/O base register, and 1039 * other PCI registers. 1040 */ 1041 1042#define DC_PCI_CFBIO PCIR_BAR(0) /* Base I/O address */ 1043#define DC_PCI_CFBMA PCIR_BAR(1) /* Base memory address */ 1044#define DC_PCI_CFDD 0x40 /* Device and driver area */ 1045#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ 1046#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ 1047#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ 1048#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ 1049#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ 1050 1051#define DC_21143_PB_REV 0x00000030 1052#define DC_21143_TB_REV 0x00000030 1053#define DC_21143_PC_REV 0x00000030 1054#define DC_21143_TC_REV 0x00000030 1055#define DC_21143_PD_REV 0x00000041 1056#define DC_21143_TD_REV 0x00000041 1057 1058/* Configuration and driver area */ 1059#define DC_CFDD_DRVUSE 0x0000FFFF 1060#define DC_CFDD_SNOOZE_MODE 0x40000000 1061#define DC_CFDD_SLEEP_MODE 0x80000000 1062 1063/* Configuration wake-up command register */ 1064#define DC_CWUC_MUST_BE_ZERO 0x00000001 1065#define DC_CWUC_SECUREON_ENB 0x00000002 1066#define DC_CWUC_FORCE_WUL 0x00000004 1067#define DC_CWUC_BNC_ABILITY 0x00000008 1068#define DC_CWUC_AUI_ABILITY 0x00000010 1069#define DC_CWUC_TP10_ABILITY 0x00000020 1070#define DC_CWUC_MII_ABILITY 0x00000040 1071#define DC_CWUC_SYM_ABILITY 0x00000080 1072#define DC_CWUC_LOCK 0x00000100 1073 1074/* 1075 * SROM nonsense. 1076 */ 1077 1078#define DC_ROM_SIZE(bits) (2 << (bits)) 1079 1080#define DC_IB_CTLRCNT 0x13 1081#define DC_IB_LEAF0_CNUM 0x1A 1082#define DC_IB_LEAF0_OFFSET 0x1B 1083 1084struct dc_info_leaf { 1085 u_int16_t dc_conntype; 1086 u_int8_t dc_blkcnt; 1087 u_int8_t dc_rsvd; 1088 u_int16_t dc_infoblk; 1089}; 1090 1091#define DC_CTYPE_10BT 0x0000 1092#define DC_CTYPE_10BT_NWAY 0x0100 1093#define DC_CTYPE_10BT_FDX 0x0204 1094#define DC_CTYPE_10B2 0x0001 1095#define DC_CTYPE_10B5 0x0002 1096#define DC_CTYPE_100BT 0x0003 1097#define DC_CTYPE_100BT_FDX 0x0205 1098#define DC_CTYPE_100T4 0x0006 1099#define DC_CTYPE_100FX 0x0007 1100#define DC_CTYPE_100FX_FDX 0x0208 1101#define DC_CTYPE_MII_10BT 0x0009 1102#define DC_CTYPE_MII_10BT_FDX 0x020A 1103#define DC_CTYPE_MII_100BT 0x000D 1104#define DC_CTYPE_MII_100BT_FDX 0x020E 1105#define DC_CTYPE_MII_100T4 0x000F 1106#define DC_CTYPE_MII_100FX 0x0010 1107#define DC_CTYPE_MII_100FX_FDX 0x0211 1108#define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 1109#define DC_CTYPE_PUP_AUTOSENSE 0x8800 1110#define DC_CTYPE_NOMEDIA 0xFFFF 1111 1112#define DC_EBLOCK_SIA 0x0002 1113#define DC_EBLOCK_MII 0x0003 1114#define DC_EBLOCK_SYM 0x0004 1115#define DC_EBLOCK_RESET 0x0005 1116#define DC_EBLOCK_PHY_SHUTDOWN 0x0006 1117 1118struct dc_leaf_hdr { 1119 u_int16_t dc_mtype; 1120 u_int8_t dc_mcnt; 1121 u_int8_t dc_rsvd; 1122}; 1123 1124struct dc_eblock_hdr { 1125 u_int8_t dc_len; 1126 u_int8_t dc_type; 1127}; 1128 1129struct dc_eblock_sia { 1130 struct dc_eblock_hdr dc_sia_hdr; 1131 u_int8_t dc_sia_code; 1132 union { 1133 struct dc_sia_ext { /* if (dc_sia_code & DC_SIA_CODE_EXT) */ 1134 u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ 1135 u_int8_t dc_sia_gpio_ctl[2]; 1136 u_int8_t dc_sia_gpio_dat[2]; 1137 } dc_sia_ext; 1138 struct dc_sia_noext { 1139 u_int8_t dc_sia_gpio_ctl[2]; 1140 u_int8_t dc_sia_gpio_dat[2]; 1141 } dc_sia_noext; 1142 } dc_un; 1143}; 1144 1145#define DC_SIA_CODE_10BT 0x00 1146#define DC_SIA_CODE_10B2 0x01 1147#define DC_SIA_CODE_10B5 0x02 1148#define DC_SIA_CODE_10BT_FDX 0x04 1149#define DC_SIA_CODE_EXT 0x40 1150 1151/* 1152 * Note that the first word in the gpr and reset 1153 * sequences is always a control word. 1154 */ 1155struct dc_eblock_mii { 1156 struct dc_eblock_hdr dc_mii_hdr; 1157 u_int8_t dc_mii_phynum; 1158 u_int8_t dc_gpr_len; 1159/* u_int16_t dc_gpr_dat[n]; */ 1160/* u_int8_t dc_reset_len; */ 1161/* u_int16_t dc_reset_dat[n]; */ 1162/* There are other fields after these, but we don't 1163 * care about them since they can be determined by looking 1164 * at the PHY. 1165 */ 1166}; 1167 1168struct dc_eblock_sym { 1169 struct dc_eblock_hdr dc_sym_hdr; 1170 u_int8_t dc_sym_code; 1171 u_int8_t dc_sym_gpio_ctl[2]; 1172 u_int8_t dc_sym_gpio_dat[2]; 1173 u_int8_t dc_sym_cmd[2]; 1174}; 1175 1176#define DC_SYM_CODE_100BT 0x03 1177#define DC_SYM_CODE_100BT_FDX 0x05 1178#define DC_SYM_CODE_100T4 0x06 1179#define DC_SYM_CODE_100FX 0x07 1180#define DC_SYM_CODE_100FX_FDX 0x08 1181 1182struct dc_eblock_reset { 1183 struct dc_eblock_hdr dc_reset_hdr; 1184 u_int8_t dc_reset_len; 1185/* u_int16_t dc_reset_dat[n]; */ 1186}; 1187