1139825Simp/*- 254134Swpaul * Copyright (c) 1997, 1998, 1999 354134Swpaul * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 454134Swpaul * 554134Swpaul * Redistribution and use in source and binary forms, with or without 654134Swpaul * modification, are permitted provided that the following conditions 754134Swpaul * are met: 854134Swpaul * 1. Redistributions of source code must retain the above copyright 954134Swpaul * notice, this list of conditions and the following disclaimer. 1054134Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1154134Swpaul * notice, this list of conditions and the following disclaimer in the 1254134Swpaul * documentation and/or other materials provided with the distribution. 1354134Swpaul * 3. All advertising materials mentioning features or use of this software 1454134Swpaul * must display the following acknowledgement: 1554134Swpaul * This product includes software developed by Bill Paul. 1654134Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1754134Swpaul * may be used to endorse or promote products derived from this software 1854134Swpaul * without specific prior written permission. 1954134Swpaul * 2054134Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2154134Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2254134Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2354134Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2454134Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2554134Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2654134Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2754134Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2854134Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2954134Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3054134Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3154134Swpaul * 3254134Swpaul * $FreeBSD$ 3354134Swpaul */ 3454134Swpaul 3554134Swpaul/* 3654134Swpaul * 21143 and clone common register definitions. 3754134Swpaul */ 3854134Swpaul 39218834Syongari#define DC_BUSCTL 0x00 /* bus control */ 40218834Syongari#define DC_TXSTART 0x08 /* tx start demand */ 41218834Syongari#define DC_RXSTART 0x10 /* rx start demand */ 42218834Syongari#define DC_RXADDR 0x18 /* rx descriptor list start addr */ 43218834Syongari#define DC_TXADDR 0x20 /* tx descriptor list start addr */ 44218834Syongari#define DC_ISR 0x28 /* interrupt status register */ 45218834Syongari#define DC_NETCFG 0x30 /* network config register */ 46218834Syongari#define DC_IMR 0x38 /* interrupt mask */ 47218834Syongari#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ 48218834Syongari#define DC_SIO 0x48 /* MII and ROM/EEPROM access */ 49218834Syongari#define DC_ROM 0x50 /* ROM programming address */ 50218834Syongari#define DC_TIMER 0x58 /* general timer */ 51218834Syongari#define DC_10BTSTAT 0x60 /* SIA status */ 52218834Syongari#define DC_SIARESET 0x68 /* SIA connectivity */ 53218834Syongari#define DC_10BTCTRL 0x70 /* SIA transmit and receive */ 54218834Syongari#define DC_WATCHDOG 0x78 /* SIA and general purpose port */ 55218834Syongari#define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */ 5654134Swpaul 5754134Swpaul/* 5854134Swpaul * There are two general 'types' of MX chips that we need to be 5954134Swpaul * concerned with. One is the original 98713, which has its internal 6054134Swpaul * NWAY support controlled via the MDIO bits in the serial I/O 6154134Swpaul * register. The other is everything else (from the 98713A on up), 6254134Swpaul * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, 6354134Swpaul * just like the 21143. This type setting also governs which of the 6454134Swpaul * 'magic' numbers we write to CSR16. The PNIC II falls into the 6554134Swpaul * 98713A/98715/98715A/98725 category. 6654134Swpaul */ 67218834Syongari#define DC_TYPE_98713 0x1 68218834Syongari#define DC_TYPE_98713A 0x2 69218834Syongari#define DC_TYPE_987x5 0x3 7054134Swpaul 7154134Swpaul/* Other type of supported chips. */ 72218834Syongari#define DC_TYPE_21143 0x4 /* Intel 21143 */ 73218834Syongari#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ 74218834Syongari#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ 75218834Syongari#define DC_TYPE_AN983 0x7 /* ADMtek AN983 Centaur */ 76218834Syongari#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ 77218834Syongari#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ 78218834Syongari#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ 7967314Sjon#define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */ 80218834Syongari#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */ 81226701Syongari#define DC_TYPE_ULI_M5261 0xD /* ALi/ULi M5261 */ 82226701Syongari#define DC_TYPE_ULI_M5263 0xE /* ALi/ULi M5263 */ 8354134Swpaul 84218834Syongari#define DC_IS_MACRONIX(x) \ 8554134Swpaul (x->dc_type == DC_TYPE_98713 || \ 8654134Swpaul x->dc_type == DC_TYPE_98713A || \ 8754134Swpaul x->dc_type == DC_TYPE_987x5) 8854134Swpaul 89218834Syongari#define DC_IS_ADMTEK(x) \ 9054134Swpaul (x->dc_type == DC_TYPE_AL981 || \ 91201430Smbr x->dc_type == DC_TYPE_AN983) 9254134Swpaul 93226701Syongari#define DC_IS_ULI(x) \ 94226701Syongari (x->dc_type == DC_TYPE_ULI_M5261 || \ 95226701Syongari x->dc_type == DC_TYPE_ULI_M5263) 96226701Syongari 97218834Syongari#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) 98218834Syongari#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) 99218834Syongari#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) 100218834Syongari#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN983) 101218834Syongari#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) 102218834Syongari#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) 103218834Syongari#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) 10467314Sjon#define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM) 105218834Syongari#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT) 10654134Swpaul 10754134Swpaul/* MII/symbol mode port types */ 108218834Syongari#define DC_PMODE_MII 0x1 109218834Syongari#define DC_PMODE_SYM 0x2 110218834Syongari#define DC_PMODE_SIA 0x3 11154134Swpaul 11254134Swpaul/* 11354134Swpaul * Bus control bits. 11454134Swpaul */ 115218834Syongari#define DC_BUSCTL_RESET 0x00000001 116218834Syongari#define DC_BUSCTL_ARBITRATION 0x00000002 117218834Syongari#define DC_BUSCTL_SKIPLEN 0x0000007C 118218834Syongari#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 119218834Syongari#define DC_BUSCTL_BURSTLEN 0x00003F00 120218834Syongari#define DC_BUSCTL_CACHEALIGN 0x0000C000 121218834Syongari#define DC_BUSCTL_TXPOLL 0x000E0000 122218834Syongari#define DC_BUSCTL_DBO 0x00100000 123218834Syongari#define DC_BUSCTL_MRME 0x00200000 124218834Syongari#define DC_BUSCTL_MRLE 0x00800000 125218834Syongari#define DC_BUSCTL_MWIE 0x01000000 126218834Syongari#define DC_BUSCTL_ONNOW_ENB 0x04000000 12754134Swpaul 128218834Syongari#define DC_SKIPLEN_1LONG 0x00000004 129218834Syongari#define DC_SKIPLEN_2LONG 0x00000008 130218834Syongari#define DC_SKIPLEN_3LONG 0x00000010 131218834Syongari#define DC_SKIPLEN_4LONG 0x00000020 132218834Syongari#define DC_SKIPLEN_5LONG 0x00000040 13354134Swpaul 134218834Syongari#define DC_CACHEALIGN_NONE 0x00000000 135218834Syongari#define DC_CACHEALIGN_8LONG 0x00004000 136218834Syongari#define DC_CACHEALIGN_16LONG 0x00008000 137218834Syongari#define DC_CACHEALIGN_32LONG 0x0000C000 13854134Swpaul 139218834Syongari#define DC_BURSTLEN_USECA 0x00000000 140218834Syongari#define DC_BURSTLEN_1LONG 0x00000100 141218834Syongari#define DC_BURSTLEN_2LONG 0x00000200 142218834Syongari#define DC_BURSTLEN_4LONG 0x00000400 143218834Syongari#define DC_BURSTLEN_8LONG 0x00000800 144218834Syongari#define DC_BURSTLEN_16LONG 0x00001000 145218834Syongari#define DC_BURSTLEN_32LONG 0x00002000 14654134Swpaul 147218834Syongari#define DC_TXPOLL_OFF 0x00000000 148218834Syongari#define DC_TXPOLL_1 0x00020000 149218834Syongari#define DC_TXPOLL_2 0x00040000 150218834Syongari#define DC_TXPOLL_3 0x00060000 151218834Syongari#define DC_TXPOLL_4 0x00080000 152218834Syongari#define DC_TXPOLL_5 0x000A0000 153218834Syongari#define DC_TXPOLL_6 0x000C0000 154218834Syongari#define DC_TXPOLL_7 0x000E0000 15554134Swpaul 15654134Swpaul/* 15754134Swpaul * Interrupt status bits. 15854134Swpaul */ 159218834Syongari#define DC_ISR_TX_OK 0x00000001 160218834Syongari#define DC_ISR_TX_IDLE 0x00000002 161218834Syongari#define DC_ISR_TX_NOBUF 0x00000004 162218834Syongari#define DC_ISR_TX_JABBERTIMEO 0x00000008 163218834Syongari#define DC_ISR_LINKGOOD 0x00000010 164218834Syongari#define DC_ISR_TX_UNDERRUN 0x00000020 165218834Syongari#define DC_ISR_RX_OK 0x00000040 166218834Syongari#define DC_ISR_RX_NOBUF 0x00000080 167218834Syongari#define DC_ISR_RX_READ 0x00000100 168218834Syongari#define DC_ISR_RX_WATDOGTIMEO 0x00000200 169218834Syongari#define DC_ISR_TX_EARLY 0x00000400 170218834Syongari#define DC_ISR_TIMER_EXPIRED 0x00000800 171218834Syongari#define DC_ISR_LINKFAIL 0x00001000 172218834Syongari#define DC_ISR_BUS_ERR 0x00002000 173218834Syongari#define DC_ISR_RX_EARLY 0x00004000 174218834Syongari#define DC_ISR_ABNORMAL 0x00008000 175218834Syongari#define DC_ISR_NORMAL 0x00010000 176218834Syongari#define DC_ISR_RX_STATE 0x000E0000 177218834Syongari#define DC_ISR_TX_STATE 0x00700000 178218834Syongari#define DC_ISR_BUSERRTYPE 0x03800000 179218834Syongari#define DC_ISR_100MBPSLINK 0x08000000 180218834Syongari#define DC_ISR_MAGICKPACK 0x10000000 18154134Swpaul 182218834Syongari#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 183218834Syongari#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 184218834Syongari#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 185218834Syongari#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 186218834Syongari#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 187218834Syongari#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 188218834Syongari#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 189218834Syongari#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 19054134Swpaul 191182461Smarius#define DC_HAS_BROKEN_RXSTATE(x) \ 192182461Smarius (DC_IS_CENTAUR(x) || DC_IS_CONEXANT(x) || (DC_IS_DAVICOM(x) && \ 193182461Smarius pci_get_revid((x)->dc_dev) >= DC_REVISION_DM9102A)) 194182461Smarius 195218834Syongari#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ 196218834Syongari#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 197218834Syongari#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 198218834Syongari#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 199218834Syongari#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 200218834Syongari#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 201218834Syongari#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 202218834Syongari#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 20354134Swpaul 20454134Swpaul/* 20554134Swpaul * Network config bits. 20654134Swpaul */ 207218834Syongari#define DC_NETCFG_RX_HASHPERF 0x00000001 208218834Syongari#define DC_NETCFG_RX_ON 0x00000002 209218834Syongari#define DC_NETCFG_RX_HASHONLY 0x00000004 210218834Syongari#define DC_NETCFG_RX_BADFRAMES 0x00000008 211218834Syongari#define DC_NETCFG_RX_INVFILT 0x00000010 212218834Syongari#define DC_NETCFG_BACKOFFCNT 0x00000020 213218834Syongari#define DC_NETCFG_RX_PROMISC 0x00000040 214218834Syongari#define DC_NETCFG_RX_ALLMULTI 0x00000080 215218834Syongari#define DC_NETCFG_FULLDUPLEX 0x00000200 216218834Syongari#define DC_NETCFG_LOOPBACK 0x00000C00 217218834Syongari#define DC_NETCFG_FORCECOLL 0x00001000 218218834Syongari#define DC_NETCFG_TX_ON 0x00002000 219218834Syongari#define DC_NETCFG_TX_THRESH 0x0000C000 220218834Syongari#define DC_NETCFG_TX_BACKOFF 0x00020000 221218834Syongari#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ 222218834Syongari#define DC_NETCFG_HEARTBEAT 0x00080000 223218834Syongari#define DC_NETCFG_STORENFWD 0x00200000 224218834Syongari#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ 225218834Syongari#define DC_NETCFG_PCS 0x00800000 226218834Syongari#define DC_NETCFG_SCRAMBLER 0x01000000 227218834Syongari#define DC_NETCFG_NO_RXCRC 0x02000000 228218834Syongari#define DC_NETCFG_RX_ALL 0x40000000 229218834Syongari#define DC_NETCFG_CAPEFFECT 0x80000000 23054134Swpaul 231218834Syongari#define DC_OPMODE_NORM 0x00000000 232218834Syongari#define DC_OPMODE_INTLOOP 0x00000400 233218834Syongari#define DC_OPMODE_EXTLOOP 0x00000800 23454134Swpaul 23572915Swpaul#if 0 236218834Syongari#define DC_TXTHRESH_72BYTES 0x00000000 237218834Syongari#define DC_TXTHRESH_96BYTES 0x00004000 238218834Syongari#define DC_TXTHRESH_128BYTES 0x00008000 239218834Syongari#define DC_TXTHRESH_160BYTES 0x0000C000 24072915Swpaul#endif 24154134Swpaul 242218834Syongari#define DC_TXTHRESH_MIN 0x00000000 243218834Syongari#define DC_TXTHRESH_INC 0x00004000 244218834Syongari#define DC_TXTHRESH_MAX 0x0000C000 24554134Swpaul 24672915Swpaul 24754134Swpaul/* 24854134Swpaul * Interrupt mask bits. 24954134Swpaul */ 250218834Syongari#define DC_IMR_TX_OK 0x00000001 251218834Syongari#define DC_IMR_TX_IDLE 0x00000002 252218834Syongari#define DC_IMR_TX_NOBUF 0x00000004 253218834Syongari#define DC_IMR_TX_JABBERTIMEO 0x00000008 254218834Syongari#define DC_IMR_LINKGOOD 0x00000010 255218834Syongari#define DC_IMR_TX_UNDERRUN 0x00000020 256218834Syongari#define DC_IMR_RX_OK 0x00000040 257218834Syongari#define DC_IMR_RX_NOBUF 0x00000080 258218834Syongari#define DC_IMR_RX_READ 0x00000100 259218834Syongari#define DC_IMR_RX_WATDOGTIMEO 0x00000200 260218834Syongari#define DC_IMR_TX_EARLY 0x00000400 261218834Syongari#define DC_IMR_TIMER_EXPIRED 0x00000800 262218834Syongari#define DC_IMR_LINKFAIL 0x00001000 263218834Syongari#define DC_IMR_BUS_ERR 0x00002000 264218834Syongari#define DC_IMR_RX_EARLY 0x00004000 265218834Syongari#define DC_IMR_ABNORMAL 0x00008000 266218834Syongari#define DC_IMR_NORMAL 0x00010000 267218834Syongari#define DC_IMR_100MBPSLINK 0x08000000 268218834Syongari#define DC_IMR_MAGICKPACK 0x10000000 26954134Swpaul 270218834Syongari#define DC_INTRS \ 27154134Swpaul (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ 27254134Swpaul DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ 27354134Swpaul DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) 27454134Swpaul/* 27554134Swpaul * Serial I/O (EEPROM/ROM) bits. 27654134Swpaul */ 277218834Syongari#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 278218834Syongari#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 279218834Syongari#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 280218834Syongari#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 281218834Syongari#define DC_SIO_ROMDATA4 0x00000010 282218834Syongari#define DC_SIO_ROMDATA5 0x00000020 283218834Syongari#define DC_SIO_ROMDATA6 0x00000040 284218834Syongari#define DC_SIO_ROMDATA7 0x00000080 285218834Syongari#define DC_SIO_EESEL 0x00000800 286218834Syongari#define DC_SIO_ROMSEL 0x00001000 287218834Syongari#define DC_SIO_ROMCTL_WRITE 0x00002000 288218834Syongari#define DC_SIO_ROMCTL_READ 0x00004000 289218834Syongari#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ 290218834Syongari#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ 291218834Syongari#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ 292218834Syongari#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ 29354134Swpaul 294218834Syongari#define DC_EECMD_WRITE 0x140 295218834Syongari#define DC_EECMD_READ 0x180 296218834Syongari#define DC_EECMD_ERASE 0x1c0 29754134Swpaul 298218834Syongari#define DC_EE_NODEADDR_OFFSET 0x70 299218834Syongari#define DC_EE_NODEADDR 10 30054134Swpaul 30154134Swpaul/* 30254134Swpaul * General purpose timer register 30354134Swpaul */ 304218834Syongari#define DC_TIMER_VALUE 0x0000FFFF 305218834Syongari#define DC_TIMER_CONTINUOUS 0x00010000 30654134Swpaul 30754134Swpaul/* 30854134Swpaul * 10baseT status register 30954134Swpaul */ 310218834Syongari#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ 311218834Syongari#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ 312218834Syongari#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ 313218834Syongari#define DC_TSTAT_AUTOPOLARITY 0x00000008 314218834Syongari#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ 315218834Syongari#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ 316218834Syongari#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ 317218834Syongari#define DC_TSTAT_REMFAULT 0x00000800 318218834Syongari#define DC_TSTAT_ANEGSTAT 0x00007000 319218834Syongari#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ 320218834Syongari#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ 32154134Swpaul 322218834Syongari#define DC_ASTAT_DISABLE 0x00000000 323218834Syongari#define DC_ASTAT_TXDISABLE 0x00001000 324218834Syongari#define DC_ASTAT_ABDETECT 0x00002000 325218834Syongari#define DC_ASTAT_ACKDETECT 0x00003000 326218834Syongari#define DC_ASTAT_CMPACKDETECT 0x00004000 327218834Syongari#define DC_ASTAT_AUTONEGCMP 0x00005000 328218834Syongari#define DC_ASTAT_LINKCHECK 0x00006000 32954134Swpaul 33054134Swpaul/* 33154134Swpaul * PHY reset register 33254134Swpaul */ 333218834Syongari#define DC_SIA_RESET 0x00000001 334218834Syongari#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ 33554134Swpaul 33654134Swpaul/* 33754134Swpaul * 10baseT control register 33854134Swpaul */ 339218834Syongari#define DC_TCTL_ENCODER_ENB 0x00000001 340218834Syongari#define DC_TCTL_LOOPBACK 0x00000002 341218834Syongari#define DC_TCTL_DRIVER_ENB 0x00000004 342218834Syongari#define DC_TCTL_LNKPULSE_ENB 0x00000008 343218834Syongari#define DC_TCTL_HALFDUPLEX 0x00000040 344218834Syongari#define DC_TCTL_AUTONEGENBL 0x00000080 345218834Syongari#define DC_TCTL_RX_SQUELCH 0x00000100 346218834Syongari#define DC_TCTL_COLL_SQUELCH 0x00000200 347218834Syongari#define DC_TCTL_COLL_DETECT 0x00000400 348218834Syongari#define DC_TCTL_SQE_ENB 0x00000800 349218834Syongari#define DC_TCTL_LINKTEST 0x00001000 350218834Syongari#define DC_TCTL_AUTOPOLARITY 0x00002000 351218834Syongari#define DC_TCTL_SET_POL_PLUS 0x00004000 352218834Syongari#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ 353218834Syongari#define DC_TCTL_100BTXHALF 0x00010000 354218834Syongari#define DC_TCTL_100BTXFULL 0x00020000 355218834Syongari#define DC_TCTL_100BT4 0x00040000 35654134Swpaul 35754134Swpaul/* 35854134Swpaul * Watchdog timer register 35954134Swpaul */ 360218834Syongari#define DC_WDOG_JABBERDIS 0x00000001 361218834Syongari#define DC_WDOG_HOSTUNJAB 0x00000002 362218834Syongari#define DC_WDOG_JABBERCLK 0x00000004 363218834Syongari#define DC_WDOG_RXWDOGDIS 0x00000010 364218834Syongari#define DC_WDOG_RXWDOGCLK 0x00000020 365218834Syongari#define DC_WDOG_MUSTBEZERO 0x00000100 366218834Syongari#define DC_WDOG_AUIBNC 0x00100000 367218834Syongari#define DC_WDOG_ACTIVITY 0x00200000 368218834Syongari#define DC_WDOG_RX_MATCH 0x00400000 369218834Syongari#define DC_WDOG_LINK 0x00800000 370218834Syongari#define DC_WDOG_CTLWREN 0x08000000 37154134Swpaul 37254134Swpaul/* 37367314Sjon * SIA and General Purpose Port register (X3201) 37467314Sjon */ 375218834Syongari#define DC_SIAGP_RXMATCH 0x40000000 376218834Syongari#define DC_SIAGP_INT1 0x20000000 377218834Syongari#define DC_SIAGP_INT0 0x10000000 378218834Syongari#define DC_SIAGP_WRITE_EN 0x08000000 379218834Syongari#define DC_SIAGP_RXMATCH_EN 0x04000000 380218834Syongari#define DC_SIAGP_INT1_EN 0x02000000 381218834Syongari#define DC_SIAGP_INT0_EN 0x01000000 382218834Syongari#define DC_SIAGP_LED3 0x00800000 383218834Syongari#define DC_SIAGP_LED2 0x00400000 384218834Syongari#define DC_SIAGP_LED1 0x00200000 385218834Syongari#define DC_SIAGP_LED0 0x00100000 386218834Syongari#define DC_SIAGP_MD_GP3_OUTPUT 0x00080000 387218834Syongari#define DC_SIAGP_MD_GP2_OUTPUT 0x00040000 388218834Syongari#define DC_SIAGP_MD_GP1_OUTPUT 0x00020000 389218834Syongari#define DC_SIAGP_MD_GP0_OUTPUT 0x00010000 39067314Sjon 39167314Sjon/* 39254134Swpaul * Size of a setup frame. 39354134Swpaul */ 394218834Syongari#define DC_SFRAME_LEN 192 39554134Swpaul 39654134Swpaul/* 39754134Swpaul * 21x4x TX/RX list structure. 39854134Swpaul */ 39954134Swpaul 40054134Swpaulstruct dc_desc { 401218835Syongari uint32_t dc_status; 402218835Syongari uint32_t dc_ctl; 403218835Syongari uint32_t dc_ptr1; 404218835Syongari uint32_t dc_ptr2; 40554134Swpaul}; 40654134Swpaul 407218834Syongari#define dc_data dc_ptr1 408218834Syongari#define dc_next dc_ptr2 40954134Swpaul 410218834Syongari#define DC_RXSTAT_FIFOOFLOW 0x00000001 411218834Syongari#define DC_RXSTAT_CRCERR 0x00000002 412218834Syongari#define DC_RXSTAT_DRIBBLE 0x00000004 413218834Syongari#define DC_RXSTAT_MIIERE 0x00000008 414218834Syongari#define DC_RXSTAT_WATCHDOG 0x00000010 415218834Syongari#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ 416218834Syongari#define DC_RXSTAT_COLLSEEN 0x00000040 417218834Syongari#define DC_RXSTAT_GIANT 0x00000080 418218834Syongari#define DC_RXSTAT_LASTFRAG 0x00000100 419218834Syongari#define DC_RXSTAT_FIRSTFRAG 0x00000200 420218834Syongari#define DC_RXSTAT_MULTICAST 0x00000400 421218834Syongari#define DC_RXSTAT_RUNT 0x00000800 422218834Syongari#define DC_RXSTAT_RXTYPE 0x00003000 423218834Syongari#define DC_RXSTAT_DE 0x00004000 424218834Syongari#define DC_RXSTAT_RXERR 0x00008000 425218834Syongari#define DC_RXSTAT_RXLEN 0x3FFF0000 426218834Syongari#define DC_RXSTAT_OWN 0x80000000 42754134Swpaul 428218834Syongari#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) 429218834Syongari#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) 43054134Swpaul 431218834Syongari#define DC_RXCTL_BUFLEN1 0x00000FFF 432218834Syongari#define DC_RXCTL_BUFLEN2 0x00FFF000 433218834Syongari#define DC_RXCTL_RLINK 0x01000000 434218834Syongari#define DC_RXCTL_RLAST 0x02000000 43554134Swpaul 436218834Syongari#define DC_TXSTAT_DEFER 0x00000001 437218834Syongari#define DC_TXSTAT_UNDERRUN 0x00000002 438218834Syongari#define DC_TXSTAT_LINKFAIL 0x00000003 439218834Syongari#define DC_TXSTAT_COLLCNT 0x00000078 440218834Syongari#define DC_TXSTAT_SQE 0x00000080 441218834Syongari#define DC_TXSTAT_EXCESSCOLL 0x00000100 442218834Syongari#define DC_TXSTAT_LATECOLL 0x00000200 443218834Syongari#define DC_TXSTAT_NOCARRIER 0x00000400 444218834Syongari#define DC_TXSTAT_CARRLOST 0x00000800 445218834Syongari#define DC_TXSTAT_JABTIMEO 0x00004000 446218834Syongari#define DC_TXSTAT_ERRSUM 0x00008000 447218834Syongari#define DC_TXSTAT_OWN 0x80000000 44854134Swpaul 449218834Syongari#define DC_TXCTL_BUFLEN1 0x000007FF 450218834Syongari#define DC_TXCTL_BUFLEN2 0x003FF800 451218834Syongari#define DC_TXCTL_FILTTYPE0 0x00400000 452218834Syongari#define DC_TXCTL_PAD 0x00800000 453218834Syongari#define DC_TXCTL_TLINK 0x01000000 454218834Syongari#define DC_TXCTL_TLAST 0x02000000 455218834Syongari#define DC_TXCTL_NOCRC 0x04000000 456218834Syongari#define DC_TXCTL_SETUP 0x08000000 457218834Syongari#define DC_TXCTL_FILTTYPE1 0x10000000 458218834Syongari#define DC_TXCTL_FIRSTFRAG 0x20000000 459218834Syongari#define DC_TXCTL_LASTFRAG 0x40000000 460218834Syongari#define DC_TXCTL_FINT 0x80000000 46154134Swpaul 462218834Syongari#define DC_FILTER_PERFECT 0x00000000 463218834Syongari#define DC_FILTER_HASHPERF 0x00400000 464218834Syongari#define DC_FILTER_INVERSE 0x10000000 465218834Syongari#define DC_FILTER_HASHONLY 0x10400000 46654134Swpaul 467218834Syongari#define DC_MAXFRAGS 16 46887902Sluigi#ifdef DEVICE_POLLING 469218834Syongari#define DC_RX_LIST_CNT 192 47087902Sluigi#else 471218834Syongari#define DC_RX_LIST_CNT 64 47287902Sluigi#endif 473218834Syongari#define DC_TX_LIST_CNT 256 474218834Syongari#define DC_TX_LIST_RSVD 5 475218834Syongari#define DC_MIN_FRAMELEN 60 476218834Syongari#define DC_RXLEN 1536 47754134Swpaul 478218834Syongari#define DC_INC(x, y) (x) = (x + 1) % y 47954134Swpaul 480218832Syongari#define DC_LIST_ALIGN (sizeof(struct dc_desc)) 481218832Syongari#define DC_RXBUF_ALIGN 4 482218832Syongari 483117295Smux/* Macros to easily get the DMA address of a descriptor. */ 484218832Syongari#define DC_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF) 485218834Syongari#define DC_RXDESC(sc, i) \ 486218832Syongari (DC_ADDR_LO(sc->dc_ldata.dc_rx_list_paddr + (sizeof(struct dc_desc) * i))) 487218834Syongari#define DC_TXDESC(sc, i) \ 488218832Syongari (DC_ADDR_LO(sc->dc_ldata.dc_tx_list_paddr + (sizeof(struct dc_desc) * i))) 489117295Smux 490117354Smux#if BYTE_ORDER == BIG_ENDIAN 491218834Syongari#define DC_SP_MAC(x) ((x) << 16) 492117354Smux#else 493218834Syongari#define DC_SP_MAC(x) (x) 494117354Smux#endif 495117354Smux 49654134Swpaulstruct dc_list_data { 497218832Syongari struct dc_desc *dc_rx_list; 498218832Syongari bus_addr_t dc_rx_list_paddr; 499218832Syongari struct dc_desc *dc_tx_list; 500218832Syongari bus_addr_t dc_tx_list_paddr; 50154134Swpaul}; 50254134Swpaul 503218832Syongari#define DC_RX_LIST_SZ ((sizeof(struct dc_desc) * DC_RX_LIST_CNT)) 504218832Syongari#define DC_TX_LIST_SZ ((sizeof(struct dc_desc) * DC_TX_LIST_CNT)) 505218832Syongari 50654134Swpaulstruct dc_chain_data { 50754134Swpaul struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; 50854134Swpaul struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; 509117295Smux bus_dmamap_t dc_rx_map[DC_RX_LIST_CNT]; 510117295Smux bus_dmamap_t dc_tx_map[DC_TX_LIST_CNT]; 511218835Syongari uint32_t *dc_sbuf; 512218835Syongari uint8_t dc_pad[DC_MIN_FRAMELEN]; 513218820Syongari int dc_tx_pkts; 514117295Smux int dc_tx_first; 51554134Swpaul int dc_tx_prod; 51654134Swpaul int dc_tx_cons; 51754134Swpaul int dc_tx_cnt; 51854134Swpaul int dc_rx_prod; 51954134Swpaul}; 52054134Swpaul 52166681Swpaulstruct dc_mediainfo { 52266681Swpaul int dc_media; 523218835Syongari uint8_t *dc_gp_ptr; 524218835Syongari uint8_t dc_gp_len; 525218835Syongari uint8_t *dc_reset_ptr; 526218835Syongari uint8_t dc_reset_len; 52766681Swpaul struct dc_mediainfo *dc_next; 52866681Swpaul}; 52966681Swpaul 53066681Swpaul 53154134Swpaulstruct dc_type { 532218835Syongari uint32_t dc_devid; 533218835Syongari uint8_t dc_minrev; 534226995Smarius const char *dc_name; 53554134Swpaul}; 53654134Swpaul 53754134Swpaul/* 53854134Swpaul * Registers specific to clone devices. 53954134Swpaul * This mainly relates to RX filter programming: not all 21x4x clones 54054134Swpaul * use the standard DEC filter programming mechanism. 54154134Swpaul */ 54254134Swpaul 54354134Swpaul/* 544201430Smbr * ADMtek specific registers and constants for the AL981 and AN983. 545201430Smbr * The AN983 doesn't use the magic PHY registers. 54654134Swpaul */ 547218834Syongari#define DC_AL_CR 0x88 /* command register */ 548218834Syongari#define DC_AL_PAR0 0xA4 /* station address */ 549218834Syongari#define DC_AL_PAR1 0xA8 /* station address */ 550218834Syongari#define DC_AL_MAR0 0xAC /* multicast hash filter */ 551218834Syongari#define DC_AL_MAR1 0xB0 /* multicast hash filter */ 552218834Syongari#define DC_AL_BMCR 0xB4 /* built in PHY control */ 553218834Syongari#define DC_AL_BMSR 0xB8 /* built in PHY status */ 554218834Syongari#define DC_AL_VENID 0xBC /* built in PHY ID0 */ 555218834Syongari#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ 556218834Syongari#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ 557218834Syongari#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ 558218834Syongari#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ 55954134Swpaul 560218834Syongari#define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */ 561218834Syongari#define DC_ADMTEK_PHYADDR 0x1 562218834Syongari#define DC_AL_EE_NODEADDR 4 56354134Swpaul/* End of ADMtek specific registers */ 56454134Swpaul 56554134Swpaul/* 56654134Swpaul * ASIX specific registers. 56754134Swpaul */ 568218834Syongari#define DC_AX_FILTIDX 0x68 /* RX filter index */ 569218834Syongari#define DC_AX_FILTDATA 0x70 /* RX filter data */ 57054134Swpaul 57154134Swpaul/* 57254134Swpaul * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). 57354134Swpaul */ 574218834Syongari#define DC_AX_NETCFG_RX_BROAD 0x00000100 57554134Swpaul 57654134Swpaul/* 57754134Swpaul * RX Filter Index Register values 57854134Swpaul */ 579218834Syongari#define DC_AX_FILTIDX_PAR0 0x00000000 580218834Syongari#define DC_AX_FILTIDX_PAR1 0x00000001 581218834Syongari#define DC_AX_FILTIDX_MAR0 0x00000002 582218834Syongari#define DC_AX_FILTIDX_MAR1 0x00000003 58354134Swpaul/* End of ASIX specific registers */ 58454134Swpaul 58554134Swpaul/* 58654134Swpaul * Macronix specific registers. The Macronix chips have a special 58754134Swpaul * register for reading the NWAY status, which we don't use, plus 58854134Swpaul * a magic packet register, which we need to tweak a bit per the 58954134Swpaul * Macronix application notes. 59054134Swpaul */ 591218834Syongari#define DC_MX_MAGICPACKET 0x80 592218834Syongari#define DC_MX_NWAYSTAT 0xA0 59354134Swpaul 59454134Swpaul/* 59554134Swpaul * Magic packet register 59654134Swpaul */ 597218834Syongari#define DC_MX_MPACK_DISABLE 0x00400000 59854134Swpaul 59954134Swpaul/* 60054134Swpaul * NWAY status register. 60154134Swpaul */ 602218834Syongari#define DC_MX_NWAY_10BTHALF 0x08000000 603218834Syongari#define DC_MX_NWAY_10BTFULL 0x10000000 604218834Syongari#define DC_MX_NWAY_100BTHALF 0x20000000 605218834Syongari#define DC_MX_NWAY_100BTFULL 0x40000000 606218834Syongari#define DC_MX_NWAY_100BT4 0x80000000 60754134Swpaul 60854134Swpaul/* 60954134Swpaul * These are magic values that must be written into CSR16 61054134Swpaul * (DC_MX_MAGICPACKET) in order to put the chip into proper 61154134Swpaul * operating mode. The magic numbers are documented in the 61254134Swpaul * Macronix 98715 application notes. 61354134Swpaul */ 614218834Syongari#define DC_MX_MAGIC_98713 0x0F370000 615218834Syongari#define DC_MX_MAGIC_98713A 0x0B3C0000 616218834Syongari#define DC_MX_MAGIC_98715 0x0B3C0000 617218834Syongari#define DC_MX_MAGIC_98725 0x0B3C0000 61854134Swpaul/* End of Macronix specific registers */ 61954134Swpaul 62054134Swpaul/* 62154134Swpaul * PNIC 82c168/82c169 specific registers. 62254134Swpaul * The PNIC has its own special NWAY support, which doesn't work, 62354134Swpaul * and shortcut ways of reading the EEPROM and MII bus. 62454134Swpaul */ 625218834Syongari#define DC_PN_GPIO 0x60 /* general purpose pins control */ 626218834Syongari#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ 627218834Syongari#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ 628218834Syongari#define DC_PN_MII 0xA0 /* MII access register */ 629218834Syongari#define DC_PN_NWAY 0xB8 /* Internal NWAY register */ 63054134Swpaul 63154134Swpaul/* Serial I/O EEPROM register */ 632218834Syongari#define DC_PN_SIOCTL_DATA 0x0000003F 633218834Syongari#define DC_PN_SIOCTL_OPCODE 0x00000300 634218834Syongari#define DC_PN_SIOCTL_BUSY 0x80000000 63554134Swpaul 636218834Syongari#define DC_PN_EEOPCODE_ERASE 0x00000300 637218834Syongari#define DC_PN_EEOPCODE_READ 0x00000600 638218834Syongari#define DC_PN_EEOPCODE_WRITE 0x00000100 63954134Swpaul 64054134Swpaul/* 64154134Swpaul * The first two general purpose pins control speed selection and 64254134Swpaul * 100Mbps loopback on the 82c168 chip. The control bits should always 64354134Swpaul * be set (to make the data pins outputs) and the speed selction and 64454134Swpaul * loopback bits set accordingly when changing media. Physically, this 64554134Swpaul * will set the state of a relay mounted on the card. 64654134Swpaul */ 647218834Syongari#define DC_PN_GPIO_DATA0 0x000000001 648218834Syongari#define DC_PN_GPIO_DATA1 0x000000002 649218834Syongari#define DC_PN_GPIO_DATA2 0x000000004 650218834Syongari#define DC_PN_GPIO_DATA3 0x000000008 651218834Syongari#define DC_PN_GPIO_CTL0 0x000000010 652218834Syongari#define DC_PN_GPIO_CTL1 0x000000020 653218834Syongari#define DC_PN_GPIO_CTL2 0x000000040 654218834Syongari#define DC_PN_GPIO_CTL3 0x000000080 655218834Syongari#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ 656218834Syongari#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ 657218834Syongari#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 658218834Syongari#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 659218834Syongari#define DC_PN_GPIO_SETBIT(sc, r) \ 66054134Swpaul DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) 661218834Syongari#define DC_PN_GPIO_CLRBIT(sc, r) \ 66254134Swpaul { \ 66354134Swpaul DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ 66454134Swpaul DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ 66554134Swpaul } 666218834Syongari 66754134Swpaul/* shortcut MII access register */ 668218834Syongari#define DC_PN_MII_DATA 0x0000FFFF 669218834Syongari#define DC_PN_MII_RESERVER 0x00020000 670218834Syongari#define DC_PN_MII_REGADDR 0x007C0000 671218834Syongari#define DC_PN_MII_PHYADDR 0x0F800000 672218834Syongari#define DC_PN_MII_OPCODE 0x30000000 673218834Syongari#define DC_PN_MII_BUSY 0x80000000 67454134Swpaul 675218834Syongari#define DC_PN_MIIOPCODE_READ 0x60020000 676218834Syongari#define DC_PN_MIIOPCODE_WRITE 0x50020000 67754134Swpaul 67854134Swpaul/* Internal NWAY bits */ 679218834Syongari#define DC_PN_NWAY_RESET 0x00000001 /* reset */ 680218834Syongari#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ 681218834Syongari#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ 682218834Syongari#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ 683218834Syongari#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ 684218834Syongari#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ 685218834Syongari#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ 686218834Syongari#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ 687218834Syongari#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ 688218834Syongari#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ 689218834Syongari#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ 690218834Syongari#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ 691218834Syongari#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ 692218834Syongari#define DC_PN_NWAY_CAP10HDX 0x00002000 693218834Syongari#define DC_PN_NWAY_CAP10FDX 0x00004000 694218834Syongari#define DC_PN_NWAY_CAP100FDX 0x00008000 695218834Syongari#define DC_PN_NWAY_CAP100HDX 0x00010000 696218834Syongari#define DC_PN_NWAY_CAP100T4 0x00020000 697218834Syongari#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ 698218834Syongari#define DC_PN_NWAY_REMFAULT 0x04000000 699218834Syongari#define DC_PN_NWAY_LPAR10HDX 0x08000000 700218834Syongari#define DC_PN_NWAY_LPAR10FDX 0x10000000 701218834Syongari#define DC_PN_NWAY_LPAR100FDX 0x20000000 702218834Syongari#define DC_PN_NWAY_LPAR100HDX 0x40000000 703218834Syongari#define DC_PN_NWAY_LPAR100T4 0x80000000 70454134Swpaul 70554134Swpaul/* End of PNIC specific registers */ 70654134Swpaul 70782978Swpaul/* 70882978Swpaul * CONEXANT specific registers. 70982978Swpaul */ 71082978Swpaul 711218834Syongari#define DC_CONEXANT_PHYADDR 0x1 712218834Syongari#define DC_CONEXANT_EE_NODEADDR 0x19A 71382978Swpaul 71482978Swpaul/* End of CONEXANT specific registers */ 71582978Swpaul 716226701Syongari/* 717226701Syongari * ULi M5263 specific registers. 718226701Syongari */ 719226701Syongari#define DC_ULI_FILTER_NPERF 14 72082978Swpaul 721226701Syongari#define DC_ULI_PHY_DATA_MASK 0x0000FFFF 722226701Syongari#define DC_ULI_PHY_REG_MASK 0x001F0000 723226701Syongari#define DC_ULI_PHY_ADDR_MASK 0x03E00000 724226701Syongari#define DC_ULI_PHY_OP_WRITE 0x04000000 725226701Syongari#define DC_ULI_PHY_OP_READ 0x08000000 726226701Syongari#define DC_ULI_PHY_OP_DONE 0x10000000 727226701Syongari 728226701Syongari#define DC_ULI_PHY_DATA_SHIFT 0 729226701Syongari#define DC_ULI_PHY_REG_SHIFT 16 730226701Syongari#define DC_ULI_PHY_ADDR_SHIFT 21 731226701Syongari 732226701Syongari/* End of ULi M5263 specific registers */ 733226701Syongari 73454134Swpaulstruct dc_softc { 735147256Sbrooks struct ifnet *dc_ifp; /* interface info */ 736162321Sglebius device_t dc_dev; /* device info */ 73754134Swpaul bus_space_handle_t dc_bhandle; /* bus space handle */ 73854134Swpaul bus_space_tag_t dc_btag; /* bus space tag */ 739218832Syongari bus_dma_tag_t dc_ptag; /* parent DMA tag */ 740117295Smux bus_dmamap_t dc_sparemap; 741218832Syongari bus_dma_tag_t dc_rx_ltag; /* tag for RX descriptors */ 742218832Syongari bus_dmamap_t dc_rx_lmap; 743218832Syongari bus_dma_tag_t dc_tx_ltag; /* tag for TX descriptors */ 744218832Syongari bus_dmamap_t dc_tx_lmap; 745117295Smux bus_dma_tag_t dc_stag; /* tag for the setup frame */ 746117295Smux bus_dmamap_t dc_smap; /* map for the setup frame */ 747218832Syongari bus_addr_t dc_saddr; /* DMA address of setup frame */ 748218832Syongari bus_dma_tag_t dc_rx_mtag; /* tag for RX mbufs */ 749218832Syongari bus_dma_tag_t dc_tx_mtag; /* tag for TX mbufs */ 75054134Swpaul void *dc_intrhand; 75154134Swpaul struct resource *dc_irq; 75254134Swpaul struct resource *dc_res; 753177561Smarius const struct dc_type *dc_info; /* adapter info */ 75454134Swpaul device_t dc_miibus; 755218835Syongari uint8_t dc_type; 756218835Syongari uint8_t dc_pmode; 757218835Syongari uint8_t dc_link; 758218835Syongari uint8_t dc_cachesize; 759104599Simp int dc_romwidth; 76054134Swpaul int dc_pnic_rx_bug_save; 76154134Swpaul unsigned char *dc_pnic_rx_buf; 76254134Swpaul int dc_if_flags; 763218835Syongari uint32_t dc_flags; 764218835Syongari uint32_t dc_txthresh; 765218835Syongari uint32_t dc_eaddr[2]; 766218835Syongari uint8_t *dc_srom; 76766681Swpaul struct dc_mediainfo *dc_mi; 768218832Syongari struct dc_list_data dc_ldata; 76954134Swpaul struct dc_chain_data dc_cdata; 77069154Sjlemon struct callout dc_stat_ch; 771164930Smarius struct callout dc_wdog_ch; 772164930Smarius int dc_wdog_timer; 77367087Swpaul struct mtx dc_mtx; 77487902Sluigi#ifdef DEVICE_POLLING 77587902Sluigi int rxcycles; /* ... when polling */ 77687902Sluigi#endif 77796111Siwasaki int suspended; /* 0 = normal 1 = suspended */ 77854134Swpaul}; 77954134Swpaul 78067087Swpaul 78172200Sbmilekic#define DC_LOCK(_sc) mtx_lock(&(_sc)->dc_mtx) 78272200Sbmilekic#define DC_UNLOCK(_sc) mtx_unlock(&(_sc)->dc_mtx) 783122689Ssam#define DC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->dc_mtx, MA_OWNED) 78467087Swpaul 785218834Syongari#define DC_TX_POLL 0x00000001 786218834Syongari#define DC_TX_COALESCE 0x00000002 787218834Syongari#define DC_TX_ADMTEK_WAR 0x00000004 788218834Syongari#define DC_TX_USE_TX_INTR 0x00000008 789218834Syongari#define DC_RX_FILTER_TULIP 0x00000010 790218834Syongari#define DC_TX_INTR_FIRSTFRAG 0x00000020 791218834Syongari#define DC_PNIC_RX_BUG_WAR 0x00000040 792218834Syongari#define DC_TX_FIXED_RING 0x00000080 793218834Syongari#define DC_TX_STORENFWD 0x00000100 794218834Syongari#define DC_REDUCED_MII_POLL 0x00000200 795218834Syongari#define DC_TX_INTR_ALWAYS 0x00000400 796218834Syongari#define DC_21143_NWAY 0x00000800 797218834Syongari#define DC_128BIT_HASH 0x00001000 798218834Syongari#define DC_64BIT_HASH 0x00002000 799218834Syongari#define DC_TULIP_LEDS 0x00004000 800218834Syongari#define DC_TX_ALIGN 0x00010000 /* align mbuf on tx */ 80154134Swpaul 80254134Swpaul/* 80354134Swpaul * register space access macros 80454134Swpaul */ 805218834Syongari#define CSR_WRITE_4(sc, reg, val) \ 80654134Swpaul bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) 80754134Swpaul 808218834Syongari#define CSR_READ_4(sc, reg) \ 80954134Swpaul bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) 81054134Swpaul 811226995Smarius#define CSR_BARRIER_4(sc, reg, flags) \ 812185750Smarius bus_space_barrier(sc->dc_btag, sc->dc_bhandle, reg, 4, flags) 813185750Smarius 814218834Syongari#define DC_TIMEOUT 1000 81554134Swpaul 81654134Swpaul/* 81754134Swpaul * General constants that are fun to know. 81854134Swpaul */ 81954134Swpaul 82054134Swpaul/* 82154134Swpaul * DEC PCI vendor ID 82254134Swpaul */ 823218834Syongari#define DC_VENDORID_DEC 0x1011 82454134Swpaul 82554134Swpaul/* 82654134Swpaul * DEC/Intel 21143 PCI device ID 82754134Swpaul */ 828218834Syongari#define DC_DEVICEID_21143 0x0019 82954134Swpaul 83054134Swpaul/* 83154134Swpaul * Macronix PCI vendor ID 83254134Swpaul */ 83354134Swpaul#define DC_VENDORID_MX 0x10D9 83454134Swpaul 83554134Swpaul/* 83654134Swpaul * Macronix PMAC device IDs. 83754134Swpaul */ 838218834Syongari#define DC_DEVICEID_98713 0x0512 839218834Syongari#define DC_DEVICEID_987x5 0x0531 840218834Syongari#define DC_DEVICEID_98727 0x0532 841218834Syongari#define DC_DEVICEID_98732 0x0532 84254134Swpaul 84354134Swpaul/* Macronix PCI revision codes. */ 844218834Syongari#define DC_REVISION_98713 0x00 845218834Syongari#define DC_REVISION_98713A 0x10 846218834Syongari#define DC_REVISION_98715 0x20 847218834Syongari#define DC_REVISION_98715AEC_C 0x25 848218834Syongari#define DC_REVISION_98725 0x30 84954134Swpaul 85054134Swpaul/* 85154134Swpaul * Compex PCI vendor ID. 85254134Swpaul */ 853218834Syongari#define DC_VENDORID_CP 0x11F6 85454134Swpaul 85554134Swpaul/* 85654134Swpaul * Compex PMAC PCI device IDs. 85754134Swpaul */ 858218834Syongari#define DC_DEVICEID_98713_CP 0x9881 85954134Swpaul 86054134Swpaul/* 86154134Swpaul * Lite-On PNIC PCI vendor ID 86254134Swpaul */ 863218834Syongari#define DC_VENDORID_LO 0x11AD 86454134Swpaul 86554134Swpaul/* 86654134Swpaul * 82c168/82c169 PNIC device IDs. Both chips have the same device 86754134Swpaul * ID but different revisions. Revision 0x10 is the 82c168, and 86854134Swpaul * 0x20 is the 82c169. 86954134Swpaul */ 870218834Syongari#define DC_DEVICEID_82C168 0x0002 87154134Swpaul 872218834Syongari#define DC_REVISION_82C168 0x10 873218834Syongari#define DC_REVISION_82C169 0x20 87454134Swpaul 87554134Swpaul/* 87654134Swpaul * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A 87754134Swpaul * with wake on lan/magic packet support. 87854134Swpaul */ 879218834Syongari#define DC_DEVICEID_82C115 0xc115 88054134Swpaul 88154134Swpaul/* 88254134Swpaul * Davicom vendor ID. 88354134Swpaul */ 884218834Syongari#define DC_VENDORID_DAVICOM 0x1282 88554134Swpaul 88654134Swpaul/* 88754134Swpaul * Davicom device IDs. 88854134Swpaul */ 889218834Syongari#define DC_DEVICEID_DM9009 0x9009 890218834Syongari#define DC_DEVICEID_DM9100 0x9100 891218834Syongari#define DC_DEVICEID_DM9102 0x9102 89254134Swpaul 89354134Swpaul/* 89456295Swpaul * The DM9102A has the same PCI device ID as the DM9102, 89556295Swpaul * but a higher revision code. 89656295Swpaul */ 897218834Syongari#define DC_REVISION_DM9102 0x10 898218834Syongari#define DC_REVISION_DM9102A 0x30 89956295Swpaul 90056295Swpaul/* 90154134Swpaul * ADMtek vendor ID. 90254134Swpaul */ 903218834Syongari#define DC_VENDORID_ADMTEK 0x1317 90454134Swpaul 90554134Swpaul/* 90654134Swpaul * ADMtek device IDs. 90754134Swpaul */ 908218834Syongari#define DC_DEVICEID_AL981 0x0981 909218834Syongari#define DC_DEVICEID_AN983 0x0985 910218834Syongari#define DC_DEVICEID_AN985 0x1985 911218834Syongari#define DC_DEVICEID_ADM9511 0x9511 912218834Syongari#define DC_DEVICEID_ADM9513 0x9513 91354134Swpaul 91454134Swpaul/* 915114957Smbr * 3COM PCI vendor ID 916114957Smbr */ 917218834Syongari#define DC_VENDORID_3COM 0x10b7 918114957Smbr 919114957Smbr/* 920114957Smbr * 3COM OfficeConnect 10/100B (3CSOHO100B-TX) 921114957Smbr */ 922218834Syongari#define DC_DEVICEID_3CSOHOB 0x9300 923114957Smbr 924114957Smbr/* 92554134Swpaul * ASIX vendor ID. 92654134Swpaul */ 927218834Syongari#define DC_VENDORID_ASIX 0x125B 92854134Swpaul 92954134Swpaul/* 93054134Swpaul * ASIX device IDs. 93154134Swpaul */ 932218834Syongari#define DC_DEVICEID_AX88140A 0x1400 93354134Swpaul 93454134Swpaul/* 93554134Swpaul * The ASIX AX88140 and ASIX AX88141 have the same vendor and 93654134Swpaul * device IDs but different revision values. 93754134Swpaul */ 938218834Syongari#define DC_REVISION_88140 0x00 939218834Syongari#define DC_REVISION_88141 0x10 94054134Swpaul 94154134Swpaul/* 94261545Sasmodai * Accton vendor ID. 94361545Sasmodai */ 944218834Syongari#define DC_VENDORID_ACCTON 0x1113 94561545Sasmodai 94661545Sasmodai/* 94761545Sasmodai * Accton device IDs. 94861545Sasmodai */ 949218834Syongari#define DC_DEVICEID_EN1217 0x1217 95068725Swpaul#define DC_DEVICEID_EN2242 0x1216 95161545Sasmodai 95261545Sasmodai/* 95367314Sjon * Xircom vendor ID 95467314Sjon */ 95567314Sjon#define DC_VENDORID_XIRCOM 0x115d 95667314Sjon 95767314Sjon/* 95867314Sjon * Xircom device IDs. 95967314Sjon */ 96067314Sjon#define DC_DEVICEID_X3201 0x0003 96167314Sjon 96267771Swpaul/* 963156785Sjhb * D-Link vendor ID 964156785Sjhb */ 965156785Sjhb#define DC_VENDORID_DLINK 0x1186 966156785Sjhb 967156785Sjhb/* 968156785Sjhb * D-Link device IDs. 969156785Sjhb */ 970156785Sjhb#define DC_DEVICEID_DRP32TXD 0x1561 971156785Sjhb 972156785Sjhb/* 97367771Swpaul * Abocom vendor ID 97467771Swpaul */ 975218834Syongari#define DC_VENDORID_ABOCOM 0x13d1 97667314Sjon 97767314Sjon/* 97867771Swpaul * Abocom device IDs. 97967771Swpaul */ 980218834Syongari#define DC_DEVICEID_FE2500 0xAB02 981218834Syongari#define DC_DEVICEID_FE2500MX 0xab08 98267771Swpaul 98367771Swpaul/* 98482978Swpaul * Conexant vendor ID. 98582978Swpaul */ 986218834Syongari#define DC_VENDORID_CONEXANT 0x14f1 98782978Swpaul 98882978Swpaul/* 98982978Swpaul * Conexant device IDs. 99082978Swpaul */ 991218834Syongari#define DC_DEVICEID_RS7112 0x1803 99282978Swpaul 99382978Swpaul/* 994113669Ssanpei * Planex vendor ID 995113669Ssanpei */ 996218834Syongari#define DC_VENDORID_PLANEX 0x14ea 997113669Ssanpei 998113669Ssanpei/* 999113669Ssanpei * Planex device IDs. 1000113669Ssanpei */ 1001218834Syongari#define DC_DEVICEID_FNW3602T 0xab08 1002113669Ssanpei 1003113669Ssanpei/* 1004109048Simp * Not sure who this vendor should be, so we'll go with HAWKING until 1005109048Simp * I can locate the right one. 1006109048Simp */ 1007218834Syongari#define DC_VENDORID_HAWKING 0x17b3 1008109048Simp 1009109048Simp/* 1010109048Simp * Sure looks like an abocom device ID, but it found on my hawking PN672TX 1011109048Simp * card. Use that for now, and upgrade later. 1012109048Simp */ 1013218834Syongari#define DC_DEVICEID_HAWKING_PN672TX 0xab08 1014109048Simp 1015109048Simp/* 1016117386Swpaul * Microsoft device ID. 1017117386Swpaul */ 1018218834Syongari#define DC_VENDORID_MICROSOFT 0x1414 1019117386Swpaul 1020117386Swpaul/* 1021201451Simp * Supported Microsoft PCI and CardBus NICs. These are really 1022117386Swpaul * ADMtek parts in disguise. 1023117386Swpaul */ 1024117386Swpaul 1025218834Syongari#define DC_DEVICEID_MSMN120 0x0001 1026218834Syongari#define DC_DEVICEID_MSMN130 0x0002 1027117386Swpaul 1028159372Sglebius/* 1029159372Sglebius * Linksys vendor ID. 1030159372Sglebius */ 1031218834Syongari#define DC_VENDORID_LINKSYS 0x1737 1032159372Sglebius 1033159372Sglebius/* 1034159372Sglebius * Linksys device IDs. 1035159372Sglebius */ 1036218834Syongari#define DC_DEVICEID_PCMPC200_AB08 0xab08 1037218834Syongari#define DC_DEVICEID_PCMPC200_AB09 0xab09 1038159372Sglebius 1039226701Syongari/* 1040226701Syongari * ULi vendor ID. 1041226701Syongari */ 1042226701Syongari#define DC_VENDORID_ULI 0x10b9 1043226701Syongari 1044226701Syongari/* 1045226701Syongari * ULi device IDs. 1046226701Syongari */ 1047226701Syongari#define DC_DEVICEID_M5261 0x5261 1048226701Syongari#define DC_DEVICEID_M5263 0x5263 1049226701Syongari 1050159202Sjhb#define DC_DEVID(vendor, device) ((device) << 16 | (vendor)) 1051159202Sjhb 1052117386Swpaul/* 105354134Swpaul * PCI low memory base and low I/O base register, and 105454134Swpaul * other PCI registers. 105554134Swpaul */ 105654134Swpaul 1057218834Syongari#define DC_PCI_CFBIO PCIR_BAR(0) /* Base I/O address */ 1058218834Syongari#define DC_PCI_CFBMA PCIR_BAR(1) /* Base memory address */ 1059218834Syongari#define DC_PCI_CFDD 0x40 /* Device and driver area */ 1060218834Syongari#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ 1061218834Syongari#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ 1062218834Syongari#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ 1063218834Syongari#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ 1064218834Syongari#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ 106554134Swpaul 1066218834Syongari#define DC_21143_PB_REV 0x00000030 1067218834Syongari#define DC_21143_TB_REV 0x00000030 1068218834Syongari#define DC_21143_PC_REV 0x00000030 1069218834Syongari#define DC_21143_TC_REV 0x00000030 1070218834Syongari#define DC_21143_PD_REV 0x00000041 1071218834Syongari#define DC_21143_TD_REV 0x00000041 107254134Swpaul 107354134Swpaul/* Configuration and driver area */ 1074218834Syongari#define DC_CFDD_DRVUSE 0x0000FFFF 1075218834Syongari#define DC_CFDD_SNOOZE_MODE 0x40000000 1076218834Syongari#define DC_CFDD_SLEEP_MODE 0x80000000 107754134Swpaul 107854134Swpaul/* Configuration wake-up command register */ 1079218834Syongari#define DC_CWUC_MUST_BE_ZERO 0x00000001 1080218834Syongari#define DC_CWUC_SECUREON_ENB 0x00000002 1081218834Syongari#define DC_CWUC_FORCE_WUL 0x00000004 1082218834Syongari#define DC_CWUC_BNC_ABILITY 0x00000008 1083218834Syongari#define DC_CWUC_AUI_ABILITY 0x00000010 1084218834Syongari#define DC_CWUC_TP10_ABILITY 0x00000020 1085218834Syongari#define DC_CWUC_MII_ABILITY 0x00000040 1086218834Syongari#define DC_CWUC_SYM_ABILITY 0x00000080 1087218834Syongari#define DC_CWUC_LOCK 0x00000100 108854134Swpaul 108966681Swpaul/* 109066681Swpaul * SROM nonsense. 109166681Swpaul */ 109266681Swpaul 1093218786Syongari#define DC_ROM_SIZE(bits) (2 << (bits)) 1094218786Syongari 1095218834Syongari#define DC_IB_CTLRCNT 0x13 1096218834Syongari#define DC_IB_LEAF0_CNUM 0x1A 1097218834Syongari#define DC_IB_LEAF0_OFFSET 0x1B 109866681Swpaul 109966681Swpaulstruct dc_info_leaf { 1100218835Syongari uint16_t dc_conntype; 1101218835Syongari uint8_t dc_blkcnt; 1102218835Syongari uint8_t dc_rsvd; 1103218835Syongari uint16_t dc_infoblk; 110466681Swpaul}; 110566681Swpaul 1106218834Syongari#define DC_CTYPE_10BT 0x0000 1107218834Syongari#define DC_CTYPE_10BT_NWAY 0x0100 1108218834Syongari#define DC_CTYPE_10BT_FDX 0x0204 1109218834Syongari#define DC_CTYPE_10B2 0x0001 1110218834Syongari#define DC_CTYPE_10B5 0x0002 1111218834Syongari#define DC_CTYPE_100BT 0x0003 1112218834Syongari#define DC_CTYPE_100BT_FDX 0x0205 1113218834Syongari#define DC_CTYPE_100T4 0x0006 1114218834Syongari#define DC_CTYPE_100FX 0x0007 1115218834Syongari#define DC_CTYPE_100FX_FDX 0x0208 1116218834Syongari#define DC_CTYPE_MII_10BT 0x0009 1117218834Syongari#define DC_CTYPE_MII_10BT_FDX 0x020A 1118218834Syongari#define DC_CTYPE_MII_100BT 0x000D 1119218834Syongari#define DC_CTYPE_MII_100BT_FDX 0x020E 1120218834Syongari#define DC_CTYPE_MII_100T4 0x000F 1121218834Syongari#define DC_CTYPE_MII_100FX 0x0010 1122218834Syongari#define DC_CTYPE_MII_100FX_FDX 0x0211 1123218834Syongari#define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 1124218834Syongari#define DC_CTYPE_PUP_AUTOSENSE 0x8800 1125218834Syongari#define DC_CTYPE_NOMEDIA 0xFFFF 112666681Swpaul 1127218834Syongari#define DC_EBLOCK_SIA 0x0002 1128218834Syongari#define DC_EBLOCK_MII 0x0003 1129218834Syongari#define DC_EBLOCK_SYM 0x0004 1130218834Syongari#define DC_EBLOCK_RESET 0x0005 1131218834Syongari#define DC_EBLOCK_PHY_SHUTDOWN 0x0006 113266681Swpaul 113366681Swpaulstruct dc_leaf_hdr { 1134218835Syongari uint16_t dc_mtype; 1135218835Syongari uint8_t dc_mcnt; 1136218835Syongari uint8_t dc_rsvd; 113766681Swpaul}; 113866681Swpaul 113966681Swpaulstruct dc_eblock_hdr { 1140218835Syongari uint8_t dc_len; 1141218835Syongari uint8_t dc_type; 114266681Swpaul}; 114366681Swpaul 114466681Swpaulstruct dc_eblock_sia { 114566681Swpaul struct dc_eblock_hdr dc_sia_hdr; 1146218835Syongari uint8_t dc_sia_code; 1147120822Smbr union { 1148120822Smbr struct dc_sia_ext { /* if (dc_sia_code & DC_SIA_CODE_EXT) */ 1149218835Syongari uint8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ 1150218835Syongari uint8_t dc_sia_gpio_ctl[2]; 1151218835Syongari uint8_t dc_sia_gpio_dat[2]; 1152120822Smbr } dc_sia_ext; 1153120822Smbr struct dc_sia_noext { 1154218835Syongari uint8_t dc_sia_gpio_ctl[2]; 1155218835Syongari uint8_t dc_sia_gpio_dat[2]; 1156120822Smbr } dc_sia_noext; 1157120822Smbr } dc_un; 115866681Swpaul}; 115966681Swpaul 1160218834Syongari#define DC_SIA_CODE_10BT 0x00 1161218834Syongari#define DC_SIA_CODE_10B2 0x01 1162218834Syongari#define DC_SIA_CODE_10B5 0x02 1163218834Syongari#define DC_SIA_CODE_10BT_FDX 0x04 1164218834Syongari#define DC_SIA_CODE_EXT 0x40 116566681Swpaul 116666681Swpaul/* 116766681Swpaul * Note that the first word in the gpr and reset 116866681Swpaul * sequences is always a control word. 116966681Swpaul */ 117066681Swpaulstruct dc_eblock_mii { 117166681Swpaul struct dc_eblock_hdr dc_mii_hdr; 1172218835Syongari uint8_t dc_mii_phynum; 1173218835Syongari uint8_t dc_gpr_len; 1174218835Syongari/* uint16_t dc_gpr_dat[n]; */ 1175218835Syongari/* uint8_t dc_reset_len; */ 1176218835Syongari/* uint16_t dc_reset_dat[n]; */ 117766681Swpaul/* There are other fields after these, but we don't 117866681Swpaul * care about them since they can be determined by looking 117966681Swpaul * at the PHY. 118066681Swpaul */ 118166681Swpaul}; 118266681Swpaul 118366681Swpaulstruct dc_eblock_sym { 118466681Swpaul struct dc_eblock_hdr dc_sym_hdr; 1185218835Syongari uint8_t dc_sym_code; 1186218835Syongari uint8_t dc_sym_gpio_ctl[2]; 1187218835Syongari uint8_t dc_sym_gpio_dat[2]; 1188218835Syongari uint8_t dc_sym_cmd[2]; 118966681Swpaul}; 119066681Swpaul 1191218834Syongari#define DC_SYM_CODE_100BT 0x03 1192218834Syongari#define DC_SYM_CODE_100BT_FDX 0x05 1193218834Syongari#define DC_SYM_CODE_100T4 0x06 1194218834Syongari#define DC_SYM_CODE_100FX 0x07 1195218834Syongari#define DC_SYM_CODE_100FX_FDX 0x08 119666681Swpaul 119766681Swpaulstruct dc_eblock_reset { 119866681Swpaul struct dc_eblock_hdr dc_reset_hdr; 1199218835Syongari uint8_t dc_reset_len; 1200218835Syongari/* uint16_t dc_reset_dat[n]; */ 120166681Swpaul}; 1202