t4_hw.h revision 239344 
1/*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/cxgbe/common/t4_hw.h 239344 2012-08-17 00:49:29Z np $
27 *
28 */
29
30#ifndef __T4_HW_H
31#define __T4_HW_H
32
33#include "osdep.h"
34
35enum {
36	NCHAN          = 4,     /* # of HW channels */
37	MAX_MTU        = 9600,  /* max MAC MTU, excluding header + FCS */
38	EEPROMSIZE     = 17408, /* Serial EEPROM physical size */
39	EEPROMVSIZE    = 32768, /* Serial EEPROM virtual address space size */
40	EEPROMPFSIZE   = 1024,  /* EEPROM writable area size for PFn, n>0 */
41	RSS_NENTRIES   = 2048,  /* # of entries in RSS mapping table */
42	TCB_SIZE       = 128,   /* TCB size */
43	NMTUS          = 16,    /* size of MTU table */
44	NCCTRL_WIN     = 32,    /* # of congestion control windows */
45	NTX_SCHED      = 8,     /* # of HW Tx scheduling queues */
46	PM_NSTATS      = 5,     /* # of PM stats */
47	MBOX_LEN       = 64,    /* mailbox size in bytes */
48	TRACE_LEN      = 112,   /* length of trace data and mask */
49	FILTER_OPT_LEN = 36,    /* filter tuple width for optional components */
50	NWOL_PAT       = 8,     /* # of WoL patterns */
51	WOL_PAT_LEN    = 128,   /* length of WoL patterns */
52};
53
54enum {
55	CIM_NUM_IBQ    = 6,     /* # of CIM IBQs */
56	CIM_NUM_OBQ    = 6,     /* # of CIM OBQs */
57	CIMLA_SIZE     = 2048,  /* # of 32-bit words in CIM LA */
58	CIM_PIFLA_SIZE = 64,    /* # of 192-bit words in CIM PIF LA */
59	CIM_MALA_SIZE  = 64,    /* # of 160-bit words in CIM MA LA */
60	CIM_IBQ_SIZE   = 128,   /* # of 128-bit words in a CIM IBQ */
61	TPLA_SIZE      = 128,   /* # of 64-bit words in TP LA */
62	ULPRX_LA_SIZE  = 512,   /* # of 256-bit words in ULP_RX LA */
63};
64
65enum {
66	SF_PAGE_SIZE = 256,           /* serial flash page size */
67	SF_SEC_SIZE = 64 * 1024,      /* serial flash sector size */
68};
69
70/* SGE context types */
71enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM };
72
73enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
74
75enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV };    /* mailbox owners */
76
77enum {
78	SGE_MAX_WR_LEN = 512,     /* max WR size in bytes */
79	SGE_CTXT_SIZE = 24,       /* size of SGE context */
80	SGE_NTIMERS = 6,          /* # of interrupt holdoff timer values */
81	SGE_NCOUNTERS = 4,        /* # of interrupt packet counter values */
82};
83
84struct sge_qstat {                /* data written to SGE queue status entries */
85	volatile __be32 qid;
86	volatile __be16 cidx;
87	volatile __be16 pidx;
88};
89
90#define S_QSTAT_PIDX    0
91#define M_QSTAT_PIDX    0xffff
92#define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX)
93
94#define S_QSTAT_CIDX    16
95#define M_QSTAT_CIDX    0xffff
96#define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX)
97
98/*
99 * Structure for last 128 bits of response descriptors
100 */
101struct rsp_ctrl {
102	__be32 hdrbuflen_pidx;
103	__be32 pldbuflen_qid;
104	union {
105		u8 type_gen;
106		__be64 last_flit;
107	} u;
108};
109
110#define S_RSPD_NEWBUF    31
111#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
112#define F_RSPD_NEWBUF    V_RSPD_NEWBUF(1U)
113
114#define S_RSPD_LEN    0
115#define M_RSPD_LEN    0x7fffffff
116#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
117#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
118
119#define S_RSPD_QID    S_RSPD_LEN
120#define M_RSPD_QID    M_RSPD_LEN
121#define V_RSPD_QID(x) V_RSPD_LEN(x)
122#define G_RSPD_QID(x) G_RSPD_LEN(x)
123
124#define S_RSPD_GEN    7
125#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
126#define F_RSPD_GEN    V_RSPD_GEN(1U)
127
128#define S_RSPD_QOVFL    6
129#define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL)
130#define F_RSPD_QOVFL    V_RSPD_QOVFL(1U)
131
132#define S_RSPD_TYPE    4
133#define M_RSPD_TYPE    0x3
134#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
135#define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
136
137/* Rx queue interrupt deferral fields: counter enable and timer index */
138#define S_QINTR_CNT_EN    0
139#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
140#define F_QINTR_CNT_EN    V_QINTR_CNT_EN(1U)
141
142#define S_QINTR_TIMER_IDX    1
143#define M_QINTR_TIMER_IDX    0x7
144#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
145#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
146
147/* # of pages a pagepod can hold without needing another pagepod */
148#define PPOD_PAGES 4U
149
150struct pagepod {
151	__be64 vld_tid_pgsz_tag_color;
152	__be64 len_offset;
153	__be64 rsvd;
154	__be64 addr[PPOD_PAGES + 1];
155};
156
157#define S_PPOD_COLOR    0
158#define M_PPOD_COLOR    0x3F
159#define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR)
160
161#define S_PPOD_TAG    6
162#define M_PPOD_TAG    0xFFFFFF
163#define V_PPOD_TAG(x) ((x) << S_PPOD_TAG)
164#define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG)
165
166#define S_PPOD_PGSZ    30
167#define M_PPOD_PGSZ    0x3
168#define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ)
169#define G_PPOD_PGSZ(x) (((x) >> S_PPOD_PGSZ) & M_PPOD_PGSZ)
170
171#define S_PPOD_TID    32
172#define M_PPOD_TID    0xFFFFFF
173#define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID)
174
175#define S_PPOD_VALID    56
176#define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID)
177#define F_PPOD_VALID    V_PPOD_VALID(1ULL)
178
179#define S_PPOD_LEN    32
180#define M_PPOD_LEN    0xFFFFFFFF
181#define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN)
182
183#define S_PPOD_OFST    0
184#define M_PPOD_OFST    0xFFFFFFFF
185#define V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
186
187/*
188 * Flash layout.
189 */
190#define FLASH_START(start)	((start) * SF_SEC_SIZE)
191#define FLASH_MAX_SIZE(nsecs)	((nsecs) * SF_SEC_SIZE)
192
193enum {
194	/*
195	 * Various Expansion-ROM boot images, etc.
196	 */
197	FLASH_EXP_ROM_START_SEC = 0,
198	FLASH_EXP_ROM_NSECS = 6,
199	FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
200	FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
201
202	/*
203	 * iSCSI Boot Firmware Table (iBFT) and other driver-related
204	 * parameters ...
205	 */
206	FLASH_IBFT_START_SEC = 6,
207	FLASH_IBFT_NSECS = 1,
208	FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
209	FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
210
211	/*
212	 * Boot configuration data.
213	 */
214	FLASH_BOOTCFG_START_SEC = 7,
215	FLASH_BOOTCFG_NSECS = 1,
216	FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
217	FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
218
219	/*
220	 * Location of firmware image in FLASH.
221	 */
222	FLASH_FW_START_SEC = 8,
223	FLASH_FW_NSECS = 8,
224	FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
225	FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
226
227	/*
228	 * iSCSI persistent/crash information.
229	 */
230	FLASH_ISCSI_CRASH_START_SEC = 29,
231	FLASH_ISCSI_CRASH_NSECS = 1,
232	FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
233	FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
234
235	/*
236	 * FCoE persistent/crash information.
237	 */
238	FLASH_FCOE_CRASH_START_SEC = 30,
239	FLASH_FCOE_CRASH_NSECS = 1,
240	FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
241	FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
242
243	/*
244	 * Location of Firmware Configuration File in FLASH.  Since the FPGA
245	 * "FLASH" is smaller we need to store the Configuration File in a
246	 * different location -- which will overlap the end of the firmware
247	 * image if firmware ever gets that large ...
248	 */
249	FLASH_CFG_START_SEC = 31,
250	FLASH_CFG_NSECS = 1,
251	FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
252	FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
253
254	FLASH_FPGA_CFG_START_SEC = 15,
255	FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
256
257	/*
258	 * Sectors 32-63 are reserved for FLASH failover.
259	 */
260};
261
262#undef FLASH_START
263#undef FLASH_MAX_SIZE
264
265#endif /* __T4_HW_H */
266