1218792Snp/*- 2218792Snp * Copyright (c) 2011 Chelsio Communications, Inc. 3218792Snp * All rights reserved. 4218792Snp * 5218792Snp * Redistribution and use in source and binary forms, with or without 6218792Snp * modification, are permitted provided that the following conditions 7218792Snp * are met: 8218792Snp * 1. Redistributions of source code must retain the above copyright 9218792Snp * notice, this list of conditions and the following disclaimer. 10218792Snp * 2. Redistributions in binary form must reproduce the above copyright 11218792Snp * notice, this list of conditions and the following disclaimer in the 12218792Snp * documentation and/or other materials provided with the distribution. 13218792Snp * 14218792Snp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15218792Snp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16218792Snp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17218792Snp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18218792Snp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19218792Snp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20218792Snp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21218792Snp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22218792Snp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23218792Snp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24218792Snp * SUCH DAMAGE. 25218792Snp * 26218792Snp * $FreeBSD$ 27218792Snp * 28218792Snp */ 29218792Snp 30218792Snp#ifndef __T4_HW_H 31218792Snp#define __T4_HW_H 32218792Snp 33218792Snp#include "osdep.h" 34218792Snp 35218792Snpenum { 36248925Snp NCHAN = 4, /* # of HW channels */ 37248925Snp MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ 38248925Snp EEPROMSIZE = 17408, /* Serial EEPROM physical size */ 39248925Snp EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ 40248925Snp EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ 41248925Snp RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ 42248925Snp TCB_SIZE = 128, /* TCB size */ 43248925Snp NMTUS = 16, /* size of MTU table */ 44248925Snp NCCTRL_WIN = 32, /* # of congestion control windows */ 45248925Snp NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 46248925Snp PM_NSTATS = 5, /* # of PM stats */ 47248925Snp MBOX_LEN = 64, /* mailbox size in bytes */ 48253691Snp NTRACE = 4, /* # of tracing filters */ 49248925Snp TRACE_LEN = 112, /* length of trace data and mask */ 50248925Snp FILTER_OPT_LEN = 36, /* filter tuple width of optional components */ 51248925Snp NWOL_PAT = 8, /* # of WoL patterns */ 52248925Snp WOL_PAT_LEN = 128, /* length of WoL patterns */ 53248925Snp UDBS_SEG_SIZE = 128, /* Segment size of BAR2 doorbells */ 54248925Snp UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */ 55248925Snp UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */ 56248925Snp UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */ 57218792Snp}; 58218792Snp 59218792Snpenum { 60218792Snp CIM_NUM_IBQ = 6, /* # of CIM IBQs */ 61218792Snp CIM_NUM_OBQ = 6, /* # of CIM OBQs */ 62248925Snp CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */ 63218792Snp CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */ 64218792Snp CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */ 65218792Snp CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */ 66218792Snp CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */ 67247122Snp CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */ 68218792Snp TPLA_SIZE = 128, /* # of 64-bit words in TP LA */ 69218792Snp ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */ 70218792Snp}; 71218792Snp 72218792Snpenum { 73218792Snp SF_PAGE_SIZE = 256, /* serial flash page size */ 74218792Snp SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ 75218792Snp}; 76218792Snp 77218792Snp/* SGE context types */ 78218792Snpenum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM }; 79218792Snp 80218792Snpenum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */ 81218792Snp 82218792Snpenum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */ 83218792Snp 84218792Snpenum { 85218792Snp SGE_MAX_WR_LEN = 512, /* max WR size in bytes */ 86218792Snp SGE_CTXT_SIZE = 24, /* size of SGE context */ 87218792Snp SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ 88218792Snp SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ 89248925Snp SGE_MAX_IQ_SIZE = 65520, 90218792Snp}; 91218792Snp 92218792Snpstruct sge_qstat { /* data written to SGE queue status entries */ 93218792Snp volatile __be32 qid; 94218792Snp volatile __be16 cidx; 95218792Snp volatile __be16 pidx; 96218792Snp}; 97218792Snp 98218792Snp#define S_QSTAT_PIDX 0 99218792Snp#define M_QSTAT_PIDX 0xffff 100218792Snp#define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX) 101218792Snp 102218792Snp#define S_QSTAT_CIDX 16 103218792Snp#define M_QSTAT_CIDX 0xffff 104218792Snp#define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX) 105218792Snp 106218792Snp/* 107218792Snp * Structure for last 128 bits of response descriptors 108218792Snp */ 109218792Snpstruct rsp_ctrl { 110218792Snp __be32 hdrbuflen_pidx; 111218792Snp __be32 pldbuflen_qid; 112218792Snp union { 113218792Snp u8 type_gen; 114218792Snp __be64 last_flit; 115218792Snp } u; 116218792Snp}; 117218792Snp 118218792Snp#define S_RSPD_NEWBUF 31 119218792Snp#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF) 120218792Snp#define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U) 121218792Snp 122218792Snp#define S_RSPD_LEN 0 123218792Snp#define M_RSPD_LEN 0x7fffffff 124218792Snp#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN) 125218792Snp#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN) 126218792Snp 127218792Snp#define S_RSPD_QID S_RSPD_LEN 128218792Snp#define M_RSPD_QID M_RSPD_LEN 129218792Snp#define V_RSPD_QID(x) V_RSPD_LEN(x) 130218792Snp#define G_RSPD_QID(x) G_RSPD_LEN(x) 131218792Snp 132218792Snp#define S_RSPD_GEN 7 133218792Snp#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN) 134218792Snp#define F_RSPD_GEN V_RSPD_GEN(1U) 135218792Snp 136218792Snp#define S_RSPD_QOVFL 6 137218792Snp#define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL) 138218792Snp#define F_RSPD_QOVFL V_RSPD_QOVFL(1U) 139218792Snp 140218792Snp#define S_RSPD_TYPE 4 141218792Snp#define M_RSPD_TYPE 0x3 142218792Snp#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE) 143218792Snp#define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE) 144218792Snp 145218792Snp/* Rx queue interrupt deferral fields: counter enable and timer index */ 146218792Snp#define S_QINTR_CNT_EN 0 147218792Snp#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN) 148218792Snp#define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U) 149218792Snp 150218792Snp#define S_QINTR_TIMER_IDX 1 151218792Snp#define M_QINTR_TIMER_IDX 0x7 152218792Snp#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX) 153218792Snp#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX) 154218792Snp 155218792Snp/* # of pages a pagepod can hold without needing another pagepod */ 156218792Snp#define PPOD_PAGES 4U 157218792Snp 158218792Snpstruct pagepod { 159218792Snp __be64 vld_tid_pgsz_tag_color; 160218792Snp __be64 len_offset; 161218792Snp __be64 rsvd; 162218792Snp __be64 addr[PPOD_PAGES + 1]; 163218792Snp}; 164218792Snp 165218792Snp#define S_PPOD_COLOR 0 166218792Snp#define M_PPOD_COLOR 0x3F 167218792Snp#define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR) 168218792Snp 169218792Snp#define S_PPOD_TAG 6 170218792Snp#define M_PPOD_TAG 0xFFFFFF 171218792Snp#define V_PPOD_TAG(x) ((x) << S_PPOD_TAG) 172239344Snp#define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG) 173218792Snp 174218792Snp#define S_PPOD_PGSZ 30 175218792Snp#define M_PPOD_PGSZ 0x3 176218792Snp#define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ) 177239344Snp#define G_PPOD_PGSZ(x) (((x) >> S_PPOD_PGSZ) & M_PPOD_PGSZ) 178218792Snp 179218792Snp#define S_PPOD_TID 32 180218792Snp#define M_PPOD_TID 0xFFFFFF 181218792Snp#define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID) 182218792Snp 183218792Snp#define S_PPOD_VALID 56 184218792Snp#define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID) 185218792Snp#define F_PPOD_VALID V_PPOD_VALID(1ULL) 186218792Snp 187218792Snp#define S_PPOD_LEN 32 188218792Snp#define M_PPOD_LEN 0xFFFFFFFF 189218792Snp#define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN) 190218792Snp 191218792Snp#define S_PPOD_OFST 0 192218792Snp#define M_PPOD_OFST 0xFFFFFFFF 193218792Snp#define V_PPOD_OFST(x) ((x) << S_PPOD_OFST) 194218792Snp 195228561Snp/* 196228561Snp * Flash layout. 197228561Snp */ 198228561Snp#define FLASH_START(start) ((start) * SF_SEC_SIZE) 199228561Snp#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE) 200228561Snp 201228561Snpenum { 202228561Snp /* 203228561Snp * Various Expansion-ROM boot images, etc. 204228561Snp */ 205228561Snp FLASH_EXP_ROM_START_SEC = 0, 206228561Snp FLASH_EXP_ROM_NSECS = 6, 207228561Snp FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC), 208228561Snp FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS), 209228561Snp 210228561Snp /* 211228561Snp * iSCSI Boot Firmware Table (iBFT) and other driver-related 212228561Snp * parameters ... 213228561Snp */ 214228561Snp FLASH_IBFT_START_SEC = 6, 215228561Snp FLASH_IBFT_NSECS = 1, 216228561Snp FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC), 217228561Snp FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS), 218228561Snp 219228561Snp /* 220228561Snp * Boot configuration data. 221228561Snp */ 222228561Snp FLASH_BOOTCFG_START_SEC = 7, 223228561Snp FLASH_BOOTCFG_NSECS = 1, 224228561Snp FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC), 225228561Snp FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS), 226228561Snp 227228561Snp /* 228228561Snp * Location of firmware image in FLASH. 229228561Snp */ 230228561Snp FLASH_FW_START_SEC = 8, 231248925Snp FLASH_FW_NSECS = 16, 232228561Snp FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), 233228561Snp FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), 234252661Snp 235228561Snp /* 236252661Snp * Location of bootstrap firmware image in FLASH. 237252661Snp */ 238252661Snp FLASH_FWBOOTSTRAP_START_SEC = 27, 239252661Snp FLASH_FWBOOTSTRAP_NSECS = 1, 240252661Snp FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC), 241252661Snp FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS), 242252661Snp 243252661Snp /* 244228561Snp * iSCSI persistent/crash information. 245228561Snp */ 246228561Snp FLASH_ISCSI_CRASH_START_SEC = 29, 247228561Snp FLASH_ISCSI_CRASH_NSECS = 1, 248228561Snp FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC), 249228561Snp FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS), 250228561Snp 251228561Snp /* 252228561Snp * FCoE persistent/crash information. 253228561Snp */ 254228561Snp FLASH_FCOE_CRASH_START_SEC = 30, 255228561Snp FLASH_FCOE_CRASH_NSECS = 1, 256228561Snp FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC), 257228561Snp FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS), 258228561Snp 259228561Snp /* 260252661Snp * Location of Firmware Configuration File in FLASH. 261228561Snp */ 262228561Snp FLASH_CFG_START_SEC = 31, 263228561Snp FLASH_CFG_NSECS = 1, 264228561Snp FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC), 265228561Snp FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS), 266228561Snp 267228561Snp /* 268228561Snp * Sectors 32-63 are reserved for FLASH failover. 269228561Snp */ 270228561Snp}; 271228561Snp 272228561Snp#undef FLASH_START 273228561Snp#undef FLASH_MAX_SIZE 274228561Snp 275218792Snp#endif /* __T4_HW_H */ 276