1167514Skmacy/************************************************************************** 2167514Skmacy 3189643SgnnCopyright (c) 2007-2009 Chelsio Inc. 4167514SkmacyAll rights reserved. 5167514Skmacy 6167514SkmacyRedistribution and use in source and binary forms, with or without 7167514Skmacymodification, are permitted provided that the following conditions are met: 8167514Skmacy 9167514Skmacy 1. Redistributions of source code must retain the above copyright notice, 10167514Skmacy this list of conditions and the following disclaimer. 11167514Skmacy 12170076Skmacy 2. Neither the name of the Chelsio Corporation nor the names of its 13167514Skmacy contributors may be used to endorse or promote products derived from 14167514Skmacy this software without specific prior written permission. 15167514Skmacy 16167514SkmacyTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17167514SkmacyAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18167514SkmacyIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19167514SkmacyARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20167514SkmacyLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21167514SkmacyCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22167514SkmacySUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23167514SkmacyINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24167514SkmacyCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25167514SkmacyARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26167514SkmacyPOSSIBILITY OF SUCH DAMAGE. 27167514Skmacy 28167514Skmacy$FreeBSD$ 29167514Skmacy 30167514Skmacy***************************************************************************/ 31167514Skmacy#ifndef T3_CPL_H 32167514Skmacy#define T3_CPL_H 33167514Skmacy 34167514Skmacyenum CPL_opcode { 35167514Skmacy CPL_PASS_OPEN_REQ = 0x1, 36167514Skmacy CPL_PASS_ACCEPT_RPL = 0x2, 37167514Skmacy CPL_ACT_OPEN_REQ = 0x3, 38167514Skmacy CPL_SET_TCB = 0x4, 39167514Skmacy CPL_SET_TCB_FIELD = 0x5, 40167514Skmacy CPL_GET_TCB = 0x6, 41167514Skmacy CPL_PCMD = 0x7, 42167514Skmacy CPL_CLOSE_CON_REQ = 0x8, 43167514Skmacy CPL_CLOSE_LISTSRV_REQ = 0x9, 44167514Skmacy CPL_ABORT_REQ = 0xA, 45167514Skmacy CPL_ABORT_RPL = 0xB, 46167514Skmacy CPL_TX_DATA = 0xC, 47167514Skmacy CPL_RX_DATA_ACK = 0xD, 48167514Skmacy CPL_TX_PKT = 0xE, 49167514Skmacy CPL_RTE_DELETE_REQ = 0xF, 50167514Skmacy CPL_RTE_WRITE_REQ = 0x10, 51167514Skmacy CPL_RTE_READ_REQ = 0x11, 52167514Skmacy CPL_L2T_WRITE_REQ = 0x12, 53167514Skmacy CPL_L2T_READ_REQ = 0x13, 54167514Skmacy CPL_SMT_WRITE_REQ = 0x14, 55167514Skmacy CPL_SMT_READ_REQ = 0x15, 56167514Skmacy CPL_TX_PKT_LSO = 0x16, 57167514Skmacy CPL_PCMD_READ = 0x17, 58167514Skmacy CPL_BARRIER = 0x18, 59167514Skmacy CPL_TID_RELEASE = 0x1A, 60167514Skmacy 61167514Skmacy CPL_CLOSE_LISTSRV_RPL = 0x20, 62167514Skmacy CPL_ERROR = 0x21, 63167514Skmacy CPL_GET_TCB_RPL = 0x22, 64167514Skmacy CPL_L2T_WRITE_RPL = 0x23, 65167514Skmacy CPL_PCMD_READ_RPL = 0x24, 66167514Skmacy CPL_PCMD_RPL = 0x25, 67167514Skmacy CPL_PEER_CLOSE = 0x26, 68167514Skmacy CPL_RTE_DELETE_RPL = 0x27, 69167514Skmacy CPL_RTE_WRITE_RPL = 0x28, 70167514Skmacy CPL_RX_DDP_COMPLETE = 0x29, 71167514Skmacy CPL_RX_PHYS_ADDR = 0x2A, 72167514Skmacy CPL_RX_PKT = 0x2B, 73167514Skmacy CPL_RX_URG_NOTIFY = 0x2C, 74167514Skmacy CPL_SET_TCB_RPL = 0x2D, 75167514Skmacy CPL_SMT_WRITE_RPL = 0x2E, 76167514Skmacy CPL_TX_DATA_ACK = 0x2F, 77167514Skmacy 78167514Skmacy CPL_ABORT_REQ_RSS = 0x30, 79167514Skmacy CPL_ABORT_RPL_RSS = 0x31, 80167514Skmacy CPL_CLOSE_CON_RPL = 0x32, 81167514Skmacy CPL_ISCSI_HDR = 0x33, 82167514Skmacy CPL_L2T_READ_RPL = 0x34, 83167514Skmacy CPL_RDMA_CQE = 0x35, 84167514Skmacy CPL_RDMA_CQE_READ_RSP = 0x36, 85167514Skmacy CPL_RDMA_CQE_ERR = 0x37, 86167514Skmacy CPL_RTE_READ_RPL = 0x38, 87167514Skmacy CPL_RX_DATA = 0x39, 88167514Skmacy 89167514Skmacy CPL_ACT_OPEN_RPL = 0x40, 90167514Skmacy CPL_PASS_OPEN_RPL = 0x41, 91167514Skmacy CPL_RX_DATA_DDP = 0x42, 92167514Skmacy CPL_SMT_READ_RPL = 0x43, 93167514Skmacy 94167514Skmacy CPL_ACT_ESTABLISH = 0x50, 95167514Skmacy CPL_PASS_ESTABLISH = 0x51, 96167514Skmacy 97167514Skmacy CPL_PASS_ACCEPT_REQ = 0x70, 98167514Skmacy 99167514Skmacy CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */ 100167514Skmacy 101167514Skmacy CPL_TX_DMA_ACK = 0xA0, 102167514Skmacy CPL_RDMA_READ_REQ = 0xA1, 103167514Skmacy CPL_RDMA_TERMINATE = 0xA2, 104167514Skmacy CPL_TRACE_PKT = 0xA3, 105167514Skmacy CPL_RDMA_EC_STATUS = 0xA5, 106180583Skmacy CPL_SGE_EC_CR_RETURN = 0xA6, 107167514Skmacy 108167514Skmacy NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 109167514Skmacy}; 110167514Skmacy 111167514Skmacyenum CPL_error { 112167514Skmacy CPL_ERR_NONE = 0, 113167514Skmacy CPL_ERR_TCAM_PARITY = 1, 114167514Skmacy CPL_ERR_TCAM_FULL = 3, 115167514Skmacy CPL_ERR_CONN_RESET = 20, 116167514Skmacy CPL_ERR_CONN_EXIST = 22, 117167514Skmacy CPL_ERR_ARP_MISS = 23, 118167514Skmacy CPL_ERR_BAD_SYN = 24, 119167514Skmacy CPL_ERR_CONN_TIMEDOUT = 30, 120167514Skmacy CPL_ERR_XMIT_TIMEDOUT = 31, 121167514Skmacy CPL_ERR_PERSIST_TIMEDOUT = 32, 122167514Skmacy CPL_ERR_FINWAIT2_TIMEDOUT = 33, 123167514Skmacy CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 124167514Skmacy CPL_ERR_RTX_NEG_ADVICE = 35, 125167514Skmacy CPL_ERR_PERSIST_NEG_ADVICE = 36, 126167514Skmacy CPL_ERR_ABORT_FAILED = 42, 127167514Skmacy CPL_ERR_GENERAL = 99 128167514Skmacy}; 129167514Skmacy 130167514Skmacyenum { 131167514Skmacy CPL_CONN_POLICY_AUTO = 0, 132167514Skmacy CPL_CONN_POLICY_ASK = 1, 133171471Skmacy CPL_CONN_POLICY_FILTER = 2, 134167514Skmacy CPL_CONN_POLICY_DENY = 3 135167514Skmacy}; 136167514Skmacy 137167514Skmacyenum { 138167514Skmacy ULP_MODE_NONE = 0, 139167514Skmacy ULP_MODE_TCP_DDP = 1, 140167514Skmacy ULP_MODE_ISCSI = 2, 141167514Skmacy ULP_MODE_RDMA = 4, 142167514Skmacy ULP_MODE_TCPDDP = 5 143167514Skmacy}; 144167514Skmacy 145167514Skmacyenum { 146167514Skmacy ULP_CRC_HEADER = 1 << 0, 147167514Skmacy ULP_CRC_DATA = 1 << 1 148167514Skmacy}; 149167514Skmacy 150167514Skmacyenum { 151167514Skmacy CPL_PASS_OPEN_ACCEPT, 152180583Skmacy CPL_PASS_OPEN_REJECT, 153180583Skmacy CPL_PASS_OPEN_ACCEPT_TNL 154167514Skmacy}; 155167514Skmacy 156167514Skmacyenum { 157167514Skmacy CPL_ABORT_SEND_RST = 0, 158167514Skmacy CPL_ABORT_NO_RST, 159167514Skmacy CPL_ABORT_POST_CLOSE_REQ = 2 160167514Skmacy}; 161167514Skmacy 162167514Skmacyenum { /* TX_PKT_LSO ethernet types */ 163167514Skmacy CPL_ETH_II, 164167514Skmacy CPL_ETH_II_VLAN, 165167514Skmacy CPL_ETH_802_3, 166167514Skmacy CPL_ETH_802_3_VLAN 167167514Skmacy}; 168167514Skmacy 169167514Skmacyenum { /* TCP congestion control algorithms */ 170167514Skmacy CONG_ALG_RENO, 171167514Skmacy CONG_ALG_TAHOE, 172167514Skmacy CONG_ALG_NEWRENO, 173167514Skmacy CONG_ALG_HIGHSPEED 174167514Skmacy}; 175167514Skmacy 176181614Skmacyenum { /* RSS hash type */ 177167514Skmacy RSS_HASH_NONE = 0, 178176472Skmacy RSS_HASH_2_TUPLE = 1, 179176472Skmacy RSS_HASH_4_TUPLE = 2, 180176472Skmacy RSS_HASH_TCPV6 = 3 181167514Skmacy}; 182167514Skmacy 183167514Skmacyunion opcode_tid { 184167514Skmacy __be32 opcode_tid; 185167514Skmacy __u8 opcode; 186167514Skmacy}; 187167514Skmacy 188167514Skmacy#define S_OPCODE 24 189167514Skmacy#define V_OPCODE(x) ((x) << S_OPCODE) 190167514Skmacy#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) 191167514Skmacy#define G_TID(x) ((x) & 0xFFFFFF) 192167514Skmacy 193167514Skmacy/* tid is assumed to be 24-bits */ 194167514Skmacy#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid)) 195167514Skmacy 196167514Skmacy#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 197167514Skmacy 198167514Skmacy/* extract the TID from a CPL command */ 199167514Skmacy#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 200167514Skmacy 201167514Skmacystruct tcp_options { 202167514Skmacy __be16 mss; 203167514Skmacy __u8 wsf; 204167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 205167514Skmacy __u8 :5; 206167514Skmacy __u8 ecn:1; 207167514Skmacy __u8 sack:1; 208167514Skmacy __u8 tstamp:1; 209167514Skmacy#else 210167514Skmacy __u8 tstamp:1; 211167514Skmacy __u8 sack:1; 212167514Skmacy __u8 ecn:1; 213167514Skmacy __u8 :5; 214167514Skmacy#endif 215167514Skmacy}; 216167514Skmacy 217167514Skmacystruct rss_header { 218167514Skmacy __u8 opcode; 219167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 220167514Skmacy __u8 cpu_idx:6; 221167514Skmacy __u8 hash_type:2; 222167514Skmacy#else 223167514Skmacy __u8 hash_type:2; 224167514Skmacy __u8 cpu_idx:6; 225167514Skmacy#endif 226167514Skmacy __be16 cq_idx; 227167514Skmacy __be32 rss_hash_val; 228167514Skmacy}; 229167514Skmacy 230181614Skmacy#define S_HASHTYPE 22 231181614Skmacy#define M_HASHTYPE 0x3 232181614Skmacy#define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 233181614Skmacy 234181614Skmacy#define S_QNUM 0 235181614Skmacy#define M_QNUM 0xFFFF 236181614Skmacy#define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 237181614Skmacy 238167514Skmacy#ifndef CHELSIO_FW 239167514Skmacystruct work_request_hdr { 240194521Skmacy union { 241194521Skmacy struct { 242194521Skmacy __be32 wr_hi; 243194521Skmacy __be32 wr_lo; 244194521Skmacy } ilp32; 245194521Skmacy struct { 246194521Skmacy __be64 wr_hilo; 247194521Skmacy } lp64; 248194521Skmacy } u; 249167514Skmacy}; 250167514Skmacy 251194521Skmacy#define wrh_hi u.ilp32.wr_hi 252194521Skmacy#define wrh_lo u.ilp32.wr_lo 253194521Skmacy#define wrh_hilo u.lp64.wr_hilo 254194521Skmacy 255167514Skmacy/* wr_hi fields */ 256167514Skmacy#define S_WR_SGE_CREDITS 0 257167514Skmacy#define M_WR_SGE_CREDITS 0xFF 258167514Skmacy#define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS) 259167514Skmacy#define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS) 260167514Skmacy 261167514Skmacy#define S_WR_SGLSFLT 8 262167514Skmacy#define M_WR_SGLSFLT 0xFF 263167514Skmacy#define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT) 264167514Skmacy#define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT) 265167514Skmacy 266167514Skmacy#define S_WR_BCNTLFLT 16 267167514Skmacy#define M_WR_BCNTLFLT 0xF 268167514Skmacy#define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT) 269167514Skmacy#define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT) 270167514Skmacy 271181614Skmacy/* 272181614Skmacy * Applicable to BYPASS WRs only: the uP will add a CPL_BARRIER before 273169978Skmacy * and after the BYPASS WR if the ATOMIC bit is set. 274169978Skmacy */ 275171471Skmacy#define S_WR_ATOMIC 16 276171471Skmacy#define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC) 277171471Skmacy#define F_WR_ATOMIC V_WR_ATOMIC(1U) 278169978Skmacy 279181614Skmacy/* 280181614Skmacy * Applicable to BYPASS WRs only: the uP will flush buffered non abort 281169978Skmacy * related WRs. 282169978Skmacy */ 283171471Skmacy#define S_WR_FLUSH 17 284171471Skmacy#define V_WR_FLUSH(x) ((x) << S_WR_FLUSH) 285171471Skmacy#define F_WR_FLUSH V_WR_FLUSH(1U) 286169978Skmacy 287189643Sgnn#define S_WR_CHN 18 288189643Sgnn#define V_WR_CHN(x) ((x) << S_WR_CHN) 289189643Sgnn#define F_WR_CHN V_WR_CHN(1U) 290189643Sgnn 291189643Sgnn#define S_WR_CHN_VLD 19 292189643Sgnn#define V_WR_CHN_VLD(x) ((x) << S_WR_CHN_VLD) 293189643Sgnn#define F_WR_CHN_VLD V_WR_CHN_VLD(1U) 294189643Sgnn 295167514Skmacy#define S_WR_DATATYPE 20 296167514Skmacy#define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE) 297167514Skmacy#define F_WR_DATATYPE V_WR_DATATYPE(1U) 298167514Skmacy 299167514Skmacy#define S_WR_COMPL 21 300167514Skmacy#define V_WR_COMPL(x) ((x) << S_WR_COMPL) 301167514Skmacy#define F_WR_COMPL V_WR_COMPL(1U) 302167514Skmacy 303167514Skmacy#define S_WR_EOP 22 304167514Skmacy#define V_WR_EOP(x) ((x) << S_WR_EOP) 305167514Skmacy#define F_WR_EOP V_WR_EOP(1U) 306167514Skmacy 307167514Skmacy#define S_WR_SOP 23 308167514Skmacy#define V_WR_SOP(x) ((x) << S_WR_SOP) 309167514Skmacy#define F_WR_SOP V_WR_SOP(1U) 310167514Skmacy 311167514Skmacy#define S_WR_OP 24 312167514Skmacy#define M_WR_OP 0xFF 313167514Skmacy#define V_WR_OP(x) ((x) << S_WR_OP) 314167514Skmacy#define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 315167514Skmacy 316167514Skmacy/* wr_lo fields */ 317167514Skmacy#define S_WR_LEN 0 318167514Skmacy#define M_WR_LEN 0xFF 319167514Skmacy#define V_WR_LEN(x) ((x) << S_WR_LEN) 320167514Skmacy#define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN) 321167514Skmacy 322167514Skmacy#define S_WR_TID 8 323167514Skmacy#define M_WR_TID 0xFFFFF 324167514Skmacy#define V_WR_TID(x) ((x) << S_WR_TID) 325167514Skmacy#define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID) 326167514Skmacy 327167514Skmacy#define S_WR_CR_FLUSH 30 328167514Skmacy#define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH) 329167514Skmacy#define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U) 330167514Skmacy 331167514Skmacy#define S_WR_GEN 31 332167514Skmacy#define V_WR_GEN(x) ((x) << S_WR_GEN) 333167514Skmacy#define F_WR_GEN V_WR_GEN(1U) 334175200Skmacy#define G_WR_GEN(x) ((x) >> S_WR_GEN) 335167514Skmacy 336167514Skmacy# define WR_HDR struct work_request_hdr wr 337167514Skmacy# define RSS_HDR 338167514Skmacy#else 339167514Skmacy# define WR_HDR 340167514Skmacy# define RSS_HDR struct rss_header rss_hdr; 341167514Skmacy#endif 342167514Skmacy 343167514Skmacy/* option 0 lower-half fields */ 344167514Skmacy#define S_CPL_STATUS 0 345167514Skmacy#define M_CPL_STATUS 0xFF 346167514Skmacy#define V_CPL_STATUS(x) ((x) << S_CPL_STATUS) 347167514Skmacy#define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS) 348167514Skmacy 349167514Skmacy#define S_INJECT_TIMER 6 350167514Skmacy#define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 351167514Skmacy#define F_INJECT_TIMER V_INJECT_TIMER(1U) 352167514Skmacy 353167514Skmacy#define S_NO_OFFLOAD 7 354167514Skmacy#define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD) 355167514Skmacy#define F_NO_OFFLOAD V_NO_OFFLOAD(1U) 356167514Skmacy 357167514Skmacy#define S_ULP_MODE 8 358167514Skmacy#define M_ULP_MODE 0xF 359167514Skmacy#define V_ULP_MODE(x) ((x) << S_ULP_MODE) 360167514Skmacy#define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 361167514Skmacy 362167514Skmacy#define S_RCV_BUFSIZ 12 363167514Skmacy#define M_RCV_BUFSIZ 0x3FFF 364167514Skmacy#define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 365167514Skmacy#define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 366167514Skmacy 367167514Skmacy#define S_TOS 26 368167514Skmacy#define M_TOS 0x3F 369167514Skmacy#define V_TOS(x) ((x) << S_TOS) 370167514Skmacy#define G_TOS(x) (((x) >> S_TOS) & M_TOS) 371167514Skmacy 372167514Skmacy/* option 0 upper-half fields */ 373167514Skmacy#define S_DELACK 0 374167514Skmacy#define V_DELACK(x) ((x) << S_DELACK) 375167514Skmacy#define F_DELACK V_DELACK(1U) 376167514Skmacy 377167514Skmacy#define S_NO_CONG 1 378167514Skmacy#define V_NO_CONG(x) ((x) << S_NO_CONG) 379167514Skmacy#define F_NO_CONG V_NO_CONG(1U) 380167514Skmacy 381167514Skmacy#define S_SRC_MAC_SEL 2 382167514Skmacy#define M_SRC_MAC_SEL 0x3 383167514Skmacy#define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL) 384167514Skmacy#define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL) 385167514Skmacy 386167514Skmacy#define S_L2T_IDX 4 387167514Skmacy#define M_L2T_IDX 0x7FF 388167514Skmacy#define V_L2T_IDX(x) ((x) << S_L2T_IDX) 389167514Skmacy#define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 390167514Skmacy 391167514Skmacy#define S_TX_CHANNEL 15 392167514Skmacy#define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL) 393167514Skmacy#define F_TX_CHANNEL V_TX_CHANNEL(1U) 394167514Skmacy 395167514Skmacy#define S_TCAM_BYPASS 16 396167514Skmacy#define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS) 397167514Skmacy#define F_TCAM_BYPASS V_TCAM_BYPASS(1U) 398167514Skmacy 399167514Skmacy#define S_NAGLE 17 400167514Skmacy#define V_NAGLE(x) ((x) << S_NAGLE) 401167514Skmacy#define F_NAGLE V_NAGLE(1U) 402167514Skmacy 403167514Skmacy#define S_WND_SCALE 18 404167514Skmacy#define M_WND_SCALE 0xF 405167514Skmacy#define V_WND_SCALE(x) ((x) << S_WND_SCALE) 406167514Skmacy#define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 407167514Skmacy 408167514Skmacy#define S_KEEP_ALIVE 22 409167514Skmacy#define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE) 410167514Skmacy#define F_KEEP_ALIVE V_KEEP_ALIVE(1U) 411167514Skmacy 412167514Skmacy#define S_MAX_RETRANS 23 413167514Skmacy#define M_MAX_RETRANS 0xF 414167514Skmacy#define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS) 415167514Skmacy#define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS) 416167514Skmacy 417167514Skmacy#define S_MAX_RETRANS_OVERRIDE 27 418167514Skmacy#define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE) 419167514Skmacy#define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U) 420167514Skmacy 421167514Skmacy#define S_MSS_IDX 28 422167514Skmacy#define M_MSS_IDX 0xF 423167514Skmacy#define V_MSS_IDX(x) ((x) << S_MSS_IDX) 424167514Skmacy#define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 425167514Skmacy 426167514Skmacy/* option 1 fields */ 427167514Skmacy#define S_RSS_ENABLE 0 428167514Skmacy#define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE) 429167514Skmacy#define F_RSS_ENABLE V_RSS_ENABLE(1U) 430167514Skmacy 431167514Skmacy#define S_RSS_MASK_LEN 1 432167514Skmacy#define M_RSS_MASK_LEN 0x7 433167514Skmacy#define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN) 434167514Skmacy#define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN) 435167514Skmacy 436167514Skmacy#define S_CPU_IDX 4 437167514Skmacy#define M_CPU_IDX 0x3F 438167514Skmacy#define V_CPU_IDX(x) ((x) << S_CPU_IDX) 439167514Skmacy#define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX) 440167514Skmacy 441171471Skmacy#define S_OPT1_VLAN 6 442171471Skmacy#define M_OPT1_VLAN 0xFFF 443171471Skmacy#define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN) 444171471Skmacy#define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN) 445171471Skmacy 446167514Skmacy#define S_MAC_MATCH_VALID 18 447167514Skmacy#define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID) 448167514Skmacy#define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U) 449167514Skmacy 450167514Skmacy#define S_CONN_POLICY 19 451167514Skmacy#define M_CONN_POLICY 0x3 452167514Skmacy#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 453167514Skmacy#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 454167514Skmacy 455167514Skmacy#define S_SYN_DEFENSE 21 456167514Skmacy#define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 457167514Skmacy#define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 458167514Skmacy 459167514Skmacy#define S_VLAN_PRI 22 460167514Skmacy#define M_VLAN_PRI 0x3 461167514Skmacy#define V_VLAN_PRI(x) ((x) << S_VLAN_PRI) 462167514Skmacy#define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI) 463167514Skmacy 464167514Skmacy#define S_VLAN_PRI_VALID 24 465167514Skmacy#define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID) 466167514Skmacy#define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U) 467167514Skmacy 468167514Skmacy#define S_PKT_TYPE 25 469167514Skmacy#define M_PKT_TYPE 0x3 470167514Skmacy#define V_PKT_TYPE(x) ((x) << S_PKT_TYPE) 471167514Skmacy#define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE) 472167514Skmacy 473167514Skmacy#define S_MAC_MATCH 27 474167514Skmacy#define M_MAC_MATCH 0x1F 475167514Skmacy#define V_MAC_MATCH(x) ((x) << S_MAC_MATCH) 476167514Skmacy#define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH) 477167514Skmacy 478167514Skmacy/* option 2 fields */ 479167514Skmacy#define S_CPU_INDEX 0 480167514Skmacy#define M_CPU_INDEX 0x7F 481167514Skmacy#define V_CPU_INDEX(x) ((x) << S_CPU_INDEX) 482167514Skmacy#define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX) 483167514Skmacy 484167514Skmacy#define S_CPU_INDEX_VALID 7 485167514Skmacy#define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID) 486167514Skmacy#define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U) 487167514Skmacy 488167514Skmacy#define S_RX_COALESCE 8 489167514Skmacy#define M_RX_COALESCE 0x3 490167514Skmacy#define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 491167514Skmacy#define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 492167514Skmacy 493167514Skmacy#define S_RX_COALESCE_VALID 10 494167514Skmacy#define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 495167514Skmacy#define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 496167514Skmacy 497167514Skmacy#define S_CONG_CONTROL_FLAVOR 11 498167514Skmacy#define M_CONG_CONTROL_FLAVOR 0x3 499167514Skmacy#define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR) 500167514Skmacy#define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR) 501167514Skmacy 502167514Skmacy#define S_PACING_FLAVOR 13 503167514Skmacy#define M_PACING_FLAVOR 0x3 504167514Skmacy#define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR) 505167514Skmacy#define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR) 506167514Skmacy 507167514Skmacy#define S_FLAVORS_VALID 15 508167514Skmacy#define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID) 509167514Skmacy#define F_FLAVORS_VALID V_FLAVORS_VALID(1U) 510167514Skmacy 511167514Skmacy#define S_RX_FC_DISABLE 16 512167514Skmacy#define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 513167514Skmacy#define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 514167514Skmacy 515167514Skmacy#define S_RX_FC_VALID 17 516167514Skmacy#define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 517167514Skmacy#define F_RX_FC_VALID V_RX_FC_VALID(1U) 518167514Skmacy 519167514Skmacystruct cpl_pass_open_req { 520167514Skmacy WR_HDR; 521167514Skmacy union opcode_tid ot; 522167514Skmacy __be16 local_port; 523167514Skmacy __be16 peer_port; 524167514Skmacy __be32 local_ip; 525167514Skmacy __be32 peer_ip; 526167514Skmacy __be32 opt0h; 527167514Skmacy __be32 opt0l; 528167514Skmacy __be32 peer_netmask; 529167514Skmacy __be32 opt1; 530167514Skmacy}; 531167514Skmacy 532167514Skmacystruct cpl_pass_open_rpl { 533167514Skmacy RSS_HDR 534167514Skmacy union opcode_tid ot; 535167514Skmacy __be16 local_port; 536167514Skmacy __be16 peer_port; 537167514Skmacy __be32 local_ip; 538167514Skmacy __be32 peer_ip; 539167514Skmacy __u8 resvd[7]; 540167514Skmacy __u8 status; 541167514Skmacy}; 542167514Skmacy 543167514Skmacystruct cpl_pass_establish { 544167514Skmacy RSS_HDR 545167514Skmacy union opcode_tid ot; 546167514Skmacy __be16 local_port; 547167514Skmacy __be16 peer_port; 548167514Skmacy __be32 local_ip; 549167514Skmacy __be32 peer_ip; 550167514Skmacy __be32 tos_tid; 551167514Skmacy __be16 l2t_idx; 552167514Skmacy __be16 tcp_opt; 553167514Skmacy __be32 snd_isn; 554167514Skmacy __be32 rcv_isn; 555167514Skmacy}; 556167514Skmacy 557167514Skmacy/* cpl_pass_establish.tos_tid fields */ 558167514Skmacy#define S_PASS_OPEN_TID 0 559167514Skmacy#define M_PASS_OPEN_TID 0xFFFFFF 560167514Skmacy#define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 561167514Skmacy#define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 562167514Skmacy 563167514Skmacy#define S_PASS_OPEN_TOS 24 564167514Skmacy#define M_PASS_OPEN_TOS 0xFF 565167514Skmacy#define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 566167514Skmacy#define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 567167514Skmacy 568167514Skmacy/* cpl_pass_establish.l2t_idx fields */ 569167514Skmacy#define S_L2T_IDX16 5 570167514Skmacy#define M_L2T_IDX16 0x7FF 571167514Skmacy#define V_L2T_IDX16(x) ((x) << S_L2T_IDX16) 572167514Skmacy#define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16) 573167514Skmacy 574167514Skmacy/* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */ 575167514Skmacy#define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 576167514Skmacy#define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 577167514Skmacy#define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 578167514Skmacy#define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 579167514Skmacy#define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 580167514Skmacy 581167514Skmacystruct cpl_pass_accept_req { 582167514Skmacy RSS_HDR 583167514Skmacy union opcode_tid ot; 584167514Skmacy __be16 local_port; 585167514Skmacy __be16 peer_port; 586167514Skmacy __be32 local_ip; 587167514Skmacy __be32 peer_ip; 588167514Skmacy __be32 tos_tid; 589167514Skmacy struct tcp_options tcp_options; 590167514Skmacy __u8 dst_mac[6]; 591167514Skmacy __be16 vlan_tag; 592167514Skmacy __u8 src_mac[6]; 593167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 594167514Skmacy __u8 :3; 595167514Skmacy __u8 addr_idx:3; 596167514Skmacy __u8 port_idx:1; 597167514Skmacy __u8 exact_match:1; 598167514Skmacy#else 599167514Skmacy __u8 exact_match:1; 600167514Skmacy __u8 port_idx:1; 601167514Skmacy __u8 addr_idx:3; 602167514Skmacy __u8 :3; 603167514Skmacy#endif 604167514Skmacy __u8 rsvd; 605167514Skmacy __be32 rcv_isn; 606167514Skmacy __be32 rsvd2; 607167514Skmacy}; 608167514Skmacy 609167514Skmacystruct cpl_pass_accept_rpl { 610167514Skmacy WR_HDR; 611167514Skmacy union opcode_tid ot; 612167514Skmacy __be32 opt2; 613167514Skmacy __be32 rsvd; 614167514Skmacy __be32 peer_ip; 615167514Skmacy __be32 opt0h; 616167514Skmacy __be32 opt0l_status; 617167514Skmacy}; 618167514Skmacy 619167514Skmacystruct cpl_act_open_req { 620167514Skmacy WR_HDR; 621167514Skmacy union opcode_tid ot; 622167514Skmacy __be16 local_port; 623167514Skmacy __be16 peer_port; 624167514Skmacy __be32 local_ip; 625167514Skmacy __be32 peer_ip; 626167514Skmacy __be32 opt0h; 627167514Skmacy __be32 opt0l; 628167514Skmacy __be32 params; 629167514Skmacy __be32 opt2; 630167514Skmacy}; 631167514Skmacy 632167514Skmacy/* cpl_act_open_req.params fields */ 633167514Skmacy#define S_AOPEN_VLAN_PRI 9 634167514Skmacy#define M_AOPEN_VLAN_PRI 0x3 635167514Skmacy#define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI) 636167514Skmacy#define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI) 637167514Skmacy 638167514Skmacy#define S_AOPEN_VLAN_PRI_VALID 11 639167514Skmacy#define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID) 640167514Skmacy#define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U) 641167514Skmacy 642167514Skmacy#define S_AOPEN_PKT_TYPE 12 643167514Skmacy#define M_AOPEN_PKT_TYPE 0x3 644167514Skmacy#define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE) 645167514Skmacy#define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE) 646167514Skmacy 647167514Skmacy#define S_AOPEN_MAC_MATCH 14 648167514Skmacy#define M_AOPEN_MAC_MATCH 0x1F 649167514Skmacy#define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH) 650167514Skmacy#define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH) 651167514Skmacy 652167514Skmacy#define S_AOPEN_MAC_MATCH_VALID 19 653167514Skmacy#define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID) 654167514Skmacy#define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U) 655167514Skmacy 656167514Skmacy#define S_AOPEN_IFF_VLAN 20 657167514Skmacy#define M_AOPEN_IFF_VLAN 0xFFF 658167514Skmacy#define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN) 659167514Skmacy#define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN) 660167514Skmacy 661167514Skmacystruct cpl_act_open_rpl { 662167514Skmacy RSS_HDR 663167514Skmacy union opcode_tid ot; 664167514Skmacy __be16 local_port; 665167514Skmacy __be16 peer_port; 666167514Skmacy __be32 local_ip; 667167514Skmacy __be32 peer_ip; 668167514Skmacy __be32 atid; 669167514Skmacy __u8 rsvd[3]; 670167514Skmacy __u8 status; 671167514Skmacy}; 672167514Skmacy 673167514Skmacystruct cpl_act_establish { 674167514Skmacy RSS_HDR 675167514Skmacy union opcode_tid ot; 676167514Skmacy __be16 local_port; 677167514Skmacy __be16 peer_port; 678167514Skmacy __be32 local_ip; 679167514Skmacy __be32 peer_ip; 680167514Skmacy __be32 tos_tid; 681167514Skmacy __be16 l2t_idx; 682167514Skmacy __be16 tcp_opt; 683167514Skmacy __be32 snd_isn; 684167514Skmacy __be32 rcv_isn; 685167514Skmacy}; 686167514Skmacy 687167514Skmacystruct cpl_get_tcb { 688167514Skmacy WR_HDR; 689167514Skmacy union opcode_tid ot; 690167514Skmacy __be16 cpuno; 691167514Skmacy __be16 rsvd; 692167514Skmacy}; 693167514Skmacy 694167514Skmacystruct cpl_get_tcb_rpl { 695167514Skmacy RSS_HDR 696167514Skmacy union opcode_tid ot; 697167514Skmacy __u8 rsvd; 698167514Skmacy __u8 status; 699167514Skmacy __be16 len; 700167514Skmacy}; 701167514Skmacy 702167514Skmacystruct cpl_set_tcb { 703167514Skmacy WR_HDR; 704167514Skmacy union opcode_tid ot; 705167514Skmacy __u8 reply; 706167514Skmacy __u8 cpu_idx; 707167514Skmacy __be16 len; 708167514Skmacy}; 709167514Skmacy 710167514Skmacy/* cpl_set_tcb.reply fields */ 711167514Skmacy#define S_NO_REPLY 7 712167514Skmacy#define V_NO_REPLY(x) ((x) << S_NO_REPLY) 713167514Skmacy#define F_NO_REPLY V_NO_REPLY(1U) 714167514Skmacy 715167514Skmacystruct cpl_set_tcb_field { 716167514Skmacy WR_HDR; 717167514Skmacy union opcode_tid ot; 718167514Skmacy __u8 reply; 719167514Skmacy __u8 cpu_idx; 720167514Skmacy __be16 word; 721167514Skmacy __be64 mask; 722167514Skmacy __be64 val; 723167514Skmacy}; 724167514Skmacy 725167514Skmacystruct cpl_set_tcb_rpl { 726167514Skmacy RSS_HDR 727167514Skmacy union opcode_tid ot; 728167514Skmacy __u8 rsvd[3]; 729167514Skmacy __u8 status; 730167514Skmacy}; 731167514Skmacy 732167514Skmacystruct cpl_pcmd { 733167514Skmacy WR_HDR; 734167514Skmacy union opcode_tid ot; 735167514Skmacy __u8 rsvd[3]; 736167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 737167514Skmacy __u8 src:1; 738167514Skmacy __u8 bundle:1; 739167514Skmacy __u8 channel:1; 740167514Skmacy __u8 :5; 741167514Skmacy#else 742167514Skmacy __u8 :5; 743167514Skmacy __u8 channel:1; 744167514Skmacy __u8 bundle:1; 745167514Skmacy __u8 src:1; 746167514Skmacy#endif 747167514Skmacy __be32 pcmd_parm[2]; 748167514Skmacy}; 749167514Skmacy 750167514Skmacystruct cpl_pcmd_reply { 751167514Skmacy RSS_HDR 752167514Skmacy union opcode_tid ot; 753167514Skmacy __u8 status; 754167514Skmacy __u8 rsvd; 755167514Skmacy __be16 len; 756167514Skmacy}; 757167514Skmacy 758167514Skmacystruct cpl_close_con_req { 759167514Skmacy WR_HDR; 760167514Skmacy union opcode_tid ot; 761167514Skmacy __be32 rsvd; 762167514Skmacy}; 763167514Skmacy 764167514Skmacystruct cpl_close_con_rpl { 765167514Skmacy RSS_HDR 766167514Skmacy union opcode_tid ot; 767167514Skmacy __u8 rsvd[3]; 768167514Skmacy __u8 status; 769167514Skmacy __be32 snd_nxt; 770167514Skmacy __be32 rcv_nxt; 771167514Skmacy}; 772167514Skmacy 773167514Skmacystruct cpl_close_listserv_req { 774167514Skmacy WR_HDR; 775167514Skmacy union opcode_tid ot; 776167514Skmacy __u8 rsvd0; 777167514Skmacy __u8 cpu_idx; 778167514Skmacy __be16 rsvd1; 779167514Skmacy}; 780167514Skmacy 781167514Skmacystruct cpl_close_listserv_rpl { 782167514Skmacy RSS_HDR 783167514Skmacy union opcode_tid ot; 784167514Skmacy __u8 rsvd[3]; 785167514Skmacy __u8 status; 786167514Skmacy}; 787167514Skmacy 788167514Skmacystruct cpl_abort_req_rss { 789167514Skmacy RSS_HDR 790167514Skmacy union opcode_tid ot; 791167514Skmacy __be32 rsvd0; 792167514Skmacy __u8 rsvd1; 793167514Skmacy __u8 status; 794167514Skmacy __u8 rsvd2[6]; 795167514Skmacy}; 796167514Skmacy 797167514Skmacystruct cpl_abort_req { 798167514Skmacy WR_HDR; 799167514Skmacy union opcode_tid ot; 800167514Skmacy __be32 rsvd0; 801167514Skmacy __u8 rsvd1; 802167514Skmacy __u8 cmd; 803167514Skmacy __u8 rsvd2[6]; 804167514Skmacy}; 805167514Skmacy 806167514Skmacystruct cpl_abort_rpl_rss { 807167514Skmacy RSS_HDR 808167514Skmacy union opcode_tid ot; 809167514Skmacy __be32 rsvd0; 810167514Skmacy __u8 rsvd1; 811167514Skmacy __u8 status; 812167514Skmacy __u8 rsvd2[6]; 813167514Skmacy}; 814167514Skmacy 815167514Skmacystruct cpl_abort_rpl { 816167514Skmacy WR_HDR; 817167514Skmacy union opcode_tid ot; 818167514Skmacy __be32 rsvd0; 819167514Skmacy __u8 rsvd1; 820167514Skmacy __u8 cmd; 821167514Skmacy __u8 rsvd2[6]; 822167514Skmacy}; 823167514Skmacy 824167514Skmacystruct cpl_peer_close { 825167514Skmacy RSS_HDR 826167514Skmacy union opcode_tid ot; 827167514Skmacy __be32 rcv_nxt; 828167514Skmacy}; 829167514Skmacy 830167514Skmacystruct tx_data_wr { 831194521Skmacy WR_HDR; 832167514Skmacy __be32 len; 833167514Skmacy __be32 flags; 834167514Skmacy __be32 sndseq; 835167514Skmacy __be32 param; 836167514Skmacy}; 837167514Skmacy 838171471Skmacy/* tx_data_wr.flags fields */ 839171471Skmacy#define S_TX_ACK_PAGES 21 840171471Skmacy#define M_TX_ACK_PAGES 0x7 841171471Skmacy#define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 842171471Skmacy#define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 843171471Skmacy 844167514Skmacy/* tx_data_wr.param fields */ 845167514Skmacy#define S_TX_PORT 0 846167514Skmacy#define M_TX_PORT 0x7 847167514Skmacy#define V_TX_PORT(x) ((x) << S_TX_PORT) 848167514Skmacy#define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 849167514Skmacy 850167514Skmacy#define S_TX_MSS 4 851167514Skmacy#define M_TX_MSS 0xF 852167514Skmacy#define V_TX_MSS(x) ((x) << S_TX_MSS) 853167514Skmacy#define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 854167514Skmacy 855167514Skmacy#define S_TX_QOS 8 856167514Skmacy#define M_TX_QOS 0xFF 857167514Skmacy#define V_TX_QOS(x) ((x) << S_TX_QOS) 858167514Skmacy#define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 859167514Skmacy 860167514Skmacy#define S_TX_SNDBUF 16 861167514Skmacy#define M_TX_SNDBUF 0xFFFF 862167514Skmacy#define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 863167514Skmacy#define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 864167514Skmacy 865167514Skmacystruct cpl_tx_data { 866167514Skmacy union opcode_tid ot; 867167514Skmacy __be32 len; 868167514Skmacy __be32 rsvd; 869167514Skmacy __be16 urg; 870167514Skmacy __be16 flags; 871167514Skmacy}; 872167514Skmacy 873167514Skmacy/* cpl_tx_data.flags fields */ 874167514Skmacy#define S_TX_ULP_SUBMODE 6 875167514Skmacy#define M_TX_ULP_SUBMODE 0xF 876167514Skmacy#define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 877167514Skmacy#define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 878167514Skmacy 879167514Skmacy#define S_TX_ULP_MODE 10 880167514Skmacy#define M_TX_ULP_MODE 0xF 881167514Skmacy#define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 882167514Skmacy#define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 883167514Skmacy 884167514Skmacy#define S_TX_SHOVE 14 885167514Skmacy#define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 886167514Skmacy#define F_TX_SHOVE V_TX_SHOVE(1U) 887167514Skmacy 888167514Skmacy#define S_TX_MORE 15 889167514Skmacy#define V_TX_MORE(x) ((x) << S_TX_MORE) 890167514Skmacy#define F_TX_MORE V_TX_MORE(1U) 891167514Skmacy 892167514Skmacy/* additional tx_data_wr.flags fields */ 893167514Skmacy#define S_TX_CPU_IDX 0 894167514Skmacy#define M_TX_CPU_IDX 0x3F 895167514Skmacy#define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 896167514Skmacy#define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 897167514Skmacy 898167514Skmacy#define S_TX_URG 16 899167514Skmacy#define V_TX_URG(x) ((x) << S_TX_URG) 900167514Skmacy#define F_TX_URG V_TX_URG(1U) 901167514Skmacy 902167514Skmacy#define S_TX_CLOSE 17 903167514Skmacy#define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 904167514Skmacy#define F_TX_CLOSE V_TX_CLOSE(1U) 905167514Skmacy 906167514Skmacy#define S_TX_INIT 18 907167514Skmacy#define V_TX_INIT(x) ((x) << S_TX_INIT) 908167514Skmacy#define F_TX_INIT V_TX_INIT(1U) 909167514Skmacy 910167514Skmacy#define S_TX_IMM_ACK 19 911167514Skmacy#define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 912167514Skmacy#define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 913167514Skmacy 914167514Skmacy#define S_TX_IMM_DMA 20 915167514Skmacy#define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 916167514Skmacy#define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 917167514Skmacy 918167514Skmacystruct cpl_tx_data_ack { 919167514Skmacy RSS_HDR 920167514Skmacy union opcode_tid ot; 921167514Skmacy __be32 ack_seq; 922167514Skmacy}; 923167514Skmacy 924167514Skmacystruct cpl_wr_ack { 925167514Skmacy RSS_HDR 926167514Skmacy union opcode_tid ot; 927167514Skmacy __be16 credits; 928167514Skmacy __be16 rsvd; 929167514Skmacy __be32 snd_nxt; 930167514Skmacy __be32 snd_una; 931167514Skmacy}; 932167514Skmacy 933180583Skmacystruct cpl_sge_ec_cr_return { 934180583Skmacy RSS_HDR 935180583Skmacy union opcode_tid ot; 936180583Skmacy __be16 sge_ec_id; 937180583Skmacy __u8 cr; 938180583Skmacy __u8 rsvd; 939180583Skmacy}; 940180583Skmacy 941167514Skmacystruct cpl_rdma_ec_status { 942167514Skmacy RSS_HDR 943167514Skmacy union opcode_tid ot; 944167514Skmacy __u8 rsvd[3]; 945167514Skmacy __u8 status; 946167514Skmacy}; 947167514Skmacy 948167514Skmacystruct mngt_pktsched_wr { 949194521Skmacy WR_HDR; 950167514Skmacy __u8 mngt_opcode; 951167514Skmacy __u8 rsvd[7]; 952167514Skmacy __u8 sched; 953167514Skmacy __u8 idx; 954167514Skmacy __u8 min; 955167514Skmacy __u8 max; 956167514Skmacy __u8 binding; 957167514Skmacy __u8 rsvd1[3]; 958167514Skmacy}; 959167514Skmacy 960167514Skmacystruct cpl_iscsi_hdr { 961167514Skmacy RSS_HDR 962167514Skmacy union opcode_tid ot; 963167514Skmacy __be16 pdu_len_ddp; 964167514Skmacy __be16 len; 965167514Skmacy __be32 seq; 966167514Skmacy __be16 urg; 967167514Skmacy __u8 rsvd; 968167514Skmacy __u8 status; 969167514Skmacy}; 970167514Skmacy 971167514Skmacy/* cpl_iscsi_hdr.pdu_len_ddp fields */ 972167514Skmacy#define S_ISCSI_PDU_LEN 0 973167514Skmacy#define M_ISCSI_PDU_LEN 0x7FFF 974167514Skmacy#define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 975167514Skmacy#define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 976167514Skmacy 977167514Skmacy#define S_ISCSI_DDP 15 978167514Skmacy#define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 979167514Skmacy#define F_ISCSI_DDP V_ISCSI_DDP(1U) 980167514Skmacy 981167514Skmacystruct cpl_rx_data { 982167514Skmacy RSS_HDR 983167514Skmacy union opcode_tid ot; 984167514Skmacy __be16 rsvd; 985167514Skmacy __be16 len; 986167514Skmacy __be32 seq; 987167514Skmacy __be16 urg; 988167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 989167514Skmacy __u8 dack_mode:2; 990167514Skmacy __u8 psh:1; 991167514Skmacy __u8 heartbeat:1; 992180583Skmacy __u8 ddp_off:1; 993180583Skmacy __u8 :3; 994167514Skmacy#else 995180583Skmacy __u8 :3; 996180583Skmacy __u8 ddp_off:1; 997167514Skmacy __u8 heartbeat:1; 998167514Skmacy __u8 psh:1; 999167514Skmacy __u8 dack_mode:2; 1000167514Skmacy#endif 1001167514Skmacy __u8 status; 1002167514Skmacy}; 1003167514Skmacy 1004167514Skmacystruct cpl_rx_data_ack { 1005167514Skmacy WR_HDR; 1006167514Skmacy union opcode_tid ot; 1007167514Skmacy __be32 credit_dack; 1008167514Skmacy}; 1009167514Skmacy 1010167514Skmacy/* cpl_rx_data_ack.ack_seq fields */ 1011167514Skmacy#define S_RX_CREDITS 0 1012167514Skmacy#define M_RX_CREDITS 0x7FFFFFF 1013167514Skmacy#define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1014167514Skmacy#define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1015167514Skmacy 1016167514Skmacy#define S_RX_MODULATE 27 1017167514Skmacy#define V_RX_MODULATE(x) ((x) << S_RX_MODULATE) 1018167514Skmacy#define F_RX_MODULATE V_RX_MODULATE(1U) 1019167514Skmacy 1020167514Skmacy#define S_RX_FORCE_ACK 28 1021167514Skmacy#define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1022167514Skmacy#define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1023167514Skmacy 1024167514Skmacy#define S_RX_DACK_MODE 29 1025167514Skmacy#define M_RX_DACK_MODE 0x3 1026167514Skmacy#define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1027167514Skmacy#define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1028167514Skmacy 1029167514Skmacy#define S_RX_DACK_CHANGE 31 1030167514Skmacy#define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1031167514Skmacy#define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1032167514Skmacy 1033167514Skmacystruct cpl_rx_urg_notify { 1034167514Skmacy RSS_HDR 1035167514Skmacy union opcode_tid ot; 1036167514Skmacy __be32 seq; 1037167514Skmacy}; 1038167514Skmacy 1039167514Skmacystruct cpl_rx_ddp_complete { 1040167514Skmacy RSS_HDR 1041167514Skmacy union opcode_tid ot; 1042167514Skmacy __be32 ddp_report; 1043167514Skmacy}; 1044167514Skmacy 1045167514Skmacystruct cpl_rx_data_ddp { 1046167514Skmacy RSS_HDR 1047167514Skmacy union opcode_tid ot; 1048167514Skmacy __be16 urg; 1049167514Skmacy __be16 len; 1050167514Skmacy __be32 seq; 1051167514Skmacy union { 1052167514Skmacy __be32 nxt_seq; 1053167514Skmacy __be32 ddp_report; 1054171471Skmacy } u; 1055167514Skmacy __be32 ulp_crc; 1056167514Skmacy __be32 ddpvld_status; 1057167514Skmacy}; 1058167514Skmacy 1059167514Skmacy/* cpl_rx_data_ddp.ddpvld_status fields */ 1060167514Skmacy#define S_DDP_STATUS 0 1061167514Skmacy#define M_DDP_STATUS 0xFF 1062167514Skmacy#define V_DDP_STATUS(x) ((x) << S_DDP_STATUS) 1063167514Skmacy#define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS) 1064167514Skmacy 1065167514Skmacy#define S_DDP_VALID 15 1066167514Skmacy#define M_DDP_VALID 0x1FFFF 1067167514Skmacy#define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1068167514Skmacy#define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1069167514Skmacy 1070167514Skmacy#define S_DDP_PPOD_MISMATCH 15 1071167514Skmacy#define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1072167514Skmacy#define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1073167514Skmacy 1074167514Skmacy#define S_DDP_PDU 16 1075167514Skmacy#define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1076167514Skmacy#define F_DDP_PDU V_DDP_PDU(1U) 1077167514Skmacy 1078167514Skmacy#define S_DDP_LLIMIT_ERR 17 1079167514Skmacy#define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1080167514Skmacy#define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1081167514Skmacy 1082167514Skmacy#define S_DDP_PPOD_PARITY_ERR 18 1083167514Skmacy#define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1084167514Skmacy#define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1085167514Skmacy 1086167514Skmacy#define S_DDP_PADDING_ERR 19 1087167514Skmacy#define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1088167514Skmacy#define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1089167514Skmacy 1090167514Skmacy#define S_DDP_HDRCRC_ERR 20 1091167514Skmacy#define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1092167514Skmacy#define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1093167514Skmacy 1094167514Skmacy#define S_DDP_DATACRC_ERR 21 1095167514Skmacy#define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1096167514Skmacy#define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1097167514Skmacy 1098167514Skmacy#define S_DDP_INVALID_TAG 22 1099167514Skmacy#define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1100167514Skmacy#define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1101167514Skmacy 1102167514Skmacy#define S_DDP_ULIMIT_ERR 23 1103167514Skmacy#define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1104167514Skmacy#define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1105167514Skmacy 1106167514Skmacy#define S_DDP_OFFSET_ERR 24 1107167514Skmacy#define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1108167514Skmacy#define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1109167514Skmacy 1110167514Skmacy#define S_DDP_COLOR_ERR 25 1111167514Skmacy#define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1112167514Skmacy#define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1113167514Skmacy 1114167514Skmacy#define S_DDP_TID_MISMATCH 26 1115167514Skmacy#define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1116167514Skmacy#define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1117167514Skmacy 1118167514Skmacy#define S_DDP_INVALID_PPOD 27 1119167514Skmacy#define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1120167514Skmacy#define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1121167514Skmacy 1122167514Skmacy#define S_DDP_ULP_MODE 28 1123167514Skmacy#define M_DDP_ULP_MODE 0xF 1124167514Skmacy#define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1125167514Skmacy#define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1126167514Skmacy 1127167514Skmacy/* cpl_rx_data_ddp.ddp_report fields */ 1128167514Skmacy#define S_DDP_OFFSET 0 1129167514Skmacy#define M_DDP_OFFSET 0x3FFFFF 1130167514Skmacy#define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1131167514Skmacy#define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1132167514Skmacy 1133176472Skmacy#define S_DDP_DACK_MODE 22 1134176472Skmacy#define M_DDP_DACK_MODE 0x3 1135176472Skmacy#define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1136176472Skmacy#define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1137176472Skmacy 1138167514Skmacy#define S_DDP_URG 24 1139167514Skmacy#define V_DDP_URG(x) ((x) << S_DDP_URG) 1140167514Skmacy#define F_DDP_URG V_DDP_URG(1U) 1141167514Skmacy 1142167514Skmacy#define S_DDP_PSH 25 1143167514Skmacy#define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1144167514Skmacy#define F_DDP_PSH V_DDP_PSH(1U) 1145167514Skmacy 1146167514Skmacy#define S_DDP_BUF_COMPLETE 26 1147167514Skmacy#define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1148167514Skmacy#define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1149167514Skmacy 1150167514Skmacy#define S_DDP_BUF_TIMED_OUT 27 1151167514Skmacy#define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1152167514Skmacy#define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1153167514Skmacy 1154167514Skmacy#define S_DDP_BUF_IDX 28 1155167514Skmacy#define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1156167514Skmacy#define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1157167514Skmacy 1158167514Skmacystruct cpl_tx_pkt { 1159167514Skmacy WR_HDR; 1160167514Skmacy __be32 cntrl; 1161167514Skmacy __be32 len; 1162167514Skmacy}; 1163167514Skmacy 1164180583Skmacystruct cpl_tx_pkt_coalesce { 1165180583Skmacy __be32 cntrl; 1166180583Skmacy __be32 len; 1167180583Skmacy __be64 addr; 1168180583Skmacy}; 1169180583Skmacy 1170180583Skmacystruct tx_pkt_coalesce_wr { 1171180583Skmacy WR_HDR; 1172180583Skmacy struct cpl_tx_pkt_coalesce cpl[0]; 1173180583Skmacy}; 1174180583Skmacy 1175167514Skmacystruct cpl_tx_pkt_lso { 1176167514Skmacy WR_HDR; 1177167514Skmacy __be32 cntrl; 1178167514Skmacy __be32 len; 1179167514Skmacy 1180167514Skmacy __be32 rsvd; 1181167514Skmacy __be32 lso_info; 1182167514Skmacy}; 1183167514Skmacy 1184174708Skmacystruct cpl_tx_pkt_batch_entry { 1185174708Skmacy __be32 cntrl; 1186174708Skmacy __be32 len; 1187174708Skmacy __be64 addr; 1188174708Skmacy}; 1189174708Skmacy 1190174708Skmacystruct cpl_tx_pkt_batch { 1191174708Skmacy WR_HDR; 1192174708Skmacy struct cpl_tx_pkt_batch_entry pkt_entry[7]; 1193174708Skmacy}; 1194174708Skmacy 1195174708Skmacy 1196167514Skmacy/* cpl_tx_pkt*.cntrl fields */ 1197167514Skmacy#define S_TXPKT_VLAN 0 1198167514Skmacy#define M_TXPKT_VLAN 0xFFFF 1199167514Skmacy#define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN) 1200167514Skmacy#define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1201167514Skmacy 1202167514Skmacy#define S_TXPKT_INTF 16 1203167514Skmacy#define M_TXPKT_INTF 0xF 1204167514Skmacy#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1205167514Skmacy#define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1206167514Skmacy 1207167514Skmacy#define S_TXPKT_IPCSUM_DIS 20 1208167514Skmacy#define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS) 1209167514Skmacy#define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U) 1210167514Skmacy 1211167514Skmacy#define S_TXPKT_L4CSUM_DIS 21 1212167514Skmacy#define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS) 1213167514Skmacy#define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U) 1214167514Skmacy 1215167514Skmacy#define S_TXPKT_VLAN_VLD 22 1216167514Skmacy#define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD) 1217167514Skmacy#define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U) 1218167514Skmacy 1219167514Skmacy#define S_TXPKT_LOOPBACK 23 1220167514Skmacy#define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1221167514Skmacy#define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1222167514Skmacy 1223167514Skmacy#define S_TXPKT_OPCODE 24 1224167514Skmacy#define M_TXPKT_OPCODE 0xFF 1225167514Skmacy#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1226167514Skmacy#define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1227167514Skmacy 1228167514Skmacy/* cpl_tx_pkt_lso.lso_info fields */ 1229167514Skmacy#define S_LSO_MSS 0 1230167514Skmacy#define M_LSO_MSS 0x3FFF 1231167514Skmacy#define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1232167514Skmacy#define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1233167514Skmacy 1234167514Skmacy#define S_LSO_ETH_TYPE 14 1235167514Skmacy#define M_LSO_ETH_TYPE 0x3 1236167514Skmacy#define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE) 1237167514Skmacy#define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE) 1238167514Skmacy 1239167514Skmacy#define S_LSO_TCPHDR_WORDS 16 1240167514Skmacy#define M_LSO_TCPHDR_WORDS 0xF 1241167514Skmacy#define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS) 1242167514Skmacy#define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS) 1243167514Skmacy 1244167514Skmacy#define S_LSO_IPHDR_WORDS 20 1245167514Skmacy#define M_LSO_IPHDR_WORDS 0xF 1246167514Skmacy#define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS) 1247167514Skmacy#define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS) 1248167514Skmacy 1249167514Skmacy#define S_LSO_IPV6 24 1250167514Skmacy#define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1251167514Skmacy#define F_LSO_IPV6 V_LSO_IPV6(1U) 1252167514Skmacy 1253167514Skmacystruct cpl_trace_pkt { 1254167514Skmacy#ifdef CHELSIO_FW 1255167514Skmacy __u8 rss_opcode; 1256167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 1257167514Skmacy __u8 err:1; 1258167514Skmacy __u8 :7; 1259167514Skmacy#else 1260167514Skmacy __u8 :7; 1261167514Skmacy __u8 err:1; 1262167514Skmacy#endif 1263167514Skmacy __u8 rsvd0; 1264167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 1265167514Skmacy __u8 qid:4; 1266167514Skmacy __u8 :4; 1267167514Skmacy#else 1268167514Skmacy __u8 :4; 1269167514Skmacy __u8 qid:4; 1270167514Skmacy#endif 1271167514Skmacy __be32 tstamp; 1272167514Skmacy#endif /* CHELSIO_FW */ 1273167514Skmacy 1274167514Skmacy __u8 opcode; 1275167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 1276167514Skmacy __u8 iff:4; 1277167514Skmacy __u8 :4; 1278167514Skmacy#else 1279167514Skmacy __u8 :4; 1280167514Skmacy __u8 iff:4; 1281167514Skmacy#endif 1282167514Skmacy __u8 rsvd[4]; 1283167514Skmacy __be16 len; 1284167514Skmacy}; 1285167514Skmacy 1286167514Skmacystruct cpl_rx_pkt { 1287167514Skmacy RSS_HDR 1288167514Skmacy __u8 opcode; 1289167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 1290167514Skmacy __u8 iff:4; 1291167514Skmacy __u8 csum_valid:1; 1292167514Skmacy __u8 ipmi_pkt:1; 1293167514Skmacy __u8 vlan_valid:1; 1294167514Skmacy __u8 fragment:1; 1295167514Skmacy#else 1296167514Skmacy __u8 fragment:1; 1297167514Skmacy __u8 vlan_valid:1; 1298167514Skmacy __u8 ipmi_pkt:1; 1299167514Skmacy __u8 csum_valid:1; 1300167514Skmacy __u8 iff:4; 1301167514Skmacy#endif 1302167514Skmacy __be16 csum; 1303167514Skmacy __be16 vlan; 1304167514Skmacy __be16 len; 1305167514Skmacy}; 1306167514Skmacy 1307167514Skmacystruct cpl_l2t_write_req { 1308167514Skmacy WR_HDR; 1309167514Skmacy union opcode_tid ot; 1310167514Skmacy __be32 params; 1311180583Skmacy __u8 rsvd; 1312180583Skmacy __u8 port_idx; 1313167514Skmacy __u8 dst_mac[6]; 1314167514Skmacy}; 1315167514Skmacy 1316167514Skmacy/* cpl_l2t_write_req.params fields */ 1317167514Skmacy#define S_L2T_W_IDX 0 1318167514Skmacy#define M_L2T_W_IDX 0x7FF 1319167514Skmacy#define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX) 1320167514Skmacy#define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX) 1321167514Skmacy 1322167514Skmacy#define S_L2T_W_VLAN 11 1323167514Skmacy#define M_L2T_W_VLAN 0xFFF 1324167514Skmacy#define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN) 1325167514Skmacy#define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN) 1326167514Skmacy 1327167514Skmacy#define S_L2T_W_IFF 23 1328167514Skmacy#define M_L2T_W_IFF 0xF 1329167514Skmacy#define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF) 1330167514Skmacy#define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF) 1331167514Skmacy 1332167514Skmacy#define S_L2T_W_PRIO 27 1333167514Skmacy#define M_L2T_W_PRIO 0x7 1334167514Skmacy#define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO) 1335167514Skmacy#define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO) 1336167514Skmacy 1337167514Skmacystruct cpl_l2t_write_rpl { 1338167514Skmacy RSS_HDR 1339167514Skmacy union opcode_tid ot; 1340167514Skmacy __u8 status; 1341167514Skmacy __u8 rsvd[3]; 1342167514Skmacy}; 1343167514Skmacy 1344167514Skmacystruct cpl_l2t_read_req { 1345167514Skmacy WR_HDR; 1346167514Skmacy union opcode_tid ot; 1347167514Skmacy __be16 rsvd; 1348167514Skmacy __be16 l2t_idx; 1349167514Skmacy}; 1350167514Skmacy 1351167514Skmacystruct cpl_l2t_read_rpl { 1352167514Skmacy RSS_HDR 1353167514Skmacy union opcode_tid ot; 1354167514Skmacy __be32 params; 1355167514Skmacy __u8 rsvd[2]; 1356167514Skmacy __u8 dst_mac[6]; 1357167514Skmacy}; 1358167514Skmacy 1359167514Skmacy/* cpl_l2t_read_rpl.params fields */ 1360167514Skmacy#define S_L2T_R_PRIO 0 1361167514Skmacy#define M_L2T_R_PRIO 0x7 1362167514Skmacy#define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO) 1363167514Skmacy#define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO) 1364167514Skmacy 1365167514Skmacy#define S_L2T_R_VLAN 8 1366167514Skmacy#define M_L2T_R_VLAN 0xFFF 1367167514Skmacy#define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN) 1368167514Skmacy#define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN) 1369167514Skmacy 1370167514Skmacy#define S_L2T_R_IFF 20 1371167514Skmacy#define M_L2T_R_IFF 0xF 1372167514Skmacy#define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF) 1373167514Skmacy#define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF) 1374167514Skmacy 1375167514Skmacy#define S_L2T_STATUS 24 1376167514Skmacy#define M_L2T_STATUS 0xFF 1377167514Skmacy#define V_L2T_STATUS(x) ((x) << S_L2T_STATUS) 1378167514Skmacy#define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS) 1379167514Skmacy 1380167514Skmacystruct cpl_smt_write_req { 1381167514Skmacy WR_HDR; 1382167514Skmacy union opcode_tid ot; 1383167514Skmacy __u8 rsvd0; 1384167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 1385167514Skmacy __u8 mtu_idx:4; 1386167514Skmacy __u8 iff:4; 1387167514Skmacy#else 1388167514Skmacy __u8 iff:4; 1389167514Skmacy __u8 mtu_idx:4; 1390167514Skmacy#endif 1391167514Skmacy __be16 rsvd2; 1392167514Skmacy __be16 rsvd3; 1393167514Skmacy __u8 src_mac1[6]; 1394167514Skmacy __be16 rsvd4; 1395167514Skmacy __u8 src_mac0[6]; 1396167514Skmacy}; 1397167514Skmacy 1398167514Skmacystruct cpl_smt_write_rpl { 1399167514Skmacy RSS_HDR 1400167514Skmacy union opcode_tid ot; 1401167514Skmacy __u8 status; 1402167514Skmacy __u8 rsvd[3]; 1403167514Skmacy}; 1404167514Skmacy 1405167514Skmacystruct cpl_smt_read_req { 1406167514Skmacy WR_HDR; 1407167514Skmacy union opcode_tid ot; 1408167514Skmacy __u8 rsvd0; 1409167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 1410167514Skmacy __u8 :4; 1411167514Skmacy __u8 iff:4; 1412167514Skmacy#else 1413167514Skmacy __u8 iff:4; 1414167514Skmacy __u8 :4; 1415167514Skmacy#endif 1416167514Skmacy __be16 rsvd2; 1417167514Skmacy}; 1418167514Skmacy 1419167514Skmacystruct cpl_smt_read_rpl { 1420167514Skmacy RSS_HDR 1421167514Skmacy union opcode_tid ot; 1422167514Skmacy __u8 status; 1423167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 1424167514Skmacy __u8 mtu_idx:4; 1425167514Skmacy __u8 :4; 1426167514Skmacy#else 1427167514Skmacy __u8 :4; 1428167514Skmacy __u8 mtu_idx:4; 1429167514Skmacy#endif 1430167514Skmacy __be16 rsvd2; 1431167514Skmacy __be16 rsvd3; 1432167514Skmacy __u8 src_mac1[6]; 1433167514Skmacy __be16 rsvd4; 1434167514Skmacy __u8 src_mac0[6]; 1435167514Skmacy}; 1436167514Skmacy 1437167514Skmacystruct cpl_rte_delete_req { 1438167514Skmacy WR_HDR; 1439167514Skmacy union opcode_tid ot; 1440167514Skmacy __be32 params; 1441167514Skmacy}; 1442167514Skmacy 1443167514Skmacy/* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */ 1444167514Skmacy#define S_RTE_REQ_LUT_IX 8 1445167514Skmacy#define M_RTE_REQ_LUT_IX 0x7FF 1446167514Skmacy#define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1447167514Skmacy#define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1448167514Skmacy 1449167514Skmacy#define S_RTE_REQ_LUT_BASE 19 1450167514Skmacy#define M_RTE_REQ_LUT_BASE 0x7FF 1451167514Skmacy#define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1452167514Skmacy#define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1453167514Skmacy 1454167514Skmacy#define S_RTE_READ_REQ_SELECT 31 1455167514Skmacy#define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1456167514Skmacy#define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1457167514Skmacy 1458167514Skmacystruct cpl_rte_delete_rpl { 1459167514Skmacy RSS_HDR 1460167514Skmacy union opcode_tid ot; 1461167514Skmacy __u8 status; 1462167514Skmacy __u8 rsvd[3]; 1463167514Skmacy}; 1464167514Skmacy 1465167514Skmacystruct cpl_rte_write_req { 1466167514Skmacy WR_HDR; 1467167514Skmacy union opcode_tid ot; 1468167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 1469167514Skmacy __u8 :6; 1470167514Skmacy __u8 write_tcam:1; 1471167514Skmacy __u8 write_l2t_lut:1; 1472167514Skmacy#else 1473167514Skmacy __u8 write_l2t_lut:1; 1474167514Skmacy __u8 write_tcam:1; 1475167514Skmacy __u8 :6; 1476167514Skmacy#endif 1477167514Skmacy __u8 rsvd[3]; 1478167514Skmacy __be32 lut_params; 1479167514Skmacy __be16 rsvd2; 1480167514Skmacy __be16 l2t_idx; 1481167514Skmacy __be32 netmask; 1482167514Skmacy __be32 faddr; 1483167514Skmacy}; 1484167514Skmacy 1485167514Skmacy/* cpl_rte_write_req.lut_params fields */ 1486167514Skmacy#define S_RTE_WRITE_REQ_LUT_IX 10 1487167514Skmacy#define M_RTE_WRITE_REQ_LUT_IX 0x7FF 1488167514Skmacy#define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX) 1489167514Skmacy#define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX) 1490167514Skmacy 1491167514Skmacy#define S_RTE_WRITE_REQ_LUT_BASE 21 1492167514Skmacy#define M_RTE_WRITE_REQ_LUT_BASE 0x7FF 1493167514Skmacy#define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE) 1494167514Skmacy#define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE) 1495167514Skmacy 1496167514Skmacystruct cpl_rte_write_rpl { 1497167514Skmacy RSS_HDR 1498167514Skmacy union opcode_tid ot; 1499167514Skmacy __u8 status; 1500167514Skmacy __u8 rsvd[3]; 1501167514Skmacy}; 1502167514Skmacy 1503167514Skmacystruct cpl_rte_read_req { 1504167514Skmacy WR_HDR; 1505167514Skmacy union opcode_tid ot; 1506167514Skmacy __be32 params; 1507167514Skmacy}; 1508167514Skmacy 1509167514Skmacystruct cpl_rte_read_rpl { 1510167514Skmacy RSS_HDR 1511167514Skmacy union opcode_tid ot; 1512167514Skmacy __u8 status; 1513167514Skmacy __u8 rsvd0; 1514167514Skmacy __be16 l2t_idx; 1515167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 1516167514Skmacy __u8 :7; 1517167514Skmacy __u8 select:1; 1518167514Skmacy#else 1519167514Skmacy __u8 select:1; 1520167514Skmacy __u8 :7; 1521167514Skmacy#endif 1522167514Skmacy __u8 rsvd2[3]; 1523167514Skmacy __be32 addr; 1524167514Skmacy}; 1525167514Skmacy 1526167514Skmacystruct cpl_tid_release { 1527167514Skmacy WR_HDR; 1528167514Skmacy union opcode_tid ot; 1529167514Skmacy __be32 rsvd; 1530167514Skmacy}; 1531167514Skmacy 1532167514Skmacystruct cpl_barrier { 1533167514Skmacy WR_HDR; 1534167514Skmacy __u8 opcode; 1535167514Skmacy __u8 rsvd[7]; 1536167514Skmacy}; 1537167514Skmacy 1538167514Skmacystruct cpl_rdma_read_req { 1539167514Skmacy __u8 opcode; 1540167514Skmacy __u8 rsvd[15]; 1541167514Skmacy}; 1542167514Skmacy 1543167514Skmacystruct cpl_rdma_terminate { 1544167514Skmacy#ifdef CHELSIO_FW 1545167514Skmacy __u8 opcode; 1546167514Skmacy __u8 rsvd[2]; 1547167514Skmacy#if defined(__LITTLE_ENDIAN_BITFIELD) 1548167514Skmacy __u8 rspq:3; 1549167514Skmacy __u8 :5; 1550167514Skmacy#else 1551167514Skmacy __u8 :5; 1552167514Skmacy __u8 rspq:3; 1553167514Skmacy#endif 1554167514Skmacy __be32 tid_len; 1555167514Skmacy#endif 1556167514Skmacy __be32 msn; 1557167514Skmacy __be32 mo; 1558167514Skmacy __u8 data[0]; 1559167514Skmacy}; 1560167514Skmacy 1561167514Skmacy/* cpl_rdma_terminate.tid_len fields */ 1562167514Skmacy#define S_FLIT_CNT 0 1563167514Skmacy#define M_FLIT_CNT 0xFF 1564167514Skmacy#define V_FLIT_CNT(x) ((x) << S_FLIT_CNT) 1565167514Skmacy#define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT) 1566167514Skmacy 1567167514Skmacy#define S_TERM_TID 8 1568167514Skmacy#define M_TERM_TID 0xFFFFF 1569167514Skmacy#define V_TERM_TID(x) ((x) << S_TERM_TID) 1570167514Skmacy#define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID) 1571169978Skmacy 1572169978Skmacy/* ULP_TX opcodes */ 1573169978Skmacyenum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 }; 1574169978Skmacy 1575169978Skmacy#define S_ULPTX_CMD 28 1576169978Skmacy#define M_ULPTX_CMD 0xF 1577169978Skmacy#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 1578169978Skmacy 1579169978Skmacy#define S_ULPTX_NFLITS 0 1580169978Skmacy#define M_ULPTX_NFLITS 0xFF 1581169978Skmacy#define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS) 1582169978Skmacy 1583169978Skmacystruct ulp_mem_io { 1584169978Skmacy WR_HDR; 1585169978Skmacy __be32 cmd_lock_addr; 1586169978Skmacy __be32 len; 1587169978Skmacy}; 1588169978Skmacy 1589171471Skmacy/* ulp_mem_io.cmd_lock_addr fields */ 1590169978Skmacy#define S_ULP_MEMIO_ADDR 0 1591169978Skmacy#define M_ULP_MEMIO_ADDR 0x7FFFFFF 1592169978Skmacy#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 1593169978Skmacy 1594169978Skmacy#define S_ULP_MEMIO_LOCK 27 1595169978Skmacy#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 1596169978Skmacy#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 1597169978Skmacy 1598171471Skmacy/* ulp_mem_io.len fields */ 1599169978Skmacy#define S_ULP_MEMIO_DATA_LEN 28 1600169978Skmacy#define M_ULP_MEMIO_DATA_LEN 0xF 1601169978Skmacy#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 1602169978Skmacy 1603169978Skmacystruct ulp_txpkt { 1604169978Skmacy __be32 cmd_dest; 1605169978Skmacy __be32 len; 1606169978Skmacy}; 1607169978Skmacy 1608171471Skmacy/* ulp_txpkt.cmd_dest fields */ 1609169978Skmacy#define S_ULP_TXPKT_DEST 24 1610169978Skmacy#define M_ULP_TXPKT_DEST 0xF 1611169978Skmacy#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 1612169978Skmacy 1613167514Skmacy#endif /* T3_CPL_H */ 1614