1139749Simp/*- 2126177Srik * Defines for Cronyx-Tau adapter, based on Hitachi HD64570 controller. 3126177Srik * 4126177Srik * Copyright (C) 1996 Cronyx Engineering. 5126177Srik * Author: Serge Vakulenko, <vak@cronyx.ru> 6126177Srik * 7126177Srik * This software is distributed with NO WARRANTIES, not even the implied 8126177Srik * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 9126177Srik * 10126177Srik * Authors grant any other persons or organisations permission to use 11126177Srik * or modify this software as long as this message is kept with the software, 12126177Srik * all derivative works or modified versions. 13126177Srik * 14126177Srik * Cronyx Id: ctaureg.h,v 1.1.2.1 2003/11/12 17:16:10 rik Exp $ 15126177Srik * $FreeBSD$ 16126177Srik */ 17126177Srik 18126177Srik/* 19126177Srik * Chip register address, B is chip base port, R is chip register number. 20126177Srik */ 21126177Srik#define R(b,r) ((b) | 0x8000 | (((r)<<6 & 0x3c00) | ((r) & 0xf))) 22126177Srik 23126177Srik/* 24126177Srik * Interface board registers, R is register number 0..7. 25126177Srik */ 26126177Srik#define GR(p,r) ((p) | 0x0010 | (r)<<1) 27126177Srik 28126177Srik/*------------------------------------------------------------ 29126177Srik * Basic Tau model. 30126177Srik */ 31126177Srik#define BSR0(p) (p) /* board status register 0, read only */ 32126177Srik#define BSR1(p) ((p) | 0x2000) /* board status register 1, read only */ 33126177Srik#define BSR2(p) ((p) | 0x4010) /* board status register 2, read only */ 34126177Srik#define BSR3(p) ((p) | 0x4000) /* board status register 3, read only */ 35126177Srik#define BCR0(p) (p) /* board command register 0, write only */ 36126177Srik#define BCR1(p) ((p) | 0x2000) /* board command register 1, write only */ 37126177Srik#define BCR2(p) ((p) | 0x4010) /* board command register 2, write only */ 38126177Srik#define BCR3(p) ((p) | 0x4000) /* board command register 3, write only */ 39126177Srik#define IACK(p) ((p) | 0x6000) /* interrupt acknowledge register, ro */ 40126177Srik 41126177Srik/* 42126177Srik * Board status register 0 bits. 43126177Srik */ 44126177Srik#define BSR0_INTR 0x01 /* interrupt pending flag */ 45126177Srik#define BSR0_HDINT 0x02 /* HD64570 interrupt pending */ 46126177Srik#define BSR0_GINT 0x04 /* interface board interrupt pending */ 47126177Srik#define BSR0_RDYERR 0x10 /* HD64570 reg.i/o error - not ready */ 48126177Srik 49126177Srik#define BSR0_TE1 0x02 /* 0 - E1 daughter board installed */ 50126177Srik#define BSR0_T703 0x04 /* 0 - G.703 daughter board installed */ 51126177Srik 52126177Srik/* 53126177Srik * Board status register 1 bits. 54126177Srik */ 55126177Srik#define BSR1_DSR0 0x01 /* DSR from channel 0 */ 56126177Srik#define BSR1_DSR1 0x02 /* DSR from channel 1 */ 57126177Srik 58126177Srik#define BSR1_CH0_CABLE 0x0c /* channel 0 cable type mask */ 59126177Srik#define BSR1_CH0_V35 0x0c /* channel 0 is V.35 */ 60126177Srik#define BSR1_CH0_RS232 0x08 /* channel 0 is RS-232 or not connected */ 61126177Srik#define BSR1_CH0_X21 0x04 /* channel 0 is X.21 */ 62126177Srik#define BSR1_CH0_RS530 0x00 /* channel 0 is RS-530 */ 63126177Srik 64126177Srik#define BSR1_CH1_CABLE 0x30 /* channel 1 cable type mask */ 65126177Srik#define BSR1_CH1_SHIFT 2 66126177Srik#define BSR1_CH1_V35 0x0c /* channel 1 is V.35 */ 67126177Srik#define BSR1_CH1_RS232 0x08 /* channel 1 is RS-232 or not connected */ 68126177Srik#define BSR1_CH1_X21 0x04 /* channel 1 is X.21 */ 69126177Srik#define BSR1_CH1_RS530 0x00 /* channel 1 is RS-530 */ 70126177Srik 71126177Srik/* 72126177Srik * Board status register 2 bits. 73126177Srik */ 74126177Srik#define BSR2_GINT0 0x08 /* interface board chan0 interrupt pending */ 75126177Srik#define BSR2_GINT1 0x40 /* interface board chan1 interrupt pending */ 76126177Srik#define BSR2_LERR 0x80 /* firmware download error signal */ 77126177Srik 78126177Srik/* 79126177Srik * Board status register 3 bits. 80126177Srik */ 81126177Srik#define BSR3_IB 0x08 /* identification bit */ 82126177Srik#define BSR3_NSTATUS 0x10 /* firmware download status */ 83126177Srik#define BSR3_CONF_DN 0x20 /* firmware download done */ 84126177Srik#define BSR3_IB_NEG 0x40 /* negated identification bit */ 85126177Srik#define BSR3_ZERO 0x80 /* always zero */ 86126177Srik 87126177Srik/* 88126177Srik * Board control register 0 bits. 89126177Srik */ 90126177Srik#define BCR0_IRQ_DIS 0x00 /* no interrupt generated */ 91126177Srik#define BCR0_IRQ_3 0x01 /* select IRQ number 3 */ 92126177Srik#define BCR0_IRQ_5 0x02 /* select IRQ number 5 */ 93126177Srik#define BCR0_IRQ_7 0x03 /* select IRQ number 7 */ 94126177Srik#define BCR0_IRQ_10 0x04 /* select IRQ number 10 */ 95126177Srik#define BCR0_IRQ_11 0x05 /* select IRQ number 11 */ 96126177Srik#define BCR0_IRQ_12 0x06 /* select IRQ number 12 */ 97126177Srik#define BCR0_IRQ_15 0x07 /* select IRQ number 15 */ 98126177Srik#define BCR0_IRQ_MASK 0x07 /* IRQ mask */ 99126177Srik 100126177Srik#define BCR0_HDRUN 0x08 /* inverted board reset flag */ 101126177Srik 102126177Srik#define BCR0_DMA_DIS 0x00 /* no interrupt generated */ 103126177Srik#define BCR0_DMA_5 0x10 /* select DMA channel 5 */ 104126177Srik#define BCR0_DMA_6 0x20 /* select DMA channel 6 */ 105126177Srik#define BCR0_DMA_7 0x30 /* select DMA channel 7 */ 106126177Srik 107126177Srik#define BCR0_TCK 0x80 /* firmware download TCK signal */ 108126177Srik 109126177Srik/* 110126177Srik * Board control register 1 bits. 111126177Srik */ 112126177Srik#define BCR1_DTR0 0x01 /* channel 0 DTR enable */ 113126177Srik#define BCR1_DTR1 0x02 /* channel 1 DTR enable */ 114126177Srik 115126177Srik#define BCR1_TXCOUT0 0x10 /* channel 0 TXCOUT enable */ 116126177Srik#define BCR1_TXCOUT1 0x20 /* channel 1 TXCOUT enable */ 117126177Srik 118126177Srik#define BCR1_TMS 0x08 /* firmware download TMS signal */ 119126177Srik#define BCR1_TDI 0x80 /* firmware download TDI signal */ 120126177Srik 121126177Srik#define BCR1_NCONFIGI 0x08 /* firmware download start */ 122126177Srik#define BCR1_DCLK 0x40 /* firmware download clock */ 123126177Srik#define BCR1_1KDAT 0x80 /* firmware download data */ 124126177Srik 125126177Srik/* 126126177Srik * Board control register 2 bits -- see ctau.h. 127126177Srik */ 128126177Srik 129126177Srik#define IMVR(b) R(b,HD_IMVR) /* interrupt modified vector reg. */ 130126177Srik#define ITCR(b) R(b,HD_ITCR) /* interrupt control register */ 131126177Srik#define ISR0(b) R(b,HD_ISR0) /* interrupt status register 0, ro */ 132126177Srik#define ISR1(b) R(b,HD_ISR1) /* interrupt status register 1, ro */ 133126177Srik#define ISR2(b) R(b,HD_ISR2) /* interrupt status register 2, ro */ 134126177Srik#define IER0(b) R(b,HD_IER0) /* interrupt enable register 0 */ 135126177Srik#define IER1(b) R(b,HD_IER1) /* interrupt enable register 1 */ 136126177Srik#define IER2(b) R(b,HD_IER2) /* interrupt enable register 2 */ 137126177Srik#define PCR(b) R(b,HD_PCR) /* DMA priority control register */ 138126177Srik#define DMER(b) R(b,HD_DMER) /* DMA master enable register */ 139126177Srik#define WCRL(b) R(b,HD_WCRL) /* wait control register L */ 140126177Srik#define WCRM(b) R(b,HD_WCRM) /* wait control register M */ 141126177Srik#define WCRH(b) R(b,HD_WCRH) /* wait control register H */ 142126177Srik 143126177Srik/*------------------------------------------------------------ 144126177Srik * Tau/E1 model. 145126177Srik */ 146126177Srik#define E1CFG(p) GR(p,0) /* control register 0, write only */ 147126177Srik#define E1SR(p) GR(p,0) /* status register, read only */ 148126177Srik#define E1CS2(p) GR(p,1) /* chip select 2/IACK, read/write */ 149126177Srik#define E1SYN(p) GR(p,3) /* sync mode enable, write only */ 150126177Srik#define E1CS0(p) GR(p,4) /* chip select 0, write only */ 151126177Srik#define E1CS1(p) GR(p,5) /* chip select 1, write only */ 152126177Srik#define E1DAT(p) GR(p,7) /* selected chip read/write */ 153126177Srik 154126177Srik/* 155126177Srik * Tau/E1 CS2/IACK register bits. 156126177Srik */ 157126177Srik#define E1CS2_IACK 0x08 /* serial controller interrupt acknowledge */ 158126177Srik#define E1CS2_SCC 0x04 /* serial controller select */ 159126177Srik#define E1CS2_AB 0x02 /* serial controller A/B signal */ 160126177Srik#define E1CS2_DC 0x01 /* serial controller D/C signal */ 161126177Srik 162126177Srik/* 163126177Srik * Tau/E1 control register bits. 164126177Srik */ 165126177Srik#define E1CFG_II 0x00 /* configuration II */ 166126177Srik#define E1CFG_K 0x01 /* configuration K */ 167126177Srik#define E1CFG_HI 0x02 /* configuration HI */ 168126177Srik#define E1CFG_D 0x03 /* configuration D */ 169126177Srik 170126177Srik#define E1CFG_CLK0_INT 0x00 /* channel E0 transmit clock - internal */ 171126177Srik#define E1CFG_CLK0_RCV 0x04 /* channel E0 transmit clock - RCLK0 */ 172126177Srik#define E1CFG_CLK0_RCLK1 0x08 /* channel E0 transmit clock - RCLK1 */ 173126177Srik 174126177Srik#define E1CFG_CLK1_INT 0x00 /* channel E1 transmit clock - internal */ 175126177Srik#define E1CFG_CLK1_RCLK0 0x10 /* channel E1 transmit clock - RCLK0 */ 176126177Srik#define E1CFG_CLK1_RCV 0x20 /* channel E1 transmit clock - RCLK1 */ 177126177Srik 178126177Srik#define E1CFG_LED 0x40 /* LED control */ 179126177Srik#define E1CFG_GRUN 0x80 /* global run flag */ 180126177Srik 181126177Srik/* 182126177Srik * Tau/E1 sync control register bits. 183126177Srik */ 184126177Srik#define E1SYN_ENS0 0x01 /* enable channel 0 sync mode */ 185126177Srik#define E1SYN_ENS1 0x02 /* enable channel 1 sync mode */ 186126177Srik 187126177Srik/* 188126177Srik * Tau/E1 status register bits. 189126177Srik */ 190126177Srik#define E1SR_E0_IRQ0 0x01 /* E0 controller interrupt 0 */ 191126177Srik#define E1SR_E0_IRQ1 0x02 /* E0 controller interrupt 1 */ 192126177Srik#define E1SR_E1_IRQ0 0x04 /* E1 controller interrupt 0 */ 193126177Srik#define E1SR_E1_IRQ1 0x08 /* E1 controller interrupt 1 */ 194126177Srik#define E1SR_SCC_IRQ 0x10 /* serial controller interrupt */ 195126177Srik#define E1SR_TP0 0x20 /* channel 0 is twisted pair */ 196126177Srik#define E1SR_TP1 0x40 /* channel 1 is twisted pair */ 197126177Srik#define E1SR_REV 0x80 /* Tau/E1 revision */ 198126177Srik 199126177Srik/* 200126177Srik * Tau/E1 serial memory register bits. 201126177Srik */ 202126177Srik 203126177Srik/*------------------------------------------------------------ 204126177Srik * Tau/G.703 model. 205126177Srik */ 206126177Srik#define GLCR0(p) GR(p,3) /* line control register 0, write only */ 207126177Srik#define GMD0(p) GR(p,4) /* mode register 0, write only */ 208126177Srik#define GMD1(p) GR(p,5) /* mode register 1, write only */ 209126177Srik#define GMD2(p) GR(p,6) /* mode register 2, write only */ 210126177Srik#define GLCR1(p) GR(p,7) /* line control register 1, write only */ 211126177Srik#define GERR(p) GR(p,0) /* error register, read/write */ 212126177Srik#define GLQ(p) GR(p,1) /* line quality register, read only */ 213126177Srik#define GLDR(p) GR(p,2) /* loop detect request, read only */ 214126177Srik 215126177Srik/* 216126177Srik * Tau/G.703 mode register 0/1 bits. 217126177Srik */ 218126177Srik#define GMD_2048 0x00 /* 2048 kbit/sec */ 219126177Srik#define GMD_1024 0x02 /* 1024 kbit/sec */ 220126177Srik#define GMD_512 0x03 /* 512 kbit/sec */ 221126177Srik#define GMD_256 0x04 /* 256 kbit/sec */ 222126177Srik#define GMD_128 0x05 /* 128 kbit/sec */ 223126177Srik#define GMD_64 0x06 /* 64 kbit/sec */ 224126177Srik 225126177Srik#define GMD_RSYNC 0x08 /* receive synchronization */ 226126177Srik#define GMD_PCE_PCM2 0x10 /* precoder enable, mode PCM2 */ 227126177Srik#define GMD_PCE_PCM2D 0x20 /* precoder enable, mode PCM2D */ 228126177Srik 229126177Srik#define GMD0_SDI 0x40 /* serial data input */ 230126177Srik#define GMD0_SCLK 0x80 /* serial data clock */ 231126177Srik 232126177Srik#define GMD1_NCS0 0x40 /* chip select 0 inverted */ 233126177Srik#define GMD1_NCS1 0x80 /* chip select 1 inverted */ 234126177Srik 235126177Srik/* 236126177Srik * Tau/G.703 mode register 2 bits. 237126177Srik */ 238126177Srik#define GMD2_SERIAL 0x01 /* channel 1 serial interface V.35/RS-232/etc */ 239126177Srik#define GMD2_LED 0x02 /* LED control */ 240126177Srik#define GMD2_RAW0 0x04 /* channel 0 raw mode (byte-sync) */ 241126177Srik#define GMD2_RAW1 0x08 /* channel 1 raw mode (byte-sync) */ 242126177Srik 243126177Srik/* 244126177Srik * Tau/G.703 interrupt status register bits. 245126177Srik */ 246126177Srik#define GERR_BPV0 0x01 /* channel 0 bipolar violation */ 247126177Srik#define GERR_ERR0 0x02 /* channel 0 test error */ 248126177Srik#define GERR_BPV1 0x04 /* channel 1 bipolar violation */ 249126177Srik#define GERR_ERR1 0x08 /* channel 1 test error */ 250126177Srik 251126177Srik/* 252126177Srik * Tau/G.703 line quality register bits. 253126177Srik */ 254126177Srik#define GLQ_MASK 0x03 /* channel 0 mask */ 255126177Srik#define GLQ_SHIFT 2 /* channel 1 shift */ 256126177Srik 257126177Srik#define GLQ_DB0 0x00 /* channel 0 level 0.0 dB */ 258126177Srik#define GLQ_DB95 0x01 /* channel 0 level -9.5 dB */ 259126177Srik#define GLQ_DB195 0x02 /* channel 0 level -19.5 dB */ 260126177Srik#define GLQ_DB285 0x03 /* channel 0 level -28.5 dB */ 261126177Srik 262126177Srik/* 263126177Srik * Tau/G.703 serial data output register bits. 264126177Srik */ 265126177Srik#define GLDR_C0 0x01 /* chip 0 serial data output */ 266126177Srik#define GLDR_LREQ0 0x02 /* channel 0 remote loop request */ 267126177Srik#define GLDR_C1 0x04 /* chip 1 serial data output */ 268126177Srik#define GLDR_LREQ1 0x08 /* channel 1 remote loop request */ 269126177Srik 270126177Srik/* 271126177Srik * Tau/G.703 line control register 0/1 bits. 272126177Srik */ 273126177Srik#define GLCR_RENABLE 0x00 /* normal mode, auto remote loop enabled */ 274126177Srik#define GLCR_RDISABLE 0x01 /* normal mode, auto remote loop disabled */ 275126177Srik#define GLCR_RREFUSE 0x02 /* send the remote loop request sequence */ 276126177Srik#define GLCR_RREQUEST 0x03 /* send the remote loop refuse sequence */ 277