ichss.c revision 141241
1/*- 2 * Copyright (c) 2004-2005 Nate Lawson (SDG) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/cpufreq/ichss.c 141241 2005-02-04 05:42:29Z njl $"); 29 30#include <sys/param.h> 31#include <sys/bus.h> 32#include <sys/cpu.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35#include <sys/module.h> 36#include <sys/pcpu.h> 37#include <sys/sysctl.h> 38#include <sys/systm.h> 39 40#include <dev/pci/pcivar.h> 41#include <machine/clock.h> 42#include <machine/resource.h> 43#include <sys/rman.h> 44 45#include "cpufreq_if.h" 46 47/* 48 * The SpeedStep ICH feature is a chipset-initiated voltage and frequency 49 * transition available on the ICH2M, 3M, and 4M. It is different from 50 * the newer Pentium-M SpeedStep feature. It offers only two levels of 51 * frequency/voltage. Often, the BIOS will select one of the levels via 52 * SMM code during the power-on process (i.e., choose a lower level if the 53 * system is off AC power.) 54 */ 55 56struct ichss_softc { 57 device_t dev; 58 int bm_rid; /* Bus-mastering control (PM2REG). */ 59 struct resource *bm_reg; 60 int ctrl_rid; /* Control/status register. */ 61 struct resource *ctrl_reg; 62 struct cf_setting sets[2]; /* Only two settings. */ 63}; 64 65/* Supported PCI IDs. */ 66#define PCI_VENDOR_INTEL 0x8086 67#define PCI_DEV_82801BA 0x244c /* ICH2M */ 68#define PCI_DEV_82801CA 0x248c /* ICH3M */ 69#define PCI_DEV_82801DB 0x24cc /* ICH4M */ 70#define PCI_DEV_82815BA 0x1130 /* Unsupported/buggy part */ 71 72/* PCI config registers for finding PMBASE and enabling SpeedStep. */ 73#define ICHSS_PMBASE_OFFSET 0x40 74#define ICHSS_PMCFG_OFFSET 0xa0 75 76/* Values and masks. */ 77#define ICHSS_ENABLE (1<<3) /* Enable SpeedStep control. */ 78#define ICHSS_IO_REG 0x1 /* Access register via I/O space. */ 79#define ICHSS_PMBASE_MASK 0xff80 /* PMBASE address bits. */ 80#define ICHSS_CTRL_BIT 0x1 /* 0 is high speed, 1 is low. */ 81#define ICHSS_BM_DISABLE 0x1 82 83/* Offsets from PMBASE for various registers. */ 84#define ICHSS_BM_OFFSET 0x20 85#define ICHSS_CTRL_OFFSET 0x50 86 87#define ICH_GET_REG(reg) \ 88 (bus_space_read_1(rman_get_bustag((reg)), \ 89 rman_get_bushandle((reg)), 0)) 90#define ICH_SET_REG(reg, val) \ 91 (bus_space_write_1(rman_get_bustag((reg)), \ 92 rman_get_bushandle((reg)), 0, (val))) 93 94static int ichss_pci_probe(device_t dev); 95static int ichss_probe(device_t dev); 96static int ichss_attach(device_t dev); 97static int ichss_detach(device_t dev); 98static int ichss_settings(device_t dev, struct cf_setting *sets, 99 int *count, int *type); 100static int ichss_set(device_t dev, const struct cf_setting *set); 101static int ichss_get(device_t dev, struct cf_setting *set); 102 103static device_method_t ichss_methods[] = { 104 /* Device interface */ 105 DEVMETHOD(device_probe, ichss_probe), 106 DEVMETHOD(device_attach, ichss_attach), 107 DEVMETHOD(device_detach, ichss_detach), 108 109 /* cpufreq interface */ 110 DEVMETHOD(cpufreq_drv_set, ichss_set), 111 DEVMETHOD(cpufreq_drv_get, ichss_get), 112 DEVMETHOD(cpufreq_drv_settings, ichss_settings), 113 {0, 0} 114}; 115static driver_t ichss_driver = { 116 "ichss", ichss_methods, sizeof(struct ichss_softc) 117}; 118static devclass_t ichss_devclass; 119DRIVER_MODULE(ichss, cpu, ichss_driver, ichss_devclass, 0, 0); 120 121static device_method_t ichss_pci_methods[] = { 122 DEVMETHOD(device_probe, ichss_pci_probe), 123 {0, 0} 124}; 125static driver_t ichss_pci_driver = { 126 "ichss_pci", ichss_pci_methods, 0 127}; 128static devclass_t ichss_pci_devclass; 129DRIVER_MODULE(ichss_pci, pci, ichss_pci_driver, ichss_pci_devclass, 0, 0); 130 131#if 0 132#define DPRINT(x...) printf(x) 133#else 134#define DPRINT(x...) 135#endif 136 137/* 138 * We detect the chipset by looking for its LPC bus ID during the PCI 139 * scan and reading its config registers during the probe. However, 140 * we add the ichss child under the cpu device since even though the 141 * chipset provides the control, it really affects the cpu only. 142 * 143 * XXX This approach does not work if the module is loaded after boot. 144 */ 145static int 146ichss_pci_probe(device_t dev) 147{ 148 device_t child, parent; 149 uint32_t pmbase; 150 uint16_t ss_en; 151 152 /* 153 * TODO: add a quirk to disable if we see the 82815_MC along 154 * with the 82801BA and revision < 5. 155 */ 156 if (pci_get_vendor(dev) != PCI_VENDOR_INTEL || 157 (pci_get_device(dev) != PCI_DEV_82801BA && 158 pci_get_device(dev) != PCI_DEV_82801CA && 159 pci_get_device(dev) != PCI_DEV_82801DB)) 160 return (ENXIO); 161 162 /* Only one CPU is supported for this hardware. */ 163 if (devclass_get_device(ichss_devclass, 0)) 164 return (ENXIO); 165 166 /* Add a child under the CPU parent. */ 167 parent = devclass_get_device(devclass_find("cpu"), 0); 168 KASSERT(parent != NULL, ("cpu parent is NULL")); 169 child = BUS_ADD_CHILD(parent, 0, "ichss", 0); 170 if (child == NULL) { 171 device_printf(parent, "add SpeedStep child failed\n"); 172 return (ENXIO); 173 } 174 175 /* Find the PMBASE register from our PCI config header. */ 176 pmbase = pci_read_config(dev, ICHSS_PMBASE_OFFSET, sizeof(pmbase)); 177 if ((pmbase & ICHSS_IO_REG) == 0) { 178 printf("ichss: invalid PMBASE memory type\n"); 179 return (ENXIO); 180 } 181 pmbase &= ICHSS_PMBASE_MASK; 182 if (pmbase == 0) { 183 printf("ichss: invalid zero PMBASE address\n"); 184 return (ENXIO); 185 } 186 DPRINT("ichss: PMBASE is %#x\n", pmbase); 187 188 /* Add the bus master arbitration and control registers. */ 189 bus_set_resource(child, SYS_RES_IOPORT, 0, pmbase + ICHSS_BM_OFFSET, 190 1); 191 bus_set_resource(child, SYS_RES_IOPORT, 1, pmbase + ICHSS_CTRL_OFFSET, 192 1); 193 194 /* Activate SpeedStep control if not already enabled. */ 195 ss_en = pci_read_config(dev, ICHSS_PMCFG_OFFSET, sizeof(ss_en)); 196 if ((ss_en & ICHSS_ENABLE) == 0) { 197 printf("ichss: enabling SpeedStep support\n"); 198 pci_write_config(dev, ICHSS_PMCFG_OFFSET, 199 ss_en | ICHSS_ENABLE, sizeof(ss_en)); 200 } 201 202 /* Attach the new CPU child now. */ 203 device_probe_and_attach(child); 204 205 return (ENXIO); 206} 207 208static int 209ichss_probe(device_t dev) 210{ 211 device_t perf_dev; 212 213 /* If the ACPI perf driver has attached, let it manage things. */ 214 perf_dev = devclass_get_device(devclass_find("acpi_perf"), 0); 215 if (perf_dev && device_is_attached(perf_dev)) 216 return (ENXIO); 217 218 device_set_desc(dev, "SpeedStep ICH"); 219 return (-1000); 220} 221 222static int 223ichss_attach(device_t dev) 224{ 225 struct ichss_softc *sc; 226 227 sc = device_get_softc(dev); 228 sc->dev = dev; 229 230 sc->bm_rid = 0; 231 sc->bm_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->bm_rid, 232 RF_ACTIVE); 233 if (sc->bm_reg == NULL) { 234 device_printf(dev, "failed to alloc BM arb register\n"); 235 return (ENXIO); 236 } 237 sc->ctrl_rid = 1; 238 sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 239 &sc->ctrl_rid, RF_ACTIVE); 240 if (sc->ctrl_reg == NULL) { 241 device_printf(dev, "failed to alloc control register\n"); 242 bus_release_resource(dev, SYS_RES_IOPORT, sc->bm_rid, 243 sc->bm_reg); 244 return (ENXIO); 245 } 246 247 /* Setup some defaults for our exported settings. */ 248 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; 249 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; 250 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; 251 sc->sets[0].lat = 1000; 252 sc->sets[0].dev = dev; 253 sc->sets[1] = sc->sets[0]; 254 cpufreq_register(dev); 255 256 return (0); 257} 258 259static int 260ichss_detach(device_t dev) 261{ 262 /* TODO: teardown BM and CTRL registers. */ 263 return (ENXIO); 264} 265 266static int 267ichss_settings(device_t dev, struct cf_setting *sets, int *count, int *type) 268{ 269 struct ichss_softc *sc; 270 struct cf_setting set; 271 int first, i; 272 273 if (sets == NULL || count == NULL) 274 return (EINVAL); 275 if (*count < 2) { 276 *count = 2; 277 return (E2BIG); 278 } 279 sc = device_get_softc(dev); 280 281 /* 282 * Estimate frequencies for both levels, temporarily switching to 283 * the other one if we haven't calibrated it yet. 284 */ 285 ichss_get(dev, &set); 286 for (i = 0; i < 2; i++) { 287 if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) { 288 first = (i == 0) ? 1 : 0; 289 ichss_set(dev, &sc->sets[i]); 290 ichss_set(dev, &sc->sets[first]); 291 } 292 } 293 294 bcopy(sc->sets, sets, sizeof(sc->sets)); 295 *count = 2; 296 *type = CPUFREQ_TYPE_ABSOLUTE; 297 298 return (0); 299} 300 301static int 302ichss_set(device_t dev, const struct cf_setting *set) 303{ 304 struct ichss_softc *sc; 305 uint8_t bmval, new_val, old_val, req_val; 306 uint64_t rate; 307 308 /* Look up appropriate bit value based on frequency. */ 309 sc = device_get_softc(dev); 310 if (CPUFREQ_CMP(set->freq, sc->sets[0].freq)) 311 req_val = 0; 312 else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq)) 313 req_val = ICHSS_CTRL_BIT; 314 else 315 return (EINVAL); 316 DPRINT("ichss: requested setting %d\n", req_val); 317 318 /* Disable interrupts and get the other register contents. */ 319 disable_intr(); 320 old_val = ICH_GET_REG(sc->ctrl_reg) & ~ICHSS_CTRL_BIT; 321 322 /* 323 * Disable bus master arbitration, write the new value to the control 324 * register, and then re-enable bus master arbitration. 325 */ 326 bmval = ICH_GET_REG(sc->bm_reg) | ICHSS_BM_DISABLE; 327 ICH_SET_REG(sc->bm_reg, bmval); 328 ICH_SET_REG(sc->ctrl_reg, old_val | req_val); 329 ICH_SET_REG(sc->bm_reg, bmval & ~ICHSS_BM_DISABLE); 330 331 /* Get the new value and re-enable interrupts. */ 332 new_val = ICH_GET_REG(sc->ctrl_reg); 333 enable_intr(); 334 335 /* Check if the desired state was indeed selected. */ 336 if (req_val != (new_val & ICHSS_CTRL_BIT)) { 337 device_printf(sc->dev, "transition to %d failed\n", req_val); 338 return (ENXIO); 339 } 340 341 /* Re-initialize our cycle counter if we don't know this new state. */ 342 if (sc->sets[req_val].freq == CPUFREQ_VAL_UNKNOWN) { 343 cpu_est_clockrate(0, &rate); 344 sc->sets[req_val].freq = rate / 1000000; 345 DPRINT("ichss: set calibrated new rate of %d\n", 346 sc->sets[req_val].freq); 347 } 348 349 return (0); 350} 351 352static int 353ichss_get(device_t dev, struct cf_setting *set) 354{ 355 struct ichss_softc *sc; 356 uint64_t rate; 357 uint8_t state; 358 359 sc = device_get_softc(dev); 360 state = ICH_GET_REG(sc->ctrl_reg) & ICHSS_CTRL_BIT; 361 362 /* If we haven't changed settings yet, estimate the current value. */ 363 if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) { 364 cpu_est_clockrate(0, &rate); 365 sc->sets[state].freq = rate / 1000000; 366 DPRINT("ichss: get calibrated new rate of %d\n", 367 sc->sets[state].freq); 368 } 369 *set = sc->sets[state]; 370 371 return (0); 372} 373