if_bwireg.h revision 192279
1191762Simp/* 2191762Simp * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3191762Simp * 4191762Simp * This code is derived from software contributed to The DragonFly Project 5191762Simp * by Sepherosa Ziehau <sepherosa@gmail.com> 6191762Simp * 7191762Simp * Redistribution and use in source and binary forms, with or without 8191762Simp * modification, are permitted provided that the following conditions 9191762Simp * are met: 10191762Simp * 11191762Simp * 1. Redistributions of source code must retain the above copyright 12191762Simp * notice, this list of conditions and the following disclaimer. 13191762Simp * 2. Redistributions in binary form must reproduce the above copyright 14191762Simp * notice, this list of conditions and the following disclaimer in 15191762Simp * the documentation and/or other materials provided with the 16191762Simp * distribution. 17191762Simp * 3. Neither the name of The DragonFly Project nor the names of its 18191762Simp * contributors may be used to endorse or promote products derived 19191762Simp * from this software without specific, prior written permission. 20191762Simp * 21191762Simp * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22191762Simp * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23191762Simp * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24191762Simp * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25191762Simp * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26191762Simp * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27191762Simp * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28191762Simp * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29191762Simp * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30191762Simp * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31191762Simp * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32191762Simp * SUCH DAMAGE. 33191762Simp * 34191762Simp * $DragonFly: src/sys/dev/netif/bwi/if_bwireg.h,v 1.4 2007/10/19 14:27:04 sephe Exp $ 35191762Simp * $FreeBSD: head/sys/dev/bwi/if_bwireg.h 192279 2009-05-18 01:07:38Z imp $ 36191762Simp */ 37191762Simp 38191762Simp#ifndef _IF_BWIREG_H 39191762Simp#define _IF_BWIREG_H 40191762Simp 41191762Simp/* 42191762Simp * Registers for all of the register windows 43191762Simp */ 44191762Simp#define BWI_FLAGS 0xf18 45191762Simp#define BWI_FLAGS_INTR_MASK __BITS(5, 0) 46191762Simp 47191762Simp#define BWI_IMSTATE 0xf90 48191762Simp#define BWI_IMSTATE_INBAND_ERR __BIT(17) 49191762Simp#define BWI_IMSTATE_TIMEOUT __BIT(18) 50191762Simp 51191762Simp#define BWI_INTRVEC 0xf94 52191762Simp 53191762Simp#define BWI_STATE_LO 0xf98 54191762Simp#define BWI_STATE_LO_RESET __BIT(0) 55191762Simp#define BWI_STATE_LO_DISABLE1 __BIT(1) 56191762Simp#define BWI_STATE_LO_DISABLE2 __BIT(2) 57191762Simp#define BWI_STATE_LO_CLOCK __BIT(16) 58191762Simp#define BWI_STATE_LO_GATED_CLOCK __BIT(17) 59191762Simp#define BWI_STATE_LO_FLAG_PHYCLKEN __BIT(0) 60191762Simp#define BWI_STATE_LO_FLAG_PHYRST __BIT(1) 61191762Simp#define BWI_STATE_LO_FLAG_PHYLNK __BIT(11) 62191762Simp#define BWI_STATE_LO_FLAGS_MASK __BITS(29, 18) 63191762Simp 64191762Simp#define BWI_STATE_HI 0xf9c 65191762Simp#define BWI_STATE_HI_SERROR __BIT(0) 66191762Simp#define BWI_STATE_HI_BUSY __BIT(2) 67191762Simp#define BWI_STATE_HI_FLAG_MAGIC1 0x1 68191762Simp#define BWI_STATE_HI_FLAG_MAGIC2 0x2 69191762Simp#define BWI_STATE_HI_FLAG_64BIT 0x1000 70191762Simp#define BWI_STATE_HI_FLAGS_MASK __BITS(28, 16) 71191762Simp 72191762Simp#define BWI_CONF_LO 0xfa8 73191762Simp#define BWI_CONF_LO_SERVTO_MASK __BITS(2, 0) /* service timeout */ 74191762Simp#define BWI_CONF_LO_SERVTO 2 75191762Simp#define BWI_CONF_LO_REQTO_MASK __BITS(6, 4) /* request timeout */ 76191762Simp#define BWI_CONF_LO_REQTO 3 77191762Simp 78191762Simp 79191762Simp#define BWI_ID_LO 0xff8 80191762Simp#define BWI_ID_LO_BUSREV_MASK __BITS(31, 28) 81191762Simp/* Bus revision */ 82191762Simp#define BWI_BUSREV_0 0 83191762Simp#define BWI_BUSREV_1 1 84191762Simp 85191762Simp#define BWI_ID_HI 0xffc 86191762Simp#define BWI_ID_HI_REGWIN_REV(v) (((v) & 0xf) | (((v) & 0x7000) >> 8)) 87191762Simp#define BWI_ID_HI_REGWIN_TYPE(v) (((v) & 0x8ff0) >> 4) 88191762Simp#define BWI_ID_HI_REGWIN_VENDOR_MASK __BITS(31, 16) 89191762Simp 90191762Simp/* 91191762Simp * Registers for common register window 92191762Simp */ 93191762Simp#define BWI_INFO 0x0 94191762Simp#define BWI_INFO_BBPID_MASK __BITS(15, 0) 95191762Simp#define BWI_INFO_BBPREV_MASK __BITS(19, 16) 96191762Simp#define BWI_INFO_BBPPKG_MASK __BITS(23, 20) 97191762Simp#define BWI_INFO_NREGWIN_MASK __BITS(27, 24) 98191762Simp 99191762Simp#define BWI_CAPABILITY 0x4 100191762Simp#define BWI_CAP_CLKMODE __BIT(18) 101191762Simp 102191762Simp#define BWI_CONTROL 0x28 103191762Simp#define BWI_CONTROL_MAGIC0 0x3a4 104191762Simp#define BWI_CONTROL_MAGIC1 0xa4 105191762Simp#define BWI_PLL_ON_DELAY 0xb0 106191762Simp#define BWI_FREQ_SEL_DELAY 0xb4 107191762Simp 108191762Simp#define BWI_CLOCK_CTRL 0xb8 109191762Simp#define BWI_CLOCK_CTRL_CLKSRC __BITS(2, 0) 110191762Simp#define BWI_CLOCK_CTRL_SLOW __BIT(11) 111191762Simp#define BWI_CLOCK_CTRL_IGNPLL __BIT(12) 112191762Simp#define BWI_CLOCK_CTRL_NODYN __BIT(13) 113191762Simp#define BWI_CLOCK_CTRL_FDIV __BITS(31, 16) /* freq divisor */ 114191762Simp 115191762Simp/* Possible values for BWI_CLOCK_CTRL_CLKSRC */ 116191762Simp#define BWI_CLKSRC_LP_OSC 0 /* Low power oscillator */ 117191762Simp#define BWI_CLKSRC_CS_OSC 1 /* Crystal oscillator */ 118191762Simp#define BWI_CLKSRC_PCI 2 119191762Simp#define BWI_CLKSRC_MAX 3 /* Maximum of clock source */ 120191762Simp/* Min/Max frequency for given clock source */ 121191762Simp#define BWI_CLKSRC_LP_OSC_FMIN 25000 122191762Simp#define BWI_CLKSRC_LP_OSC_FMAX 43000 123191762Simp#define BWI_CLKSRC_CS_OSC_FMIN 19800000 124191762Simp#define BWI_CLKSRC_CS_OSC_FMAX 20200000 125191762Simp#define BWI_CLKSRC_PCI_FMIN 25000000 126191762Simp#define BWI_CLKSRC_PCI_FMAX 34000000 127191762Simp 128191762Simp#define BWI_CLOCK_INFO 0xc0 129191762Simp#define BWI_CLOCK_INFO_FDIV __BITS(31, 16) /* freq divisor */ 130191762Simp 131191762Simp/* 132191762Simp * Registers for bus register window 133191762Simp */ 134191762Simp#define BWI_BUS_ADDR 0x50 135191762Simp#define BWI_BUS_ADDR_MAGIC 0xfd8 136191762Simp 137191762Simp#define BWI_BUS_DATA 0x54 138191762Simp 139191762Simp#define BWI_BUS_CONFIG 0x108 140191762Simp#define BWI_BUS_CONFIG_PREFETCH __BIT(2) 141191762Simp#define BWI_BUS_CONFIG_BURST __BIT(3) 142191762Simp#define BWI_BUS_CONFIG_MRM __BIT(5) 143191762Simp 144191762Simp/* 145191762Simp * Register for MAC 146191762Simp */ 147191762Simp#define BWI_TXRX_INTR_STATUS_BASE 0x20 148191762Simp#define BWI_TXRX_INTR_MASK_BASE 0x24 149191762Simp#define BWI_TXRX_INTR_STATUS(i) (BWI_TXRX_INTR_STATUS_BASE + ((i) * 8)) 150191762Simp#define BWI_TXRX_INTR_MASK(i) (BWI_TXRX_INTR_MASK_BASE + ((i) * 8)) 151191762Simp 152191762Simp#define BWI_MAC_STATUS 0x120 153191762Simp#define BWI_MAC_STATUS_ENABLE __BIT(0) 154191762Simp#define BWI_MAC_STATUS_UCODE_START __BIT(1) 155191762Simp#define BWI_MAC_STATUS_UCODE_JUMP0 __BIT(2) 156191762Simp#define BWI_MAC_STATUS_IHREN __BIT(10) 157191762Simp#define BWI_MAC_STATUS_GPOSEL_MASK __BITS(15, 14) 158191762Simp#define BWI_MAC_STATUS_BSWAP __BIT(16) 159191762Simp#define BWI_MAC_STATUS_INFRA __BIT(17) 160191762Simp#define BWI_MAC_STATUS_OPMODE_HOSTAP __BIT(18) 161191762Simp#define BWI_MAC_STATUS_RFLOCK __BIT(19) 162191762Simp#define BWI_MAC_STATUS_PASS_BCN __BIT(20) 163191762Simp#define BWI_MAC_STATUS_PASS_BADPLCP __BIT(21) 164191762Simp#define BWI_MAC_STATUS_PASS_CTL __BIT(22) 165191762Simp#define BWI_MAC_STATUS_PASS_BADFCS __BIT(23) 166191762Simp#define BWI_MAC_STATUS_PROMISC __BIT(24) 167191762Simp#define BWI_MAC_STATUS_HW_PS __BIT(25) 168191762Simp#define BWI_MAC_STATUS_WAKEUP __BIT(26) 169191762Simp#define BWI_MAC_STATUS_PHYLNK __BIT(31) 170191762Simp 171191762Simp#define BWI_MAC_INTR_STATUS 0x128 172191762Simp#define BWI_MAC_INTR_MASK 0x12c 173191762Simp 174191762Simp#define BWI_MAC_TMPLT_CTRL 0x130 175191762Simp#define BWI_MAC_TMPLT_DATA 0x134 176191762Simp 177191762Simp#define BWI_MAC_PS_STATUS 0x140 178191762Simp 179191762Simp#define BWI_MOBJ_CTRL 0x160 180191762Simp#define BWI_MOBJ_CTRL_VAL(objid, ofs) ((objid) << 16 | (ofs)) 181191762Simp#define BWI_MOBJ_DATA 0x164 182191762Simp#define BWI_MOBJ_DATA_UNALIGN 0x166 183191762Simp/* 184191762Simp * Memory object IDs 185191762Simp */ 186191762Simp#define BWI_WR_MOBJ_AUTOINC 0x100 /* Auto-increment wr */ 187191762Simp#define BWI_RD_MOBJ_AUTOINC 0x200 /* Auto-increment rd */ 188191762Simp/* Firmware ucode object */ 189191762Simp#define BWI_FW_UCODE_MOBJ 0x0 190191762Simp/* Common object */ 191191762Simp#define BWI_COMM_MOBJ 0x1 192191762Simp#define BWI_COMM_MOBJ_FWREV 0x0 193191762Simp#define BWI_COMM_MOBJ_FWPATCHLV 0x2 194191762Simp#define BWI_COMM_MOBJ_SLOTTIME 0x10 195191762Simp#define BWI_COMM_MOBJ_MACREV 0x16 196191762Simp#define BWI_COMM_MOBJ_TX_ACK 0x22 197191762Simp#define BWI_COMM_MOBJ_UCODE_STATE 0x40 198191762Simp#define BWI_COMM_MOBJ_SHRETRY_FB 0x44 199191762Simp#define BWI_COMM_MOBJ_LGRETEY_FB 0x46 200191762Simp#define BWI_COMM_MOBJ_TX_BEACON 0x54 201191762Simp#define BWI_COMM_MOBJ_KEYTABLE_OFS 0x56 202191762Simp#define BWI_COMM_MOBJ_TSSI_DS 0x58 203191762Simp#define BWI_COMM_MOBJ_HFLAGS_LO 0x5e 204191762Simp#define BWI_COMM_MOBJ_HFLAGS_MI 0x60 205191762Simp#define BWI_COMM_MOBJ_HFLAGS_HI 0x62 206191762Simp#define BWI_COMM_MOBJ_RF_ATTEN 0x64 207191762Simp#define BWI_COMM_MOBJ_RF_NOISE 0x6e 208191762Simp#define BWI_COMM_MOBJ_TSSI_OFDM 0x70 209191762Simp#define BWI_COMM_MOBJ_PROBE_RESP_TO 0x74 210191762Simp#define BWI_COMM_MOBJ_CHAN 0xa0 211191762Simp#define BWI_COMM_MOBJ_KEY_ALGO 0x100 212191762Simp#define BWI_COMM_MOBJ_TX_PROBE_RESP 0x188 213191762Simp#define BWI_HFLAG_AUTO_ANTDIV 0x1ULL 214191762Simp#define BWI_HFLAG_SYM_WA 0x2ULL /* ??? SYM work around */ 215191762Simp#define BWI_HFLAG_PWR_BOOST_DS 0x8ULL 216191762Simp#define BWI_HFLAG_GDC_WA 0x20ULL /* ??? GDC work around */ 217191762Simp#define BWI_HFLAG_OFDM_PA 0x40ULL 218191762Simp#define BWI_HFLAG_NOT_JAPAN 0x80ULL 219191762Simp#define BWI_HFLAG_MAGIC1 0x200ULL 220191762Simp#define BWI_UCODE_STATE_PS 4 221191762Simp#define BWI_LO_TSSI_MASK __BITS(7, 0) 222191762Simp#define BWI_HI_TSSI_MASK __BITS(15, 8) 223191762Simp#define BWI_INVALID_TSSI 0x7f 224191762Simp/* 802.11 object */ 225191762Simp#define BWI_80211_MOBJ 0x2 226191762Simp#define BWI_80211_MOBJ_CWMIN 0xc 227191762Simp#define BWI_80211_MOBJ_CWMAX 0x10 228191762Simp#define BWI_80211_MOBJ_SHRETRY 0x18 229191762Simp#define BWI_80211_MOBJ_LGRETRY 0x1c 230191762Simp/* Firmware PCM object */ 231191762Simp#define BWI_FW_PCM_MOBJ 0x3 232191762Simp/* MAC address of pairwise keys */ 233191762Simp#define BWI_PKEY_ADDR_MOBJ 0x4 234191762Simp 235191762Simp#define BWI_TXSTATUS0 0x170 236191762Simp#define BWI_TXSTATUS0_VALID __BIT(0) 237191762Simp#define BWI_TXSTATUS0_ACKED __BIT(1) 238191762Simp#define BWI_TXSTATUS0_FREASON_MASK __BITS(4, 2) /* Failure reason */ 239191762Simp#define BWI_TXSTATUS0_AMPDU __BIT(5) 240191762Simp#define BWI_TXSTATUS0_PENDING __BIT(6) 241191762Simp#define BWI_TXSTATUS0_PM __BIT(7) 242191762Simp#define BWI_TXSTATUS0_RTS_TXCNT_MASK __BITS(11, 8) 243191762Simp#define BWI_TXSTATUS0_DATA_TXCNT_MASK __BITS(15, 12) 244191762Simp#define BWI_TXSTATUS0_TXID_MASK __BITS(31, 16) 245191762Simp#define BWI_TXSTATUS1 0x174 246191762Simp 247191762Simp#define BWI_TXRX_CTRL_BASE 0x200 248191762Simp#define BWI_TX32_CTRL 0x0 249191762Simp#define BWI_TX32_RINGINFO 0x4 250191762Simp#define BWI_TX32_INDEX 0x8 251191762Simp#define BWI_TX32_STATUS 0xc 252191762Simp#define BWI_TX32_STATUS_STATE_MASK __BITS(15, 12) 253191762Simp#define BWI_TX32_STATUS_STATE_DISABLED 0 254191762Simp#define BWI_TX32_STATUS_STATE_IDLE 2 255191762Simp#define BWI_TX32_STATUS_STATE_STOPPED 3 256191762Simp#define BWI_RX32_CTRL 0x10 257191762Simp#define BWI_RX32_CTRL_HDRSZ_MASK __BITS(7, 1) 258191762Simp#define BWI_RX32_RINGINFO 0x14 259191762Simp#define BWI_RX32_INDEX 0x18 260191762Simp#define BWI_RX32_STATUS 0x1c 261191762Simp#define BWI_RX32_STATUS_INDEX_MASK __BITS(11, 0) 262191762Simp#define BWI_RX32_STATUS_STATE_MASK __BITS(15, 12) 263191762Simp#define BWI_RX32_STATUS_STATE_DISABLED 0 264191762Simp/* Shared by 32bit TX/RX CTRL */ 265191762Simp#define BWI_TXRX32_CTRL_ENABLE __BIT(0) 266191762Simp#define BWI_TXRX32_CTRL_ADDRHI_MASK __BITS(17, 16) 267191762Simp/* Shared by 32bit TX/RX RINGINFO */ 268191762Simp#define BWI_TXRX32_RINGINFO_FUNC_TXRX 0x1 269191762Simp#define BWI_TXRX32_RINGINFO_FUNC_MASK __BITS(31, 30) 270191762Simp#define BWI_TXRX32_RINGINFO_ADDR_MASK __BITS(29, 0) 271191762Simp 272191762Simp#define BWI_PHYINFO 0x3e0 273191762Simp#define BWI_PHYINFO_REV_MASK __BITS(3, 0) 274191762Simp#define BWI_PHYINFO_TYPE_MASK __BITS(11, 8) 275191762Simp#define BWI_PHYINFO_TYPE_11A 0 276191762Simp#define BWI_PHYINFO_TYPE_11B 1 277191762Simp#define BWI_PHYINFO_TYPE_11G 2 278192279Simp#define BWI_PHYINFO_TYPE_11N 4 279192279Simp#define BWI_PHYINFO_TYPE_11LP 5 280191762Simp#define BWI_PHYINFO_VER_MASK __BITS(15, 12) 281191762Simp 282191762Simp#define BWI_RF_ANTDIV 0x3e2 /* Antenna Diversity?? */ 283191762Simp 284191762Simp#define BWI_PHY_MAGIC_REG1 0x3e4 285191762Simp#define BWI_PHY_MAGIC_REG1_VAL1 0x3000 286191762Simp#define BWI_PHY_MAGIC_REG1_VAL2 0x9 287191762Simp 288191762Simp#define BWI_BBP_ATTEN 0x3e6 289191762Simp#define BWI_BBP_ATTEN_MAGIC 0xf4 290191762Simp#define BWI_BBP_ATTEN_MAGIC2 0x8140 291191762Simp 292191762Simp#define BWI_BPHY_CTRL 0x3ec 293191762Simp#define BWI_BPHY_CTRL_INIT 0x3f22 294191762Simp 295191762Simp#define BWI_RF_CHAN 0x3f0 296191762Simp#define BWI_RF_CHAN_EX 0x3f4 297191762Simp 298191762Simp#define BWI_RF_CTRL 0x3f6 299191762Simp/* Register values for BWI_RF_CTRL */ 300191762Simp#define BWI_RF_CTRL_RFINFO 0x1 301191762Simp/* XXX extra bits for reading from radio */ 302191762Simp#define BWI_RF_CTRL_RD_11A 0x40 303191762Simp#define BWI_RF_CTRL_RD_11BG 0x80 304191762Simp#define BWI_RF_DATA_HI 0x3f8 305191762Simp#define BWI_RF_DATA_LO 0x3fa 306191762Simp/* Values read from BWI_RF_DATA_{HI,LO} after BWI_RF_CTRL_RFINFO */ 307191762Simp#define BWI_RFINFO_MANUFACT_MASK __BITS(11, 0) 308191762Simp#define BWI_RF_MANUFACT_BCM 0x17f /* XXX */ 309191762Simp#define BWI_RFINFO_TYPE_MASK __BITS(27, 12) 310191762Simp#define BWI_RF_T_BCM2050 0x2050 311191762Simp#define BWI_RF_T_BCM2053 0x2053 312191762Simp#define BWI_RF_T_BCM2060 0x2060 313191762Simp#define BWI_RFINFO_REV_MASK __BITS(31, 28) 314191762Simp 315191762Simp#define BWI_PHY_CTRL 0x3fc 316191762Simp#define BWI_PHY_DATA 0x3fe 317191762Simp 318191762Simp#define BWI_ADDR_FILTER_CTRL 0x420 319191762Simp#define BWI_ADDR_FILTER_CTRL_SET 0x20 320191762Simp#define BWI_ADDR_FILTER_MYADDR 0 321191762Simp#define BWI_ADDR_FILTER_BSSID 3 322191762Simp#define BWI_ADDR_FILTER_DATA 0x422 323191762Simp 324191762Simp#define BWI_MAC_GPIO_CTRL 0x49c 325191762Simp#define BWI_MAC_GPIO_MASK 0x49e 326191762Simp#define BWI_MAC_PRE_TBTT 0x612 327191762Simp#define BWI_MAC_SLOTTIME 0x684 328191762Simp#define BWI_MAC_SLOTTIME_ADJUST 510 329191762Simp#define BWI_MAC_POWERUP_DELAY 0x6a8 330191762Simp 331191762Simp/* 332191762Simp * Special registers 333191762Simp */ 334191762Simp/* 335191762Simp * GPIO control 336191762Simp * If common regwin exists, then it is within common regwin, 337191762Simp * else it is in bus regwin. 338191762Simp */ 339191762Simp#define BWI_GPIO_CTRL 0x6c 340191762Simp 341191762Simp#define PCI_VENDOR_BROADCOM 0x14e4 /* Broadcom */ 342191762Simp#define PCI_PRODUCT_BROADCOM_BCM4309 0x4324 343191762Simp 344191762Simp/* 345191762Simp * Extended PCI registers 346191762Simp */ 347191762Simp#define BWI_PCIR_BAR PCIR_BAR(0) 348191762Simp#define BWI_PCIR_SEL_REGWIN 0x80 349191762Simp/* Register value for BWI_PCIR_SEL_REGWIN */ 350191762Simp#define BWI_PCIM_REGWIN(id) (((id) * 0x1000) + 0x18000000) 351191762Simp#define BWI_PCIR_GPIO_IN 0xb0 352191762Simp#define BWI_PCIR_GPIO_OUT 0xb4 353191762Simp#define BWI_PCIM_GPIO_OUT_CLKSRC __BIT(4) 354191762Simp#define BWI_PCIR_GPIO_ENABLE 0xb8 355191762Simp/* Register values for BWI_PCIR_GPIO_{IN,OUT,ENABLE} */ 356191762Simp#define BWI_PCIM_GPIO_PWR_ON __BIT(6) 357191762Simp#define BWI_PCIM_GPIO_PLL_PWR_OFF __BIT(7) 358191762Simp#define BWI_PCIR_INTCTL 0x94 359191762Simp 360191762Simp/* 361191762Simp * PCI subdevice IDs 362191762Simp */ 363191762Simp#define BWI_PCI_SUBDEVICE_BU4306 0x416 364191762Simp#define BWI_PCI_SUBDEVICE_BCM4309G 0x421 365191762Simp 366191762Simp#define BWI_IS_BRCM_BU4306(sc) \ 367191762Simp ((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \ 368191762Simp (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BU4306) 369191762Simp#define BWI_IS_BRCM_BCM4309G(sc) \ 370191762Simp ((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \ 371191762Simp (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BCM4309G) 372191762Simp 373191762Simp/* 374191762Simp * EEPROM start address 375191762Simp */ 376191762Simp#define BWI_SPROM_START 0x1000 377191762Simp#define BWI_SPROM_11BG_EADDR 0x48 378191762Simp#define BWI_SPROM_11A_EADDR 0x54 379191762Simp#define BWI_SPROM_CARD_INFO 0x5c 380191762Simp#define BWI_SPROM_CARD_INFO_LOCALE __BITS(11, 8) 381191762Simp#define BWI_SPROM_LOCALE_JAPAN 5 382191762Simp#define BWI_SPROM_PA_PARAM_11BG 0x5e 383191762Simp#define BWI_SPROM_GPIO01 0x64 384191762Simp#define BWI_SPROM_GPIO_0 __BITS(7, 0) 385191762Simp#define BWI_SPROM_GPIO_1 __BITS(15, 8) 386191762Simp#define BWI_SPROM_GPIO23 0x66 387191762Simp#define BWI_SPROM_GPIO_2 __BITS(7, 0) 388191762Simp#define BWI_SPROM_GPIO_3 __BITS(15, 8) 389191762Simp#define BWI_SPROM_MAX_TXPWR 0x68 390191762Simp#define BWI_SPROM_MAX_TXPWR_MASK_11BG __BITS(7, 0) /* XXX */ 391191762Simp#define BWI_SPROM_MAX_TXPWR_MASK_11A __BITS(15, 8) /* XXX */ 392191762Simp#define BWI_SPROM_PA_PARAM_11A 0x6a 393191762Simp#define BWI_SPROM_IDLE_TSSI 0x70 394191762Simp#define BWI_SPROM_IDLE_TSSI_MASK_11BG __BITS(7, 0) /* XXX */ 395191762Simp#define BWI_SPROM_IDLE_TSSI_MASK_11A __BITS(15, 8) /* XXX */ 396191762Simp#define BWI_SPROM_CARD_FLAGS 0x72 397191762Simp#define BWI_SPROM_ANT_GAIN 0x74 398191762Simp#define BWI_SPROM_ANT_GAIN_MASK_11A __BITS(7, 0) 399191762Simp#define BWI_SPROM_ANT_GAIN_MASK_11BG __BITS(15, 8) 400191762Simp 401191762Simp/* 402191762Simp * SPROM card flags 403191762Simp */ 404191762Simp#define BWI_CARD_F_BT_COEXIST __BIT(0) /* Bluetooth coexist */ 405191762Simp#define BWI_CARD_F_PA_GPIO9 __BIT(1) /* GPIO 9 controls PA */ 406191762Simp#define BWI_CARD_F_SW_NRSSI __BIT(3) 407191762Simp#define BWI_CARD_F_NO_SLOWCLK __BIT(5) /* no slow clock */ 408191762Simp#define BWI_CARD_F_EXT_LNA __BIT(12) /* external LNA */ 409191762Simp#define BWI_CARD_F_ALT_IQ __BIT(15) /* alternate I/Q */ 410191762Simp 411191762Simp/* 412191762Simp * SPROM GPIO 413191762Simp */ 414191762Simp#define BWI_LED_ACT_LOW __BIT(7) 415191762Simp#define BWI_LED_ACT_MASK __BITS(6, 0) 416191762Simp#define BWI_LED_ACT_OFF 0 417191762Simp#define BWI_LED_ACT_ON 1 418191762Simp#define BWI_LED_ACT_BLINK 2 419191762Simp#define BWI_LED_ACT_RF_ENABLED 3 420191762Simp#define BWI_LED_ACT_5GHZ 4 421191762Simp#define BWI_LED_ACT_2GHZ 5 422191762Simp#define BWI_LED_ACT_11G 6 423191762Simp#define BWI_LED_ACT_BLINK_SLOW 7 424191762Simp#define BWI_LED_ACT_BLINK_POLL 8 425191762Simp#define BWI_LED_ACT_UNKN 9 426191762Simp#define BWI_LED_ACT_ASSOC 10 427191762Simp#define BWI_LED_ACT_NULL 11 428191762Simp 429191762Simp#define BWI_VENDOR_LED_ACT_COMPAQ \ 430191762Simp BWI_LED_ACT_RF_ENABLED, \ 431191762Simp BWI_LED_ACT_2GHZ, \ 432191762Simp BWI_LED_ACT_5GHZ, \ 433191762Simp BWI_LED_ACT_OFF 434191762Simp 435191762Simp#define BWI_VENDOR_LED_ACT_LINKSYS \ 436191762Simp BWI_LED_ACT_ASSOC, \ 437191762Simp BWI_LED_ACT_2GHZ, \ 438191762Simp BWI_LED_ACT_5GHZ, \ 439191762Simp BWI_LED_ACT_OFF 440191762Simp 441191762Simp#define BWI_VENDOR_LED_ACT_DEFAULT \ 442191762Simp BWI_LED_ACT_BLINK, \ 443191762Simp BWI_LED_ACT_2GHZ, \ 444191762Simp BWI_LED_ACT_5GHZ, \ 445191762Simp BWI_LED_ACT_OFF 446191762Simp 447191762Simp/* 448191762Simp * BBP IDs 449191762Simp */ 450191762Simp#define BWI_BBPID_BCM4301 0x4301 451191762Simp#define BWI_BBPID_BCM4306 0x4306 452191762Simp#define BWI_BBPID_BCM4317 0x4317 453191762Simp#define BWI_BBPID_BCM4320 0x4320 454191762Simp#define BWI_BBPID_BCM4321 0x4321 455191762Simp 456191762Simp/* 457191762Simp * Register window types 458191762Simp */ 459191762Simp#define BWI_REGWIN_T_COM 0x800 460191762Simp#define BWI_REGWIN_T_BUSPCI 0x804 461191762Simp#define BWI_REGWIN_T_MAC 0x812 462191762Simp#define BWI_REGWIN_T_BUSPCIE 0x820 463191762Simp 464191762Simp/* 465191762Simp * MAC interrupts 466191762Simp */ 467191762Simp#define BWI_INTR_READY __BIT(0) 468191762Simp#define BWI_INTR_BEACON __BIT(1) 469191762Simp#define BWI_INTR_TBTT __BIT(2) 470191762Simp#define BWI_INTR_EO_ATIM __BIT(5) /* End of ATIM */ 471191762Simp#define BWI_INTR_PMQ __BIT(6) /* XXX?? */ 472191762Simp#define BWI_INTR_MAC_TXERR __BIT(9) 473191762Simp#define BWI_INTR_PHY_TXERR __BIT(11) 474191762Simp#define BWI_INTR_TIMER1 __BIT(14) 475191762Simp#define BWI_INTR_RX_DONE __BIT(15) 476191762Simp#define BWI_INTR_TX_FIFO __BIT(16) /* XXX?? */ 477191762Simp#define BWI_INTR_NOISE __BIT(18) 478191762Simp#define BWI_INTR_RF_DISABLED __BIT(28) 479191762Simp#define BWI_INTR_TX_DONE __BIT(29) 480191762Simp 481191762Simp#define BWI_INIT_INTRS \ 482191762Simp (BWI_INTR_READY | BWI_INTR_BEACON | BWI_INTR_TBTT | \ 483191762Simp BWI_INTR_EO_ATIM | BWI_INTR_PMQ | BWI_INTR_MAC_TXERR | \ 484191762Simp BWI_INTR_PHY_TXERR | BWI_INTR_RX_DONE | BWI_INTR_TX_FIFO | \ 485191762Simp BWI_INTR_NOISE | BWI_INTR_RF_DISABLED | BWI_INTR_TX_DONE) 486191762Simp#define BWI_ALL_INTRS 0xffffffff 487191762Simp 488191762Simp/* 489191762Simp * TX/RX interrupts 490191762Simp */ 491191762Simp#define BWI_TXRX_INTR_ERROR (__BIT(15) | __BIT(14) | __BITS(12, 10)) 492191762Simp#define BWI_TXRX_INTR_RX __BIT(16) 493191762Simp#define BWI_TXRX_TX_INTRS BWI_TXRX_INTR_ERROR 494191762Simp#define BWI_TXRX_RX_INTRS (BWI_TXRX_INTR_ERROR | BWI_TXRX_INTR_RX) 495191762Simp#define BWI_TXRX_IS_RX(i) ((i) % 3 == 0) 496191762Simp 497191762Simp#endif /* !_IF_BWIREG_H */ 498