if_bgereg.h revision 92934
1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 92934 2002-03-22 06:45:40Z wpaul $ 34 */ 35 36/* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 */ 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SOFTWARE_GENCOMM 0x00000B50 75#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 76#define BGE_UNMAPPED 0x00001000 77#define BGE_UNMAPPED_END 0x00001FFF 78#define BGE_DMA_DESCRIPTORS 0x00002000 79#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 80#define BGE_SEND_RING_1_TO_4 0x00004000 81#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 82 83/* Mappings for internal memory configuration */ 84#define BGE_STD_RX_RINGS 0x00006000 85#define BGE_STD_RX_RINGS_END 0x00006FFF 86#define BGE_JUMBO_RX_RINGS 0x00007000 87#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 88#define BGE_BUFFPOOL_1 0x00008000 89#define BGE_BUFFPOOL_1_END 0x0000FFFF 90#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 91#define BGE_BUFFPOOL_2_END 0x00017FFF 92#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 93#define BGE_BUFFPOOL_3_END 0x0001FFFF 94 95/* Mappings for external SSRAM configurations */ 96#define BGE_SEND_RING_5_TO_6 0x00006000 97#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 98#define BGE_SEND_RING_7_TO_8 0x00007000 99#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 100#define BGE_SEND_RING_9_TO_16 0x00008000 101#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 102#define BGE_EXT_STD_RX_RINGS 0x0000C000 103#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 104#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 105#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 106#define BGE_MINI_RX_RINGS 0x0000E000 107#define BGE_MINI_RX_RINGS_END 0x0000FFFF 108#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 109#define BGE_AVAIL_REGION1_END 0x00017FFF 110#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 111#define BGE_AVAIL_REGION2_END 0x0001FFFF 112#define BGE_EXT_SSRAM 0x00020000 113#define BGE_EXT_SSRAM_END 0x000FFFFF 114 115 116/* 117 * BCM570x register offsets. These are memory mapped registers 118 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 119 * Each register must be accessed using 32 bit operations. 120 * 121 * All registers are accessed through a 32K shared memory block. 122 * The first group of registers are actually copies of the PCI 123 * configuration space registers. 124 */ 125 126/* 127 * PCI registers defined in the PCI 2.2 spec. 128 */ 129#define BGE_PCI_VID 0x00 130#define BGE_PCI_DID 0x02 131#define BGE_PCI_CMD 0x04 132#define BGE_PCI_STS 0x06 133#define BGE_PCI_REV 0x08 134#define BGE_PCI_CLASS 0x09 135#define BGE_PCI_CACHESZ 0x0C 136#define BGE_PCI_LATTIMER 0x0D 137#define BGE_PCI_HDRTYPE 0x0E 138#define BGE_PCI_BIST 0x0F 139#define BGE_PCI_BAR0 0x10 140#define BGE_PCI_BAR1 0x14 141#define BGE_PCI_SUBSYS 0x2C 142#define BGE_PCI_SUBVID 0x2E 143#define BGE_PCI_ROMBASE 0x30 144#define BGE_PCI_CAPPTR 0x34 145#define BGE_PCI_INTLINE 0x3C 146#define BGE_PCI_INTPIN 0x3D 147#define BGE_PCI_MINGNT 0x3E 148#define BGE_PCI_MAXLAT 0x3F 149#define BGE_PCI_PCIXCAP 0x40 150#define BGE_PCI_NEXTPTR_PM 0x41 151#define BGE_PCI_PCIX_CMD 0x42 152#define BGE_PCI_PCIX_STS 0x44 153#define BGE_PCI_PWRMGMT_CAPID 0x48 154#define BGE_PCI_NEXTPTR_VPD 0x49 155#define BGE_PCI_PWRMGMT_CAPS 0x4A 156#define BGE_PCI_PWRMGMT_CMD 0x4C 157#define BGE_PCI_PWRMGMT_STS 0x4D 158#define BGE_PCI_PWRMGMT_DATA 0x4F 159#define BGE_PCI_VPD_CAPID 0x50 160#define BGE_PCI_NEXTPTR_MSI 0x51 161#define BGE_PCI_VPD_ADDR 0x52 162#define BGE_PCI_VPD_DATA 0x54 163#define BGE_PCI_MSI_CAPID 0x58 164#define BGE_PCI_NEXTPTR_NONE 0x59 165#define BGE_PCI_MSI_CTL 0x5A 166#define BGE_PCI_MSI_ADDR_HI 0x5C 167#define BGE_PCI_MSI_ADDR_LO 0x60 168#define BGE_PCI_MSI_DATA 0x64 169 170/* 171 * PCI registers specific to the BCM570x family. 172 */ 173#define BGE_PCI_MISC_CTL 0x68 174#define BGE_PCI_DMA_RW_CTL 0x6C 175#define BGE_PCI_PCISTATE 0x70 176#define BGE_PCI_CLKCTL 0x74 177#define BGE_PCI_REG_BASEADDR 0x78 178#define BGE_PCI_MEMWIN_BASEADDR 0x7C 179#define BGE_PCI_REG_DATA 0x80 180#define BGE_PCI_MEMWIN_DATA 0x84 181#define BGE_PCI_MODECTL 0x88 182#define BGE_PCI_MISC_CFG 0x8C 183#define BGE_PCI_MISC_LOCALCTL 0x90 184#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 185#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 186#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 187#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 188#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 189#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 190#define BGE_PCI_ISR_MBX_HI 0xB0 191#define BGE_PCI_ISR_MBX_LO 0xB4 192 193/* PCI Misc. Host control register */ 194#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 195#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 196#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 197#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 198#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 199#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 200#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 201#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 202#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 203 204#define BGE_BIGENDIAN_INIT \ 205 (BGE_BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 206 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 207 BGE_PCIMISCCTL_INDIRECT_ACCESS|PCIMISCCTL_MASK_PCI_INTR) 208 209#define BGE_LITTLEENDIAN_INIT \ 210 (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 211 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 212 213#define BGE_ASICREV_TIGON_I 0x40000000 214#define BGE_ASICREV_TIGON_II 0x60000000 215#define BGE_ASICREV_BCM5700_B0 0x71000000 216#define BGE_ASICREV_BCM5700_B1 0x71020000 217#define BGE_ASICREV_BCM5700_B2 0x71030000 218#define BGE_ASICREV_BCM5700_ALTIMA 0x71040000 219#define BGE_ASICREV_BCM5700_C0 0x72000000 220#define BGE_ASICREV_BCM5701_A0 0x00000000 /* grrrr */ 221#define BGE_ASICREV_BCM5701_B0 0x01000000 222#define BGE_ASICREV_BCM5701_B2 0x01020000 223#define BGE_ASICREV_BCM5701_B5 0x01050000 224 225/* PCI DMA Read/Write Control register */ 226#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 227#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 228#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 229#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 230#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 231#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 232#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 233#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 234#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 235#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 236 237#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 238#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 239#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 240#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 241#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 242#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 243#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 244#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 245 246#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 247#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 248#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 249#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 250#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 251#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 252#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 253#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 254 255/* 256 * PCI state register -- note, this register is read only 257 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 258 * register is set. 259 */ 260#define BGE_PCISTATE_FORCE_RESET 0x00000001 261#define BGE_PCISTATE_INTR_STATE 0x00000002 262#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 263#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 264#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 265#define BGE_PCISTATE_WANT_EXPROM 0x00000020 266#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 267#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 268#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 269 270/* 271 * PCI Clock Control register -- note, this register is read only 272 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 273 * register is set. 274 */ 275#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 276#define BGE_PCICLOCKCTL_M66EN 0x00000080 277#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 278#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 279#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 280#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 281#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 282#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 283#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 284#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 285 286 287#ifndef PCIM_CMD_MWIEN 288#define PCIM_CMD_MWIEN 0x0010 289#endif 290 291/* 292 * High priority mailbox registers 293 * Each mailbox is 64-bits wide, though we only use the 294 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 295 * first. The NIC will load the mailbox after the lower 32 bit word 296 * has been updated. 297 */ 298#define BGE_MBX_IRQ0_HI 0x0200 299#define BGE_MBX_IRQ0_LO 0x0204 300#define BGE_MBX_IRQ1_HI 0x0208 301#define BGE_MBX_IRQ1_LO 0x020C 302#define BGE_MBX_IRQ2_HI 0x0210 303#define BGE_MBX_IRQ2_LO 0x0214 304#define BGE_MBX_IRQ3_HI 0x0218 305#define BGE_MBX_IRQ3_LO 0x021C 306#define BGE_MBX_GEN0_HI 0x0220 307#define BGE_MBX_GEN0_LO 0x0224 308#define BGE_MBX_GEN1_HI 0x0228 309#define BGE_MBX_GEN1_LO 0x022C 310#define BGE_MBX_GEN2_HI 0x0230 311#define BGE_MBX_GEN2_LO 0x0234 312#define BGE_MBX_GEN3_HI 0x0228 313#define BGE_MBX_GEN3_LO 0x022C 314#define BGE_MBX_GEN4_HI 0x0240 315#define BGE_MBX_GEN4_LO 0x0244 316#define BGE_MBX_GEN5_HI 0x0248 317#define BGE_MBX_GEN5_LO 0x024C 318#define BGE_MBX_GEN6_HI 0x0250 319#define BGE_MBX_GEN6_LO 0x0254 320#define BGE_MBX_GEN7_HI 0x0258 321#define BGE_MBX_GEN7_LO 0x025C 322#define BGE_MBX_RELOAD_STATS_HI 0x0260 323#define BGE_MBX_RELOAD_STATS_LO 0x0264 324#define BGE_MBX_RX_STD_PROD_HI 0x0268 325#define BGE_MBX_RX_STD_PROD_LO 0x026C 326#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 327#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 328#define BGE_MBX_RX_MINI_PROD_HI 0x0278 329#define BGE_MBX_RX_MINI_PROD_LO 0x027C 330#define BGE_MBX_RX_CONS0_HI 0x0280 331#define BGE_MBX_RX_CONS0_LO 0x0284 332#define BGE_MBX_RX_CONS1_HI 0x0288 333#define BGE_MBX_RX_CONS1_LO 0x028C 334#define BGE_MBX_RX_CONS2_HI 0x0290 335#define BGE_MBX_RX_CONS2_LO 0x0294 336#define BGE_MBX_RX_CONS3_HI 0x0298 337#define BGE_MBX_RX_CONS3_LO 0x029C 338#define BGE_MBX_RX_CONS4_HI 0x02A0 339#define BGE_MBX_RX_CONS4_LO 0x02A4 340#define BGE_MBX_RX_CONS5_HI 0x02A8 341#define BGE_MBX_RX_CONS5_LO 0x02AC 342#define BGE_MBX_RX_CONS6_HI 0x02B0 343#define BGE_MBX_RX_CONS6_LO 0x02B4 344#define BGE_MBX_RX_CONS7_HI 0x02B8 345#define BGE_MBX_RX_CONS7_LO 0x02BC 346#define BGE_MBX_RX_CONS8_HI 0x02C0 347#define BGE_MBX_RX_CONS8_LO 0x02C4 348#define BGE_MBX_RX_CONS9_HI 0x02C8 349#define BGE_MBX_RX_CONS9_LO 0x02CC 350#define BGE_MBX_RX_CONS10_HI 0x02D0 351#define BGE_MBX_RX_CONS10_LO 0x02D4 352#define BGE_MBX_RX_CONS11_HI 0x02D8 353#define BGE_MBX_RX_CONS11_LO 0x02DC 354#define BGE_MBX_RX_CONS12_HI 0x02E0 355#define BGE_MBX_RX_CONS12_LO 0x02E4 356#define BGE_MBX_RX_CONS13_HI 0x02E8 357#define BGE_MBX_RX_CONS13_LO 0x02EC 358#define BGE_MBX_RX_CONS14_HI 0x02F0 359#define BGE_MBX_RX_CONS14_LO 0x02F4 360#define BGE_MBX_RX_CONS15_HI 0x02F8 361#define BGE_MBX_RX_CONS15_LO 0x02FC 362#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 363#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 364#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 365#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 366#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 367#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 368#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 369#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 370#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 371#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 372#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 373#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 374#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 375#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 376#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 377#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 378#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 379#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 380#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 381#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 382#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 383#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 384#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 385#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 386#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 387#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 388#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 389#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 390#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 391#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 392#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 393#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 394#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 395#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 396#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 397#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 398#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 399#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 400#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 401#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 402#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 403#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 404#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 405#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 406#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 407#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 408#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 409#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 410#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 411#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 412#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 413#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 414#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 415#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 416#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 417#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 418#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 419#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 420#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 421#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 422#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 423#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 424#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 425#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 426 427#define BGE_TX_RINGS_MAX 4 428#define BGE_TX_RINGS_EXTSSRAM_MAX 16 429#define BGE_RX_RINGS_MAX 16 430 431/* Ethernet MAC control registers */ 432#define BGE_MAC_MODE 0x0400 433#define BGE_MAC_STS 0x0404 434#define BGE_MAC_EVT_ENB 0x0408 435#define BGE_MAC_LED_CTL 0x040C 436#define BGE_MAC_ADDR1_LO 0x0410 437#define BGE_MAC_ADDR1_HI 0x0414 438#define BGE_MAC_ADDR2_LO 0x0418 439#define BGE_MAC_ADDR2_HI 0x041C 440#define BGE_MAC_ADDR3_LO 0x0420 441#define BGE_MAC_ADDR3_HI 0x0424 442#define BGE_MAC_ADDR4_LO 0x0428 443#define BGE_MAC_ADDR4_HI 0x042C 444#define BGE_WOL_PATPTR 0x0430 445#define BGE_WOL_PATCFG 0x0434 446#define BGE_TX_RANDOM_BACKOFF 0x0438 447#define BGE_RX_MTU 0x043C 448#define BGE_GBIT_PCS_TEST 0x0440 449#define BGE_TX_TBI_AUTONEG 0x0444 450#define BGE_RX_TBI_AUTONEG 0x0448 451#define BGE_MI_COMM 0x044C 452#define BGE_MI_STS 0x0450 453#define BGE_MI_MODE 0x0454 454#define BGE_AUTOPOLL_STS 0x0458 455#define BGE_TX_MODE 0x045C 456#define BGE_TX_STS 0x0460 457#define BGE_TX_LENGTHS 0x0464 458#define BGE_RX_MODE 0x0468 459#define BGE_RX_STS 0x046C 460#define BGE_MAR0 0x0470 461#define BGE_MAR1 0x0474 462#define BGE_MAR2 0x0478 463#define BGE_MAR3 0x047C 464#define BGE_RX_BD_RULES_CTL0 0x0480 465#define BGE_RX_BD_RULES_MASKVAL0 0x0484 466#define BGE_RX_BD_RULES_CTL1 0x0488 467#define BGE_RX_BD_RULES_MASKVAL1 0x048C 468#define BGE_RX_BD_RULES_CTL2 0x0490 469#define BGE_RX_BD_RULES_MASKVAL2 0x0494 470#define BGE_RX_BD_RULES_CTL3 0x0498 471#define BGE_RX_BD_RULES_MASKVAL3 0x049C 472#define BGE_RX_BD_RULES_CTL4 0x04A0 473#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 474#define BGE_RX_BD_RULES_CTL5 0x04A8 475#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 476#define BGE_RX_BD_RULES_CTL6 0x04B0 477#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 478#define BGE_RX_BD_RULES_CTL7 0x04B8 479#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 480#define BGE_RX_BD_RULES_CTL8 0x04C0 481#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 482#define BGE_RX_BD_RULES_CTL9 0x04C8 483#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 484#define BGE_RX_BD_RULES_CTL10 0x04D0 485#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 486#define BGE_RX_BD_RULES_CTL11 0x04D8 487#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 488#define BGE_RX_BD_RULES_CTL12 0x04E0 489#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 490#define BGE_RX_BD_RULES_CTL13 0x04E8 491#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 492#define BGE_RX_BD_RULES_CTL14 0x04F0 493#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 494#define BGE_RX_BD_RULES_CTL15 0x04F8 495#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 496#define BGE_RX_RULES_CFG 0x0500 497#define BGE_RX_STATS 0x0800 498#define BGE_TX_STATS 0x0880 499 500/* Ethernet MAC Mode register */ 501#define BGE_MACMODE_RESET 0x00000001 502#define BGE_MACMODE_HALF_DUPLEX 0x00000002 503#define BGE_MACMODE_PORTMODE 0x0000000C 504#define BGE_MACMODE_LOOPBACK 0x00000010 505#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 506#define BGE_MACMODE_TX_BURST_ENB 0x00000100 507#define BGE_MACMODE_MAX_DEFER 0x00000200 508#define BGE_MACMODE_LINK_POLARITY 0x00000400 509#define BGE_MACMODE_RX_STATS_ENB 0x00000800 510#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 511#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 512#define BGE_MACMODE_TX_STATS_ENB 0x00004000 513#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 514#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 515#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 516#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 517#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 518#define BGE_MACMODE_MIP_ENB 0x00100000 519#define BGE_MACMODE_TXDMA_ENB 0x00200000 520#define BGE_MACMODE_RXDMA_ENB 0x00400000 521#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 522 523#define BGE_PORTMODE_NONE 0x00000000 524#define BGE_PORTMODE_MII 0x00000004 525#define BGE_PORTMODE_GMII 0x00000008 526#define BGE_PORTMODE_TBI 0x0000000C 527 528/* MAC Status register */ 529#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 530#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 531#define BGE_MACSTAT_RX_CFG 0x00000004 532#define BGE_MACSTAT_CFG_CHANGED 0x00000008 533#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 534#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 535#define BGE_MACSTAT_LINK_CHANGED 0x00001000 536#define BGE_MACSTAT_MI_COMPLETE 0x00400000 537#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 538#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 539#define BGE_MACSTAT_ODI_ERROR 0x02000000 540#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 541#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 542 543/* MAC Event Enable Register */ 544#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 545#define BGE_EVTENB_LINK_CHANGED 0x00001000 546#define BGE_EVTENB_MI_COMPLETE 0x00400000 547#define BGE_EVTENB_MI_INTERRUPT 0x00800000 548#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 549#define BGE_EVTENB_ODI_ERROR 0x02000000 550#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 551#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 552 553/* LED Control Register */ 554#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 555#define BGE_LEDCTL_1000MBPS_LED 0x00000002 556#define BGE_LEDCTL_100MBPS_LED 0x00000004 557#define BGE_LEDCTL_10MBPS_LED 0x00000008 558#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 559#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 560#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 561#define BGE_LEDCTL_1000MBPS_STS 0x00000080 562#define BGE_LEDCTL_100MBPS_STS 0x00000100 563#define BGE_LEDCTL_10MBPS_STS 0x00000200 564#define BGE_LEDCTL_TRADLED_STS 0x00000400 565#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 566#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 567 568/* TX backoff seed register */ 569#define BGE_TX_BACKOFF_SEED_MASK 0x3F 570 571/* Autopoll status register */ 572#define BGE_AUTOPOLLSTS_ERROR 0x00000001 573 574/* Transmit MAC mode register */ 575#define BGE_TXMODE_RESET 0x00000001 576#define BGE_TXMODE_ENABLE 0x00000002 577#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 578#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 579#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 580 581/* Transmit MAC status register */ 582#define BGE_TXSTAT_RX_XOFFED 0x00000001 583#define BGE_TXSTAT_SENT_XOFF 0x00000002 584#define BGE_TXSTAT_SENT_XON 0x00000004 585#define BGE_TXSTAT_LINK_UP 0x00000008 586#define BGE_TXSTAT_ODI_UFLOW 0x00000010 587#define BGE_TXSTAT_ODI_OFLOW 0x00000020 588 589/* Transmit MAC lengths register */ 590#define BGE_TXLEN_SLOTTIME 0x000000FF 591#define BGE_TXLEN_IPG 0x00000F00 592#define BGE_TXLEN_CRS 0x00003000 593 594/* Receive MAC mode register */ 595#define BGE_RXMODE_RESET 0x00000001 596#define BGE_RXMODE_ENABLE 0x00000002 597#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 598#define BGE_RXMODE_RX_GIANTS 0x00000020 599#define BGE_RXMODE_RX_RUNTS 0x00000040 600#define BGE_RXMODE_8022_LENCHECK 0x00000080 601#define BGE_RXMODE_RX_PROMISC 0x00000100 602#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 603#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 604 605/* Receive MAC status register */ 606#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 607#define BGE_RXSTAT_RCVD_XOFF 0x00000002 608#define BGE_RXSTAT_RCVD_XON 0x00000004 609 610/* Receive Rules Control register */ 611#define BGE_RXRULECTL_OFFSET 0x000000FF 612#define BGE_RXRULECTL_CLASS 0x00001F00 613#define BGE_RXRULECTL_HDRTYPE 0x0000E000 614#define BGE_RXRULECTL_COMPARE_OP 0x00030000 615#define BGE_RXRULECTL_MAP 0x01000000 616#define BGE_RXRULECTL_DISCARD 0x02000000 617#define BGE_RXRULECTL_MASK 0x04000000 618#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 619#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 620#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 621#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 622 623/* Receive Rules Mask register */ 624#define BGE_RXRULEMASK_VALUE 0x0000FFFF 625#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 626 627/* MI communication register */ 628#define BGE_MICOMM_DATA 0x0000FFFF 629#define BGE_MICOMM_REG 0x001F0000 630#define BGE_MICOMM_PHY 0x03E00000 631#define BGE_MICOMM_CMD 0x0C000000 632#define BGE_MICOMM_READFAIL 0x10000000 633#define BGE_MICOMM_BUSY 0x20000000 634 635#define BGE_MIREG(x) ((x & 0x1F) << 16) 636#define BGE_MIPHY(x) ((x & 0x1F) << 21) 637#define BGE_MICMD_WRITE 0x04000000 638#define BGE_MICMD_READ 0x08000000 639 640/* MI status register */ 641#define BGE_MISTS_LINK 0x00000001 642#define BGE_MISTS_10MBPS 0x00000002 643 644#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 645#define BGE_MIMODE_AUTOPOLL 0x00000010 646#define BGE_MIMODE_CLKCNT 0x001F0000 647 648 649/* 650 * Send data initiator control registers. 651 */ 652#define BGE_SDI_MODE 0x0C00 653#define BGE_SDI_STATUS 0x0C04 654#define BGE_SDI_STATS_CTL 0x0C08 655#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 656#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 657#define BGE_LOCSTATS_COS0 0x0C80 658#define BGE_LOCSTATS_COS1 0x0C84 659#define BGE_LOCSTATS_COS2 0x0C88 660#define BGE_LOCSTATS_COS3 0x0C8C 661#define BGE_LOCSTATS_COS4 0x0C90 662#define BGE_LOCSTATS_COS5 0x0C84 663#define BGE_LOCSTATS_COS6 0x0C98 664#define BGE_LOCSTATS_COS7 0x0C9C 665#define BGE_LOCSTATS_COS8 0x0CA0 666#define BGE_LOCSTATS_COS9 0x0CA4 667#define BGE_LOCSTATS_COS10 0x0CA8 668#define BGE_LOCSTATS_COS11 0x0CAC 669#define BGE_LOCSTATS_COS12 0x0CB0 670#define BGE_LOCSTATS_COS13 0x0CB4 671#define BGE_LOCSTATS_COS14 0x0CB8 672#define BGE_LOCSTATS_COS15 0x0CBC 673#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 674#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 675#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 676#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 677#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 678#define BGE_LOCSTATS_IRQS 0x0CD4 679#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 680#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 681 682/* Send Data Initiator mode register */ 683#define BGE_SDIMODE_RESET 0x00000001 684#define BGE_SDIMODE_ENABLE 0x00000002 685#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 686 687/* Send Data Initiator stats register */ 688#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 689 690/* Send Data Initiator stats control register */ 691#define BGE_SDISTATSCTL_ENABLE 0x00000001 692#define BGE_SDISTATSCTL_FASTER 0x00000002 693#define BGE_SDISTATSCTL_CLEAR 0x00000004 694#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 695#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 696 697/* 698 * Send Data Completion Control registers 699 */ 700#define BGE_SDC_MODE 0x1000 701#define BGE_SDC_STATUS 0x1004 702 703/* Send Data completion mode register */ 704#define BGE_SDCMODE_RESET 0x00000001 705#define BGE_SDCMODE_ENABLE 0x00000002 706#define BGE_SDCMODE_ATTN 0x00000004 707 708/* Send Data completion status register */ 709#define BGE_SDCSTAT_ATTN 0x00000004 710 711/* 712 * Send BD Ring Selector Control registers 713 */ 714#define BGE_SRS_MODE 0x1400 715#define BGE_SRS_STATUS 0x1404 716#define BGE_SRS_HWDIAG 0x1408 717#define BGE_SRS_LOC_NIC_CONS0 0x1440 718#define BGE_SRS_LOC_NIC_CONS1 0x1444 719#define BGE_SRS_LOC_NIC_CONS2 0x1448 720#define BGE_SRS_LOC_NIC_CONS3 0x144C 721#define BGE_SRS_LOC_NIC_CONS4 0x1450 722#define BGE_SRS_LOC_NIC_CONS5 0x1454 723#define BGE_SRS_LOC_NIC_CONS6 0x1458 724#define BGE_SRS_LOC_NIC_CONS7 0x145C 725#define BGE_SRS_LOC_NIC_CONS8 0x1460 726#define BGE_SRS_LOC_NIC_CONS9 0x1464 727#define BGE_SRS_LOC_NIC_CONS10 0x1468 728#define BGE_SRS_LOC_NIC_CONS11 0x146C 729#define BGE_SRS_LOC_NIC_CONS12 0x1470 730#define BGE_SRS_LOC_NIC_CONS13 0x1474 731#define BGE_SRS_LOC_NIC_CONS14 0x1478 732#define BGE_SRS_LOC_NIC_CONS15 0x147C 733 734/* Send BD Ring Selector Mode register */ 735#define BGE_SRSMODE_RESET 0x00000001 736#define BGE_SRSMODE_ENABLE 0x00000002 737#define BGE_SRSMODE_ATTN 0x00000004 738 739/* Send BD Ring Selector Status register */ 740#define BGE_SRSSTAT_ERROR 0x00000004 741 742/* Send BD Ring Selector HW Diagnostics register */ 743#define BGE_SRSHWDIAG_STATE 0x0000000F 744#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 745#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 746#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 747 748/* 749 * Send BD Initiator Selector Control registers 750 */ 751#define BGE_SBDI_MODE 0x1800 752#define BGE_SBDI_STATUS 0x1804 753#define BGE_SBDI_LOC_NIC_PROD0 0x1808 754#define BGE_SBDI_LOC_NIC_PROD1 0x180C 755#define BGE_SBDI_LOC_NIC_PROD2 0x1810 756#define BGE_SBDI_LOC_NIC_PROD3 0x1814 757#define BGE_SBDI_LOC_NIC_PROD4 0x1818 758#define BGE_SBDI_LOC_NIC_PROD5 0x181C 759#define BGE_SBDI_LOC_NIC_PROD6 0x1820 760#define BGE_SBDI_LOC_NIC_PROD7 0x1824 761#define BGE_SBDI_LOC_NIC_PROD8 0x1828 762#define BGE_SBDI_LOC_NIC_PROD9 0x182C 763#define BGE_SBDI_LOC_NIC_PROD10 0x1830 764#define BGE_SBDI_LOC_NIC_PROD11 0x1834 765#define BGE_SBDI_LOC_NIC_PROD12 0x1838 766#define BGE_SBDI_LOC_NIC_PROD13 0x183C 767#define BGE_SBDI_LOC_NIC_PROD14 0x1840 768#define BGE_SBDI_LOC_NIC_PROD15 0x1844 769 770/* Send BD Initiator Mode register */ 771#define BGE_SBDIMODE_RESET 0x00000001 772#define BGE_SBDIMODE_ENABLE 0x00000002 773#define BGE_SBDIMODE_ATTN 0x00000004 774 775/* Send BD Initiator Status register */ 776#define BGE_SBDISTAT_ERROR 0x00000004 777 778/* 779 * Send BD Completion Control registers 780 */ 781#define BGE_SBDC_MODE 0x1C00 782#define BGE_SBDC_STATUS 0x1C04 783 784/* Send BD Completion Control Mode register */ 785#define BGE_SBDCMODE_RESET 0x00000001 786#define BGE_SBDCMODE_ENABLE 0x00000002 787#define BGE_SBDCMODE_ATTN 0x00000004 788 789/* Send BD Completion Control Status register */ 790#define BGE_SBDCSTAT_ATTN 0x00000004 791 792/* 793 * Receive List Placement Control registers 794 */ 795#define BGE_RXLP_MODE 0x2000 796#define BGE_RXLP_STATUS 0x2004 797#define BGE_RXLP_SEL_LIST_LOCK 0x2008 798#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 799#define BGE_RXLP_CFG 0x2010 800#define BGE_RXLP_STATS_CTL 0x2014 801#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 802#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 803#define BGE_RXLP_HEAD0 0x2100 804#define BGE_RXLP_TAIL0 0x2104 805#define BGE_RXLP_COUNT0 0x2108 806#define BGE_RXLP_HEAD1 0x2110 807#define BGE_RXLP_TAIL1 0x2114 808#define BGE_RXLP_COUNT1 0x2118 809#define BGE_RXLP_HEAD2 0x2120 810#define BGE_RXLP_TAIL2 0x2124 811#define BGE_RXLP_COUNT2 0x2128 812#define BGE_RXLP_HEAD3 0x2130 813#define BGE_RXLP_TAIL3 0x2134 814#define BGE_RXLP_COUNT3 0x2138 815#define BGE_RXLP_HEAD4 0x2140 816#define BGE_RXLP_TAIL4 0x2144 817#define BGE_RXLP_COUNT4 0x2148 818#define BGE_RXLP_HEAD5 0x2150 819#define BGE_RXLP_TAIL5 0x2154 820#define BGE_RXLP_COUNT5 0x2158 821#define BGE_RXLP_HEAD6 0x2160 822#define BGE_RXLP_TAIL6 0x2164 823#define BGE_RXLP_COUNT6 0x2168 824#define BGE_RXLP_HEAD7 0x2170 825#define BGE_RXLP_TAIL7 0x2174 826#define BGE_RXLP_COUNT7 0x2178 827#define BGE_RXLP_HEAD8 0x2180 828#define BGE_RXLP_TAIL8 0x2184 829#define BGE_RXLP_COUNT8 0x2188 830#define BGE_RXLP_HEAD9 0x2190 831#define BGE_RXLP_TAIL9 0x2194 832#define BGE_RXLP_COUNT9 0x2198 833#define BGE_RXLP_HEAD10 0x21A0 834#define BGE_RXLP_TAIL10 0x21A4 835#define BGE_RXLP_COUNT10 0x21A8 836#define BGE_RXLP_HEAD11 0x21B0 837#define BGE_RXLP_TAIL11 0x21B4 838#define BGE_RXLP_COUNT11 0x21B8 839#define BGE_RXLP_HEAD12 0x21C0 840#define BGE_RXLP_TAIL12 0x21C4 841#define BGE_RXLP_COUNT12 0x21C8 842#define BGE_RXLP_HEAD13 0x21D0 843#define BGE_RXLP_TAIL13 0x21D4 844#define BGE_RXLP_COUNT13 0x21D8 845#define BGE_RXLP_HEAD14 0x21E0 846#define BGE_RXLP_TAIL14 0x21E4 847#define BGE_RXLP_COUNT14 0x21E8 848#define BGE_RXLP_HEAD15 0x21F0 849#define BGE_RXLP_TAIL15 0x21F4 850#define BGE_RXLP_COUNT15 0x21F8 851#define BGE_RXLP_LOCSTAT_COS0 0x2200 852#define BGE_RXLP_LOCSTAT_COS1 0x2204 853#define BGE_RXLP_LOCSTAT_COS2 0x2208 854#define BGE_RXLP_LOCSTAT_COS3 0x220C 855#define BGE_RXLP_LOCSTAT_COS4 0x2210 856#define BGE_RXLP_LOCSTAT_COS5 0x2214 857#define BGE_RXLP_LOCSTAT_COS6 0x2218 858#define BGE_RXLP_LOCSTAT_COS7 0x221C 859#define BGE_RXLP_LOCSTAT_COS8 0x2220 860#define BGE_RXLP_LOCSTAT_COS9 0x2224 861#define BGE_RXLP_LOCSTAT_COS10 0x2228 862#define BGE_RXLP_LOCSTAT_COS11 0x222C 863#define BGE_RXLP_LOCSTAT_COS12 0x2230 864#define BGE_RXLP_LOCSTAT_COS13 0x2234 865#define BGE_RXLP_LOCSTAT_COS14 0x2238 866#define BGE_RXLP_LOCSTAT_COS15 0x223C 867#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 868#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 869#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 870#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 871#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 872#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 873#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 874 875 876/* Receive List Placement mode register */ 877#define BGE_RXLPMODE_RESET 0x00000001 878#define BGE_RXLPMODE_ENABLE 0x00000002 879#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 880#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 881#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 882 883/* Receive List Placement Status register */ 884#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 885#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 886#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 887 888/* 889 * Receive Data and Receive BD Initiator Control Registers 890 */ 891#define BGE_RDBDI_MODE 0x2400 892#define BGE_RDBDI_STATUS 0x2404 893#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 894#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 895#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 896#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 897#define BGE_RX_STD_RCB_HADDR_HI 0x2450 898#define BGE_RX_STD_RCB_HADDR_LO 0x2454 899#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 900#define BGE_RX_STD_RCB_NICADDR 0x245C 901#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 902#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 903#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 904#define BGE_RX_MINI_RCB_NICADDR 0x246C 905#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 906#define BGE_RDBDI_STD_RX_CONS 0x2474 907#define BGE_RDBDI_MINI_RX_CONS 0x2478 908#define BGE_RDBDI_RETURN_PROD0 0x2480 909#define BGE_RDBDI_RETURN_PROD1 0x2484 910#define BGE_RDBDI_RETURN_PROD2 0x2488 911#define BGE_RDBDI_RETURN_PROD3 0x248C 912#define BGE_RDBDI_RETURN_PROD4 0x2490 913#define BGE_RDBDI_RETURN_PROD5 0x2494 914#define BGE_RDBDI_RETURN_PROD6 0x2498 915#define BGE_RDBDI_RETURN_PROD7 0x249C 916#define BGE_RDBDI_RETURN_PROD8 0x24A0 917#define BGE_RDBDI_RETURN_PROD9 0x24A4 918#define BGE_RDBDI_RETURN_PROD10 0x24A8 919#define BGE_RDBDI_RETURN_PROD11 0x24AC 920#define BGE_RDBDI_RETURN_PROD12 0x24B0 921#define BGE_RDBDI_RETURN_PROD13 0x24B4 922#define BGE_RDBDI_RETURN_PROD14 0x24B8 923#define BGE_RDBDI_RETURN_PROD15 0x24BC 924#define BGE_RDBDI_HWDIAG 0x24C0 925 926 927/* Receive Data and Receive BD Initiator Mode register */ 928#define BGE_RDBDIMODE_RESET 0x00000001 929#define BGE_RDBDIMODE_ENABLE 0x00000002 930#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 931#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 932#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 933 934/* Receive Data and Receive BD Initiator Status register */ 935#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 936#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 937#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 938 939 940/* 941 * Receive Data Completion Control registers 942 */ 943#define BGE_RDC_MODE 0x2800 944 945/* Receive Data Completion Mode register */ 946#define BGE_RDCMODE_RESET 0x00000001 947#define BGE_RDCMODE_ENABLE 0x00000002 948#define BGE_RDCMODE_ATTN 0x00000004 949 950/* 951 * Receive BD Initiator Control registers 952 */ 953#define BGE_RBDI_MODE 0x2C00 954#define BGE_RBDI_STATUS 0x2C04 955#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 956#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 957#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 958#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 959#define BGE_RBDI_STD_REPL_THRESH 0x2C18 960#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 961 962/* Receive BD Initiator Mode register */ 963#define BGE_RBDIMODE_RESET 0x00000001 964#define BGE_RBDIMODE_ENABLE 0x00000002 965#define BGE_RBDIMODE_ATTN 0x00000004 966 967/* Receive BD Initiator Status register */ 968#define BGE_RBDISTAT_ATTN 0x00000004 969 970/* 971 * Receive BD Completion Control registers 972 */ 973#define BGE_RBDC_MODE 0x3000 974#define BGE_RBDC_STATUS 0x3004 975#define BGE_RBDC_JUMBO_BD_PROD 0x3008 976#define BGE_RBDC_STD_BD_PROD 0x300C 977#define BGE_RBDC_MINI_BD_PROD 0x3010 978 979/* Receive BD completion mode register */ 980#define BGE_RBDCMODE_RESET 0x00000001 981#define BGE_RBDCMODE_ENABLE 0x00000002 982#define BGE_RBDCMODE_ATTN 0x00000004 983 984/* Receive BD completion status register */ 985#define BGE_RBDCSTAT_ERROR 0x00000004 986 987/* 988 * Receive List Selector Control registers 989 */ 990#define BGE_RXLS_MODE 0x3400 991#define BGE_RXLS_STATUS 0x3404 992 993/* Receive List Selector Mode register */ 994#define BGE_RXLSMODE_RESET 0x00000001 995#define BGE_RXLSMODE_ENABLE 0x00000002 996#define BGE_RXLSMODE_ATTN 0x00000004 997 998/* Receive List Selector Status register */ 999#define BGE_RXLSSTAT_ERROR 0x00000004 1000 1001/* 1002 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1003 */ 1004#define BGE_MBCF_MODE 0x3800 1005#define BGE_MBCF_STATUS 0x3804 1006 1007/* Mbuf Cluster Free mode register */ 1008#define BGE_MBCFMODE_RESET 0x00000001 1009#define BGE_MBCFMODE_ENABLE 0x00000002 1010#define BGE_MBCFMODE_ATTN 0x00000004 1011 1012/* Mbuf Cluster Free status register */ 1013#define BGE_MBCFSTAT_ERROR 0x00000004 1014 1015/* 1016 * Host Coalescing Control registers 1017 */ 1018#define BGE_HCC_MODE 0x3C00 1019#define BGE_HCC_STATUS 0x3C04 1020#define BGE_HCC_RX_COAL_TICKS 0x3C08 1021#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1022#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1023#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1024#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1025#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1026#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1027#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ 1028#define BGE_HCC_STATS_TICKS 0x3C28 1029#define BGE_HCC_STATS_ADDR_HI 0x3C30 1030#define BGE_HCC_STATS_ADDR_LO 0x3C34 1031#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1032#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1033#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1034#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1035#define BGE_FLOW_ATTN 0x3C48 1036#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1037#define BGE_HCC_STD_BD_CONS 0x3C54 1038#define BGE_HCC_MINI_BD_CONS 0x3C58 1039#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1040#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1041#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1042#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1043#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1044#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1045#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1046#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1047#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1048#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1049#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1050#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1051#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1052#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1053#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1054#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1055#define BGE_HCC_TX_BD_CONS0 0x3CC0 1056#define BGE_HCC_TX_BD_CONS1 0x3CC4 1057#define BGE_HCC_TX_BD_CONS2 0x3CC8 1058#define BGE_HCC_TX_BD_CONS3 0x3CCC 1059#define BGE_HCC_TX_BD_CONS4 0x3CD0 1060#define BGE_HCC_TX_BD_CONS5 0x3CD4 1061#define BGE_HCC_TX_BD_CONS6 0x3CD8 1062#define BGE_HCC_TX_BD_CONS7 0x3CDC 1063#define BGE_HCC_TX_BD_CONS8 0x3CE0 1064#define BGE_HCC_TX_BD_CONS9 0x3CE4 1065#define BGE_HCC_TX_BD_CONS10 0x3CE8 1066#define BGE_HCC_TX_BD_CONS11 0x3CEC 1067#define BGE_HCC_TX_BD_CONS12 0x3CF0 1068#define BGE_HCC_TX_BD_CONS13 0x3CF4 1069#define BGE_HCC_TX_BD_CONS14 0x3CF8 1070#define BGE_HCC_TX_BD_CONS15 0x3CFC 1071 1072 1073/* Host coalescing mode register */ 1074#define BGE_HCCMODE_RESET 0x00000001 1075#define BGE_HCCMODE_ENABLE 0x00000002 1076#define BGE_HCCMODE_ATTN 0x00000004 1077#define BGE_HCCMODE_COAL_NOW 0x00000008 1078#define BGE_HCCMODE_MSI_BITS 0x0x000070 1079#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1080 1081#define BGE_STATBLKSZ_FULL 0x00000000 1082#define BGE_STATBLKSZ_64BYTE 0x00000080 1083#define BGE_STATBLKSZ_32BYTE 0x00000100 1084 1085/* Host coalescing status register */ 1086#define BGE_HCCSTAT_ERROR 0x00000004 1087 1088/* Flow attention register */ 1089#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1090#define BGE_FLOWATTN_MEMARB 0x00000080 1091#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1092#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1093#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1094#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1095#define BGE_FLOWATTN_RDBDI 0x00080000 1096#define BGE_FLOWATTN_RXLS 0x00100000 1097#define BGE_FLOWATTN_RXLP 0x00200000 1098#define BGE_FLOWATTN_RBDC 0x00400000 1099#define BGE_FLOWATTN_RBDI 0x00800000 1100#define BGE_FLOWATTN_SDC 0x08000000 1101#define BGE_FLOWATTN_SDI 0x10000000 1102#define BGE_FLOWATTN_SRS 0x20000000 1103#define BGE_FLOWATTN_SBDC 0x40000000 1104#define BGE_FLOWATTN_SBDI 0x80000000 1105 1106/* 1107 * Memory arbiter registers 1108 */ 1109#define BGE_MARB_MODE 0x4000 1110#define BGE_MARB_STATUS 0x4004 1111#define BGE_MARB_TRAPADDR_HI 0x4008 1112#define BGE_MARB_TRAPADDR_LO 0x400C 1113 1114/* Memory arbiter mode register */ 1115#define BGE_MARBMODE_RESET 0x00000001 1116#define BGE_MARBMODE_ENABLE 0x00000002 1117#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1118#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1119#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1120#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1121#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1122#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1123#define BGE_MARBMODE_PCI_TRAP 0x00000100 1124#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1125#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1126#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1127#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1128#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1129#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1130#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1131#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1132#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1133#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1134#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1135#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1136#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1137#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1138#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1139#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1140#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1141 1142/* Memory arbiter status register */ 1143#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1144#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1145#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1146#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1147#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1148#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1149#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1150#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1151#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1152#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1153#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1154#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1155#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1156#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1157#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1158#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1159#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1160#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1161#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1162#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1163#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1164#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1165#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1166#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1167 1168/* 1169 * Buffer manager control registers 1170 */ 1171#define BGE_BMAN_MODE 0x4400 1172#define BGE_BMAN_STATUS 0x4404 1173#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1174#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1175#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1176#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1177#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1178#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1179#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1180#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1181#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1182#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1183#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1184#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1185#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1186#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1187#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1188#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1189#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1190#define BGE_BMAN_HWDIAG_1 0x444C 1191#define BGE_BMAN_HWDIAG_2 0x4450 1192#define BGE_BMAN_HWDIAG_3 0x4454 1193 1194/* Buffer manager mode register */ 1195#define BGE_BMANMODE_RESET 0x00000001 1196#define BGE_BMANMODE_ENABLE 0x00000002 1197#define BGE_BMANMODE_ATTN 0x00000004 1198#define BGE_BMANMODE_TESTMODE 0x00000008 1199#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1200 1201/* Buffer manager status register */ 1202#define BGE_BMANSTAT_ERRO 0x00000004 1203#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1204 1205 1206/* 1207 * Read DMA Control registers 1208 */ 1209#define BGE_RDMA_MODE 0x4800 1210#define BGE_RDMA_STATUS 0x4804 1211 1212/* Read DMA mode register */ 1213#define BGE_RDMAMODE_RESET 0x00000001 1214#define BGE_RDMAMODE_ENABLE 0x00000002 1215#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1216#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1217#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1218#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1219#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1220#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1221#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1222#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1223#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1224 1225/* Read DMA status register */ 1226#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1227#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1228#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1229#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1230#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1231#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1232#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1233#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1234 1235/* 1236 * Write DMA control registers 1237 */ 1238#define BGE_WDMA_MODE 0x4C00 1239#define BGE_WDMA_STATUS 0x4C04 1240 1241/* Write DMA mode register */ 1242#define BGE_WDMAMODE_RESET 0x00000001 1243#define BGE_WDMAMODE_ENABLE 0x00000002 1244#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1245#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1246#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1247#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1248#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1249#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1250#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1251#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1252#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1253 1254/* Write DMA status register */ 1255#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1256#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1257#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1258#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1259#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1260#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1261#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1262#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1263 1264 1265/* 1266 * RX CPU registers 1267 */ 1268#define BGE_RXCPU_MODE 0x5000 1269#define BGE_RXCPU_STATUS 0x5004 1270#define BGE_RXCPU_PC 0x501C 1271 1272/* RX CPU mode register */ 1273#define BGE_RXCPUMODE_RESET 0x00000001 1274#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1275#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1276#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1277#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1278#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1279#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1280#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1281#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1282#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1283#define BGE_RXCPUMODE_HALTCPU 0x00000400 1284#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1285#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1286#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1287 1288/* RX CPU status register */ 1289#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1290#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1291#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1292#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1293#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1294#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1295#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1296#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1297#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1298#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1299#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1300#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1301#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1302#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1303#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1304#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1305#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1306 1307 1308/* 1309 * TX CPU registers 1310 */ 1311#define BGE_TXCPU_MODE 0x5400 1312#define BGE_TXCPU_STATUS 0x5404 1313#define BGE_TXCPU_PC 0x541C 1314 1315/* TX CPU mode register */ 1316#define BGE_TXCPUMODE_RESET 0x00000001 1317#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1318#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1319#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1320#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1321#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1322#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1323#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1324#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1325#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1326#define BGE_TXCPUMODE_HALTCPU 0x00000400 1327#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1328#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1329 1330/* TX CPU status register */ 1331#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1332#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1333#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1334#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1335#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1336#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1337#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1338#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1339#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1340#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1341#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1342#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1343#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1344#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1345#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1346#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1347#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1348 1349 1350/* 1351 * Low priority mailbox registers 1352 */ 1353#define BGE_LPMBX_IRQ0_HI 0x5800 1354#define BGE_LPMBX_IRQ0_LO 0x5804 1355#define BGE_LPMBX_IRQ1_HI 0x5808 1356#define BGE_LPMBX_IRQ1_LO 0x580C 1357#define BGE_LPMBX_IRQ2_HI 0x5810 1358#define BGE_LPMBX_IRQ2_LO 0x5814 1359#define BGE_LPMBX_IRQ3_HI 0x5818 1360#define BGE_LPMBX_IRQ3_LO 0x581C 1361#define BGE_LPMBX_GEN0_HI 0x5820 1362#define BGE_LPMBX_GEN0_LO 0x5824 1363#define BGE_LPMBX_GEN1_HI 0x5828 1364#define BGE_LPMBX_GEN1_LO 0x582C 1365#define BGE_LPMBX_GEN2_HI 0x5830 1366#define BGE_LPMBX_GEN2_LO 0x5834 1367#define BGE_LPMBX_GEN3_HI 0x5828 1368#define BGE_LPMBX_GEN3_LO 0x582C 1369#define BGE_LPMBX_GEN4_HI 0x5840 1370#define BGE_LPMBX_GEN4_LO 0x5844 1371#define BGE_LPMBX_GEN5_HI 0x5848 1372#define BGE_LPMBX_GEN5_LO 0x584C 1373#define BGE_LPMBX_GEN6_HI 0x5850 1374#define BGE_LPMBX_GEN6_LO 0x5854 1375#define BGE_LPMBX_GEN7_HI 0x5858 1376#define BGE_LPMBX_GEN7_LO 0x585C 1377#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1378#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1379#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1380#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1381#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1382#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1383#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1384#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1385#define BGE_LPMBX_RX_CONS0_HI 0x5880 1386#define BGE_LPMBX_RX_CONS0_LO 0x5884 1387#define BGE_LPMBX_RX_CONS1_HI 0x5888 1388#define BGE_LPMBX_RX_CONS1_LO 0x588C 1389#define BGE_LPMBX_RX_CONS2_HI 0x5890 1390#define BGE_LPMBX_RX_CONS2_LO 0x5894 1391#define BGE_LPMBX_RX_CONS3_HI 0x5898 1392#define BGE_LPMBX_RX_CONS3_LO 0x589C 1393#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1394#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1395#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1396#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1397#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1398#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1399#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1400#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1401#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1402#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1403#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1404#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1405#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1406#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1407#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1408#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1409#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1410#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1411#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1412#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1413#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1414#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1415#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1416#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1417#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1418#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1419#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1420#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1421#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1422#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1423#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1424#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1425#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1426#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1427#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1428#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1429#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1430#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1431#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1432#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1433#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1434#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1435#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1436#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1437#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1438#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1439#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1440#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1441#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1442#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1443#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1444#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1445#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1446#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1447#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1448#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1449#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1450#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1451#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1452#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1453#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1454#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1455#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1456#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1457#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1458#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1459#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1460#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1461#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1462#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1463#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1464#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1465#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1466#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1467#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1468#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1469#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1470#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1471#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1472#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1473#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1474#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1475#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1476#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1477#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1478#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1479#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1480#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1481 1482/* 1483 * Flow throw Queue reset register 1484 */ 1485#define BGE_FTQ_RESET 0x5C00 1486 1487#define BGE_FTQRESET_DMAREAD 0x00000002 1488#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1489#define BGE_FTQRESET_DMADONE 0x00000010 1490#define BGE_FTQRESET_SBDC 0x00000020 1491#define BGE_FTQRESET_SDI 0x00000040 1492#define BGE_FTQRESET_WDMA 0x00000080 1493#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1494#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1495#define BGE_FTQRESET_SDC 0x00000400 1496#define BGE_FTQRESET_HCC 0x00000800 1497#define BGE_FTQRESET_TXFIFO 0x00001000 1498#define BGE_FTQRESET_MBC 0x00002000 1499#define BGE_FTQRESET_RBDC 0x00004000 1500#define BGE_FTQRESET_RXLP 0x00008000 1501#define BGE_FTQRESET_RDBDI 0x00010000 1502#define BGE_FTQRESET_RDC 0x00020000 1503#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1504 1505/* 1506 * Message Signaled Interrupt registers 1507 */ 1508#define BGE_MSI_MODE 0x6000 1509#define BGE_MSI_STATUS 0x6004 1510#define BGE_MSI_FIFOACCESS 0x6008 1511 1512/* MSI mode register */ 1513#define BGE_MSIMODE_RESET 0x00000001 1514#define BGE_MSIMODE_ENABLE 0x00000002 1515#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1516#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1517#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1518#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1519#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1520 1521/* MSI status register */ 1522#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1523#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1524#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1525#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1526#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1527 1528 1529/* 1530 * DMA Completion registers 1531 */ 1532#define BGE_DMAC_MODE 0x6400 1533 1534/* DMA Completion mode register */ 1535#define BGE_DMACMODE_RESET 0x00000001 1536#define BGE_DMACMODE_ENABLE 0x00000002 1537 1538 1539/* 1540 * General control registers. 1541 */ 1542#define BGE_MODE_CTL 0x6800 1543#define BGE_MISC_CFG 0x6804 1544#define BGE_MISC_LOCAL_CTL 0x6808 1545#define BGE_EE_ADDR 0x6838 1546#define BGE_EE_DATA 0x683C 1547#define BGE_EE_CTL 0x6840 1548#define BGE_MDI_CTL 0x6844 1549#define BGE_EE_DELAY 0x6848 1550 1551/* Mode control register */ 1552#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1553#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1554#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1555#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1556#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1557#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1558#define BGE_MODECTL_NO_RX_CRC 0x00000400 1559#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1560#define BGE_MODECTL_NO_TX_INTR 0x00002000 1561#define BGE_MODECTL_NO_RX_INTR 0x00004000 1562#define BGE_MODECTL_FORCE_PCI32 0x00008000 1563#define BGE_MODECTL_STACKUP 0x00010000 1564#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1565#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1566#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1567#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1568#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1569#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1570#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1571#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1572#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1573#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1574 1575/* Misc. config register */ 1576#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1577#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1578 1579#define BGE_32BITTIME_66MHZ (0x41 << 1) 1580 1581/* Misc. Local Control */ 1582#define BGE_MLC_INTR_STATE 0x00000001 1583#define BGE_MLC_INTR_CLR 0x00000002 1584#define BGE_MLC_INTR_SET 0x00000004 1585#define BGE_MLC_INTR_ONATTN 0x00000008 1586#define BGE_MLC_MISCIO_IN0 0x00000100 1587#define BGE_MLC_MISCIO_IN1 0x00000200 1588#define BGE_MLC_MISCIO_IN2 0x00000400 1589#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1590#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1591#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1592#define BGE_MLC_MISCIO_OUT0 0x00004000 1593#define BGE_MLC_MISCIO_OUT1 0x00008000 1594#define BGE_MLC_MISCIO_OUT2 0x00010000 1595#define BGE_MLC_EXTRAM_ENB 0x00020000 1596#define BGE_MLC_SRAM_SIZE 0x001C0000 1597#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1598#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1599#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1600#define BGE_MLC_AUTO_EEPROM 0x01000000 1601 1602#define BGE_SSRAMSIZE_256KB 0x00000000 1603#define BGE_SSRAMSIZE_512KB 0x00040000 1604#define BGE_SSRAMSIZE_1MB 0x00080000 1605#define BGE_SSRAMSIZE_2MB 0x000C0000 1606#define BGE_SSRAMSIZE_4MB 0x00100000 1607#define BGE_SSRAMSIZE_8MB 0x00140000 1608#define BGE_SSRAMSIZE_16M 0x00180000 1609 1610/* EEPROM address register */ 1611#define BGE_EEADDR_ADDRESS 0x0000FFFC 1612#define BGE_EEADDR_HALFCLK 0x01FF0000 1613#define BGE_EEADDR_START 0x02000000 1614#define BGE_EEADDR_DEVID 0x1C000000 1615#define BGE_EEADDR_RESET 0x20000000 1616#define BGE_EEADDR_DONE 0x40000000 1617#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1618 1619#define BGE_EEDEVID(x) ((x & 7) << 26) 1620#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1621#define BGE_HALFCLK_384SCL 0x60 1622#define BGE_EE_READCMD \ 1623 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1624 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1625#define BGE_EE_WRCMD \ 1626 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1627 BGE_EEADDR_START|BGE_EEADDR_DONE) 1628 1629/* EEPROM Control register */ 1630#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1631#define BGE_EECTL_CLKOUT 0x00000002 1632#define BGE_EECTL_CLKIN 0x00000004 1633#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1634#define BGE_EECTL_DATAOUT 0x00000010 1635#define BGE_EECTL_DATAIN 0x00000020 1636 1637/* MDI (MII/GMII) access register */ 1638#define BGE_MDI_DATA 0x00000001 1639#define BGE_MDI_DIR 0x00000002 1640#define BGE_MDI_SEL 0x00000004 1641#define BGE_MDI_CLK 0x00000008 1642 1643#define BGE_MEMWIN_START 0x00008000 1644#define BGE_MEMWIN_END 0x0000FFFF 1645 1646 1647#define BGE_MEMWIN_READ(sc, x, val) \ 1648 do { \ 1649 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1650 (0xFFFF0000 & x), 4); \ 1651 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1652 } while(0) 1653 1654#define BGE_MEMWIN_WRITE(sc, x, val) \ 1655 do { \ 1656 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1657 (0xFFFF0000 & x), 4); \ 1658 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1659 } while(0) 1660 1661/* 1662 * This magic number is used to prevent PXE restart when we 1663 * issue a software reset. We write this magic number to the 1664 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1665 * code from running. 1666 */ 1667#define BGE_MAGIC_NUMBER 0x4B657654 1668 1669typedef struct { 1670 u_int32_t bge_addr_hi; 1671 u_int32_t bge_addr_lo; 1672} bge_hostaddr; 1673#define BGE_HOSTADDR(x) x.bge_addr_lo 1674 1675/* Ring control block structure */ 1676struct bge_rcb { 1677 bge_hostaddr bge_hostaddr; 1678 u_int16_t bge_flags; 1679 u_int16_t bge_max_len; 1680 u_int32_t bge_nicaddr; 1681}; 1682 1683struct bge_rcb_opaque { 1684 u_int32_t bge_reg0; 1685 u_int32_t bge_reg1; 1686 u_int32_t bge_reg2; 1687 u_int32_t bge_reg3; 1688}; 1689 1690#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1691#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1692 1693struct bge_tx_bd { 1694 bge_hostaddr bge_addr; 1695 u_int16_t bge_flags; 1696 u_int16_t bge_len; 1697 u_int16_t bge_vlan_tag; 1698 u_int16_t bge_rsvd; 1699}; 1700 1701#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1702#define BGE_TXBDFLAG_IP_CSUM 0x0002 1703#define BGE_TXBDFLAG_END 0x0004 1704#define BGE_TXBDFLAG_IP_FRAG 0x0008 1705#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1706#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1707#define BGE_TXBDFLAG_COAL_NOW 0x0080 1708#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1709#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1710#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1711#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1712#define BGE_TXBDFLAG_NO_CRC 0x8000 1713 1714#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1715 BGE_SEND_RING_1_TO_4 + \ 1716 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1717 1718struct bge_rx_bd { 1719 bge_hostaddr bge_addr; 1720 u_int16_t bge_len; 1721 u_int16_t bge_idx; 1722 u_int16_t bge_flags; 1723 u_int16_t bge_type; 1724 u_int16_t bge_tcp_udp_csum; 1725 u_int16_t bge_ip_csum; 1726 u_int16_t bge_vlan_tag; 1727 u_int16_t bge_error_flag; 1728 u_int32_t bge_rsvd; 1729 u_int32_t bge_opaque; 1730}; 1731 1732#define BGE_RXBDFLAG_END 0x0004 1733#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1734#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1735#define BGE_RXBDFLAG_ERROR 0x0400 1736#define BGE_RXBDFLAG_MINI_RING 0x0800 1737#define BGE_RXBDFLAG_IP_CSUM 0x1000 1738#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1739#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1740 1741#define BGE_RXERRFLAG_BAD_CRC 0x0001 1742#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1743#define BGE_RXERRFLAG_LINK_LOST 0x0004 1744#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1745#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1746#define BGE_RXERRFLAG_RUNT 0x0020 1747#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1748#define BGE_RXERRFLAG_GIANT 0x0080 1749 1750struct bge_sts_idx { 1751 u_int16_t bge_rx_prod_idx; 1752 u_int16_t bge_tx_cons_idx; 1753}; 1754 1755struct bge_status_block { 1756 u_int32_t bge_status; 1757 u_int32_t bge_rsvd0; 1758 u_int16_t bge_rx_jumbo_cons_idx; 1759 u_int16_t bge_rx_std_cons_idx; 1760 u_int16_t bge_rx_mini_cons_idx; 1761 u_int16_t bge_rsvd1; 1762 struct bge_sts_idx bge_idx[16]; 1763}; 1764 1765#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1766#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1767 1768#define BGE_STATFLAG_UPDATED 0x00000001 1769#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1770#define BGE_STATFLAG_ERROR 0x00000004 1771 1772 1773/* 1774 * Broadcom Vendor ID 1775 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1776 * even though they're now manufactured by Broadcom) 1777 */ 1778#define BCOM_VENDORID 0x14E4 1779#define BCOM_DEVICEID_BCM5700 0x1644 1780#define BCOM_DEVICEID_BCM5701 0x1645 1781 1782/* 1783 * Alteon AceNIC PCI vendor/device ID. 1784 */ 1785#define ALT_VENDORID 0x12AE 1786#define ALT_DEVICEID_ACENIC 0x0001 1787#define ALT_DEVICEID_ACENIC_COPPER 0x0002 1788#define ALT_DEVICEID_BCM5700 0x0003 1789#define ALT_DEVICEID_BCM5701 0x0004 1790 1791/* 1792 * 3Com 3c985 PCI vendor/device ID. 1793 */ 1794#define TC_VENDORID 0x10B7 1795#define TC_DEVICEID_3C985 0x0001 1796#define TC_DEVICEID_3C996 0x0003 1797 1798/* 1799 * SysKonnect PCI vendor ID 1800 */ 1801#define SK_VENDORID 0x1148 1802#define SK_DEVICEID_ALTIMA 0x4400 1803#define SK_SUBSYSID_9D21 0x4421 1804#define SK_SUBSYSID_9D41 0x4441 1805 1806/* 1807 * Altima PCI vendor/device ID. 1808 */ 1809#define ALTIMA_VENDORID 0x173b 1810#define ALTIMA_DEVICE_AC1000 0x03e8 1811 1812/* 1813 * Offset of MAC address inside EEPROM. 1814 */ 1815#define BGE_EE_MAC_OFFSET 0x7C 1816#define BGE_EE_HWCFG_OFFSET 0xC8 1817 1818#define BGE_PCI_READ_CMD 0x06000000 1819#define BGE_PCI_WRITE_CMD 0x70000000 1820 1821#define BGE_TICKS_PER_SEC 1000000 1822 1823/* 1824 * Ring size constants. 1825 */ 1826#define BGE_EVENT_RING_CNT 256 1827#define BGE_CMD_RING_CNT 64 1828#define BGE_STD_RX_RING_CNT 512 1829#define BGE_JUMBO_RX_RING_CNT 256 1830#define BGE_MINI_RX_RING_CNT 1024 1831#define BGE_RETURN_RING_CNT 1024 1832 1833/* 1834 * Possible TX ring sizes. 1835 */ 1836#define BGE_TX_RING_CNT_128 128 1837#define BGE_TX_RING_BASE_128 0x3800 1838 1839#define BGE_TX_RING_CNT_256 256 1840#define BGE_TX_RING_BASE_256 0x3000 1841 1842#define BGE_TX_RING_CNT_512 512 1843#define BGE_TX_RING_BASE_512 0x2000 1844 1845#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1846#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1847 1848/* 1849 * Tigon III statistics counters. 1850 */ 1851struct bge_stats { 1852 u_int8_t Reserved0[256]; 1853 1854 /* Statistics maintained by Receive MAC. */ 1855 bge_hostaddr ifHCInOctets; 1856 bge_hostaddr Reserved1; 1857 bge_hostaddr etherStatsFragments; 1858 bge_hostaddr ifHCInUcastPkts; 1859 bge_hostaddr ifHCInMulticastPkts; 1860 bge_hostaddr ifHCInBroadcastPkts; 1861 bge_hostaddr dot3StatsFCSErrors; 1862 bge_hostaddr dot3StatsAlignmentErrors; 1863 bge_hostaddr xonPauseFramesReceived; 1864 bge_hostaddr xoffPauseFramesReceived; 1865 bge_hostaddr macControlFramesReceived; 1866 bge_hostaddr xoffStateEntered; 1867 bge_hostaddr dot3StatsFramesTooLong; 1868 bge_hostaddr etherStatsJabbers; 1869 bge_hostaddr etherStatsUndersizePkts; 1870 bge_hostaddr inRangeLengthError; 1871 bge_hostaddr outRangeLengthError; 1872 bge_hostaddr etherStatsPkts64Octets; 1873 bge_hostaddr etherStatsPkts65Octetsto127Octets; 1874 bge_hostaddr etherStatsPkts128Octetsto255Octets; 1875 bge_hostaddr etherStatsPkts256Octetsto511Octets; 1876 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 1877 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 1878 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 1879 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 1880 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 1881 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 1882 1883 bge_hostaddr Unused1[37]; 1884 1885 /* Statistics maintained by Transmit MAC. */ 1886 bge_hostaddr ifHCOutOctets; 1887 bge_hostaddr Reserved2; 1888 bge_hostaddr etherStatsCollisions; 1889 bge_hostaddr outXonSent; 1890 bge_hostaddr outXoffSent; 1891 bge_hostaddr flowControlDone; 1892 bge_hostaddr dot3StatsInternalMacTransmitErrors; 1893 bge_hostaddr dot3StatsSingleCollisionFrames; 1894 bge_hostaddr dot3StatsMultipleCollisionFrames; 1895 bge_hostaddr dot3StatsDeferredTransmissions; 1896 bge_hostaddr Reserved3; 1897 bge_hostaddr dot3StatsExcessiveCollisions; 1898 bge_hostaddr dot3StatsLateCollisions; 1899 bge_hostaddr dot3Collided2Times; 1900 bge_hostaddr dot3Collided3Times; 1901 bge_hostaddr dot3Collided4Times; 1902 bge_hostaddr dot3Collided5Times; 1903 bge_hostaddr dot3Collided6Times; 1904 bge_hostaddr dot3Collided7Times; 1905 bge_hostaddr dot3Collided8Times; 1906 bge_hostaddr dot3Collided9Times; 1907 bge_hostaddr dot3Collided10Times; 1908 bge_hostaddr dot3Collided11Times; 1909 bge_hostaddr dot3Collided12Times; 1910 bge_hostaddr dot3Collided13Times; 1911 bge_hostaddr dot3Collided14Times; 1912 bge_hostaddr dot3Collided15Times; 1913 bge_hostaddr ifHCOutUcastPkts; 1914 bge_hostaddr ifHCOutMulticastPkts; 1915 bge_hostaddr ifHCOutBroadcastPkts; 1916 bge_hostaddr dot3StatsCarrierSenseErrors; 1917 bge_hostaddr ifOutDiscards; 1918 bge_hostaddr ifOutErrors; 1919 1920 bge_hostaddr Unused2[31]; 1921 1922 /* Statistics maintained by Receive List Placement. */ 1923 bge_hostaddr COSIfHCInPkts[16]; 1924 bge_hostaddr COSFramesDroppedDueToFilters; 1925 bge_hostaddr nicDmaWriteQueueFull; 1926 bge_hostaddr nicDmaWriteHighPriQueueFull; 1927 bge_hostaddr nicNoMoreRxBDs; 1928 bge_hostaddr ifInDiscards; 1929 bge_hostaddr ifInErrors; 1930 bge_hostaddr nicRecvThresholdHit; 1931 1932 bge_hostaddr Unused3[9]; 1933 1934 /* Statistics maintained by Send Data Initiator. */ 1935 bge_hostaddr COSIfHCOutPkts[16]; 1936 bge_hostaddr nicDmaReadQueueFull; 1937 bge_hostaddr nicDmaReadHighPriQueueFull; 1938 bge_hostaddr nicSendDataCompQueueFull; 1939 1940 /* Statistics maintained by Host Coalescing. */ 1941 bge_hostaddr nicRingSetSendProdIndex; 1942 bge_hostaddr nicRingStatusUpdate; 1943 bge_hostaddr nicInterrupts; 1944 bge_hostaddr nicAvoidedInterrupts; 1945 bge_hostaddr nicSendThresholdHit; 1946 1947 u_int8_t Reserved4[320]; 1948}; 1949 1950/* 1951 * Tigon general information block. This resides in host memory 1952 * and contains the status counters, ring control blocks and 1953 * producer pointers. 1954 */ 1955 1956struct bge_gib { 1957 struct bge_stats bge_stats; 1958 struct bge_rcb bge_tx_rcb[16]; 1959 struct bge_rcb bge_std_rx_rcb; 1960 struct bge_rcb bge_jumbo_rx_rcb; 1961 struct bge_rcb bge_mini_rx_rcb; 1962 struct bge_rcb bge_return_rcb; 1963}; 1964 1965/* 1966 * NOTE! On the Alpha, we have an alignment constraint. 1967 * The first thing in the packet is a 14-byte Ethernet header. 1968 * This means that the packet is misaligned. To compensate, 1969 * we actually offset the data 2 bytes into the cluster. This 1970 * alignes the packet after the Ethernet header at a 32-bit 1971 * boundary. 1972 */ 1973 1974#define ETHER_ALIGN 2 1975 1976#define BGE_FRAMELEN 1518 1977#define BGE_MAX_FRAMELEN 1536 1978#define BGE_JUMBO_FRAMELEN 9018 1979#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1980#define BGE_PAGE_SIZE PAGE_SIZE 1981#define BGE_MIN_FRAMELEN 60 1982 1983/* 1984 * Other utility macros. 1985 */ 1986#define BGE_INC(x, y) (x) = (x + 1) % y 1987 1988/* 1989 * Vital product data and structures. 1990 */ 1991#define BGE_VPD_FLAG 0x8000 1992 1993/* VPD structures */ 1994struct vpd_res { 1995 u_int8_t vr_id; 1996 u_int8_t vr_len; 1997 u_int8_t vr_pad; 1998}; 1999 2000struct vpd_key { 2001 char vk_key[2]; 2002 u_int8_t vk_len; 2003}; 2004 2005#define VPD_RES_ID 0x82 /* ID string */ 2006#define VPD_RES_READ 0x90 /* start of read only area */ 2007#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2008#define VPD_RES_END 0x78 /* end tag */ 2009 2010 2011/* 2012 * Register access macros. The Tigon always uses memory mapped register 2013 * accesses and all registers must be accessed with 32 bit operations. 2014 */ 2015 2016#define CSR_WRITE_4(sc, reg, val) \ 2017 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2018 2019#define CSR_READ_4(sc, reg) \ 2020 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2021 2022#define BGE_SETBIT(sc, reg, x) \ 2023 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 2024#define BGE_CLRBIT(sc, reg, x) \ 2025 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 2026 2027#define PCI_SETBIT(dev, reg, x, s) \ 2028 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s) 2029#define PCI_CLRBIT(dev, reg, x, s) \ 2030 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s) 2031 2032/* 2033 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2034 * values are tuneable. They control the actual amount of buffers 2035 * allocated for the standard, mini and jumbo receive rings. 2036 */ 2037 2038#define BGE_SSLOTS 256 2039#define BGE_MSLOTS 256 2040#define BGE_JSLOTS 384 2041 2042#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2043#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2044 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2045#define BGE_JPAGESZ PAGE_SIZE 2046#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2047#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2048 2049/* 2050 * Ring structures. Most of these reside in host memory and we tell 2051 * the NIC where they are via the ring control blocks. The exceptions 2052 * are the tx and command rings, which live in NIC memory and which 2053 * we access via the shared memory window. 2054 */ 2055struct bge_ring_data { 2056 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2057 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2058 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2059 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2060 struct bge_status_block bge_status_block; 2061 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2062 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2063 struct bge_gib bge_info; 2064}; 2065 2066/* 2067 * Mbuf pointers. We need these to keep track of the virtual addresses 2068 * of our mbuf chains since we can only convert from physical to virtual, 2069 * not the other way around. 2070 */ 2071struct bge_chain_data { 2072 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2073 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2074 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2075 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2076 /* Stick the jumbo mem management stuff here too. */ 2077 caddr_t bge_jslots[BGE_JSLOTS]; 2078 void *bge_jumbo_buf; 2079}; 2080 2081struct bge_type { 2082 u_int16_t bge_vid; 2083 u_int16_t bge_did; 2084 char *bge_name; 2085}; 2086 2087#define BGE_HWREV_TIGON 0x01 2088#define BGE_HWREV_TIGON_II 0x02 2089#define BGE_TIMEOUT 1000 2090#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2091 2092struct bge_jpool_entry { 2093 int slot; 2094 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 2095}; 2096 2097struct bge_bcom_hack { 2098 int reg; 2099 int val; 2100}; 2101 2102struct bge_softc { 2103 struct arpcom arpcom; /* interface info */ 2104 device_t bge_dev; 2105 device_t bge_miibus; 2106 bus_space_handle_t bge_bhandle; 2107 vm_offset_t bge_vhandle; 2108 bus_space_tag_t bge_btag; 2109 void *bge_intrhand; 2110 struct resource *bge_irq; 2111 struct resource *bge_res; 2112 struct ifmedia bge_ifmedia; /* TBI media info */ 2113 u_int8_t bge_unit; /* interface number */ 2114 u_int8_t bge_extram; /* has external SSRAM */ 2115 u_int8_t bge_tbi; 2116 u_int32_t bge_asicrev; 2117 struct bge_ring_data *bge_rdata; /* rings */ 2118 struct bge_chain_data bge_cdata; /* mbufs */ 2119 u_int16_t bge_tx_saved_considx; 2120 u_int16_t bge_rx_saved_considx; 2121 u_int16_t bge_ev_saved_considx; 2122 u_int16_t bge_std; /* current std ring head */ 2123 u_int16_t bge_jumbo; /* current jumo ring head */ 2124 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2125 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2126 u_int32_t bge_stat_ticks; 2127 u_int32_t bge_rx_coal_ticks; 2128 u_int32_t bge_tx_coal_ticks; 2129 u_int32_t bge_rx_max_coal_bds; 2130 u_int32_t bge_tx_max_coal_bds; 2131 u_int32_t bge_tx_buf_ratio; 2132 int bge_if_flags; 2133 int bge_txcnt; 2134 int bge_link; 2135 struct callout_handle bge_stat_ch; 2136 char *bge_vpd_prodname; 2137 char *bge_vpd_readonly; 2138}; 2139 2140#ifdef __alpha__ 2141#undef vtophys 2142#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 2143#endif 2144