if_bgereg.h revision 241388
1101099Srwatson/*- 2166533Srwatson * Copyright (c) 2001 Wind River Systems 3140628Srwatson * Copyright (c) 1997, 1998, 1999, 2001 4172930Srwatson * Bill Paul <wpaul@windriver.com>. All rights reserved. 5101099Srwatson * 6101099Srwatson * Redistribution and use in source and binary forms, with or without 7101099Srwatson * modification, are permitted provided that the following conditions 8101099Srwatson * are met: 9140628Srwatson * 1. Redistributions of source code must retain the above copyright 10140628Srwatson * notice, this list of conditions and the following disclaimer. 11140628Srwatson * 2. Redistributions in binary form must reproduce the above copyright 12140628Srwatson * notice, this list of conditions and the following disclaimer in the 13101099Srwatson * documentation and/or other materials provided with the distribution. 14172930Srwatson * 3. All advertising materials mentioning features or use of this software 15172930Srwatson * must display the following acknowledgement: 16172930Srwatson * This product includes software developed by Bill Paul. 17101099Srwatson * 4. Neither the name of the author nor the names of any co-contributors 18101099Srwatson * may be used to endorse or promote products derived from this software 19101099Srwatson * without specific prior written permission. 20101099Srwatson * 21101099Srwatson * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22101099Srwatson * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23101099Srwatson * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24101099Srwatson * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25101099Srwatson * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26101099Srwatson * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27101099Srwatson * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28101099Srwatson * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29101099Srwatson * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30101099Srwatson * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31101099Srwatson * THE POSSIBILITY OF SUCH DAMAGE. 32101099Srwatson * 33101099Srwatson * $FreeBSD: head/sys/dev/bge/if_bgereg.h 241388 2012-10-10 01:24:02Z yongari $ 34101099Srwatson */ 35101099Srwatson 36101099Srwatson/* 37101099Srwatson * BCM570x memory map. The internal memory layout varies somewhat 38101099Srwatson * depending on whether or not we have external SSRAM attached. 39101099Srwatson * The BCM5700 can have up to 16MB of external memory. The BCM5701 40101099Srwatson * is apparently not designed to use external SSRAM. The mappings 41101099Srwatson * up to the first 4 send rings are the same for both internal and 42101099Srwatson * external memory configurations. Note that mini RX ring space is 43168951Srwatson * only available with external SSRAM configurations, which means 44101099Srwatson * the mini RX ring is not supported on the BCM5701. 45101099Srwatson * 46101099Srwatson * The NIC's memory can be accessed by the host in one of 3 ways: 47101099Srwatson * 48101099Srwatson * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49105988Srwatson * registers in PCI config space can be used to read any 32-bit 50101099Srwatson * address within the NIC's memory. 51164184Strhodes * 52103183Sbde * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53145076Scsjp * space can be used in conjunction with the memory window in the 54101099Srwatson * device register space at offset 0x8000 to read any 32K chunk 55168951Srwatson * of NIC memory. 56101099Srwatson * 57115497Srwatson * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58101099Srwatson * set, the device I/O mapping consumes 32MB of host address space, 59101099Srwatson * allowing all of the registers and internal NIC memory to be 60101099Srwatson * accessed directly. NIC memory addresses are offset by 0x01000000. 61105696Srwatson * Flat mode consumes so much host address space that it is not 62101099Srwatson * recommended. 63101099Srwatson */ 64101099Srwatson#define BGE_PAGE_ZERO 0x00000000 65101099Srwatson#define BGE_PAGE_ZERO_END 0x000000FF 66101099Srwatson#define BGE_SEND_RING_RCB 0x00000100 67150340Sphk#define BGE_SEND_RING_RCB_END 0x000001FF 68101099Srwatson#define BGE_RX_RETURN_RING_RCB 0x00000200 69140628Srwatson#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70140628Srwatson#define BGE_STATS_BLOCK 0x00000300 71140628Srwatson#define BGE_STATS_BLOCK_END 0x00000AFF 72101099Srwatson#define BGE_STATUS_BLOCK 0x00000B00 73101099Srwatson#define BGE_STATUS_BLOCK_END 0x00000B4F 74101099Srwatson#define BGE_SRAM_FW_MB 0x00000B50 75101099Srwatson#define BGE_SRAM_DATA_SIG 0x00000B54 76101099Srwatson#define BGE_SRAM_DATA_CFG 0x00000B58 77101099Srwatson#define BGE_SRAM_FW_CMD_MB 0x00000B78 78101099Srwatson#define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C 79101099Srwatson#define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80 80101099Srwatson#define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04 81122875Srwatson#define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14 82101099Srwatson#define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18 83101099Srwatson#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 84122879Srwatson#define BGE_UNMAPPED 0x00001000 85101099Srwatson#define BGE_UNMAPPED_END 0x00001FFF 86101099Srwatson#define BGE_DMA_DESCRIPTORS 0x00002000 87165469Srwatson#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 88101099Srwatson#define BGE_SEND_RING_5717 0x00004000 89101099Srwatson#define BGE_SEND_RING_1_TO_4 0x00004000 90101099Srwatson#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 91101099Srwatson 92101099Srwatson/* Firmware interface */ 93101099Srwatson#define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */ 94101099Srwatson 95172955Srwatson#define BGE_FW_CMD_DRV_ALIVE 0x00000001 96105988Srwatson#define BGE_FW_CMD_PAUSE 0x00000002 97172955Srwatson#define BGE_FW_CMD_IPV4_ADDR_CHANGE 0x00000003 98105988Srwatson#define BGE_FW_CMD_IPV6_ADDR_CHANGE 0x00000004 99172955Srwatson#define BGE_FW_CMD_LINK_UPDATE 0x0000000C 100172955Srwatson#define BGE_FW_CMD_DRV_ALIVE2 0x0000000D 101172955Srwatson#define BGE_FW_CMD_DRV_ALIVE3 0x0000000E 102172955Srwatson 103101099Srwatson#define BGE_FW_HB_TIMEOUT_SEC 3 104101099Srwatson 105101099Srwatson#define BGE_FW_DRV_STATE_START 0x00000001 106101099Srwatson#define BGE_FW_DRV_STATE_START_DONE 0x80000001 107101099Srwatson#define BGE_FW_DRV_STATE_UNLOAD 0x00000002 108101099Srwatson#define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002 109101099Srwatson#define BGE_FW_DRV_STATE_WOL 0x00000003 110101099Srwatson#define BGE_FW_DRV_STATE_SUSPEND 0x00000004 111101099Srwatson 112101099Srwatson/* Mappings for internal memory configuration */ 113101099Srwatson#define BGE_STD_RX_RINGS 0x00006000 114101099Srwatson#define BGE_STD_RX_RINGS_END 0x00006FFF 115101099Srwatson#define BGE_JUMBO_RX_RINGS 0x00007000 116101099Srwatson#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 117101099Srwatson#define BGE_BUFFPOOL_1 0x00008000 118101099Srwatson#define BGE_BUFFPOOL_1_END 0x0000FFFF 119105643Srwatson#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 120105643Srwatson#define BGE_BUFFPOOL_2_END 0x00017FFF 121105643Srwatson#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 122105643Srwatson#define BGE_BUFFPOOL_3_END 0x0001FFFF 123105606Srwatson#define BGE_STD_RX_RINGS_5717 0x00040000 124105606Srwatson#define BGE_JUMBO_RX_RINGS_5717 0x00044400 125105606Srwatson 126105606Srwatson/* Mappings for external SSRAM configurations */ 127105606Srwatson#define BGE_SEND_RING_5_TO_6 0x00006000 128153927Scsjp#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 129153927Scsjp#define BGE_SEND_RING_7_TO_8 0x00007000 130153927Scsjp#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 131153927Scsjp#define BGE_SEND_RING_9_TO_16 0x00008000 132153927Scsjp#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 133105637Srwatson#define BGE_EXT_STD_RX_RINGS 0x0000C000 134101099Srwatson#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 135105637Srwatson#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 136105637Srwatson#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 137101099Srwatson#define BGE_MINI_RX_RINGS 0x0000E000 138172955Srwatson#define BGE_MINI_RX_RINGS_END 0x0000FFFF 139172955Srwatson#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 140172955Srwatson#define BGE_AVAIL_REGION1_END 0x00017FFF 141101099Srwatson#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 142122879Srwatson#define BGE_AVAIL_REGION2_END 0x0001FFFF 143101099Srwatson#define BGE_EXT_SSRAM 0x00020000 144105643Srwatson#define BGE_EXT_SSRAM_END 0x000FFFFF 145105643Srwatson 146105643Srwatson 147105643Srwatson/* 148105643Srwatson * BCM570x register offsets. These are memory mapped registers 149105643Srwatson * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 150105643Srwatson * Each register must be accessed using 32 bit operations. 151105643Srwatson * 152105643Srwatson * All registers are accessed through a 32K shared memory block. 153105643Srwatson * The first group of registers are actually copies of the PCI 154101099Srwatson * configuration space registers. 155104514Srwatson */ 156101099Srwatson 157101099Srwatson/* 158122879Srwatson * PCI registers defined in the PCI 2.2 spec. 159101099Srwatson */ 160101099Srwatson#define BGE_PCI_VID 0x00 161101099Srwatson#define BGE_PCI_DID 0x02 162172955Srwatson#define BGE_PCI_CMD 0x04 163101099Srwatson#define BGE_PCI_STS 0x06 164101099Srwatson#define BGE_PCI_REV 0x08 165172955Srwatson#define BGE_PCI_CLASS 0x09 166172955Srwatson#define BGE_PCI_CACHESZ 0x0C 167101099Srwatson#define BGE_PCI_LATTIMER 0x0D 168101099Srwatson#define BGE_PCI_HDRTYPE 0x0E 169101099Srwatson#define BGE_PCI_BIST 0x0F 170101099Srwatson#define BGE_PCI_BAR0 0x10 171101099Srwatson#define BGE_PCI_BAR1 0x14 172172955Srwatson#define BGE_PCI_SUBSYS 0x2C 173105634Srwatson#define BGE_PCI_SUBVID 0x2E 174105634Srwatson#define BGE_PCI_ROMBASE 0x30 175172955Srwatson#define BGE_PCI_CAPPTR 0x34 176105634Srwatson#define BGE_PCI_INTLINE 0x3C 177105634Srwatson#define BGE_PCI_INTPIN 0x3D 178105634Srwatson#define BGE_PCI_MINGNT 0x3E 179105634Srwatson#define BGE_PCI_MAXLAT 0x3F 180105634Srwatson#define BGE_PCI_PCIXCAP 0x40 181172955Srwatson#define BGE_PCI_NEXTPTR_PM 0x41 182101099Srwatson#define BGE_PCI_PCIX_CMD 0x42 183105643Srwatson#define BGE_PCI_PCIX_STS 0x44 184101099Srwatson#define BGE_PCI_PWRMGMT_CAPID 0x48 185105736Srwatson#define BGE_PCI_NEXTPTR_VPD 0x49 186101099Srwatson#define BGE_PCI_PWRMGMT_CAPS 0x4A 187101099Srwatson#define BGE_PCI_PWRMGMT_CMD 0x4C 188101099Srwatson#define BGE_PCI_PWRMGMT_STS 0x4D 189101099Srwatson#define BGE_PCI_PWRMGMT_DATA 0x4F 190101099Srwatson#define BGE_PCI_VPD_CAPID 0x50 191101099Srwatson#define BGE_PCI_NEXTPTR_MSI 0x51 192101099Srwatson#define BGE_PCI_VPD_ADDR 0x52 193101099Srwatson#define BGE_PCI_VPD_DATA 0x54 194101099Srwatson#define BGE_PCI_MSI_CAPID 0x58 195101099Srwatson#define BGE_PCI_NEXTPTR_NONE 0x59 196101099Srwatson#define BGE_PCI_MSI_CTL 0x5A 197101099Srwatson#define BGE_PCI_MSI_ADDR_HI 0x5C 198101099Srwatson#define BGE_PCI_MSI_ADDR_LO 0x60 199101099Srwatson#define BGE_PCI_MSI_DATA 0x64 200101099Srwatson 201172955Srwatson/* 202101099Srwatson * PCI Express definitions 203101099Srwatson * According to 204101099Srwatson * PCI Express base specification, REV. 1.0a 205101099Srwatson */ 206101099Srwatson 207101099Srwatson/* PCI Express device control, 16bits */ 208101099Srwatson#define BGE_PCIE_DEVCTL 0x08 209101099Srwatson#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 210101099Srwatson#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 211101099Srwatson#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 212101099Srwatson#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 213101099Srwatson#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 214105643Srwatson#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 215105643Srwatson#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 216105643Srwatson 217105643Srwatson/* PCI MSI. ??? */ 218105643Srwatson#define BGE_PCIE_CAPID_REG 0xD0 219101099Srwatson#define BGE_PCIE_CAPID 0x10 220101099Srwatson 221101099Srwatson/* 222172955Srwatson * PCI registers specific to the BCM570x family. 223101099Srwatson */ 224101099Srwatson#define BGE_PCI_MISC_CTL 0x68 225101099Srwatson#define BGE_PCI_DMA_RW_CTL 0x6C 226172955Srwatson#define BGE_PCI_PCISTATE 0x70 227101099Srwatson#define BGE_PCI_CLKCTL 0x74 228101099Srwatson#define BGE_PCI_REG_BASEADDR 0x78 229101099Srwatson#define BGE_PCI_MEMWIN_BASEADDR 0x7C 230101099Srwatson#define BGE_PCI_REG_DATA 0x80 231101099Srwatson#define BGE_PCI_MEMWIN_DATA 0x84 232101099Srwatson#define BGE_PCI_MODECTL 0x88 233172955Srwatson#define BGE_PCI_MISC_CFG 0x8C 234105988Srwatson#define BGE_PCI_MISC_LOCALCTL 0x90 235105988Srwatson#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 236105988Srwatson#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 237172955Srwatson#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 238172955Srwatson#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 239172955Srwatson#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 240105988Srwatson#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 241105988Srwatson#define BGE_PCI_ISR_MBX_HI 0xB0 242105988Srwatson#define BGE_PCI_ISR_MBX_LO 0xB4 243105988Srwatson#define BGE_PCI_PRODID_ASICREV 0xBC 244105988Srwatson#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 245105988Srwatson#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 246172955Srwatson 247101099Srwatson/* PCI Misc. Host control register */ 248101099Srwatson#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 249172955Srwatson#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 250101099Srwatson#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 251172955Srwatson#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 252101099Srwatson#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 253101099Srwatson#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 254101099Srwatson#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 255101099Srwatson#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 256172955Srwatson#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 257101099Srwatson#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 258101099Srwatson#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 259132232Srwatson 260172955Srwatson#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 261103750Srwatson 262172955Srwatson#define BGE_INIT \ 263101099Srwatson (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 264172955Srwatson BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 265132232Srwatson 266172955Srwatson#define BGE_CHIPID_TIGON_I 0x4000 267101099Srwatson#define BGE_CHIPID_TIGON_II 0x6000 268101099Srwatson#define BGE_CHIPID_BCM5700_A0 0x7000 269101099Srwatson#define BGE_CHIPID_BCM5700_A1 0x7001 270101099Srwatson#define BGE_CHIPID_BCM5700_B0 0x7100 271101099Srwatson#define BGE_CHIPID_BCM5700_B1 0x7101 272101099Srwatson#define BGE_CHIPID_BCM5700_B2 0x7102 273172955Srwatson#define BGE_CHIPID_BCM5700_B3 0x7103 274101099Srwatson#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 275132232Srwatson#define BGE_CHIPID_BCM5700_C0 0x7200 276172955Srwatson#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 277132232Srwatson#define BGE_CHIPID_BCM5701_B0 0x0100 278172955Srwatson#define BGE_CHIPID_BCM5701_B2 0x0102 279101099Srwatson#define BGE_CHIPID_BCM5701_B5 0x0105 280172955Srwatson#define BGE_CHIPID_BCM5703_A0 0x1000 281101099Srwatson#define BGE_CHIPID_BCM5703_A1 0x1001 282101099Srwatson#define BGE_CHIPID_BCM5703_A2 0x1002 283101099Srwatson#define BGE_CHIPID_BCM5703_A3 0x1003 284172955Srwatson#define BGE_CHIPID_BCM5703_B0 0x1100 285101099Srwatson#define BGE_CHIPID_BCM5704_A0 0x2000 286101099Srwatson#define BGE_CHIPID_BCM5704_A1 0x2001 287101099Srwatson#define BGE_CHIPID_BCM5704_A2 0x2002 288101099Srwatson#define BGE_CHIPID_BCM5704_A3 0x2003 289101099Srwatson#define BGE_CHIPID_BCM5704_B0 0x2100 290101099Srwatson#define BGE_CHIPID_BCM5705_A0 0x3000 291101099Srwatson#define BGE_CHIPID_BCM5705_A1 0x3001 292101099Srwatson#define BGE_CHIPID_BCM5705_A2 0x3002 293101099Srwatson#define BGE_CHIPID_BCM5705_A3 0x3003 294101099Srwatson#define BGE_CHIPID_BCM5750_A0 0x4000 295172955Srwatson#define BGE_CHIPID_BCM5750_A1 0x4001 296101099Srwatson#define BGE_CHIPID_BCM5750_A3 0x4000 297101099Srwatson#define BGE_CHIPID_BCM5750_B0 0x4100 298132232Srwatson#define BGE_CHIPID_BCM5750_B1 0x4101 299172955Srwatson#define BGE_CHIPID_BCM5750_C0 0x4200 300132232Srwatson#define BGE_CHIPID_BCM5750_C1 0x4201 301172955Srwatson#define BGE_CHIPID_BCM5750_C2 0x4202 302101099Srwatson#define BGE_CHIPID_BCM5714_A0 0x5000 303172955Srwatson#define BGE_CHIPID_BCM5752_A0 0x6000 304101099Srwatson#define BGE_CHIPID_BCM5752_A1 0x6001 305101099Srwatson#define BGE_CHIPID_BCM5752_A2 0x6002 306101099Srwatson#define BGE_CHIPID_BCM5714_B0 0x8000 307172955Srwatson#define BGE_CHIPID_BCM5714_B3 0x8003 308105634Srwatson#define BGE_CHIPID_BCM5715_A0 0x9000 309105634Srwatson#define BGE_CHIPID_BCM5715_A1 0x9001 310172955Srwatson#define BGE_CHIPID_BCM5715_A3 0x9003 311172955Srwatson#define BGE_CHIPID_BCM5755_A0 0xa000 312105634Srwatson#define BGE_CHIPID_BCM5755_A1 0xa001 313172955Srwatson#define BGE_CHIPID_BCM5755_A2 0xa002 314105634Srwatson#define BGE_CHIPID_BCM5722_A0 0xa200 315172955Srwatson#define BGE_CHIPID_BCM5754_A0 0xb000 316172955Srwatson#define BGE_CHIPID_BCM5754_A1 0xb001 317105634Srwatson#define BGE_CHIPID_BCM5754_A2 0xb002 318172955Srwatson#define BGE_CHIPID_BCM5761_A0 0x5761000 319105637Srwatson#define BGE_CHIPID_BCM5761_A1 0x5761100 320105634Srwatson#define BGE_CHIPID_BCM5784_A0 0x5784000 321105634Srwatson#define BGE_CHIPID_BCM5784_A1 0x5784100 322105634Srwatson#define BGE_CHIPID_BCM5787_A0 0xb000 323105634Srwatson#define BGE_CHIPID_BCM5787_A1 0xb001 324105634Srwatson#define BGE_CHIPID_BCM5787_A2 0xb002 325105634Srwatson#define BGE_CHIPID_BCM5906_A0 0xc000 326172955Srwatson#define BGE_CHIPID_BCM5906_A1 0xc001 327105634Srwatson#define BGE_CHIPID_BCM5906_A2 0xc002 328105634Srwatson#define BGE_CHIPID_BCM57780_A0 0x57780000 329172955Srwatson#define BGE_CHIPID_BCM57780_A1 0x57780001 330172955Srwatson#define BGE_CHIPID_BCM5717_A0 0x05717000 331105634Srwatson#define BGE_CHIPID_BCM5717_B0 0x05717100 332132232Srwatson#define BGE_CHIPID_BCM5719_A0 0x05719000 333172955Srwatson#define BGE_CHIPID_BCM5720_A0 0x05720000 334105634Srwatson#define BGE_CHIPID_BCM57765_A0 0x57785000 335105634Srwatson#define BGE_CHIPID_BCM57765_B0 0x57785100 336105634Srwatson 337172955Srwatson/* shorthand one */ 338172955Srwatson#define BGE_ASICREV(x) ((x) >> 12) 339105634Srwatson#define BGE_ASICREV_BCM5701 0x00 340105634Srwatson#define BGE_ASICREV_BCM5703 0x01 341105634Srwatson#define BGE_ASICREV_BCM5704 0x02 342172955Srwatson#define BGE_ASICREV_BCM5705 0x03 343172955Srwatson#define BGE_ASICREV_BCM5750 0x04 344105634Srwatson#define BGE_ASICREV_BCM5714_A0 0x05 345105634Srwatson#define BGE_ASICREV_BCM5752 0x06 346105634Srwatson#define BGE_ASICREV_BCM5700 0x07 347105634Srwatson#define BGE_ASICREV_BCM5780 0x08 348105634Srwatson#define BGE_ASICREV_BCM5714 0x09 349105634Srwatson#define BGE_ASICREV_BCM5755 0x0a 350106091Srwatson#define BGE_ASICREV_BCM5754 0x0b 351172955Srwatson#define BGE_ASICREV_BCM5787 0x0b 352105988Srwatson#define BGE_ASICREV_BCM5906 0x0c 353105988Srwatson/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 354172955Srwatson#define BGE_ASICREV_USE_PRODID_REG 0x0f 355172955Srwatson/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 356105988Srwatson#define BGE_ASICREV_BCM5717 0x5717 357172955Srwatson#define BGE_ASICREV_BCM5719 0x5719 358105988Srwatson#define BGE_ASICREV_BCM5720 0x5720 359105988Srwatson#define BGE_ASICREV_BCM5761 0x5761 360105634Srwatson#define BGE_ASICREV_BCM5784 0x5784 361172955Srwatson#define BGE_ASICREV_BCM5785 0x5785 362101099Srwatson#define BGE_ASICREV_BCM57765 0x57785 363101099Srwatson#define BGE_ASICREV_BCM57780 0x57780 364172955Srwatson 365172955Srwatson/* chip revisions */ 366101099Srwatson#define BGE_CHIPREV(x) ((x) >> 8) 367101099Srwatson#define BGE_CHIPREV_5700_AX 0x70 368101099Srwatson#define BGE_CHIPREV_5700_BX 0x71 369101099Srwatson#define BGE_CHIPREV_5700_CX 0x72 370101099Srwatson#define BGE_CHIPREV_5701_AX 0x00 371101099Srwatson#define BGE_CHIPREV_5703_AX 0x10 372172955Srwatson#define BGE_CHIPREV_5704_AX 0x20 373105643Srwatson#define BGE_CHIPREV_5704_BX 0x21 374172955Srwatson#define BGE_CHIPREV_5750_AX 0x40 375101099Srwatson#define BGE_CHIPREV_5750_BX 0x41 376101099Srwatson/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 377101099Srwatson#define BGE_CHIPREV_5717_AX 0x57170 378101099Srwatson#define BGE_CHIPREV_5717_BX 0x57171 379101099Srwatson#define BGE_CHIPREV_5761_AX 0x57611 380101099Srwatson#define BGE_CHIPREV_5784_AX 0x57841 381101099Srwatson 382172955Srwatson/* PCI DMA Read/Write Control register */ 383101099Srwatson#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 384101099Srwatson#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 385101099Srwatson#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 386172955Srwatson#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 387172955Srwatson#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 388101099Srwatson#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 389101099Srwatson#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 390101099Srwatson#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 391101099Srwatson#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 392101099Srwatson#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 393101099Srwatson#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 394172955Srwatson#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 395105643Srwatson#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 396172955Srwatson 397101099Srwatson#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 398101099Srwatson#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 399101099Srwatson#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 400101099Srwatson#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 401101099Srwatson 402101099Srwatson#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 403101099Srwatson#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 404172955Srwatson 405101099Srwatson#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 406101099Srwatson#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 407101099Srwatson#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 408101099Srwatson#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 409101099Srwatson#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 410101099Srwatson#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 411172955Srwatson#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 412105643Srwatson#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 413172955Srwatson 414101099Srwatson#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 415101099Srwatson#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 416101099Srwatson#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 417101099Srwatson#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 418101099Srwatson#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 419101099Srwatson#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 420172955Srwatson#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 421172955Srwatson#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 422101099Srwatson 423101099Srwatson/* 424172955Srwatson * PCI state register -- note, this register is read only 425172955Srwatson * unless the PCISTATE_WR bit of the PCI Misc. Host Control 426101099Srwatson * register is set. 427101099Srwatson */ 428101099Srwatson#define BGE_PCISTATE_FORCE_RESET 0x00000001 429101099Srwatson#define BGE_PCISTATE_INTR_STATE 0x00000002 430101099Srwatson#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 431101099Srwatson#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 432101099Srwatson#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 433172955Srwatson#define BGE_PCISTATE_WANT_EXPROM 0x00000020 434172955Srwatson#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 435172955Srwatson#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 436101099Srwatson#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 437101099Srwatson 438172955Srwatson/* 439172955Srwatson * PCI Clock Control register -- note, this register is read only 440105643Srwatson * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 441172955Srwatson * register is set. 442172955Srwatson */ 443172955Srwatson#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 444172955Srwatson#define BGE_PCICLOCKCTL_M66EN 0x00000080 445105643Srwatson#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 446172955Srwatson#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 447172955Srwatson#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 448172955Srwatson#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 449101099Srwatson#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 450101099Srwatson#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 451101099Srwatson#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 452172955Srwatson#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 453105643Srwatson 454101099Srwatson 455101099Srwatson#ifndef PCIM_CMD_MWIEN 456172955Srwatson#define PCIM_CMD_MWIEN 0x0010 457172955Srwatson#endif 458105643Srwatson#ifndef PCIM_CMD_INTxDIS 459172955Srwatson#define PCIM_CMD_INTxDIS 0x0400 460172955Srwatson#endif 461172955Srwatson 462101099Srwatson/* 463101099Srwatson * High priority mailbox registers 464101099Srwatson * Each mailbox is 64-bits wide, though we only use the 465172955Srwatson * lower 32 bits. To write a 64-bit value, write the upper 32 bits 466101099Srwatson * first. The NIC will load the mailbox after the lower 32 bit word 467105643Srwatson * has been updated. 468101099Srwatson */ 469172955Srwatson#define BGE_MBX_IRQ0_HI 0x0200 470101099Srwatson#define BGE_MBX_IRQ0_LO 0x0204 471101099Srwatson#define BGE_MBX_IRQ1_HI 0x0208 472101099Srwatson#define BGE_MBX_IRQ1_LO 0x020C 473101099Srwatson#define BGE_MBX_IRQ2_HI 0x0210 474101099Srwatson#define BGE_MBX_IRQ2_LO 0x0214 475101099Srwatson#define BGE_MBX_IRQ3_HI 0x0218 476101099Srwatson#define BGE_MBX_IRQ3_LO 0x021C 477172955Srwatson#define BGE_MBX_GEN0_HI 0x0220 478101099Srwatson#define BGE_MBX_GEN0_LO 0x0224 479101099Srwatson#define BGE_MBX_GEN1_HI 0x0228 480132232Srwatson#define BGE_MBX_GEN1_LO 0x022C 481172955Srwatson#define BGE_MBX_GEN2_HI 0x0230 482101099Srwatson#define BGE_MBX_GEN2_LO 0x0234 483132232Srwatson#define BGE_MBX_GEN3_HI 0x0228 484132232Srwatson#define BGE_MBX_GEN3_LO 0x022C 485101099Srwatson#define BGE_MBX_GEN4_HI 0x0240 486101099Srwatson#define BGE_MBX_GEN4_LO 0x0244 487105656Srwatson#define BGE_MBX_GEN5_HI 0x0248 488172955Srwatson#define BGE_MBX_GEN5_LO 0x024C 489105656Srwatson#define BGE_MBX_GEN6_HI 0x0250 490105656Srwatson#define BGE_MBX_GEN6_LO 0x0254 491132232Srwatson#define BGE_MBX_GEN7_HI 0x0258 492172955Srwatson#define BGE_MBX_GEN7_LO 0x025C 493105656Srwatson#define BGE_MBX_RELOAD_STATS_HI 0x0260 494172955Srwatson#define BGE_MBX_RELOAD_STATS_LO 0x0264 495105656Srwatson#define BGE_MBX_RX_STD_PROD_HI 0x0268 496105656Srwatson#define BGE_MBX_RX_STD_PROD_LO 0x026C 497101099Srwatson#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 498101099Srwatson#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 499101099Srwatson#define BGE_MBX_RX_MINI_PROD_HI 0x0278 500101099Srwatson#define BGE_MBX_RX_MINI_PROD_LO 0x027C 501172955Srwatson#define BGE_MBX_RX_CONS0_HI 0x0280 502101099Srwatson#define BGE_MBX_RX_CONS0_LO 0x0284 503101099Srwatson#define BGE_MBX_RX_CONS1_HI 0x0288 504122879Srwatson#define BGE_MBX_RX_CONS1_LO 0x028C 505122879Srwatson#define BGE_MBX_RX_CONS2_HI 0x0290 506101099Srwatson#define BGE_MBX_RX_CONS2_LO 0x0294 507101099Srwatson#define BGE_MBX_RX_CONS3_HI 0x0298 508101099Srwatson#define BGE_MBX_RX_CONS3_LO 0x029C 509101099Srwatson#define BGE_MBX_RX_CONS4_HI 0x02A0 510101099Srwatson#define BGE_MBX_RX_CONS4_LO 0x02A4 511101099Srwatson#define BGE_MBX_RX_CONS5_HI 0x02A8 512172955Srwatson#define BGE_MBX_RX_CONS5_LO 0x02AC 513101099Srwatson#define BGE_MBX_RX_CONS6_HI 0x02B0 514101099Srwatson#define BGE_MBX_RX_CONS6_LO 0x02B4 515132781Skan#define BGE_MBX_RX_CONS7_HI 0x02B8 516101099Srwatson#define BGE_MBX_RX_CONS7_LO 0x02BC 517101099Srwatson#define BGE_MBX_RX_CONS8_HI 0x02C0 518101099Srwatson#define BGE_MBX_RX_CONS8_LO 0x02C4 519172955Srwatson#define BGE_MBX_RX_CONS9_HI 0x02C8 520101099Srwatson#define BGE_MBX_RX_CONS9_LO 0x02CC 521101099Srwatson#define BGE_MBX_RX_CONS10_HI 0x02D0 522132781Skan#define BGE_MBX_RX_CONS10_LO 0x02D4 523101099Srwatson#define BGE_MBX_RX_CONS11_HI 0x02D8 524101099Srwatson#define BGE_MBX_RX_CONS11_LO 0x02DC 525101099Srwatson#define BGE_MBX_RX_CONS12_HI 0x02E0 526101099Srwatson#define BGE_MBX_RX_CONS12_LO 0x02E4 527101099Srwatson#define BGE_MBX_RX_CONS13_HI 0x02E8 528101099Srwatson#define BGE_MBX_RX_CONS13_LO 0x02EC 529101099Srwatson#define BGE_MBX_RX_CONS14_HI 0x02F0 530172955Srwatson#define BGE_MBX_RX_CONS14_LO 0x02F4 531101099Srwatson#define BGE_MBX_RX_CONS15_HI 0x02F8 532101099Srwatson#define BGE_MBX_RX_CONS15_LO 0x02FC 533101099Srwatson#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 534132781Skan#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 535101099Srwatson#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 536101099Srwatson#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 537105696Srwatson#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 538172955Srwatson#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 539172955Srwatson#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 540172955Srwatson#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 541105696Srwatson#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 542115497Srwatson#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 543172955Srwatson#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 544105696Srwatson#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 545115497Srwatson#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 546105696Srwatson#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 547105696Srwatson#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 548105696Srwatson#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 549115497Srwatson#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 550105696Srwatson#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 551105696Srwatson#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 552115497Srwatson#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 553105696Srwatson#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 554105696Srwatson#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 555115497Srwatson#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 556105696Srwatson#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 557105696Srwatson#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 558115497Srwatson#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 559115497Srwatson#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 560115497Srwatson#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 561115497Srwatson#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 562115497Srwatson#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 563115497Srwatson#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 564115497Srwatson#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 565115497Srwatson#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 566115497Srwatson#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 567115497Srwatson#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 568115497Srwatson#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 569115497Srwatson#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 570115497Srwatson#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 571115497Srwatson#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 572115497Srwatson#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 573115497Srwatson#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 574115497Srwatson#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 575105696Srwatson#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 576115497Srwatson#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 577105696Srwatson#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 578105696Srwatson#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 579172955Srwatson#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 580105696Srwatson#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 581105696Srwatson#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 582105696Srwatson#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 583105696Srwatson#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 584115497Srwatson#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 585172955Srwatson#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 586172955Srwatson#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 587172955Srwatson#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 588172955Srwatson#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 589172955Srwatson#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 590115497Srwatson#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 591101099Srwatson#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 592172955Srwatson#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 593101099Srwatson#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 594105696Srwatson#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 595172955Srwatson#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 596172955Srwatson#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 597105696Srwatson 598105696Srwatson#define BGE_TX_RINGS_MAX 4 599105696Srwatson#define BGE_TX_RINGS_EXTSSRAM_MAX 16 600172955Srwatson#define BGE_RX_RINGS_MAX 16 601116701Srwatson#define BGE_RX_RINGS_MAX_5717 17 602105696Srwatson 603105696Srwatson/* Ethernet MAC control registers */ 604172955Srwatson#define BGE_MAC_MODE 0x0400 605105696Srwatson#define BGE_MAC_STS 0x0404 606105696Srwatson#define BGE_MAC_EVT_ENB 0x0408 607116701Srwatson#define BGE_MAC_LED_CTL 0x040C 608105696Srwatson#define BGE_MAC_ADDR1_LO 0x0410 609105696Srwatson#define BGE_MAC_ADDR1_HI 0x0414 610172955Srwatson#define BGE_MAC_ADDR2_LO 0x0418 611105696Srwatson#define BGE_MAC_ADDR2_HI 0x041C 612105696Srwatson#define BGE_MAC_ADDR3_LO 0x0420 613116701Srwatson#define BGE_MAC_ADDR3_HI 0x0424 614105696Srwatson#define BGE_MAC_ADDR4_LO 0x0428 615105696Srwatson#define BGE_MAC_ADDR4_HI 0x042C 616105696Srwatson#define BGE_WOL_PATPTR 0x0430 617105696Srwatson#define BGE_WOL_PATCFG 0x0434 618105696Srwatson#define BGE_TX_RANDOM_BACKOFF 0x0438 619105696Srwatson#define BGE_RX_MTU 0x043C 620105696Srwatson#define BGE_GBIT_PCS_TEST 0x0440 621172955Srwatson#define BGE_TX_TBI_AUTONEG 0x0444 622116701Srwatson#define BGE_RX_TBI_AUTONEG 0x0448 623105696Srwatson#define BGE_MI_COMM 0x044C 624172955Srwatson#define BGE_MI_STS 0x0450 625101099Srwatson#define BGE_MI_MODE 0x0454 626105696Srwatson#define BGE_AUTOPOLL_STS 0x0458 627105696Srwatson#define BGE_TX_MODE 0x045C 628105696Srwatson#define BGE_TX_STS 0x0460 629105696Srwatson#define BGE_TX_LENGTHS 0x0464 630105696Srwatson#define BGE_RX_MODE 0x0468 631172955Srwatson#define BGE_RX_STS 0x046C 632172955Srwatson#define BGE_MAR0 0x0470 633105696Srwatson#define BGE_MAR1 0x0474 634105696Srwatson#define BGE_MAR2 0x0478 635105696Srwatson#define BGE_MAR3 0x047C 636172955Srwatson#define BGE_RX_BD_RULES_CTL0 0x0480 637101099Srwatson#define BGE_RX_BD_RULES_MASKVAL0 0x0484 638115395Srwatson#define BGE_RX_BD_RULES_CTL1 0x0488 639115395Srwatson#define BGE_RX_BD_RULES_MASKVAL1 0x048C 640105696Srwatson#define BGE_RX_BD_RULES_CTL2 0x0490 641105696Srwatson#define BGE_RX_BD_RULES_MASKVAL2 0x0494 642105696Srwatson#define BGE_RX_BD_RULES_CTL3 0x0498 643105696Srwatson#define BGE_RX_BD_RULES_MASKVAL3 0x049C 644105696Srwatson#define BGE_RX_BD_RULES_CTL4 0x04A0 645105696Srwatson#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 646105696Srwatson#define BGE_RX_BD_RULES_CTL5 0x04A8 647105696Srwatson#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 648105696Srwatson#define BGE_RX_BD_RULES_CTL6 0x04B0 649105696Srwatson#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 650105696Srwatson#define BGE_RX_BD_RULES_CTL7 0x04B8 651105696Srwatson#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 652105696Srwatson#define BGE_RX_BD_RULES_CTL8 0x04C0 653105696Srwatson#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 654115395Srwatson#define BGE_RX_BD_RULES_CTL9 0x04C8 655105696Srwatson#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 656115395Srwatson#define BGE_RX_BD_RULES_CTL10 0x04D0 657115395Srwatson#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 658115395Srwatson#define BGE_RX_BD_RULES_CTL11 0x04D8 659115395Srwatson#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 660115395Srwatson#define BGE_RX_BD_RULES_CTL12 0x04E0 661115395Srwatson#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 662105696Srwatson#define BGE_RX_BD_RULES_CTL13 0x04E8 663115395Srwatson#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 664115395Srwatson#define BGE_RX_BD_RULES_CTL14 0x04F0 665115395Srwatson#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 666105696Srwatson#define BGE_RX_BD_RULES_CTL15 0x04F8 667115395Srwatson#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 668115395Srwatson#define BGE_RX_RULES_CFG 0x0500 669115395Srwatson#define BGE_MAX_RX_FRAME_LOWAT 0x0504 670115395Srwatson#define BGE_SERDES_CFG 0x0590 671115395Srwatson#define BGE_SERDES_STS 0x0594 672115395Srwatson#define BGE_SGDIG_CFG 0x05B0 673115395Srwatson#define BGE_SGDIG_STS 0x05B4 674115395Srwatson#define BGE_TX_MAC_STATS_OCTETS 0x0800 675115395Srwatson#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 676105696Srwatson#define BGE_TX_MAC_STATS_COLLS 0x0808 677115395Srwatson#define BGE_TX_MAC_STATS_XON_SENT 0x080C 678115395Srwatson#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 679115395Srwatson#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 680105696Srwatson#define BGE_TX_MAC_STATS_ERRORS 0x0818 681115395Srwatson#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 682105696Srwatson#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 683115395Srwatson#define BGE_TX_MAC_STATS_DEFERRED 0x0824 684105696Srwatson#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 685105696Srwatson#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 686105696Srwatson#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 687105696Srwatson#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 688105696Srwatson#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 689105696Srwatson#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 690105696Srwatson#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 691105696Srwatson#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 692105696Srwatson#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 693105696Srwatson#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 694105696Srwatson#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 695172955Srwatson#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 696105696Srwatson#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 697132232Srwatson#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 698101099Srwatson#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 699101099Srwatson#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 700132232Srwatson#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 701132232Srwatson#define BGE_TX_MAC_STATS_UCAST 0x086C 702132232Srwatson#define BGE_TX_MAC_STATS_MCAST 0x0870 703115395Srwatson#define BGE_TX_MAC_STATS_BCAST 0x0874 704115395Srwatson#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 705115395Srwatson#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 706115395Srwatson#define BGE_RX_MAC_STATS_OCTESTS 0x0880 707105696Srwatson#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 708115395Srwatson#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 709115395Srwatson#define BGE_RX_MAC_STATS_UCAST 0x088C 710105696Srwatson#define BGE_RX_MAC_STATS_MCAST 0x0890 711115395Srwatson#define BGE_RX_MAC_STATS_BCAST 0x0894 712105696Srwatson#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 713115395Srwatson#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 714115395Srwatson#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 715115395Srwatson#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 716105696Srwatson#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 717115395Srwatson#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 718105696Srwatson#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 719105696Srwatson#define BGE_RX_MAC_STATS_JABBERS 0x08B4 720172955Srwatson#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 721101099Srwatson 722172955Srwatson/* Ethernet MAC Mode register */ 723132232Srwatson#define BGE_MACMODE_RESET 0x00000001 724172955Srwatson#define BGE_MACMODE_HALF_DUPLEX 0x00000002 725105696Srwatson#define BGE_MACMODE_PORTMODE 0x0000000C 726105696Srwatson#define BGE_MACMODE_LOOPBACK 0x00000010 727172955Srwatson#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 728105696Srwatson#define BGE_MACMODE_TX_BURST_ENB 0x00000100 729105696Srwatson#define BGE_MACMODE_MAX_DEFER 0x00000200 730105696Srwatson#define BGE_MACMODE_LINK_POLARITY 0x00000400 731172955Srwatson#define BGE_MACMODE_RX_STATS_ENB 0x00000800 732105696Srwatson#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 733105696Srwatson#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 734172955Srwatson#define BGE_MACMODE_TX_STATS_ENB 0x00004000 735105696Srwatson#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 736105696Srwatson#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 737172955Srwatson#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 738105696Srwatson#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 739105696Srwatson#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 740172955Srwatson#define BGE_MACMODE_MIP_ENB 0x00100000 741101099Srwatson#define BGE_MACMODE_TXDMA_ENB 0x00200000 742101099Srwatson#define BGE_MACMODE_RXDMA_ENB 0x00400000 743101099Srwatson#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 744105696Srwatson 745105696Srwatson#define BGE_PORTMODE_NONE 0x00000000 746101099Srwatson#define BGE_PORTMODE_MII 0x00000004 747105696Srwatson#define BGE_PORTMODE_GMII 0x00000008 748172955Srwatson#define BGE_PORTMODE_TBI 0x0000000C 749105696Srwatson 750105696Srwatson/* MAC Status register */ 751172955Srwatson#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 752105696Srwatson#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 753105696Srwatson#define BGE_MACSTAT_RX_CFG 0x00000004 754105696Srwatson#define BGE_MACSTAT_CFG_CHANGED 0x00000008 755105696Srwatson#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 756105696Srwatson#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 757105696Srwatson#define BGE_MACSTAT_LINK_CHANGED 0x00001000 758105696Srwatson#define BGE_MACSTAT_MI_COMPLETE 0x00400000 759172955Srwatson#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 760105696Srwatson#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 761105696Srwatson#define BGE_MACSTAT_ODI_ERROR 0x02000000 762105696Srwatson#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 763172955Srwatson#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 764172955Srwatson 765105696Srwatson/* MAC Event Enable Register */ 766101099Srwatson#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 767101099Srwatson#define BGE_EVTENB_LINK_CHANGED 0x00001000 768101099Srwatson#define BGE_EVTENB_MI_COMPLETE 0x00400000 769105696Srwatson#define BGE_EVTENB_MI_INTERRUPT 0x00800000 770172955Srwatson#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 771105696Srwatson#define BGE_EVTENB_ODI_ERROR 0x02000000 772105696Srwatson#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 773105696Srwatson#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 774105696Srwatson 775105696Srwatson/* LED Control Register */ 776101099Srwatson#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 777172955Srwatson#define BGE_LEDCTL_1000MBPS_LED 0x00000002 778172955Srwatson#define BGE_LEDCTL_100MBPS_LED 0x00000004 779101099Srwatson#define BGE_LEDCTL_10MBPS_LED 0x00000008 780101099Srwatson#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 781172955Srwatson#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 782168976Srwatson#define BGE_LEDCTL_TRAFLED_BLINK_2 0x00000040 783101099Srwatson#define BGE_LEDCTL_1000MBPS_STS 0x00000080 784172955Srwatson#define BGE_LEDCTL_100MBPS_STS 0x00000100 785101099Srwatson#define BGE_LEDCTL_10MBPS_STS 0x00000200 786101099Srwatson#define BGE_LEDCTL_TRAFLED_STS 0x00000400 787172955Srwatson#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 788101099Srwatson#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 789101099Srwatson 790101099Srwatson/* TX backoff seed register */ 791101099Srwatson#define BGE_TX_BACKOFF_SEED_MASK 0x3F 792101099Srwatson 793105606Srwatson/* Autopoll status register */ 794105606Srwatson#define BGE_AUTOPOLLSTS_ERROR 0x00000001 795105606Srwatson 796105606Srwatson/* Transmit MAC mode register */ 797101099Srwatson#define BGE_TXMODE_RESET 0x00000001 798101099Srwatson#define BGE_TXMODE_ENABLE 0x00000002 799172955Srwatson#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 800101099Srwatson#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 801101099Srwatson#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 802101099Srwatson#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 803172955Srwatson#define BGE_TXMODE_JMB_FRM_LEN 0x00400000 804172955Srwatson#define BGE_TXMODE_CNT_DN_MODE 0x00800000 805101099Srwatson 806172955Srwatson/* Transmit MAC status register */ 807101099Srwatson#define BGE_TXSTAT_RX_XOFFED 0x00000001 808172955Srwatson#define BGE_TXSTAT_SENT_XOFF 0x00000002 809172955Srwatson#define BGE_TXSTAT_SENT_XON 0x00000004 810172955Srwatson#define BGE_TXSTAT_LINK_UP 0x00000008 811101099Srwatson#define BGE_TXSTAT_ODI_UFLOW 0x00000010 812101099Srwatson#define BGE_TXSTAT_ODI_OFLOW 0x00000020 813101099Srwatson 814172955Srwatson/* Transmit MAC lengths register */ 815107698Srwatson#define BGE_TXLEN_SLOTTIME 0x000000FF 816122563Srwatson#define BGE_TXLEN_IPG 0x00000F00 817104535Srwatson#define BGE_TXLEN_CRS 0x00003000 818104535Srwatson#define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 819104535Srwatson#define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 820122524Srwatson 821104535Srwatson/* Receive MAC mode register */ 822104535Srwatson#define BGE_RXMODE_RESET 0x00000001 823172955Srwatson#define BGE_RXMODE_ENABLE 0x00000002 824104535Srwatson#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 825104535Srwatson#define BGE_RXMODE_RX_GIANTS 0x00000020 826104535Srwatson#define BGE_RXMODE_RX_RUNTS 0x00000040 827172955Srwatson#define BGE_RXMODE_8022_LENCHECK 0x00000080 828168976Srwatson#define BGE_RXMODE_RX_PROMISC 0x00000100 829101099Srwatson#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 830101099Srwatson#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 831101099Srwatson 832122524Srwatson/* Receive MAC status register */ 833168976Srwatson#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 834172955Srwatson#define BGE_RXSTAT_RCVD_XOFF 0x00000002 835172955Srwatson#define BGE_RXSTAT_RCVD_XON 0x00000004 836101099Srwatson 837101099Srwatson/* Receive Rules Control register */ 838101099Srwatson#define BGE_RXRULECTL_OFFSET 0x000000FF 839172955Srwatson#define BGE_RXRULECTL_CLASS 0x00001F00 840168976Srwatson#define BGE_RXRULECTL_HDRTYPE 0x0000E000 841101099Srwatson#define BGE_RXRULECTL_COMPARE_OP 0x00030000 842101099Srwatson#define BGE_RXRULECTL_MAP 0x01000000 843101099Srwatson#define BGE_RXRULECTL_DISCARD 0x02000000 844168976Srwatson#define BGE_RXRULECTL_MASK 0x04000000 845168976Srwatson#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 846101099Srwatson#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 847172955Srwatson#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 848101099Srwatson#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 849101099Srwatson 850101099Srwatson/* Receive Rules Mask register */ 851172955Srwatson#define BGE_RXRULEMASK_VALUE 0x0000FFFF 852168976Srwatson#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 853101099Srwatson 854101099Srwatson/* SERDES configuration register */ 855101099Srwatson#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 856168976Srwatson#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 857168976Srwatson#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 858101099Srwatson#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 859172955Srwatson#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 860101099Srwatson#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 861101099Srwatson#define BGE_SERDESCFG_TXMODE 0x00001000 862101099Srwatson#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 863172955Srwatson#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 864105988Srwatson#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 865168976Srwatson#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 866101099Srwatson#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 867101099Srwatson#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 868101099Srwatson#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 869105988Srwatson#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 870168976Srwatson#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 871101099Srwatson 872172955Srwatson/* SERDES status register */ 873101099Srwatson#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 874101099Srwatson#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 875101099Srwatson 876172955Srwatson/* SGDIG config (not documented) */ 877168976Srwatson#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 878101099Srwatson#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 879172955Srwatson#define BGE_SGDIGCFG_SEND 0x40000000 880106354Smux#define BGE_SGDIGCFG_AUTO 0x80000000 881101099Srwatson 882168976Srwatson/* SGDIG status (not documented) */ 883168976Srwatson#define BGE_SGDIGSTS_DONE 0x00000002 884101099Srwatson#define BGE_SGDIGSTS_IS_SERDES 0x00000100 885172955Srwatson#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 886172955Srwatson#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 887105988Srwatson 888105988Srwatson 889172955Srwatson/* MI communication register */ 890105988Srwatson#define BGE_MICOMM_DATA 0x0000FFFF 891168954Srwatson#define BGE_MICOMM_REG 0x001F0000 892172955Srwatson#define BGE_MICOMM_PHY 0x03E00000 893105988Srwatson#define BGE_MICOMM_CMD 0x0C000000 894105988Srwatson#define BGE_MICOMM_READFAIL 0x10000000 895101099Srwatson#define BGE_MICOMM_BUSY 0x20000000 896101099Srwatson 897172955Srwatson#define BGE_MIREG(x) ((x & 0x1F) << 16) 898172955Srwatson#define BGE_MIPHY(x) ((x & 0x1F) << 21) 899105988Srwatson#define BGE_MICMD_WRITE 0x04000000 900105988Srwatson#define BGE_MICMD_READ 0x08000000 901105988Srwatson 902172955Srwatson/* MI status register */ 903172955Srwatson#define BGE_MISTS_LINK 0x00000001 904105988Srwatson#define BGE_MISTS_10MBPS 0x00000002 905105988Srwatson 906172955Srwatson#define BGE_MIMODE_CLK_10MHZ 0x00000001 907172955Srwatson#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 908172955Srwatson#define BGE_MIMODE_AUTOPOLL 0x00000010 909105988Srwatson#define BGE_MIMODE_CLKCNT 0x001F0000 910105988Srwatson#define BGE_MIMODE_500KHZ_CONST 0x00008000 911101099Srwatson#define BGE_MIMODE_BASE 0x000C0000 912172955Srwatson 913101099Srwatson 914101099Srwatson/* 915101099Srwatson * Send data initiator control registers. 916101099Srwatson */ 917172955Srwatson#define BGE_SDI_MODE 0x0C00 918172955Srwatson#define BGE_SDI_STATUS 0x0C04 919101099Srwatson#define BGE_SDI_STATS_CTL 0x0C08 920101099Srwatson#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 921101099Srwatson#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 922168976Srwatson#define BGE_ISO_PKT_TX 0x0C20 923168976Srwatson#define BGE_LOCSTATS_COS0 0x0C80 924101099Srwatson#define BGE_LOCSTATS_COS1 0x0C84 925172955Srwatson#define BGE_LOCSTATS_COS2 0x0C88 926101099Srwatson#define BGE_LOCSTATS_COS3 0x0C8C 927101099Srwatson#define BGE_LOCSTATS_COS4 0x0C90 928105988Srwatson#define BGE_LOCSTATS_COS5 0x0C84 929172955Srwatson#define BGE_LOCSTATS_COS6 0x0C98 930168976Srwatson#define BGE_LOCSTATS_COS7 0x0C9C 931168976Srwatson#define BGE_LOCSTATS_COS8 0x0CA0 932105988Srwatson#define BGE_LOCSTATS_COS9 0x0CA4 933172955Srwatson#define BGE_LOCSTATS_COS10 0x0CA8 934105988Srwatson#define BGE_LOCSTATS_COS11 0x0CAC 935105988Srwatson#define BGE_LOCSTATS_COS12 0x0CB0 936105988Srwatson#define BGE_LOCSTATS_COS13 0x0CB4 937172955Srwatson#define BGE_LOCSTATS_COS14 0x0CB8 938172955Srwatson#define BGE_LOCSTATS_COS15 0x0CBC 939105988Srwatson#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 940122524Srwatson#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 941168976Srwatson#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 942172955Srwatson#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 943105988Srwatson#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 944105988Srwatson#define BGE_LOCSTATS_IRQS 0x0CD4 945172955Srwatson#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 946105988Srwatson#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 947172955Srwatson 948105988Srwatson/* Send Data Initiator mode register */ 949105988Srwatson#define BGE_SDIMODE_RESET 0x00000001 950105988Srwatson#define BGE_SDIMODE_ENABLE 0x00000002 951105988Srwatson#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 952172955Srwatson#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 953168976Srwatson 954105988Srwatson/* Send Data Initiator stats register */ 955172955Srwatson#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 956105988Srwatson 957105988Srwatson/* Send Data Initiator stats control register */ 958105988Srwatson#define BGE_SDISTATSCTL_ENABLE 0x00000001 959172955Srwatson#define BGE_SDISTATSCTL_FASTER 0x00000002 960172955Srwatson#define BGE_SDISTATSCTL_CLEAR 0x00000004 961105988Srwatson#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 962105988Srwatson#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 963132232Srwatson 964105988Srwatson/* 965105988Srwatson * Send Data Completion Control registers 966172955Srwatson */ 967105988Srwatson#define BGE_SDC_MODE 0x1000 968105988Srwatson#define BGE_SDC_STATUS 0x1004 969172955Srwatson 970105988Srwatson/* Send Data completion mode register */ 971105988Srwatson#define BGE_SDCMODE_RESET 0x00000001 972105988Srwatson#define BGE_SDCMODE_ENABLE 0x00000002 973101099Srwatson#define BGE_SDCMODE_ATTN 0x00000004 974101099Srwatson#define BGE_SDCMODE_CDELAY 0x00000010 975101099Srwatson 976101099Srwatson/* Send Data completion status register */ 977172955Srwatson#define BGE_SDCSTAT_ATTN 0x00000004 978122875Srwatson 979122875Srwatson/* 980122875Srwatson * Send BD Ring Selector Control registers 981122875Srwatson */ 982122875Srwatson#define BGE_SRS_MODE 0x1400 983122875Srwatson#define BGE_SRS_STATUS 0x1404 984122875Srwatson#define BGE_SRS_HWDIAG 0x1408 985172955Srwatson#define BGE_SRS_LOC_NIC_CONS0 0x1440 986122875Srwatson#define BGE_SRS_LOC_NIC_CONS1 0x1444 987122875Srwatson#define BGE_SRS_LOC_NIC_CONS2 0x1448 988122875Srwatson#define BGE_SRS_LOC_NIC_CONS3 0x144C 989172955Srwatson#define BGE_SRS_LOC_NIC_CONS4 0x1450 990168976Srwatson#define BGE_SRS_LOC_NIC_CONS5 0x1454 991101099Srwatson#define BGE_SRS_LOC_NIC_CONS6 0x1458 992101099Srwatson#define BGE_SRS_LOC_NIC_CONS7 0x145C 993101099Srwatson#define BGE_SRS_LOC_NIC_CONS8 0x1460 994168976Srwatson#define BGE_SRS_LOC_NIC_CONS9 0x1464 995168976Srwatson#define BGE_SRS_LOC_NIC_CONS10 0x1468 996101099Srwatson#define BGE_SRS_LOC_NIC_CONS11 0x146C 997172955Srwatson#define BGE_SRS_LOC_NIC_CONS12 0x1470 998101099Srwatson#define BGE_SRS_LOC_NIC_CONS13 0x1474 999101099Srwatson#define BGE_SRS_LOC_NIC_CONS14 0x1478 1000101099Srwatson#define BGE_SRS_LOC_NIC_CONS15 0x147C 1001172955Srwatson 1002168976Srwatson/* Send BD Ring Selector Mode register */ 1003101099Srwatson#define BGE_SRSMODE_RESET 0x00000001 1004101099Srwatson#define BGE_SRSMODE_ENABLE 0x00000002 1005101099Srwatson#define BGE_SRSMODE_ATTN 0x00000004 1006122524Srwatson 1007168976Srwatson/* Send BD Ring Selector Status register */ 1008101099Srwatson#define BGE_SRSSTAT_ERROR 0x00000004 1009172955Srwatson 1010101099Srwatson/* Send BD Ring Selector HW Diagnostics register */ 1011101099Srwatson#define BGE_SRSHWDIAG_STATE 0x0000000F 1012101099Srwatson#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1013172955Srwatson#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1014168976Srwatson#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 1015101099Srwatson 1016101099Srwatson/* 1017101099Srwatson * Send BD Initiator Selector Control registers 1018122524Srwatson */ 1019168976Srwatson#define BGE_SBDI_MODE 0x1800 1020101099Srwatson#define BGE_SBDI_STATUS 0x1804 1021172955Srwatson#define BGE_SBDI_LOC_NIC_PROD0 0x1808 1022101099Srwatson#define BGE_SBDI_LOC_NIC_PROD1 0x180C 1023101099Srwatson#define BGE_SBDI_LOC_NIC_PROD2 0x1810 1024101099Srwatson#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1025172955Srwatson#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1026172850Srwatson#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1027145855Srwatson#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1028145855Srwatson#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1029145855Srwatson#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1030145855Srwatson#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1031172850Srwatson#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1032145855Srwatson#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1033172955Srwatson#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1034145855Srwatson#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1035145855Srwatson#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1036145855Srwatson#define BGE_SBDI_LOC_NIC_PROD15 0x1844 1037172955Srwatson 1038172930Srwatson/* Send BD Initiator Mode register */ 1039101099Srwatson#define BGE_SBDIMODE_RESET 0x00000001 1040101099Srwatson#define BGE_SBDIMODE_ENABLE 0x00000002 1041101099Srwatson#define BGE_SBDIMODE_ATTN 0x00000004 1042168976Srwatson 1043168976Srwatson/* Send BD Initiator Status register */ 1044101099Srwatson#define BGE_SBDISTAT_ERROR 0x00000004 1045172955Srwatson 1046101099Srwatson/* 1047101099Srwatson * Send BD Completion Control registers 1048101099Srwatson */ 1049172955Srwatson#define BGE_SBDC_MODE 0x1C00 1050168976Srwatson#define BGE_SBDC_STATUS 0x1C04 1051101099Srwatson 1052101099Srwatson/* Send BD Completion Control Mode register */ 1053101099Srwatson#define BGE_SBDCMODE_RESET 0x00000001 1054101099Srwatson#define BGE_SBDCMODE_ENABLE 0x00000002 1055168976Srwatson#define BGE_SBDCMODE_ATTN 0x00000004 1056101099Srwatson 1057172955Srwatson/* Send BD Completion Control Status register */ 1058101099Srwatson#define BGE_SBDCSTAT_ATTN 0x00000004 1059101099Srwatson 1060101099Srwatson/* 1061172955Srwatson * Receive List Placement Control registers 1062168976Srwatson */ 1063101099Srwatson#define BGE_RXLP_MODE 0x2000 1064101099Srwatson#define BGE_RXLP_STATUS 0x2004 1065101099Srwatson#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1066101099Srwatson#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1067168976Srwatson#define BGE_RXLP_CFG 0x2010 1068101099Srwatson#define BGE_RXLP_STATS_CTL 0x2014 1069172955Srwatson#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1070101099Srwatson#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1071101099Srwatson#define BGE_RXLP_HEAD0 0x2100 1072101099Srwatson#define BGE_RXLP_TAIL0 0x2104 1073172955Srwatson#define BGE_RXLP_COUNT0 0x2108 1074168976Srwatson#define BGE_RXLP_HEAD1 0x2110 1075101099Srwatson#define BGE_RXLP_TAIL1 0x2114 1076101099Srwatson#define BGE_RXLP_COUNT1 0x2118 1077101099Srwatson#define BGE_RXLP_HEAD2 0x2120 1078168976Srwatson#define BGE_RXLP_TAIL2 0x2124 1079168976Srwatson#define BGE_RXLP_COUNT2 0x2128 1080101099Srwatson#define BGE_RXLP_HEAD3 0x2130 1081172955Srwatson#define BGE_RXLP_TAIL3 0x2134 1082101099Srwatson#define BGE_RXLP_COUNT3 0x2138 1083101099Srwatson#define BGE_RXLP_HEAD4 0x2140 1084101099Srwatson#define BGE_RXLP_TAIL4 0x2144 1085140628Srwatson#define BGE_RXLP_COUNT4 0x2148 1086140628Srwatson#define BGE_RXLP_HEAD5 0x2150 1087140628Srwatson#define BGE_RXLP_TAIL5 0x2154 1088172955Srwatson#define BGE_RXLP_COUNT5 0x2158 1089140628Srwatson#define BGE_RXLP_HEAD6 0x2160 1090140628Srwatson#define BGE_RXLP_TAIL6 0x2164 1091140628Srwatson#define BGE_RXLP_COUNT6 0x2168 1092140628Srwatson#define BGE_RXLP_HEAD7 0x2170 1093140628Srwatson#define BGE_RXLP_TAIL7 0x2174 1094140628Srwatson#define BGE_RXLP_COUNT7 0x2178 1095140628Srwatson#define BGE_RXLP_HEAD8 0x2180 1096140628Srwatson#define BGE_RXLP_TAIL8 0x2184 1097172955Srwatson#define BGE_RXLP_COUNT8 0x2188 1098140628Srwatson#define BGE_RXLP_HEAD9 0x2190 1099140628Srwatson#define BGE_RXLP_TAIL9 0x2194 1100140628Srwatson#define BGE_RXLP_COUNT9 0x2198 1101172955Srwatson#define BGE_RXLP_HEAD10 0x21A0 1102172955Srwatson#define BGE_RXLP_TAIL10 0x21A4 1103140628Srwatson#define BGE_RXLP_COUNT10 0x21A8 1104140628Srwatson#define BGE_RXLP_HEAD11 0x21B0 1105140628Srwatson#define BGE_RXLP_TAIL11 0x21B4 1106140628Srwatson#define BGE_RXLP_COUNT11 0x21B8 1107140628Srwatson#define BGE_RXLP_HEAD12 0x21C0 1108140628Srwatson#define BGE_RXLP_TAIL12 0x21C4 1109172955Srwatson#define BGE_RXLP_COUNT12 0x21C8 1110140628Srwatson#define BGE_RXLP_HEAD13 0x21D0 1111140628Srwatson#define BGE_RXLP_TAIL13 0x21D4 1112140628Srwatson#define BGE_RXLP_COUNT13 0x21D8 1113172955Srwatson#define BGE_RXLP_HEAD14 0x21E0 1114140628Srwatson#define BGE_RXLP_TAIL14 0x21E4 1115140628Srwatson#define BGE_RXLP_COUNT14 0x21E8 1116140628Srwatson#define BGE_RXLP_HEAD15 0x21F0 1117140628Srwatson#define BGE_RXLP_TAIL15 0x21F4 1118140628Srwatson#define BGE_RXLP_COUNT15 0x21F8 1119140628Srwatson#define BGE_RXLP_LOCSTAT_COS0 0x2200 1120140628Srwatson#define BGE_RXLP_LOCSTAT_COS1 0x2204 1121172955Srwatson#define BGE_RXLP_LOCSTAT_COS2 0x2208 1122140628Srwatson#define BGE_RXLP_LOCSTAT_COS3 0x220C 1123140628Srwatson#define BGE_RXLP_LOCSTAT_COS4 0x2210 1124140628Srwatson#define BGE_RXLP_LOCSTAT_COS5 0x2214 1125172955Srwatson#define BGE_RXLP_LOCSTAT_COS6 0x2218 1126140628Srwatson#define BGE_RXLP_LOCSTAT_COS7 0x221C 1127140628Srwatson#define BGE_RXLP_LOCSTAT_COS8 0x2220 1128140628Srwatson#define BGE_RXLP_LOCSTAT_COS9 0x2224 1129140628Srwatson#define BGE_RXLP_LOCSTAT_COS10 0x2228 1130140628Srwatson#define BGE_RXLP_LOCSTAT_COS11 0x222C 1131140628Srwatson#define BGE_RXLP_LOCSTAT_COS12 0x2230 1132140628Srwatson#define BGE_RXLP_LOCSTAT_COS13 0x2234 1133172955Srwatson#define BGE_RXLP_LOCSTAT_COS14 0x2238 1134140628Srwatson#define BGE_RXLP_LOCSTAT_COS15 0x223C 1135140628Srwatson#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1136140628Srwatson#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1137101099Srwatson#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1138101099Srwatson#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1139101099Srwatson#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1140172955Srwatson#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1141168976Srwatson#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1142168976Srwatson 1143101099Srwatson 1144101099Srwatson/* Receive List Placement mode register */ 1145101099Srwatson#define BGE_RXLPMODE_RESET 0x00000001 1146168976Srwatson#define BGE_RXLPMODE_ENABLE 0x00000002 1147168976Srwatson#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1148101099Srwatson#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1149172955Srwatson#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1150101099Srwatson 1151101099Srwatson/* Receive List Placement Status register */ 1152101099Srwatson#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1153172955Srwatson#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1154168976Srwatson#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1155101099Srwatson 1156101099Srwatson/* 1157101099Srwatson * Receive Data and Receive BD Initiator Control Registers 1158122524Srwatson */ 1159168976Srwatson#define BGE_RDBDI_MODE 0x2400 1160101099Srwatson#define BGE_RDBDI_STATUS 0x2404 1161172955Srwatson#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1162101099Srwatson#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1163101099Srwatson#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1164101099Srwatson#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1165172955Srwatson#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1166101099Srwatson#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1167121816Sbrooks#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1168101099Srwatson#define BGE_RX_STD_RCB_NICADDR 0x245C 1169101099Srwatson#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1170110350Srwatson#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1171101099Srwatson#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1172168976Srwatson#define BGE_RX_MINI_RCB_NICADDR 0x246C 1173101099Srwatson#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1174168976Srwatson#define BGE_RDBDI_STD_RX_CONS 0x2474 1175110350Srwatson#define BGE_RDBDI_MINI_RX_CONS 0x2478 1176101099Srwatson#define BGE_RDBDI_RETURN_PROD0 0x2480 1177101099Srwatson#define BGE_RDBDI_RETURN_PROD1 0x2484 1178101099Srwatson#define BGE_RDBDI_RETURN_PROD2 0x2488 1179101099Srwatson#define BGE_RDBDI_RETURN_PROD3 0x248C 1180110350Srwatson#define BGE_RDBDI_RETURN_PROD4 0x2490 1181101099Srwatson#define BGE_RDBDI_RETURN_PROD5 0x2494 1182101099Srwatson#define BGE_RDBDI_RETURN_PROD6 0x2498 1183101099Srwatson#define BGE_RDBDI_RETURN_PROD7 0x249C 1184110350Srwatson#define BGE_RDBDI_RETURN_PROD8 0x24A0 1185101099Srwatson#define BGE_RDBDI_RETURN_PROD9 0x24A4 1186101099Srwatson#define BGE_RDBDI_RETURN_PROD10 0x24A8 1187101099Srwatson#define BGE_RDBDI_RETURN_PROD11 0x24AC 1188101099Srwatson#define BGE_RDBDI_RETURN_PROD12 0x24B0 1189101099Srwatson#define BGE_RDBDI_RETURN_PROD13 0x24B4 1190106089Srwatson#define BGE_RDBDI_RETURN_PROD14 0x24B8 1191101099Srwatson#define BGE_RDBDI_RETURN_PROD15 0x24BC 1192101099Srwatson#define BGE_RDBDI_HWDIAG 0x24C0 1193101099Srwatson 1194101099Srwatson 1195101099Srwatson/* Receive Data and Receive BD Initiator Mode register */ 1196101099Srwatson#define BGE_RDBDIMODE_RESET 0x00000001 1197101099Srwatson#define BGE_RDBDIMODE_ENABLE 0x00000002 1198101099Srwatson#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1199101099Srwatson#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1200101099Srwatson#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1201168976Srwatson 1202110350Srwatson/* Receive Data and Receive BD Initiator Status register */ 1203101099Srwatson#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1204101099Srwatson#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1205106089Srwatson#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1206106089Srwatson 1207106089Srwatson 1208106089Srwatson/* 1209106089Srwatson * Receive Data Completion Control registers 1210101099Srwatson */ 1211101099Srwatson#define BGE_RDC_MODE 0x2800 1212101099Srwatson 1213101099Srwatson/* Receive Data Completion Mode register */ 1214101099Srwatson#define BGE_RDCMODE_RESET 0x00000001 1215101099Srwatson#define BGE_RDCMODE_ENABLE 0x00000002 1216101099Srwatson#define BGE_RDCMODE_ATTN 0x00000004 1217172955Srwatson 1218172955Srwatson/* 1219101099Srwatson * Receive BD Initiator Control registers 1220101099Srwatson */ 1221101099Srwatson#define BGE_RBDI_MODE 0x2C00 1222172955Srwatson#define BGE_RBDI_STATUS 0x2C04 1223168976Srwatson#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1224101099Srwatson#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1225101099Srwatson#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1226101099Srwatson#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1227168976Srwatson#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1228101099Srwatson#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1229101099Srwatson 1230172955Srwatson#define BGE_STD_REPLENISH_LWM 0x2D00 1231101099Srwatson#define BGE_JMB_REPLENISH_LWM 0x2D04 1232101099Srwatson 1233101099Srwatson/* Receive BD Initiator Mode register */ 1234172955Srwatson#define BGE_RBDIMODE_RESET 0x00000001 1235172955Srwatson#define BGE_RBDIMODE_ENABLE 0x00000002 1236101099Srwatson#define BGE_RBDIMODE_ATTN 0x00000004 1237101099Srwatson 1238101099Srwatson/* Receive BD Initiator Status register */ 1239101099Srwatson#define BGE_RBDISTAT_ATTN 0x00000004 1240168976Srwatson 1241101099Srwatson/* 1242101099Srwatson * Receive BD Completion Control registers 1243172955Srwatson */ 1244101099Srwatson#define BGE_RBDC_MODE 0x3000 1245101099Srwatson#define BGE_RBDC_STATUS 0x3004 1246101099Srwatson#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1247172955Srwatson#define BGE_RBDC_STD_BD_PROD 0x300C 1248168976Srwatson#define BGE_RBDC_MINI_BD_PROD 0x3010 1249101099Srwatson 1250101099Srwatson/* Receive BD completion mode register */ 1251101099Srwatson#define BGE_RBDCMODE_RESET 0x00000001 1252168976Srwatson#define BGE_RBDCMODE_ENABLE 0x00000002 1253168976Srwatson#define BGE_RBDCMODE_ATTN 0x00000004 1254101099Srwatson 1255172955Srwatson/* Receive BD completion status register */ 1256101099Srwatson#define BGE_RBDCSTAT_ERROR 0x00000004 1257101099Srwatson 1258101099Srwatson/* 1259172955Srwatson * Receive List Selector Control registers 1260123607Srwatson */ 1261123607Srwatson#define BGE_RXLS_MODE 0x3400 1262123607Srwatson#define BGE_RXLS_STATUS 0x3404 1263123607Srwatson 1264123607Srwatson/* Receive List Selector Mode register */ 1265123607Srwatson#define BGE_RXLSMODE_RESET 0x00000001 1266123607Srwatson#define BGE_RXLSMODE_ENABLE 0x00000002 1267172955Srwatson#define BGE_RXLSMODE_ATTN 0x00000004 1268123607Srwatson 1269123607Srwatson/* Receive List Selector Status register */ 1270123607Srwatson#define BGE_RXLSSTAT_ERROR 0x00000004 1271172955Srwatson 1272168976Srwatson#define BGE_CPMU_CTRL 0x3600 1273101099Srwatson#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1274101099Srwatson#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1275101099Srwatson#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1276168976Srwatson#define BGE_CPMU_HST_ACC 0x361C 1277101099Srwatson#define BGE_CPMU_CLCK_ORIDE 0x3624 1278172955Srwatson#define BGE_CPMU_CLCK_STAT 0x3630 1279101099Srwatson#define BGE_CPMU_MUTEX_REQ 0x365C 1280101099Srwatson#define BGE_CPMU_MUTEX_GNT 0x3660 1281101099Srwatson#define BGE_CPMU_PHY_STRAP 0x3664 1282172955Srwatson 1283168976Srwatson/* Central Power Management Unit (CPMU) register */ 1284101099Srwatson#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1285101099Srwatson#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1286101099Srwatson#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1287168976Srwatson#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1288168976Srwatson 1289101099Srwatson/* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1290172955Srwatson#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1291101099Srwatson#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1292101099Srwatson 1293101099Srwatson/* Link Speed 1000MB Power Mode Clock Policy register */ 1294172955Srwatson#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1295168976Srwatson#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1296101099Srwatson#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1297101099Srwatson 1298101099Srwatson/* Link Aware Power Mode Clock Policy register */ 1299168976Srwatson#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1300168976Srwatson#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1301101099Srwatson 1302172955Srwatson#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1303101099Srwatson#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1304101099Srwatson 1305101099Srwatson/* Clock Speed Override Policy register */ 1306172955Srwatson#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1307168976Srwatson 1308168976Srwatson/* CPMU Clock Status register */ 1309101099Srwatson#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1310101099Srwatson#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1311101099Srwatson#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1312168976Srwatson#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1313168976Srwatson 1314101099Srwatson/* CPMU Mutex Request register */ 1315172955Srwatson#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1316101099Srwatson#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1317101099Srwatson 1318101099Srwatson/* CPMU GPHY Strap register */ 1319172955Srwatson#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1320168976Srwatson 1321101099Srwatson/* 1322101099Srwatson * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1323101099Srwatson */ 1324168976Srwatson#define BGE_MBCF_MODE 0x3800 1325168976Srwatson#define BGE_MBCF_STATUS 0x3804 1326101099Srwatson 1327172955Srwatson/* Mbuf Cluster Free mode register */ 1328101099Srwatson#define BGE_MBCFMODE_RESET 0x00000001 1329101099Srwatson#define BGE_MBCFMODE_ENABLE 0x00000002 1330101099Srwatson#define BGE_MBCFMODE_ATTN 0x00000004 1331172955Srwatson 1332172930Srwatson/* Mbuf Cluster Free status register */ 1333101099Srwatson#define BGE_MBCFSTAT_ERROR 0x00000004 1334101099Srwatson 1335101099Srwatson/* 1336101099Srwatson * Host Coalescing Control registers 1337168976Srwatson */ 1338101099Srwatson#define BGE_HCC_MODE 0x3C00 1339172955Srwatson#define BGE_HCC_STATUS 0x3C04 1340101099Srwatson#define BGE_HCC_RX_COAL_TICKS 0x3C08 1341101099Srwatson#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1342101099Srwatson#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1343172955Srwatson#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1344168976Srwatson#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1345101099Srwatson#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1346101099Srwatson#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1347101099Srwatson#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1348101099Srwatson#define BGE_HCC_STATS_TICKS 0x3C28 1349168976Srwatson#define BGE_HCC_STATS_ADDR_HI 0x3C30 1350101099Srwatson#define BGE_HCC_STATS_ADDR_LO 0x3C34 1351172955Srwatson#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1352101099Srwatson#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1353101099Srwatson#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1354101099Srwatson#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1355172955Srwatson#define BGE_FLOW_ATTN 0x3C48 1356168976Srwatson#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1357101099Srwatson#define BGE_HCC_STD_BD_CONS 0x3C54 1358101099Srwatson#define BGE_HCC_MINI_BD_CONS 0x3C58 1359101099Srwatson#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1360101099Srwatson#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1361101099Srwatson#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1362122875Srwatson#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1363172955Srwatson#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1364122875Srwatson#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1365122875Srwatson#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1366122875Srwatson#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1367122875Srwatson#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1368122875Srwatson#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1369122875Srwatson#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1370122875Srwatson#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1371172955Srwatson#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1372122875Srwatson#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1373122875Srwatson#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1374162238Scsjp#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1375172955Srwatson#define BGE_HCC_TX_BD_CONS0 0x3CC0 1376162238Scsjp#define BGE_HCC_TX_BD_CONS1 0x3CC4 1377162238Scsjp#define BGE_HCC_TX_BD_CONS2 0x3CC8 1378162238Scsjp#define BGE_HCC_TX_BD_CONS3 0x3CCC 1379162238Scsjp#define BGE_HCC_TX_BD_CONS4 0x3CD0 1380162238Scsjp#define BGE_HCC_TX_BD_CONS5 0x3CD4 1381162238Scsjp#define BGE_HCC_TX_BD_CONS6 0x3CD8 1382172955Srwatson#define BGE_HCC_TX_BD_CONS7 0x3CDC 1383162238Scsjp#define BGE_HCC_TX_BD_CONS8 0x3CE0 1384162238Scsjp#define BGE_HCC_TX_BD_CONS9 0x3CE4 1385101099Srwatson#define BGE_HCC_TX_BD_CONS10 0x3CE8 1386101099Srwatson#define BGE_HCC_TX_BD_CONS11 0x3CEC 1387101099Srwatson#define BGE_HCC_TX_BD_CONS12 0x3CF0 1388101099Srwatson#define BGE_HCC_TX_BD_CONS13 0x3CF4 1389172955Srwatson#define BGE_HCC_TX_BD_CONS14 0x3CF8 1390101099Srwatson#define BGE_HCC_TX_BD_CONS15 0x3CFC 1391101099Srwatson 1392101099Srwatson 1393122524Srwatson/* Host coalescing mode register */ 1394101099Srwatson#define BGE_HCCMODE_RESET 0x00000001 1395172955Srwatson#define BGE_HCCMODE_ENABLE 0x00000002 1396172955Srwatson#define BGE_HCCMODE_ATTN 0x00000004 1397172955Srwatson#define BGE_HCCMODE_COAL_NOW 0x00000008 1398101099Srwatson#define BGE_HCCMODE_MSI_BITS 0x00000070 1399101099Srwatson#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1400101099Srwatson 1401172955Srwatson#define BGE_STATBLKSZ_FULL 0x00000000 1402101099Srwatson#define BGE_STATBLKSZ_64BYTE 0x00000080 1403101099Srwatson#define BGE_STATBLKSZ_32BYTE 0x00000100 1404101099Srwatson 1405122524Srwatson/* Host coalescing status register */ 1406101099Srwatson#define BGE_HCCSTAT_ERROR 0x00000004 1407172955Srwatson 1408172955Srwatson/* Flow attention register */ 1409172955Srwatson#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1410101099Srwatson#define BGE_FLOWATTN_MEMARB 0x00000080 1411101099Srwatson#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1412101099Srwatson#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1413172955Srwatson#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1414101099Srwatson#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1415101099Srwatson#define BGE_FLOWATTN_RDBDI 0x00080000 1416101099Srwatson#define BGE_FLOWATTN_RXLS 0x00100000 1417101099Srwatson#define BGE_FLOWATTN_RXLP 0x00200000 1418122524Srwatson#define BGE_FLOWATTN_RBDC 0x00400000 1419101099Srwatson#define BGE_FLOWATTN_RBDI 0x00800000 1420172955Srwatson#define BGE_FLOWATTN_SDC 0x08000000 1421101099Srwatson#define BGE_FLOWATTN_SDI 0x10000000 1422101099Srwatson#define BGE_FLOWATTN_SRS 0x20000000 1423101099Srwatson#define BGE_FLOWATTN_SBDC 0x40000000 1424140628Srwatson#define BGE_FLOWATTN_SBDI 0x80000000 1425140628Srwatson 1426140628Srwatson/* 1427172955Srwatson * Memory arbiter registers 1428140628Srwatson */ 1429140628Srwatson#define BGE_MARB_MODE 0x4000 1430140628Srwatson#define BGE_MARB_STATUS 0x4004 1431140628Srwatson#define BGE_MARB_TRAPADDR_HI 0x4008 1432140628Srwatson#define BGE_MARB_TRAPADDR_LO 0x400C 1433140628Srwatson 1434172955Srwatson/* Memory arbiter mode register */ 1435140628Srwatson#define BGE_MARBMODE_RESET 0x00000001 1436140628Srwatson#define BGE_MARBMODE_ENABLE 0x00000002 1437140628Srwatson#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1438140628Srwatson#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1439140628Srwatson#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1440140628Srwatson#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1441172955Srwatson#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1442140628Srwatson#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1443140628Srwatson#define BGE_MARBMODE_PCI_TRAP 0x00000100 1444140628Srwatson#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1445140628Srwatson#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1446140628Srwatson#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1447140628Srwatson#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1448172955Srwatson#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1449140628Srwatson#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1450140628Srwatson#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1451140628Srwatson#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1452140628Srwatson#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1453140628Srwatson#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1454101099Srwatson#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1455101099Srwatson#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1456101099Srwatson#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1457172955Srwatson#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1458168976Srwatson#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1459101099Srwatson#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1460101099Srwatson#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1461101099Srwatson 1462172955Srwatson/* Memory arbiter status register */ 1463101099Srwatson#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1464101099Srwatson#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1465168976Srwatson#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1466168976Srwatson#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1467101099Srwatson#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1468172955Srwatson#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1469101099Srwatson#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1470101099Srwatson#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1471101099Srwatson#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1472101099Srwatson#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1473101099Srwatson#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1474172955Srwatson#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1475101099Srwatson#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1476101099Srwatson#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1477105634Srwatson#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1478101099Srwatson#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1479122524Srwatson#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1480101099Srwatson#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1481101099Srwatson#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1482101099Srwatson#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1483105634Srwatson#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1484132232Srwatson#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1485101099Srwatson#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1486105634Srwatson#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1487105634Srwatson 1488105634Srwatson/* 1489101099Srwatson * Buffer manager control registers 1490101099Srwatson */ 1491105634Srwatson#define BGE_BMAN_MODE 0x4400 1492101099Srwatson#define BGE_BMAN_STATUS 0x4404 1493105634Srwatson#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1494105634Srwatson#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1495110351Srwatson#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1496132232Srwatson#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1497110351Srwatson#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1498110351Srwatson#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1499110351Srwatson#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1500110351Srwatson#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1501172955Srwatson#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1502110351Srwatson#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1503110351Srwatson#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1504110351Srwatson#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1505132232Srwatson#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1506132232Srwatson#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1507105634Srwatson#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1508132232Srwatson#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1509172955Srwatson#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1510105634Srwatson#define BGE_BMAN_HWDIAG_1 0x444C 1511101099Srwatson#define BGE_BMAN_HWDIAG_2 0x4450 1512105634Srwatson#define BGE_BMAN_HWDIAG_3 0x4454 1513172955Srwatson 1514172955Srwatson/* Buffer manager mode register */ 1515105634Srwatson#define BGE_BMANMODE_RESET 0x00000001 1516105634Srwatson#define BGE_BMANMODE_ENABLE 0x00000002 1517172955Srwatson#define BGE_BMANMODE_ATTN 0x00000004 1518105634Srwatson#define BGE_BMANMODE_TESTMODE 0x00000008 1519101099Srwatson#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1520105634Srwatson#define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 1521172955Srwatson 1522172955Srwatson/* Buffer manager status register */ 1523105634Srwatson#define BGE_BMANSTAT_ERRO 0x00000004 1524172955Srwatson#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1525172955Srwatson 1526105634Srwatson 1527105634Srwatson/* 1528105634Srwatson * Read DMA Control registers 1529105634Srwatson */ 1530105634Srwatson#define BGE_RDMA_MODE 0x4800 1531101099Srwatson#define BGE_RDMA_STATUS 0x4804 1532101099Srwatson#define BGE_RDMA_RSRVCTRL 0x4900 1533101099Srwatson#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 1534101099Srwatson 1535172955Srwatson/* Read DMA mode register */ 1536101099Srwatson#define BGE_RDMAMODE_RESET 0x00000001 1537101099Srwatson#define BGE_RDMAMODE_ENABLE 0x00000002 1538101099Srwatson#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1539172955Srwatson#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1540101099Srwatson#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1541101099Srwatson#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1542122524Srwatson#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1543122524Srwatson#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1544101099Srwatson#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1545101099Srwatson#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1546172955Srwatson#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1547101099Srwatson#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1548101099Srwatson#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1549101099Srwatson#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1550101099Srwatson#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1551101099Srwatson#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1552101099Srwatson#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1553172955Srwatson#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1554168976Srwatson#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1555101099Srwatson#define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 1556101099Srwatson 1557105634Srwatson/* Read DMA status register */ 1558101099Srwatson#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1559122524Srwatson#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1560101099Srwatson#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1561101099Srwatson#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1562105634Srwatson#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1563172955Srwatson#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1564172955Srwatson#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1565105634Srwatson#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1566105634Srwatson 1567105634Srwatson/* Read DMA Reserved Control register */ 1568105634Srwatson#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1569101099Srwatson#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1570105634Srwatson#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1571106160Srwatson#define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1572106160Srwatson#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1573172955Srwatson#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1574106160Srwatson#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1575106160Srwatson 1576106160Srwatson#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 1577105634Srwatson#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1578101099Srwatson#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1579101099Srwatson 1580103759Srwatson/* 1581172955Srwatson * Write DMA control registers 1582168976Srwatson */ 1583101099Srwatson#define BGE_WDMA_MODE 0x4C00 1584101099Srwatson#define BGE_WDMA_STATUS 0x4C04 1585103761Srwatson 1586172955Srwatson/* Write DMA mode register */ 1587101099Srwatson#define BGE_WDMAMODE_RESET 0x00000001 1588101099Srwatson#define BGE_WDMAMODE_ENABLE 0x00000002 1589168976Srwatson#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1590168976Srwatson#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1591103759Srwatson#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1592172955Srwatson#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1593101099Srwatson#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1594101099Srwatson#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1595101099Srwatson#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1596172955Srwatson#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1597122875Srwatson#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1598122875Srwatson#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1599122875Srwatson#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1600122875Srwatson 1601172955Srwatson/* Write DMA status register */ 1602122875Srwatson#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1603122875Srwatson#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1604122875Srwatson#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1605122875Srwatson#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1606122875Srwatson#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1607172955Srwatson#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1608122875Srwatson#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1609122875Srwatson#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1610122875Srwatson 1611172955Srwatson 1612140628Srwatson/* 1613140628Srwatson * RX CPU registers 1614140628Srwatson */ 1615140628Srwatson#define BGE_RXCPU_MODE 0x5000 1616172955Srwatson#define BGE_RXCPU_STATUS 0x5004 1617140628Srwatson#define BGE_RXCPU_PC 0x501C 1618140628Srwatson 1619140628Srwatson/* RX CPU mode register */ 1620140628Srwatson#define BGE_RXCPUMODE_RESET 0x00000001 1621140628Srwatson#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1622172955Srwatson#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1623140628Srwatson#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1624140628Srwatson#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1625140628Srwatson#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1626140628Srwatson#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1627140628Srwatson#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1628140628Srwatson#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1629172955Srwatson#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1630140628Srwatson#define BGE_RXCPUMODE_HALTCPU 0x00000400 1631140628Srwatson#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1632140628Srwatson#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1633140628Srwatson#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1634172955Srwatson 1635140628Srwatson/* RX CPU status register */ 1636140628Srwatson#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1637140628Srwatson#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1638140628Srwatson#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1639140628Srwatson#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1640172955Srwatson#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1641140628Srwatson#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1642140628Srwatson#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1643140628Srwatson#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1644140628Srwatson#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1645140628Srwatson#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1646140628Srwatson#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1647172955Srwatson#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1648172955Srwatson#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1649140628Srwatson#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1650140628Srwatson#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1651140628Srwatson#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1652172955Srwatson#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1653140628Srwatson 1654140628Srwatson/* 1655140628Srwatson * V? CPU registers 1656140628Srwatson */ 1657140628Srwatson#define BGE_VCPU_STATUS 0x5100 1658172955Srwatson#define BGE_VCPU_EXT_CTRL 0x6890 1659140628Srwatson 1660140628Srwatson#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1661140628Srwatson#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1662140628Srwatson 1663140628Srwatson#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1664140628Srwatson#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1665172955Srwatson 1666172955Srwatson/* 1667140628Srwatson * TX CPU registers 1668140628Srwatson */ 1669140628Srwatson#define BGE_TXCPU_MODE 0x5400 1670172955Srwatson#define BGE_TXCPU_STATUS 0x5404 1671140628Srwatson#define BGE_TXCPU_PC 0x541C 1672140628Srwatson 1673140628Srwatson/* TX CPU mode register */ 1674140628Srwatson#define BGE_TXCPUMODE_RESET 0x00000001 1675140628Srwatson#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1676172955Srwatson#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1677140628Srwatson#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1678140628Srwatson#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1679140628Srwatson#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1680140628Srwatson#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1681140628Srwatson#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1682140628Srwatson#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1683172955Srwatson#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1684172955Srwatson#define BGE_TXCPUMODE_HALTCPU 0x00000400 1685140628Srwatson#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1686140628Srwatson#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1687140628Srwatson 1688172955Srwatson/* TX CPU status register */ 1689140628Srwatson#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1690140628Srwatson#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1691140628Srwatson#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1692140628Srwatson#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1693140628Srwatson#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1694172955Srwatson#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1695140628Srwatson#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1696140628Srwatson#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1697140628Srwatson#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1698140628Srwatson#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1699140628Srwatson#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1700140628Srwatson#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1701172955Srwatson#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1702172955Srwatson#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1703140628Srwatson#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1704140628Srwatson#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1705140628Srwatson#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1706172955Srwatson 1707140628Srwatson 1708140628Srwatson/* 1709140628Srwatson * Low priority mailbox registers 1710140628Srwatson */ 1711140628Srwatson#define BGE_LPMBX_IRQ0_HI 0x5800 1712140628Srwatson#define BGE_LPMBX_IRQ0_LO 0x5804 1713140628Srwatson#define BGE_LPMBX_IRQ1_HI 0x5808 1714140628Srwatson#define BGE_LPMBX_IRQ1_LO 0x580C 1715172955Srwatson#define BGE_LPMBX_IRQ2_HI 0x5810 1716140628Srwatson#define BGE_LPMBX_IRQ2_LO 0x5814 1717140628Srwatson#define BGE_LPMBX_IRQ3_HI 0x5818 1718140628Srwatson#define BGE_LPMBX_IRQ3_LO 0x581C 1719140628Srwatson#define BGE_LPMBX_GEN0_HI 0x5820 1720172955Srwatson#define BGE_LPMBX_GEN0_LO 0x5824 1721140628Srwatson#define BGE_LPMBX_GEN1_HI 0x5828 1722140628Srwatson#define BGE_LPMBX_GEN1_LO 0x582C 1723140628Srwatson#define BGE_LPMBX_GEN2_HI 0x5830 1724140628Srwatson#define BGE_LPMBX_GEN2_LO 0x5834 1725140628Srwatson#define BGE_LPMBX_GEN3_HI 0x5828 1726140628Srwatson#define BGE_LPMBX_GEN3_LO 0x582C 1727140628Srwatson#define BGE_LPMBX_GEN4_HI 0x5840 1728140628Srwatson#define BGE_LPMBX_GEN4_LO 0x5844 1729140628Srwatson#define BGE_LPMBX_GEN5_HI 0x5848 1730140628Srwatson#define BGE_LPMBX_GEN5_LO 0x584C 1731140628Srwatson#define BGE_LPMBX_GEN6_HI 0x5850 1732172955Srwatson#define BGE_LPMBX_GEN6_LO 0x5854 1733172955Srwatson#define BGE_LPMBX_GEN7_HI 0x5858 1734140628Srwatson#define BGE_LPMBX_GEN7_LO 0x585C 1735140628Srwatson#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1736140628Srwatson#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1737172955Srwatson#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1738140628Srwatson#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1739140628Srwatson#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1740140628Srwatson#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1741140628Srwatson#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1742140628Srwatson#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1743140628Srwatson#define BGE_LPMBX_RX_CONS0_HI 0x5880 1744140628Srwatson#define BGE_LPMBX_RX_CONS0_LO 0x5884 1745140628Srwatson#define BGE_LPMBX_RX_CONS1_HI 0x5888 1746140628Srwatson#define BGE_LPMBX_RX_CONS1_LO 0x588C 1747140628Srwatson#define BGE_LPMBX_RX_CONS2_HI 0x5890 1748172955Srwatson#define BGE_LPMBX_RX_CONS2_LO 0x5894 1749140628Srwatson#define BGE_LPMBX_RX_CONS3_HI 0x5898 1750140628Srwatson#define BGE_LPMBX_RX_CONS3_LO 0x589C 1751140628Srwatson#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1752140628Srwatson#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1753140628Srwatson#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1754140628Srwatson#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1755140628Srwatson#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1756140628Srwatson#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1757140628Srwatson#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1758172955Srwatson#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1759140628Srwatson#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1760140628Srwatson#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1761140628Srwatson#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1762140628Srwatson#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1763140628Srwatson#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1764140628Srwatson#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1765140628Srwatson#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1766140628Srwatson#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1767140628Srwatson#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1768140628Srwatson#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1769140628Srwatson#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1770172955Srwatson#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1771172955Srwatson#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1772140628Srwatson#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1773140628Srwatson#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1774140628Srwatson#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1775172955Srwatson#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1776140628Srwatson#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1777140628Srwatson#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1778140628Srwatson#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1779140628Srwatson#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1780140628Srwatson#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1781172955Srwatson#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1782140628Srwatson#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1783140628Srwatson#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1784140628Srwatson#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1785140628Srwatson#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1786140628Srwatson#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1787140628Srwatson#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1788172955Srwatson#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1789172955Srwatson#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1790140628Srwatson#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1791140628Srwatson#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1792140628Srwatson#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1793172955Srwatson#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1794140628Srwatson#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1795140628Srwatson#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1796140628Srwatson#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1797140628Srwatson#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1798140628Srwatson#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1799140628Srwatson#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1800172955Srwatson#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1801140628Srwatson#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1802140628Srwatson#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1803140628Srwatson#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1804172955Srwatson#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1805140628Srwatson#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1806140628Srwatson#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1807140628Srwatson#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1808140628Srwatson#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1809140628Srwatson#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1810140628Srwatson#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1811172955Srwatson#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1812172955Srwatson#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1813140628Srwatson#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1814140628Srwatson#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1815140628Srwatson#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1816172955Srwatson#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1817140628Srwatson#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1818140628Srwatson#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1819140628Srwatson#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1820140628Srwatson#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1821140628Srwatson#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1822172955Srwatson#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1823140628Srwatson#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1824140628Srwatson#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1825172955Srwatson#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1826140628Srwatson#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1827140628Srwatson#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1828140628Srwatson#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1829140628Srwatson#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1830140628Srwatson#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1831140628Srwatson#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1832140628Srwatson#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1833172955Srwatson#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1834172955Srwatson#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1835140628Srwatson#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1836140628Srwatson#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1837140628Srwatson#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1838172955Srwatson#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1839140628Srwatson 1840140628Srwatson/* 1841140628Srwatson * Flow throw Queue reset register 1842140628Srwatson */ 1843140628Srwatson#define BGE_FTQ_RESET 0x5C00 1844140628Srwatson 1845140628Srwatson#define BGE_FTQRESET_DMAREAD 0x00000002 1846140628Srwatson#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1847172955Srwatson#define BGE_FTQRESET_DMADONE 0x00000010 1848140628Srwatson#define BGE_FTQRESET_SBDC 0x00000020 1849140628Srwatson#define BGE_FTQRESET_SDI 0x00000040 1850140628Srwatson#define BGE_FTQRESET_WDMA 0x00000080 1851140628Srwatson#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1852140628Srwatson#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1853172955Srwatson#define BGE_FTQRESET_SDC 0x00000400 1854140628Srwatson#define BGE_FTQRESET_HCC 0x00000800 1855140628Srwatson#define BGE_FTQRESET_TXFIFO 0x00001000 1856140628Srwatson#define BGE_FTQRESET_MBC 0x00002000 1857140628Srwatson#define BGE_FTQRESET_RBDC 0x00004000 1858140628Srwatson#define BGE_FTQRESET_RXLP 0x00008000 1859140628Srwatson#define BGE_FTQRESET_RDBDI 0x00010000 1860140628Srwatson#define BGE_FTQRESET_RDC 0x00020000 1861140628Srwatson#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1862140628Srwatson 1863140628Srwatson/* 1864140628Srwatson * Message Signaled Interrupt registers 1865172955Srwatson */ 1866172955Srwatson#define BGE_MSI_MODE 0x6000 1867140628Srwatson#define BGE_MSI_STATUS 0x6004 1868140628Srwatson#define BGE_MSI_FIFOACCESS 0x6008 1869140628Srwatson 1870172955Srwatson/* MSI mode register */ 1871140628Srwatson#define BGE_MSIMODE_RESET 0x00000001 1872140628Srwatson#define BGE_MSIMODE_ENABLE 0x00000002 1873140628Srwatson#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1874140628Srwatson#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1875140628Srwatson 1876172955Srwatson/* MSI status register */ 1877140628Srwatson#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1878140628Srwatson#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1879140628Srwatson#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1880140628Srwatson#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1881140628Srwatson#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1882140628Srwatson 1883172955Srwatson 1884168976Srwatson/* 1885110354Srwatson * DMA Completion registers 1886110354Srwatson */ 1887110354Srwatson#define BGE_DMAC_MODE 0x6400 1888110354Srwatson 1889172955Srwatson/* DMA Completion mode register */ 1890110354Srwatson#define BGE_DMACMODE_RESET 0x00000001 1891110354Srwatson#define BGE_DMACMODE_ENABLE 0x00000002 1892122524Srwatson 1893110354Srwatson 1894172955Srwatson/* 1895110354Srwatson * General control registers. 1896110354Srwatson */ 1897110354Srwatson#define BGE_MODE_CTL 0x6800 1898168976Srwatson#define BGE_MISC_CFG 0x6804 1899172955Srwatson#define BGE_MISC_LOCAL_CTL 0x6808 1900110354Srwatson#define BGE_RX_CPU_EVENT 0x6810 1901110354Srwatson#define BGE_TX_CPU_EVENT 0x6820 1902110354Srwatson#define BGE_EE_ADDR 0x6838 1903110354Srwatson#define BGE_EE_DATA 0x683C 1904110354Srwatson#define BGE_EE_CTL 0x6840 1905110354Srwatson#define BGE_MDI_CTL 0x6844 1906172955Srwatson#define BGE_EE_DELAY 0x6848 1907168976Srwatson#define BGE_FASTBOOT_PC 0x6894 1908101099Srwatson 1909101099Srwatson#define BGE_RX_CPU_DRV_EVENT 0x00004000 1910101099Srwatson 1911172955Srwatson/* 1912101099Srwatson * NVRAM Control registers 1913101099Srwatson */ 1914122524Srwatson#define BGE_NVRAM_CMD 0x7000 1915168976Srwatson#define BGE_NVRAM_STAT 0x7004 1916101099Srwatson#define BGE_NVRAM_WRDATA 0x7008 1917172955Srwatson#define BGE_NVRAM_ADDR 0x700c 1918101099Srwatson#define BGE_NVRAM_RDDATA 0x7010 1919101099Srwatson#define BGE_NVRAM_CFG1 0x7014 1920101099Srwatson#define BGE_NVRAM_CFG2 0x7018 1921101099Srwatson#define BGE_NVRAM_CFG3 0x701c 1922101099Srwatson#define BGE_NVRAM_SWARB 0x7020 1923101099Srwatson#define BGE_NVRAM_ACCESS 0x7024 1924172955Srwatson#define BGE_NVRAM_WRITE1 0x7028 1925168976Srwatson 1926101099Srwatson#define BGE_NVRAMCMD_RESET 0x00000001 1927103759Srwatson#define BGE_NVRAMCMD_DONE 0x00000008 1928172955Srwatson#define BGE_NVRAMCMD_START 0x00000010 1929101099Srwatson#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1930101099Srwatson#define BGE_NVRAMCMD_ERASE 0x00000040 1931101099Srwatson#define BGE_NVRAMCMD_FIRST 0x00000080 1932101099Srwatson#define BGE_NVRAMCMD_LAST 0x00000100 1933101099Srwatson 1934101099Srwatson#define BGE_NVRAM_READCMD \ 1935101099Srwatson (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1936101099Srwatson BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1937172955Srwatson#define BGE_NVRAM_WRITECMD \ 1938168976Srwatson (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1939101099Srwatson BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1940101099Srwatson 1941101099Srwatson#define BGE_NVRAMSWARB_SET0 0x00000001 1942172955Srwatson#define BGE_NVRAMSWARB_SET1 0x00000002 1943101099Srwatson#define BGE_NVRAMSWARB_SET2 0x00000003 1944101099Srwatson#define BGE_NVRAMSWARB_SET3 0x00000004 1945122524Srwatson#define BGE_NVRAMSWARB_CLR0 0x00000010 1946168976Srwatson#define BGE_NVRAMSWARB_CLR1 0x00000020 1947101099Srwatson#define BGE_NVRAMSWARB_CLR2 0x00000040 1948172955Srwatson#define BGE_NVRAMSWARB_CLR3 0x00000080 1949102115Srwatson#define BGE_NVRAMSWARB_GNT0 0x00000100 1950101099Srwatson#define BGE_NVRAMSWARB_GNT1 0x00000200 1951101099Srwatson#define BGE_NVRAMSWARB_GNT2 0x00000400 1952101099Srwatson#define BGE_NVRAMSWARB_GNT3 0x00000800 1953101099Srwatson#define BGE_NVRAMSWARB_REQ0 0x00001000 1954101099Srwatson#define BGE_NVRAMSWARB_REQ1 0x00002000 1955172955Srwatson#define BGE_NVRAMSWARB_REQ2 0x00004000 1956168976Srwatson#define BGE_NVRAMSWARB_REQ3 0x00008000 1957102115Srwatson 1958102115Srwatson#define BGE_NVRAMACC_ENABLE 0x00000001 1959102115Srwatson#define BGE_NVRAMACC_WRENABLE 0x00000002 1960172955Srwatson 1961102115Srwatson/* Mode control register */ 1962102115Srwatson#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1963122524Srwatson#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1964168976Srwatson#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1965102115Srwatson#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1966172955Srwatson#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1967102115Srwatson#define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 1968102115Srwatson#define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 1969102115Srwatson#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1970102115Srwatson#define BGE_MODECTL_NO_RX_CRC 0x00000400 1971102115Srwatson#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1972102115Srwatson#define BGE_MODECTL_NO_TX_INTR 0x00002000 1973172955Srwatson#define BGE_MODECTL_NO_RX_INTR 0x00004000 1974168976Srwatson#define BGE_MODECTL_FORCE_PCI32 0x00008000 1975101099Srwatson#define BGE_MODECTL_B2HRX_ENABLE 0x00008000 1976101099Srwatson#define BGE_MODECTL_STACKUP 0x00010000 1977105634Srwatson#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1978101099Srwatson#define BGE_MODECTL_HTX2B_ENABLE 0x00040000 1979101099Srwatson#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1980122524Srwatson#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1981168976Srwatson#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1982101099Srwatson#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1983101099Srwatson#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1984172955Srwatson#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1985172955Srwatson#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1986101099Srwatson#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1987132232Srwatson#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1988105634Srwatson 1989105634Srwatson/* Misc. config register */ 1990101099Srwatson#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1991101099Srwatson#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1992105634Srwatson#define BGE_MISCCFG_BOARD_ID_MASK 0x0001E000 1993105634Srwatson#define BGE_MISCCFG_BOARD_ID_5704 0x00000000 1994101099Srwatson#define BGE_MISCCFG_BOARD_ID_5704CIOBE 0x00004000 1995172955Srwatson#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1996101099Srwatson#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1997101099Srwatson#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1998101099Srwatson#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 1999105634Srwatson 2000101099Srwatson#define BGE_32BITTIME_66MHZ (0x41 << 1) 2001132232Srwatson 2002105634Srwatson/* Misc. Local Control */ 2003105634Srwatson#define BGE_MLC_INTR_STATE 0x00000001 2004105634Srwatson#define BGE_MLC_INTR_CLR 0x00000002 2005105634Srwatson#define BGE_MLC_INTR_SET 0x00000004 2006172955Srwatson#define BGE_MLC_INTR_ONATTN 0x00000008 2007105634Srwatson#define BGE_MLC_MISCIO_IN0 0x00000100 2008101099Srwatson#define BGE_MLC_MISCIO_IN1 0x00000200 2009105634Srwatson#define BGE_MLC_MISCIO_IN2 0x00000400 2010105634Srwatson#define BGE_MLC_MISCIO_OUTEN0 0x00000800 2011105634Srwatson#define BGE_MLC_MISCIO_OUTEN1 0x00001000 2012105634Srwatson#define BGE_MLC_MISCIO_OUTEN2 0x00002000 2013172955Srwatson#define BGE_MLC_MISCIO_OUT0 0x00004000 2014172955Srwatson#define BGE_MLC_MISCIO_OUT1 0x00008000 2015105634Srwatson#define BGE_MLC_MISCIO_OUT2 0x00010000 2016105634Srwatson#define BGE_MLC_EXTRAM_ENB 0x00020000 2017105634Srwatson#define BGE_MLC_SRAM_SIZE 0x001C0000 2018105634Srwatson#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 2019105634Srwatson#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 2020101099Srwatson#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 2021101099Srwatson#define BGE_MLC_AUTO_EEPROM 0x01000000 2022101099Srwatson 2023101099Srwatson#define BGE_SSRAMSIZE_256KB 0x00000000 2024172955Srwatson#define BGE_SSRAMSIZE_512KB 0x00040000 2025168976Srwatson#define BGE_SSRAMSIZE_1MB 0x00080000 2026102115Srwatson#define BGE_SSRAMSIZE_2MB 0x000C0000 2027102115Srwatson#define BGE_SSRAMSIZE_4MB 0x00100000 2028102115Srwatson#define BGE_SSRAMSIZE_8MB 0x00140000 2029172955Srwatson#define BGE_SSRAMSIZE_16M 0x00180000 2030102115Srwatson 2031102115Srwatson/* EEPROM address register */ 2032122524Srwatson#define BGE_EEADDR_ADDRESS 0x0000FFFC 2033168976Srwatson#define BGE_EEADDR_HALFCLK 0x01FF0000 2034102115Srwatson#define BGE_EEADDR_START 0x02000000 2035172955Srwatson#define BGE_EEADDR_DEVID 0x1C000000 2036102115Srwatson#define BGE_EEADDR_RESET 0x20000000 2037102115Srwatson#define BGE_EEADDR_DONE 0x40000000 2038102115Srwatson#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 2039102115Srwatson 2040102115Srwatson#define BGE_EEDEVID(x) ((x & 7) << 26) 2041102115Srwatson#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2042172955Srwatson#define BGE_HALFCLK_384SCL 0x60 2043168976Srwatson#define BGE_EE_READCMD \ 2044102115Srwatson (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2045102115Srwatson BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2046102115Srwatson#define BGE_EE_WRCMD \ 2047172955Srwatson (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2048102115Srwatson BGE_EEADDR_START|BGE_EEADDR_DONE) 2049102115Srwatson 2050122524Srwatson/* EEPROM Control register */ 2051168976Srwatson#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2052102115Srwatson#define BGE_EECTL_CLKOUT 0x00000002 2053172955Srwatson#define BGE_EECTL_CLKIN 0x00000004 2054102115Srwatson#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2055102115Srwatson#define BGE_EECTL_DATAOUT 0x00000010 2056102115Srwatson#define BGE_EECTL_DATAIN 0x00000020 2057102115Srwatson 2058102115Srwatson/* MDI (MII/GMII) access register */ 2059102115Srwatson#define BGE_MDI_DATA 0x00000001 2060172955Srwatson#define BGE_MDI_DIR 0x00000002 2061172850Srwatson#define BGE_MDI_SEL 0x00000004 2062145855Srwatson#define BGE_MDI_CLK 0x00000008 2063145855Srwatson 2064145855Srwatson#define BGE_MEMWIN_START 0x00008000 2065172955Srwatson#define BGE_MEMWIN_END 0x0000FFFF 2066145855Srwatson 2067145855Srwatson 2068145855Srwatson#define BGE_MEMWIN_READ(sc, x, val) \ 2069172850Srwatson do { \ 2070145855Srwatson pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2071172955Srwatson (0xFFFF0000 & x), 4); \ 2072145855Srwatson val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2073145855Srwatson } while(0) 2074145855Srwatson 2075145855Srwatson#define BGE_MEMWIN_WRITE(sc, x, val) \ 2076145855Srwatson do { \ 2077145855Srwatson pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2078172955Srwatson (0xFFFF0000 & x), 4); \ 2079172850Srwatson CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2080145855Srwatson } while(0) 2081145855Srwatson 2082145855Srwatson/* 2083172955Srwatson * This magic number is written to the firmware mailbox at 0xb50 2084145855Srwatson * before a software reset is issued. After the internal firmware 2085145855Srwatson * has completed its initialization it will write the opposite of 2086145855Srwatson * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location, 2087172850Srwatson * allowing the driver to synchronize with the firmware. 2088145855Srwatson */ 2089172955Srwatson#define BGE_SRAM_FW_MB_MAGIC 0x4B657654 2090145855Srwatson 2091145855Srwatsontypedef struct { 2092145855Srwatson uint32_t bge_addr_hi; 2093145855Srwatson uint32_t bge_addr_lo; 2094145855Srwatson} bge_hostaddr; 2095145855Srwatson 2096172955Srwatson#define BGE_HOSTADDR(x, y) \ 2097101099Srwatson do { \ 2098101099Srwatson (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 2099101099Srwatson (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 2100172955Srwatson } while(0) 2101101099Srwatson 2102101099Srwatson#define BGE_ADDR_LO(y) \ 2103122524Srwatson ((uint64_t) (y) & 0xFFFFFFFF) 2104168976Srwatson#define BGE_ADDR_HI(y) \ 2105101099Srwatson ((uint64_t) (y) >> 32) 2106101099Srwatson 2107172955Srwatson/* Ring control block structure */ 2108101099Srwatsonstruct bge_rcb { 2109172955Srwatson bge_hostaddr bge_hostaddr; 2110101099Srwatson uint32_t bge_maxlen_flags; 2111101099Srwatson uint32_t bge_nicaddr; 2112101099Srwatson}; 2113101099Srwatson 2114101099Srwatson#define RCB_WRITE_4(sc, rcb, offset, val) \ 2115101099Srwatson bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 2116172955Srwatson#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2117101099Srwatson 2118101099Srwatson#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2119103759Srwatson#define BGE_RCB_FLAG_RING_DISABLED 0x0002 2120172955Srwatson 2121101099Srwatsonstruct bge_tx_bd { 2122101099Srwatson bge_hostaddr bge_addr; 2123122524Srwatson#if BYTE_ORDER == LITTLE_ENDIAN 2124168976Srwatson uint16_t bge_flags; 2125103759Srwatson uint16_t bge_len; 2126101099Srwatson uint16_t bge_vlan_tag; 2127172955Srwatson uint16_t bge_mss; 2128101099Srwatson#else 2129172955Srwatson uint16_t bge_len; 2130101099Srwatson uint16_t bge_flags; 2131101099Srwatson uint16_t bge_mss; 2132101099Srwatson uint16_t bge_vlan_tag; 2133101099Srwatson#endif 2134101099Srwatson}; 2135101099Srwatson 2136172955Srwatson#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2137101099Srwatson#define BGE_TXBDFLAG_IP_CSUM 0x0002 2138101099Srwatson#define BGE_TXBDFLAG_END 0x0004 2139103759Srwatson#define BGE_TXBDFLAG_IP_FRAG 0x0008 2140172955Srwatson#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ 2141101099Srwatson#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2142101099Srwatson#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */ 2143122524Srwatson#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ 2144168976Srwatson#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2145103759Srwatson#define BGE_TXBDFLAG_COAL_NOW 0x0080 2146101099Srwatson#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2147172955Srwatson#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2148101099Srwatson#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */ 2149172955Srwatson#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */ 2150101099Srwatson#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2151101099Srwatson#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */ 2152101099Srwatson#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */ 2153101099Srwatson#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */ 2154101099Srwatson#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2155101099Srwatson#define BGE_TXBDFLAG_NO_CRC 0x8000 2156172955Srwatson 2157168976Srwatson#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2158101099Srwatson/* Bits [1:0] of the MSS header length. */ 2159101099Srwatson#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2160101099Srwatson 2161172955Srwatson#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2162101099Srwatson BGE_SEND_RING_1_TO_4 + \ 2163101099Srwatson ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2164168976Srwatson 2165168976Srwatsonstruct bge_rx_bd { 2166101099Srwatson bge_hostaddr bge_addr; 2167172955Srwatson#if BYTE_ORDER == LITTLE_ENDIAN 2168101099Srwatson uint16_t bge_len; 2169101099Srwatson uint16_t bge_idx; 2170101099Srwatson uint16_t bge_flags; 2171172955Srwatson uint16_t bge_type; 2172168976Srwatson uint16_t bge_tcp_udp_csum; 2173101099Srwatson uint16_t bge_ip_csum; 2174101099Srwatson uint16_t bge_vlan_tag; 2175105634Srwatson uint16_t bge_error_flag; 2176101099Srwatson#else 2177101099Srwatson uint16_t bge_idx; 2178122524Srwatson uint16_t bge_len; 2179168976Srwatson uint16_t bge_type; 2180101099Srwatson uint16_t bge_flags; 2181101099Srwatson uint16_t bge_ip_csum; 2182172955Srwatson uint16_t bge_tcp_udp_csum; 2183172955Srwatson uint16_t bge_error_flag; 2184101099Srwatson uint16_t bge_vlan_tag; 2185132232Srwatson#endif 2186105634Srwatson uint32_t bge_rsvd; 2187105634Srwatson uint32_t bge_opaque; 2188101099Srwatson}; 2189101099Srwatson 2190172955Srwatsonstruct bge_extrx_bd { 2191172955Srwatson bge_hostaddr bge_addr1; 2192101099Srwatson bge_hostaddr bge_addr2; 2193172955Srwatson bge_hostaddr bge_addr3; 2194101099Srwatson#if BYTE_ORDER == LITTLE_ENDIAN 2195101099Srwatson uint16_t bge_len2; 2196101099Srwatson uint16_t bge_len1; 2197105634Srwatson uint16_t bge_rsvd1; 2198101099Srwatson uint16_t bge_len3; 2199132232Srwatson#else 2200105634Srwatson uint16_t bge_len1; 2201132232Srwatson uint16_t bge_len2; 2202105634Srwatson uint16_t bge_len3; 2203105634Srwatson uint16_t bge_rsvd1; 2204172955Srwatson#endif 2205105634Srwatson bge_hostaddr bge_addr0; 2206101099Srwatson#if BYTE_ORDER == LITTLE_ENDIAN 2207105634Srwatson uint16_t bge_len0; 2208105634Srwatson uint16_t bge_idx; 2209105634Srwatson uint16_t bge_flags; 2210105634Srwatson uint16_t bge_type; 2211172955Srwatson uint16_t bge_tcp_udp_csum; 2212172955Srwatson uint16_t bge_ip_csum; 2213105634Srwatson uint16_t bge_vlan_tag; 2214105634Srwatson uint16_t bge_error_flag; 2215105634Srwatson#else 2216105634Srwatson uint16_t bge_idx; 2217105634Srwatson uint16_t bge_len0; 2218101099Srwatson uint16_t bge_type; 2219101099Srwatson uint16_t bge_flags; 2220101099Srwatson uint16_t bge_ip_csum; 2221101099Srwatson uint16_t bge_tcp_udp_csum; 2222172955Srwatson uint16_t bge_error_flag; 2223168976Srwatson uint16_t bge_vlan_tag; 2224101099Srwatson#endif 2225101099Srwatson uint32_t bge_rsvd0; 2226101099Srwatson uint32_t bge_opaque; 2227172955Srwatson}; 2228105722Srwatson 2229105722Srwatson#define BGE_RXBDFLAG_END 0x0004 2230122524Srwatson#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2231168976Srwatson#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2232101099Srwatson#define BGE_RXBDFLAG_ERROR 0x0400 2233172955Srwatson#define BGE_RXBDFLAG_MINI_RING 0x0800 2234101099Srwatson#define BGE_RXBDFLAG_IP_CSUM 0x1000 2235101099Srwatson#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2236101099Srwatson#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2237101099Srwatson#define BGE_RXBDFLAG_IPV6 0x8000 2238101099Srwatson 2239168951Srwatson#define BGE_RXERRFLAG_BAD_CRC 0x0001 2240168951Srwatson#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2241168951Srwatson#define BGE_RXERRFLAG_LINK_LOST 0x0004 2242168951Srwatson#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2243168951Srwatson#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2244101099Srwatson#define BGE_RXERRFLAG_RUNT 0x0020 2245172955Srwatson#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2246112574Srwatson#define BGE_RXERRFLAG_GIANT 0x0080 2247112574Srwatson#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 2248112574Srwatson 2249112574Srwatsonstruct bge_sts_idx { 2250172955Srwatson#if BYTE_ORDER == LITTLE_ENDIAN 2251112574Srwatson uint16_t bge_rx_prod_idx; 2252112574Srwatson uint16_t bge_tx_cons_idx; 2253168951Srwatson#else 2254168951Srwatson uint16_t bge_tx_cons_idx; 2255168951Srwatson uint16_t bge_rx_prod_idx; 2256168951Srwatson#endif 2257168951Srwatson}; 2258168951Srwatson 2259112574Srwatsonstruct bge_status_block { 2260168951Srwatson uint32_t bge_status; 2261168951Srwatson uint32_t bge_status_tag; 2262168951Srwatson#if BYTE_ORDER == LITTLE_ENDIAN 2263168951Srwatson uint16_t bge_rx_jumbo_cons_idx; 2264168951Srwatson uint16_t bge_rx_std_cons_idx; 2265168951Srwatson uint16_t bge_rx_mini_cons_idx; 2266168951Srwatson uint16_t bge_rsvd1; 2267112574Srwatson#else 2268168951Srwatson uint16_t bge_rx_std_cons_idx; 2269168951Srwatson uint16_t bge_rx_jumbo_cons_idx; 2270168951Srwatson uint16_t bge_rsvd1; 2271168951Srwatson uint16_t bge_rx_mini_cons_idx; 2272168951Srwatson#endif 2273168951Srwatson struct bge_sts_idx bge_idx[16]; 2274168951Srwatson}; 2275168951Srwatson 2276168951Srwatson#define BGE_STATFLAG_UPDATED 0x00000001 2277168951Srwatson#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2278168951Srwatson#define BGE_STATFLAG_ERROR 0x00000004 2279168951Srwatson 2280168951Srwatson 2281168951Srwatson/* 2282168951Srwatson * Broadcom Vendor ID 2283168951Srwatson * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2284168951Srwatson * even though they're now manufactured by Broadcom) 2285168951Srwatson */ 2286168951Srwatson#define BCOM_VENDORID 0x14E4 2287168951Srwatson#define BCOM_DEVICEID_BCM5700 0x1644 2288168951Srwatson#define BCOM_DEVICEID_BCM5701 0x1645 2289168951Srwatson#define BCOM_DEVICEID_BCM5702 0x1646 2290168951Srwatson#define BCOM_DEVICEID_BCM5702X 0x16A6 2291168951Srwatson#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2292168951Srwatson#define BCOM_DEVICEID_BCM5703 0x1647 2293168951Srwatson#define BCOM_DEVICEID_BCM5703X 0x16A7 2294168951Srwatson#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2295168951Srwatson#define BCOM_DEVICEID_BCM5704C 0x1648 2296168951Srwatson#define BCOM_DEVICEID_BCM5704S 0x16A8 2297168951Srwatson#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2298168951Srwatson#define BCOM_DEVICEID_BCM5705 0x1653 2299168951Srwatson#define BCOM_DEVICEID_BCM5705K 0x1654 2300168951Srwatson#define BCOM_DEVICEID_BCM5705F 0x166E 2301168951Srwatson#define BCOM_DEVICEID_BCM5705M 0x165D 2302168951Srwatson#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2303168951Srwatson#define BCOM_DEVICEID_BCM5714C 0x1668 2304168951Srwatson#define BCOM_DEVICEID_BCM5714S 0x1669 2305168951Srwatson#define BCOM_DEVICEID_BCM5715 0x1678 2306168951Srwatson#define BCOM_DEVICEID_BCM5715S 0x1679 2307168951Srwatson#define BCOM_DEVICEID_BCM5717 0x1655 2308168951Srwatson#define BCOM_DEVICEID_BCM5718 0x1656 2309168951Srwatson#define BCOM_DEVICEID_BCM5719 0x1657 2310168951Srwatson#define BCOM_DEVICEID_BCM5720_PP 0x1658 /* Not released to public. */ 2311168951Srwatson#define BCOM_DEVICEID_BCM5720 0x165F 2312168951Srwatson#define BCOM_DEVICEID_BCM5721 0x1659 2313168951Srwatson#define BCOM_DEVICEID_BCM5722 0x165A 2314168951Srwatson#define BCOM_DEVICEID_BCM5723 0x165B 2315168951Srwatson#define BCOM_DEVICEID_BCM5750 0x1676 2316168951Srwatson#define BCOM_DEVICEID_BCM5750M 0x167C 2317168951Srwatson#define BCOM_DEVICEID_BCM5751 0x1677 2318168951Srwatson#define BCOM_DEVICEID_BCM5751F 0x167E 2319168951Srwatson#define BCOM_DEVICEID_BCM5751M 0x167D 2320168951Srwatson#define BCOM_DEVICEID_BCM5752 0x1600 2321168951Srwatson#define BCOM_DEVICEID_BCM5752M 0x1601 2322168951Srwatson#define BCOM_DEVICEID_BCM5753 0x16F7 2323168951Srwatson#define BCOM_DEVICEID_BCM5753F 0x16FE 2324168951Srwatson#define BCOM_DEVICEID_BCM5753M 0x16FD 2325168951Srwatson#define BCOM_DEVICEID_BCM5754 0x167A 2326168951Srwatson#define BCOM_DEVICEID_BCM5754M 0x1672 2327168951Srwatson#define BCOM_DEVICEID_BCM5755 0x167B 2328168951Srwatson#define BCOM_DEVICEID_BCM5755M 0x1673 2329168951Srwatson#define BCOM_DEVICEID_BCM5756 0x1674 2330168951Srwatson#define BCOM_DEVICEID_BCM5761 0x1681 2331168951Srwatson#define BCOM_DEVICEID_BCM5761E 0x1680 2332168951Srwatson#define BCOM_DEVICEID_BCM5761S 0x1688 2333168951Srwatson#define BCOM_DEVICEID_BCM5761SE 0x1689 2334168951Srwatson#define BCOM_DEVICEID_BCM5764 0x1684 2335168951Srwatson#define BCOM_DEVICEID_BCM5780 0x166A 2336168951Srwatson#define BCOM_DEVICEID_BCM5780S 0x166B 2337168951Srwatson#define BCOM_DEVICEID_BCM5781 0x16DD 2338168951Srwatson#define BCOM_DEVICEID_BCM5782 0x1696 2339168951Srwatson#define BCOM_DEVICEID_BCM5784 0x1698 2340168951Srwatson#define BCOM_DEVICEID_BCM5785F 0x16a0 2341168951Srwatson#define BCOM_DEVICEID_BCM5785G 0x1699 2342168951Srwatson#define BCOM_DEVICEID_BCM5786 0x169A 2343168951Srwatson#define BCOM_DEVICEID_BCM5787 0x169B 2344168951Srwatson#define BCOM_DEVICEID_BCM5787M 0x1693 2345168951Srwatson#define BCOM_DEVICEID_BCM5787F 0x167f 2346168951Srwatson#define BCOM_DEVICEID_BCM5788 0x169C 2347168951Srwatson#define BCOM_DEVICEID_BCM5789 0x169D 2348168951Srwatson#define BCOM_DEVICEID_BCM5901 0x170D 2349168951Srwatson#define BCOM_DEVICEID_BCM5901A2 0x170E 2350168951Srwatson#define BCOM_DEVICEID_BCM5903M 0x16FF 2351168951Srwatson#define BCOM_DEVICEID_BCM5906 0x1712 2352168951Srwatson#define BCOM_DEVICEID_BCM5906M 0x1713 2353168951Srwatson#define BCOM_DEVICEID_BCM57760 0x1690 2354168951Srwatson#define BCOM_DEVICEID_BCM57761 0x16B0 2355168951Srwatson#define BCOM_DEVICEID_BCM57765 0x16B4 2356168951Srwatson#define BCOM_DEVICEID_BCM57780 0x1692 2357168951Srwatson#define BCOM_DEVICEID_BCM57781 0x16B1 2358168951Srwatson#define BCOM_DEVICEID_BCM57785 0x16B5 2359168951Srwatson#define BCOM_DEVICEID_BCM57788 0x1691 2360168951Srwatson#define BCOM_DEVICEID_BCM57790 0x1694 2361168951Srwatson#define BCOM_DEVICEID_BCM57791 0x16B2 2362168951Srwatson#define BCOM_DEVICEID_BCM57795 0x16B6 2363168951Srwatson 2364168951Srwatson/* 2365168951Srwatson * Alteon AceNIC PCI vendor/device ID. 2366168951Srwatson */ 2367168951Srwatson#define ALTEON_VENDORID 0x12AE 2368168951Srwatson#define ALTEON_DEVICEID_ACENIC 0x0001 2369168951Srwatson#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2370168951Srwatson#define ALTEON_DEVICEID_BCM5700 0x0003 2371168951Srwatson#define ALTEON_DEVICEID_BCM5701 0x0004 2372168951Srwatson 2373168951Srwatson/* 2374168951Srwatson * 3Com 3c996 PCI vendor/device ID. 2375168951Srwatson */ 2376168951Srwatson#define TC_VENDORID 0x10B7 2377168951Srwatson#define TC_DEVICEID_3C996 0x0003 2378168951Srwatson 2379168951Srwatson/* 2380168951Srwatson * SysKonnect PCI vendor ID 2381168951Srwatson */ 2382168951Srwatson#define SK_VENDORID 0x1148 2383168951Srwatson#define SK_DEVICEID_ALTIMA 0x4400 2384168951Srwatson#define SK_SUBSYSID_9D21 0x4421 2385168951Srwatson#define SK_SUBSYSID_9D41 0x4441 2386168951Srwatson 2387168951Srwatson/* 2388168951Srwatson * Altima PCI vendor/device ID. 2389168951Srwatson */ 2390168951Srwatson#define ALTIMA_VENDORID 0x173b 2391168951Srwatson#define ALTIMA_DEVICE_AC1000 0x03e8 2392168951Srwatson#define ALTIMA_DEVICE_AC1002 0x03e9 2393168951Srwatson#define ALTIMA_DEVICE_AC9100 0x03ea 2394168951Srwatson 2395168951Srwatson/* 2396168951Srwatson * Dell PCI vendor ID 2397168951Srwatson */ 2398168951Srwatson 2399168951Srwatson#define DELL_VENDORID 0x1028 2400168951Srwatson 2401168951Srwatson/* 2402168951Srwatson * Apple PCI vendor ID. 2403168951Srwatson */ 2404168951Srwatson#define APPLE_VENDORID 0x106b 2405168951Srwatson#define APPLE_DEVICE_BCM5701 0x1645 2406168951Srwatson 2407168951Srwatson/* 2408168951Srwatson * Sun PCI vendor ID 2409168951Srwatson */ 2410168951Srwatson#define SUN_VENDORID 0x108e 2411168951Srwatson 2412168951Srwatson/* 2413168951Srwatson * Fujitsu vendor/device IDs 2414168951Srwatson */ 2415168951Srwatson#define FJTSU_VENDORID 0x10cf 2416168951Srwatson#define FJTSU_DEVICEID_PW008GE5 0x11a1 2417168951Srwatson#define FJTSU_DEVICEID_PW008GE4 0x11a2 2418168951Srwatson#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */ 2419168951Srwatson 2420168951Srwatson/* 2421172955Srwatson * Offset of MAC address inside EEPROM. 2422168951Srwatson */ 2423168951Srwatson#define BGE_EE_MAC_OFFSET 0x7C 2424168951Srwatson#define BGE_EE_MAC_OFFSET_5906 0x10 2425112574Srwatson#define BGE_EE_HWCFG_OFFSET 0xC8 2426112574Srwatson 2427112574Srwatson#define BGE_HWCFG_VOLTAGE 0x00000003 2428112574Srwatson#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2429172955Srwatson#define BGE_HWCFG_MEDIA 0x00000030 2430168976Srwatson#define BGE_HWCFG_ASF 0x00000080 2431106418Srwatson 2432106418Srwatson#define BGE_VOLTAGE_1POINT3 0x00000000 2433106418Srwatson#define BGE_VOLTAGE_1POINT8 0x00000001 2434106418Srwatson 2435172955Srwatson#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2436106418Srwatson#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2437106418Srwatson#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2438122524Srwatson 2439106418Srwatson#define BGE_MEDIA_UNSPEC 0x00000000 2440172955Srwatson#define BGE_MEDIA_COPPER 0x00000010 2441106418Srwatson#define BGE_MEDIA_FIBER 0x00000020 2442106418Srwatson 2443106418Srwatson#define BGE_TICKS_PER_SEC 1000000 2444168976Srwatson 2445106418Srwatson/* 2446106418Srwatson * Ring size constants. 2447168976Srwatson */ 2448172955Srwatson#define BGE_EVENT_RING_CNT 256 2449106418Srwatson#define BGE_CMD_RING_CNT 64 2450106418Srwatson#define BGE_STD_RX_RING_CNT 512 2451106418Srwatson#define BGE_JUMBO_RX_RING_CNT 256 2452106418Srwatson#define BGE_MINI_RX_RING_CNT 1024 2453106418Srwatson#define BGE_RETURN_RING_CNT 1024 2454106418Srwatson 2455172955Srwatson/* 5705 has smaller return ring size */ 2456168933Srwatson 2457168933Srwatson#define BGE_RETURN_RING_CNT_5705 512 2458168933Srwatson 2459168933Srwatson/* 2460168933Srwatson * Possible TX ring sizes. 2461172955Srwatson */ 2462168933Srwatson#define BGE_TX_RING_CNT_128 128 2463168933Srwatson#define BGE_TX_RING_BASE_128 0x3800 2464168933Srwatson 2465168933Srwatson#define BGE_TX_RING_CNT_256 256 2466172955Srwatson#define BGE_TX_RING_BASE_256 0x3000 2467168933Srwatson 2468168933Srwatson#define BGE_TX_RING_CNT_512 512 2469168933Srwatson#define BGE_TX_RING_BASE_512 0x2000 2470168933Srwatson 2471168933Srwatson#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2472168933Srwatson#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2473168933Srwatson 2474172955Srwatson/* 2475168933Srwatson * Tigon III statistics counters. 2476168933Srwatson */ 2477168933Srwatson/* Statistics maintained MAC Receive block. */ 2478168933Srwatsonstruct bge_rx_mac_stats { 2479168933Srwatson bge_hostaddr ifHCInOctets; 2480168933Srwatson bge_hostaddr Reserved1; 2481172955Srwatson bge_hostaddr etherStatsFragments; 2482168933Srwatson bge_hostaddr ifHCInUcastPkts; 2483168933Srwatson bge_hostaddr ifHCInMulticastPkts; 2484168933Srwatson bge_hostaddr ifHCInBroadcastPkts; 2485168933Srwatson bge_hostaddr dot3StatsFCSErrors; 2486172955Srwatson bge_hostaddr dot3StatsAlignmentErrors; 2487168933Srwatson bge_hostaddr xonPauseFramesReceived; 2488168933Srwatson bge_hostaddr xoffPauseFramesReceived; 2489168933Srwatson bge_hostaddr macControlFramesReceived; 2490168933Srwatson bge_hostaddr xoffStateEntered; 2491172955Srwatson bge_hostaddr dot3StatsFramesTooLong; 2492168933Srwatson bge_hostaddr etherStatsJabbers; 2493168933Srwatson bge_hostaddr etherStatsUndersizePkts; 2494168933Srwatson bge_hostaddr inRangeLengthError; 2495168933Srwatson bge_hostaddr outRangeLengthError; 2496168933Srwatson bge_hostaddr etherStatsPkts64Octets; 2497168933Srwatson bge_hostaddr etherStatsPkts65Octetsto127Octets; 2498168933Srwatson bge_hostaddr etherStatsPkts128Octetsto255Octets; 2499172955Srwatson bge_hostaddr etherStatsPkts256Octetsto511Octets; 2500168976Srwatson bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2501106161Srwatson bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2502106161Srwatson bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2503106416Srwatson bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2504106161Srwatson bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2505172955Srwatson bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2506106161Srwatson}; 2507106161Srwatson 2508122524Srwatson 2509168976Srwatson/* Statistics maintained MAC Transmit block. */ 2510106161Srwatsonstruct bge_tx_mac_stats { 2511172955Srwatson bge_hostaddr ifHCOutOctets; 2512106416Srwatson bge_hostaddr Reserved2; 2513106416Srwatson bge_hostaddr etherStatsCollisions; 2514106161Srwatson bge_hostaddr outXonSent; 2515172955Srwatson bge_hostaddr outXoffSent; 2516106161Srwatson bge_hostaddr flowControlDone; 2517106161Srwatson bge_hostaddr dot3StatsInternalMacTransmitErrors; 2518106161Srwatson bge_hostaddr dot3StatsSingleCollisionFrames; 2519106161Srwatson bge_hostaddr dot3StatsMultipleCollisionFrames; 2520106161Srwatson bge_hostaddr dot3StatsDeferredTransmissions; 2521106161Srwatson bge_hostaddr Reserved3; 2522172955Srwatson bge_hostaddr dot3StatsExcessiveCollisions; 2523112574Srwatson bge_hostaddr dot3StatsLateCollisions; 2524112574Srwatson bge_hostaddr dot3Collided2Times; 2525166617Srwatson bge_hostaddr dot3Collided3Times; 2526112574Srwatson bge_hostaddr dot3Collided4Times; 2527112574Srwatson bge_hostaddr dot3Collided5Times; 2528172955Srwatson bge_hostaddr dot3Collided6Times; 2529112574Srwatson bge_hostaddr dot3Collided7Times; 2530112574Srwatson bge_hostaddr dot3Collided8Times; 2531122524Srwatson bge_hostaddr dot3Collided9Times; 2532112574Srwatson bge_hostaddr dot3Collided10Times; 2533172955Srwatson bge_hostaddr dot3Collided11Times; 2534112574Srwatson bge_hostaddr dot3Collided12Times; 2535112574Srwatson bge_hostaddr dot3Collided13Times; 2536112574Srwatson bge_hostaddr dot3Collided14Times; 2537112574Srwatson bge_hostaddr dot3Collided15Times; 2538112574Srwatson bge_hostaddr ifHCOutUcastPkts; 2539112574Srwatson bge_hostaddr ifHCOutMulticastPkts; 2540112574Srwatson bge_hostaddr ifHCOutBroadcastPkts; 2541172955Srwatson bge_hostaddr dot3StatsCarrierSenseErrors; 2542126121Spjd bge_hostaddr ifOutDiscards; 2543106161Srwatson bge_hostaddr ifOutErrors; 2544106161Srwatson}; 2545106161Srwatson 2546106161Srwatson/* Stats counters access through registers */ 2547172955Srwatsonstruct bge_mac_stats { 2548106161Srwatson /* TX MAC statistics */ 2549106161Srwatson uint64_t ifHCOutOctets; 2550122524Srwatson uint64_t Reserved0; 2551106161Srwatson uint64_t etherStatsCollisions; 2552106161Srwatson uint64_t outXonSent; 2553172955Srwatson uint64_t outXoffSent; 2554172955Srwatson uint64_t Reserved1; 2555106161Srwatson uint64_t dot3StatsInternalMacTransmitErrors; 2556126121Spjd uint64_t dot3StatsSingleCollisionFrames; 2557172955Srwatson uint64_t dot3StatsMultipleCollisionFrames; 2558106161Srwatson uint64_t dot3StatsDeferredTransmissions; 2559106161Srwatson uint64_t Reserved2; 2560172955Srwatson uint64_t dot3StatsExcessiveCollisions; 2561106161Srwatson uint64_t dot3StatsLateCollisions; 2562106161Srwatson uint64_t Reserved3[14]; 2563106161Srwatson uint64_t ifHCOutUcastPkts; 2564106161Srwatson uint64_t ifHCOutMulticastPkts; 2565106161Srwatson uint64_t ifHCOutBroadcastPkts; 2566106161Srwatson uint64_t Reserved4[2]; 2567106161Srwatson /* RX MAC statistics */ 2568106161Srwatson uint64_t ifHCInOctets; 2569172955Srwatson uint64_t Reserved5; 2570168976Srwatson uint64_t etherStatsFragments; 2571101099Srwatson uint64_t ifHCInUcastPkts; 2572101099Srwatson uint64_t ifHCInMulticastPkts; 2573101099Srwatson uint64_t ifHCInBroadcastPkts; 2574172955Srwatson uint64_t dot3StatsFCSErrors; 2575101099Srwatson uint64_t dot3StatsAlignmentErrors; 2576101099Srwatson uint64_t xonPauseFramesReceived; 2577122524Srwatson uint64_t xoffPauseFramesReceived; 2578168976Srwatson uint64_t macControlFramesReceived; 2579101099Srwatson uint64_t xoffStateEntered; 2580172955Srwatson uint64_t dot3StatsFramesTooLong; 2581101099Srwatson uint64_t etherStatsJabbers; 2582101099Srwatson uint64_t etherStatsUndersizePkts; 2583101099Srwatson /* Receive List Placement control */ 2584101099Srwatson uint64_t FramesDroppedDueToFilters; 2585101099Srwatson uint64_t DmaWriteQueueFull; 2586101099Srwatson uint64_t DmaWriteHighPriQueueFull; 2587172955Srwatson uint64_t NoMoreRxBDs; 2588168976Srwatson uint64_t InputDiscards; 2589101099Srwatson uint64_t InputErrors; 2590101099Srwatson uint64_t RecvThresholdHit; 2591101099Srwatson}; 2592172955Srwatson 2593101099Srwatsonstruct bge_stats { 2594101099Srwatson uint8_t Reserved0[256]; 2595122524Srwatson 2596168976Srwatson /* Statistics maintained by Receive MAC. */ 2597101099Srwatson struct bge_rx_mac_stats rxstats; 2598172955Srwatson 2599101099Srwatson bge_hostaddr Unused1[37]; 2600101099Srwatson 2601101099Srwatson /* Statistics maintained by Transmit MAC. */ 2602101099Srwatson struct bge_tx_mac_stats txstats; 2603101099Srwatson 2604101099Srwatson bge_hostaddr Unused2[31]; 2605172955Srwatson 2606168976Srwatson /* Statistics maintained by Receive List Placement. */ 2607101099Srwatson bge_hostaddr COSIfHCInPkts[16]; 2608101099Srwatson bge_hostaddr COSFramesDroppedDueToFilters; 2609101099Srwatson bge_hostaddr nicDmaWriteQueueFull; 2610172955Srwatson bge_hostaddr nicDmaWriteHighPriQueueFull; 2611101099Srwatson bge_hostaddr nicNoMoreRxBDs; 2612101099Srwatson bge_hostaddr ifInDiscards; 2613122524Srwatson bge_hostaddr ifInErrors; 2614168976Srwatson bge_hostaddr nicRecvThresholdHit; 2615101099Srwatson 2616172955Srwatson bge_hostaddr Unused3[9]; 2617101099Srwatson 2618101099Srwatson /* Statistics maintained by Send Data Initiator. */ 2619101099Srwatson bge_hostaddr COSIfHCOutPkts[16]; 2620101099Srwatson bge_hostaddr nicDmaReadQueueFull; 2621101099Srwatson bge_hostaddr nicDmaReadHighPriQueueFull; 2622101099Srwatson bge_hostaddr nicSendDataCompQueueFull; 2623172955Srwatson 2624168976Srwatson /* Statistics maintained by Host Coalescing. */ 2625101099Srwatson bge_hostaddr nicRingSetSendProdIndex; 2626101099Srwatson bge_hostaddr nicRingStatusUpdate; 2627101099Srwatson bge_hostaddr nicInterrupts; 2628172955Srwatson bge_hostaddr nicAvoidedInterrupts; 2629101099Srwatson bge_hostaddr nicSendThresholdHit; 2630101099Srwatson 2631122524Srwatson uint8_t Reserved4[320]; 2632168976Srwatson}; 2633101099Srwatson 2634172955Srwatson/* 2635101099Srwatson * Tigon general information block. This resides in host memory 2636101099Srwatson * and contains the status counters, ring control blocks and 2637101099Srwatson * producer pointers. 2638101099Srwatson */ 2639101099Srwatson 2640101099Srwatsonstruct bge_gib { 2641172955Srwatson struct bge_stats bge_stats; 2642168976Srwatson struct bge_rcb bge_tx_rcb[16]; 2643119202Srwatson struct bge_rcb bge_std_rx_rcb; 2644119202Srwatson struct bge_rcb bge_jumbo_rx_rcb; 2645119202Srwatson struct bge_rcb bge_mini_rx_rcb; 2646172955Srwatson struct bge_rcb bge_return_rcb; 2647119202Srwatson}; 2648119202Srwatson 2649122524Srwatson#define BGE_FRAMELEN 1518 2650168976Srwatson#define BGE_MAX_FRAMELEN 1536 2651119202Srwatson#define BGE_JUMBO_FRAMELEN 9018 2652172955Srwatson#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2653119202Srwatson#define BGE_MIN_FRAMELEN 60 2654119202Srwatson 2655119202Srwatson/* 2656119202Srwatson * Other utility macros. 2657119202Srwatson */ 2658119202Srwatson#define BGE_INC(x, y) (x) = (x + 1) % y 2659172955Srwatson 2660168976Srwatson/* 2661106648Srwatson * Register access macros. The Tigon always uses memory mapped register 2662101099Srwatson * accesses and all registers must be accessed with 32 bit operations. 2663106648Srwatson */ 2664106648Srwatson 2665101099Srwatson#define CSR_WRITE_4(sc, reg, val) \ 2666106648Srwatson bus_write_4(sc->bge_res, reg, val) 2667106648Srwatson 2668106648Srwatson#define CSR_READ_4(sc, reg) \ 2669172955Srwatson bus_read_4(sc->bge_res, reg) 2670172955Srwatson 2671106648Srwatson#define BGE_SETBIT(sc, reg, x) \ 2672106648Srwatson CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2673106648Srwatson#define BGE_CLRBIT(sc, reg, x) \ 2674106648Srwatson CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2675106648Srwatson 2676106648Srwatson#define PCI_SETBIT(dev, reg, x, s) \ 2677106648Srwatson pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2678172955Srwatson#define PCI_CLRBIT(dev, reg, x, s) \ 2679101099Srwatson pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2680101099Srwatson 2681122524Srwatson/* 2682168976Srwatson * Memory management stuff. 2683101099Srwatson */ 2684172955Srwatson 2685101099Srwatson#define BGE_NSEG_JUMBO 4 2686101099Srwatson#define BGE_NSEG_NEW 32 2687101099Srwatson#define BGE_TSOSEG_SZ 4096 2688101099Srwatson 2689101099Srwatson/* Maximum DMA address for controllers that have 40bit DMA address bug. */ 2690101099Srwatson#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2691172955Srwatson#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2692168976Srwatson#else 2693101099Srwatson#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2694101099Srwatson#endif 2695101099Srwatson 2696172955Srwatson/* 2697101099Srwatson * Ring structures. Most of these reside in host memory and we tell 2698101099Srwatson * the NIC where they are via the ring control blocks. The exceptions 2699122524Srwatson * are the tx and command rings, which live in NIC memory and which 2700168976Srwatson * we access via the shared memory window. 2701101099Srwatson */ 2702172955Srwatson 2703101099Srwatsonstruct bge_ring_data { 2704101099Srwatson struct bge_rx_bd *bge_rx_std_ring; 2705101099Srwatson bus_addr_t bge_rx_std_ring_paddr; 2706101099Srwatson struct bge_extrx_bd *bge_rx_jumbo_ring; 2707101099Srwatson bus_addr_t bge_rx_jumbo_ring_paddr; 2708101099Srwatson struct bge_rx_bd *bge_rx_return_ring; 2709172955Srwatson bus_addr_t bge_rx_return_ring_paddr; 2710168976Srwatson struct bge_tx_bd *bge_tx_ring; 2711168976Srwatson bus_addr_t bge_tx_ring_paddr; 2712101099Srwatson struct bge_status_block *bge_status_block; 2713101099Srwatson bus_addr_t bge_status_block_paddr; 2714101099Srwatson struct bge_stats *bge_stats; 2715172955Srwatson bus_addr_t bge_stats_paddr; 2716101099Srwatson struct bge_gib bge_info; 2717101099Srwatson}; 2718122524Srwatson 2719168976Srwatson#define BGE_STD_RX_RING_SZ \ 2720101099Srwatson (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2721172955Srwatson#define BGE_JUMBO_RX_RING_SZ \ 2722101099Srwatson (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2723101099Srwatson#define BGE_TX_RING_SZ \ 2724101099Srwatson (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2725101099Srwatson#define BGE_RX_RTN_RING_SZ(x) \ 2726101099Srwatson (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2727101099Srwatson 2728172955Srwatson#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2729168976Srwatson 2730104530Srwatson#define BGE_STATS_SZ sizeof (struct bge_stats) 2731104530Srwatson 2732104530Srwatson/* 2733104530Srwatson * Mbuf pointers. We need these to keep track of the virtual addresses 2734172955Srwatson * of our mbuf chains since we can only convert from physical to virtual, 2735104530Srwatson * not the other way around. 2736104530Srwatson */ 2737122524Srwatsonstruct bge_chain_data { 2738168976Srwatson bus_dma_tag_t bge_parent_tag; 2739104530Srwatson bus_dma_tag_t bge_buffer_tag; 2740172955Srwatson bus_dma_tag_t bge_rx_std_ring_tag; 2741104530Srwatson bus_dma_tag_t bge_rx_jumbo_ring_tag; 2742104530Srwatson bus_dma_tag_t bge_rx_return_ring_tag; 2743168976Srwatson bus_dma_tag_t bge_tx_ring_tag; 2744104530Srwatson bus_dma_tag_t bge_status_tag; 2745172955Srwatson bus_dma_tag_t bge_stats_tag; 2746104530Srwatson bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */ 2747104530Srwatson bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */ 2748104530Srwatson bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */ 2749104530Srwatson bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2750104530Srwatson bus_dmamap_t bge_rx_std_sparemap; 2751104530Srwatson bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2752172955Srwatson bus_dmamap_t bge_rx_jumbo_sparemap; 2753168976Srwatson bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2754119202Srwatson bus_dmamap_t bge_rx_std_ring_map; 2755119202Srwatson bus_dmamap_t bge_rx_jumbo_ring_map; 2756119202Srwatson bus_dmamap_t bge_tx_ring_map; 2757172955Srwatson bus_dmamap_t bge_rx_return_ring_map; 2758119202Srwatson bus_dmamap_t bge_status_map; 2759119202Srwatson bus_dmamap_t bge_stats_map; 2760122524Srwatson struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2761168976Srwatson struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2762119202Srwatson struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2763172955Srwatson int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2764119202Srwatson int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 2765119202Srwatson}; 2766119202Srwatson 2767119202Srwatsonstruct bge_dmamap_arg { 2768119202Srwatson bus_addr_t bge_busaddr; 2769119202Srwatson}; 2770172955Srwatson 2771168976Srwatson#define BGE_HWREV_TIGON 0x01 2772101099Srwatson#define BGE_HWREV_TIGON_II 0x02 2773101099Srwatson#define BGE_TIMEOUT 100000 2774103759Srwatson#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2775172955Srwatson 2776101099Srwatsonstruct bge_bcom_hack { 2777103759Srwatson int reg; 2778122524Srwatson int val; 2779168976Srwatson}; 2780103759Srwatson 2781172955Srwatson#define ASF_ENABLE 1 2782101099Srwatson#define ASF_NEW_HANDSHAKE 2 2783101099Srwatson#define ASF_STACKUP 4 2784103759Srwatson 2785101099Srwatsonstruct bge_softc { 2786101099Srwatson struct ifnet *bge_ifp; /* interface info */ 2787101099Srwatson device_t bge_dev; 2788172955Srwatson struct mtx bge_mtx; 2789168976Srwatson device_t bge_miibus; 2790104546Srwatson void *bge_intrhand; 2791104546Srwatson struct resource *bge_irq; 2792104546Srwatson struct resource *bge_res; 2793104546Srwatson struct ifmedia bge_ifmedia; /* TBI media info */ 2794104546Srwatson int bge_expcap; 2795104546Srwatson int bge_expmrq; 2796104546Srwatson int bge_msicap; 2797172955Srwatson int bge_pcixcap; 2798104546Srwatson uint32_t bge_flags; 2799104546Srwatson#define BGE_FLAG_TBI 0x00000001 2800122524Srwatson#define BGE_FLAG_JUMBO 0x00000002 2801168976Srwatson#define BGE_FLAG_JUMBO_STD 0x00000004 2802104546Srwatson#define BGE_FLAG_EADDR 0x00000008 2803104546Srwatson#define BGE_FLAG_MII_SERDES 0x00000010 2804172955Srwatson#define BGE_FLAG_CPMU_PRESENT 0x00000020 2805104546Srwatson#define BGE_FLAG_TAGGED_STATUS 0x00000040 2806104546Srwatson#define BGE_FLAG_MSI 0x00000100 2807145076Scsjp#define BGE_FLAG_PCIX 0x00000200 2808172955Srwatson#define BGE_FLAG_PCIE 0x00000400 2809104546Srwatson#define BGE_FLAG_TSO 0x00000800 2810104546Srwatson#define BGE_FLAG_TSO3 0x00001000 2811104546Srwatson#define BGE_FLAG_JUMBO_FRAME 0x00002000 2812104569Srwatson#define BGE_FLAG_5700_FAMILY 0x00010000 2813104546Srwatson#define BGE_FLAG_5705_PLUS 0x00020000 2814104546Srwatson#define BGE_FLAG_5714_FAMILY 0x00040000 2815104546Srwatson#define BGE_FLAG_575X_PLUS 0x00080000 2816172955Srwatson#define BGE_FLAG_5755_PLUS 0x00100000 2817168976Srwatson#define BGE_FLAG_5788 0x00200000 2818101099Srwatson#define BGE_FLAG_5717_PLUS 0x00400000 2819101099Srwatson#define BGE_FLAG_40BIT_BUG 0x01000000 2820101099Srwatson#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2821172955Srwatson#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2822101099Srwatson#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2823101099Srwatson#define BGE_FLAG_4K_RDMA_BUG 0x10000000 2824122524Srwatson#define BGE_FLAG_MBOX_REORDER 0x20000000 2825168976Srwatson uint32_t bge_phy_flags; 2826101099Srwatson#define BGE_PHY_NO_WIRESPEED 0x00000001 2827101099Srwatson#define BGE_PHY_ADC_BUG 0x00000002 2828101099Srwatson#define BGE_PHY_5704_A0_BUG 0x00000004 2829172955Srwatson#define BGE_PHY_JITTER_BUG 0x00000008 2830101099Srwatson#define BGE_PHY_BER_BUG 0x00000010 2831101099Srwatson#define BGE_PHY_ADJUST_TRIM 0x00000020 2832101099Srwatson#define BGE_PHY_CRC_BUG 0x00000040 2833172955Srwatson#define BGE_PHY_NO_3LED 0x00000080 2834101099Srwatson uint32_t bge_chipid; 2835101099Srwatson uint32_t bge_asicrev; 2836101099Srwatson uint32_t bge_chiprev; 2837101099Srwatson uint8_t bge_asf_mode; 2838101099Srwatson uint8_t bge_asf_count; 2839101099Srwatson uint16_t bge_mps; 2840101099Srwatson struct bge_ring_data bge_ldata; /* rings */ 2841172955Srwatson struct bge_chain_data bge_cdata; /* mbufs */ 2842168976Srwatson uint16_t bge_tx_saved_considx; 2843102112Srwatson uint16_t bge_rx_saved_considx; 2844102112Srwatson uint16_t bge_ev_saved_considx; 2845102112Srwatson uint16_t bge_return_ring_cnt; 2846172955Srwatson uint16_t bge_std; /* current std ring head */ 2847102112Srwatson uint16_t bge_jumbo; /* current jumo ring head */ 2848102112Srwatson uint32_t bge_stat_ticks; 2849122524Srwatson uint32_t bge_rx_coal_ticks; 2850168976Srwatson uint32_t bge_tx_coal_ticks; 2851102112Srwatson uint32_t bge_tx_prodidx; 2852172955Srwatson uint32_t bge_rx_max_coal_bds; 2853102112Srwatson uint32_t bge_tx_max_coal_bds; 2854102112Srwatson uint32_t bge_mi_mode; 2855102112Srwatson int bge_if_flags; 2856102112Srwatson int bge_txcnt; 2857102112Srwatson int bge_link; /* link state */ 2858102112Srwatson int bge_link_evt; /* pending link event */ 2859172955Srwatson int bge_timer; 2860168976Srwatson int bge_forced_collapse; 2861102112Srwatson int bge_forced_udpcsum; 2862102112Srwatson int bge_msi; 2863102112Srwatson int bge_csum_features; 2864172955Srwatson struct callout bge_stat_ch; 2865102112Srwatson uint32_t bge_rx_discards; 2866102112Srwatson uint32_t bge_rx_inerrs; 2867122524Srwatson uint32_t bge_rx_nobds; 2868168976Srwatson uint32_t bge_tx_discards; 2869102112Srwatson uint32_t bge_tx_collisions; 2870172955Srwatson#ifdef DEVICE_POLLING 2871102112Srwatson int rxcycles; 2872102112Srwatson#endif /* DEVICE_POLLING */ 2873102112Srwatson struct bge_mac_stats bge_mac_stats; 2874102112Srwatson struct task bge_intr_task; 2875102112Srwatson struct taskqueue *bge_tq; 2876102112Srwatson}; 2877172955Srwatson 2878168976Srwatson#define BGE_LOCK_INIT(_sc, _name) \ 2879101099Srwatson mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2880101099Srwatson#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2881101099Srwatson#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2882172955Srwatson#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2883101099Srwatson#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2884101099Srwatson