if_bgereg.h revision 226815
1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 226815 2011-10-26 21:11:40Z yongari $ 34 */ 35 36/* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 */ 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SRAM_FW_MB 0x00000B50 75#define BGE_SRAM_DATA_SIG 0x00000B54 76#define BGE_SRAM_DATA_CFG 0x00000B58 77#define BGE_SRAM_FW_CMD_MB 0x00000B78 78#define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C 79#define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80 80#define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14 81#define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18 82#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 83#define BGE_UNMAPPED 0x00001000 84#define BGE_UNMAPPED_END 0x00001FFF 85#define BGE_DMA_DESCRIPTORS 0x00002000 86#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 87#define BGE_SEND_RING_5717 0x00004000 88#define BGE_SEND_RING_1_TO_4 0x00004000 89#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 90 91/* Firmware interface */ 92#define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */ 93#define BGE_FW_DRV_ALIVE 0x00000001 94#define BGE_FW_PAUSE 0x00000002 95 96/* Mappings for internal memory configuration */ 97#define BGE_STD_RX_RINGS 0x00006000 98#define BGE_STD_RX_RINGS_END 0x00006FFF 99#define BGE_JUMBO_RX_RINGS 0x00007000 100#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 101#define BGE_BUFFPOOL_1 0x00008000 102#define BGE_BUFFPOOL_1_END 0x0000FFFF 103#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 104#define BGE_BUFFPOOL_2_END 0x00017FFF 105#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 106#define BGE_BUFFPOOL_3_END 0x0001FFFF 107#define BGE_STD_RX_RINGS_5717 0x00040000 108#define BGE_JUMBO_RX_RINGS_5717 0x00044400 109 110/* Mappings for external SSRAM configurations */ 111#define BGE_SEND_RING_5_TO_6 0x00006000 112#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 113#define BGE_SEND_RING_7_TO_8 0x00007000 114#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 115#define BGE_SEND_RING_9_TO_16 0x00008000 116#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 117#define BGE_EXT_STD_RX_RINGS 0x0000C000 118#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 119#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 120#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 121#define BGE_MINI_RX_RINGS 0x0000E000 122#define BGE_MINI_RX_RINGS_END 0x0000FFFF 123#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 124#define BGE_AVAIL_REGION1_END 0x00017FFF 125#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 126#define BGE_AVAIL_REGION2_END 0x0001FFFF 127#define BGE_EXT_SSRAM 0x00020000 128#define BGE_EXT_SSRAM_END 0x000FFFFF 129 130 131/* 132 * BCM570x register offsets. These are memory mapped registers 133 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 134 * Each register must be accessed using 32 bit operations. 135 * 136 * All registers are accessed through a 32K shared memory block. 137 * The first group of registers are actually copies of the PCI 138 * configuration space registers. 139 */ 140 141/* 142 * PCI registers defined in the PCI 2.2 spec. 143 */ 144#define BGE_PCI_VID 0x00 145#define BGE_PCI_DID 0x02 146#define BGE_PCI_CMD 0x04 147#define BGE_PCI_STS 0x06 148#define BGE_PCI_REV 0x08 149#define BGE_PCI_CLASS 0x09 150#define BGE_PCI_CACHESZ 0x0C 151#define BGE_PCI_LATTIMER 0x0D 152#define BGE_PCI_HDRTYPE 0x0E 153#define BGE_PCI_BIST 0x0F 154#define BGE_PCI_BAR0 0x10 155#define BGE_PCI_BAR1 0x14 156#define BGE_PCI_SUBSYS 0x2C 157#define BGE_PCI_SUBVID 0x2E 158#define BGE_PCI_ROMBASE 0x30 159#define BGE_PCI_CAPPTR 0x34 160#define BGE_PCI_INTLINE 0x3C 161#define BGE_PCI_INTPIN 0x3D 162#define BGE_PCI_MINGNT 0x3E 163#define BGE_PCI_MAXLAT 0x3F 164#define BGE_PCI_PCIXCAP 0x40 165#define BGE_PCI_NEXTPTR_PM 0x41 166#define BGE_PCI_PCIX_CMD 0x42 167#define BGE_PCI_PCIX_STS 0x44 168#define BGE_PCI_PWRMGMT_CAPID 0x48 169#define BGE_PCI_NEXTPTR_VPD 0x49 170#define BGE_PCI_PWRMGMT_CAPS 0x4A 171#define BGE_PCI_PWRMGMT_CMD 0x4C 172#define BGE_PCI_PWRMGMT_STS 0x4D 173#define BGE_PCI_PWRMGMT_DATA 0x4F 174#define BGE_PCI_VPD_CAPID 0x50 175#define BGE_PCI_NEXTPTR_MSI 0x51 176#define BGE_PCI_VPD_ADDR 0x52 177#define BGE_PCI_VPD_DATA 0x54 178#define BGE_PCI_MSI_CAPID 0x58 179#define BGE_PCI_NEXTPTR_NONE 0x59 180#define BGE_PCI_MSI_CTL 0x5A 181#define BGE_PCI_MSI_ADDR_HI 0x5C 182#define BGE_PCI_MSI_ADDR_LO 0x60 183#define BGE_PCI_MSI_DATA 0x64 184 185/* 186 * PCI Express definitions 187 * According to 188 * PCI Express base specification, REV. 1.0a 189 */ 190 191/* PCI Express device control, 16bits */ 192#define BGE_PCIE_DEVCTL 0x08 193#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 194#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 195#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 196#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 197#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 198#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 199#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 200 201/* PCI MSI. ??? */ 202#define BGE_PCIE_CAPID_REG 0xD0 203#define BGE_PCIE_CAPID 0x10 204 205/* 206 * PCI registers specific to the BCM570x family. 207 */ 208#define BGE_PCI_MISC_CTL 0x68 209#define BGE_PCI_DMA_RW_CTL 0x6C 210#define BGE_PCI_PCISTATE 0x70 211#define BGE_PCI_CLKCTL 0x74 212#define BGE_PCI_REG_BASEADDR 0x78 213#define BGE_PCI_MEMWIN_BASEADDR 0x7C 214#define BGE_PCI_REG_DATA 0x80 215#define BGE_PCI_MEMWIN_DATA 0x84 216#define BGE_PCI_MODECTL 0x88 217#define BGE_PCI_MISC_CFG 0x8C 218#define BGE_PCI_MISC_LOCALCTL 0x90 219#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 220#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 221#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 222#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 223#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 224#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 225#define BGE_PCI_ISR_MBX_HI 0xB0 226#define BGE_PCI_ISR_MBX_LO 0xB4 227#define BGE_PCI_PRODID_ASICREV 0xBC 228#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 229#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 230 231/* PCI Misc. Host control register */ 232#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 233#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 234#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 235#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 236#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 237#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 238#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 239#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 240#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 241#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 242#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 243 244#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 245#if BYTE_ORDER == LITTLE_ENDIAN 246#define BGE_DMA_SWAP_OPTIONS \ 247 BGE_MODECTL_WORDSWAP_NONFRAME| \ 248 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 249#else 250#define BGE_DMA_SWAP_OPTIONS \ 251 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 252 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 253#endif 254 255#define BGE_INIT \ 256 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 257 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 258 259#define BGE_CHIPID_TIGON_I 0x4000 260#define BGE_CHIPID_TIGON_II 0x6000 261#define BGE_CHIPID_BCM5700_A0 0x7000 262#define BGE_CHIPID_BCM5700_A1 0x7001 263#define BGE_CHIPID_BCM5700_B0 0x7100 264#define BGE_CHIPID_BCM5700_B1 0x7101 265#define BGE_CHIPID_BCM5700_B2 0x7102 266#define BGE_CHIPID_BCM5700_B3 0x7103 267#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 268#define BGE_CHIPID_BCM5700_C0 0x7200 269#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 270#define BGE_CHIPID_BCM5701_B0 0x0100 271#define BGE_CHIPID_BCM5701_B2 0x0102 272#define BGE_CHIPID_BCM5701_B5 0x0105 273#define BGE_CHIPID_BCM5703_A0 0x1000 274#define BGE_CHIPID_BCM5703_A1 0x1001 275#define BGE_CHIPID_BCM5703_A2 0x1002 276#define BGE_CHIPID_BCM5703_A3 0x1003 277#define BGE_CHIPID_BCM5703_B0 0x1100 278#define BGE_CHIPID_BCM5704_A0 0x2000 279#define BGE_CHIPID_BCM5704_A1 0x2001 280#define BGE_CHIPID_BCM5704_A2 0x2002 281#define BGE_CHIPID_BCM5704_A3 0x2003 282#define BGE_CHIPID_BCM5704_B0 0x2100 283#define BGE_CHIPID_BCM5705_A0 0x3000 284#define BGE_CHIPID_BCM5705_A1 0x3001 285#define BGE_CHIPID_BCM5705_A2 0x3002 286#define BGE_CHIPID_BCM5705_A3 0x3003 287#define BGE_CHIPID_BCM5750_A0 0x4000 288#define BGE_CHIPID_BCM5750_A1 0x4001 289#define BGE_CHIPID_BCM5750_A3 0x4000 290#define BGE_CHIPID_BCM5750_B0 0x4100 291#define BGE_CHIPID_BCM5750_B1 0x4101 292#define BGE_CHIPID_BCM5750_C0 0x4200 293#define BGE_CHIPID_BCM5750_C1 0x4201 294#define BGE_CHIPID_BCM5750_C2 0x4202 295#define BGE_CHIPID_BCM5714_A0 0x5000 296#define BGE_CHIPID_BCM5752_A0 0x6000 297#define BGE_CHIPID_BCM5752_A1 0x6001 298#define BGE_CHIPID_BCM5752_A2 0x6002 299#define BGE_CHIPID_BCM5714_B0 0x8000 300#define BGE_CHIPID_BCM5714_B3 0x8003 301#define BGE_CHIPID_BCM5715_A0 0x9000 302#define BGE_CHIPID_BCM5715_A1 0x9001 303#define BGE_CHIPID_BCM5715_A3 0x9003 304#define BGE_CHIPID_BCM5755_A0 0xa000 305#define BGE_CHIPID_BCM5755_A1 0xa001 306#define BGE_CHIPID_BCM5755_A2 0xa002 307#define BGE_CHIPID_BCM5722_A0 0xa200 308#define BGE_CHIPID_BCM5754_A0 0xb000 309#define BGE_CHIPID_BCM5754_A1 0xb001 310#define BGE_CHIPID_BCM5754_A2 0xb002 311#define BGE_CHIPID_BCM5761_A0 0x5761000 312#define BGE_CHIPID_BCM5761_A1 0x5761100 313#define BGE_CHIPID_BCM5784_A0 0x5784000 314#define BGE_CHIPID_BCM5784_A1 0x5784100 315#define BGE_CHIPID_BCM5787_A0 0xb000 316#define BGE_CHIPID_BCM5787_A1 0xb001 317#define BGE_CHIPID_BCM5787_A2 0xb002 318#define BGE_CHIPID_BCM5906_A0 0xc000 319#define BGE_CHIPID_BCM5906_A1 0xc001 320#define BGE_CHIPID_BCM5906_A2 0xc002 321#define BGE_CHIPID_BCM57780_A0 0x57780000 322#define BGE_CHIPID_BCM57780_A1 0x57780001 323#define BGE_CHIPID_BCM5717_A0 0x05717000 324#define BGE_CHIPID_BCM5717_B0 0x05717100 325#define BGE_CHIPID_BCM5719_A0 0x05719000 326#define BGE_CHIPID_BCM57765_A0 0x57785000 327#define BGE_CHIPID_BCM57765_B0 0x57785100 328 329/* shorthand one */ 330#define BGE_ASICREV(x) ((x) >> 12) 331#define BGE_ASICREV_BCM5701 0x00 332#define BGE_ASICREV_BCM5703 0x01 333#define BGE_ASICREV_BCM5704 0x02 334#define BGE_ASICREV_BCM5705 0x03 335#define BGE_ASICREV_BCM5750 0x04 336#define BGE_ASICREV_BCM5714_A0 0x05 337#define BGE_ASICREV_BCM5752 0x06 338#define BGE_ASICREV_BCM5700 0x07 339#define BGE_ASICREV_BCM5780 0x08 340#define BGE_ASICREV_BCM5714 0x09 341#define BGE_ASICREV_BCM5755 0x0a 342#define BGE_ASICREV_BCM5754 0x0b 343#define BGE_ASICREV_BCM5787 0x0b 344#define BGE_ASICREV_BCM5906 0x0c 345/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 346#define BGE_ASICREV_USE_PRODID_REG 0x0f 347/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 348#define BGE_ASICREV_BCM5717 0x5717 349#define BGE_ASICREV_BCM5719 0x5719 350#define BGE_ASICREV_BCM5761 0x5761 351#define BGE_ASICREV_BCM5784 0x5784 352#define BGE_ASICREV_BCM5785 0x5785 353#define BGE_ASICREV_BCM57765 0x57785 354#define BGE_ASICREV_BCM57780 0x57780 355 356/* chip revisions */ 357#define BGE_CHIPREV(x) ((x) >> 8) 358#define BGE_CHIPREV_5700_AX 0x70 359#define BGE_CHIPREV_5700_BX 0x71 360#define BGE_CHIPREV_5700_CX 0x72 361#define BGE_CHIPREV_5701_AX 0x00 362#define BGE_CHIPREV_5703_AX 0x10 363#define BGE_CHIPREV_5704_AX 0x20 364#define BGE_CHIPREV_5704_BX 0x21 365#define BGE_CHIPREV_5750_AX 0x40 366#define BGE_CHIPREV_5750_BX 0x41 367/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 368#define BGE_CHIPREV_5717_AX 0x57170 369#define BGE_CHIPREV_5717_BX 0x57171 370#define BGE_CHIPREV_5761_AX 0x57611 371#define BGE_CHIPREV_5784_AX 0x57841 372 373/* PCI DMA Read/Write Control register */ 374#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 375#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 376#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 377#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 378#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 379#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 380#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 381#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 382#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 383#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 384#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 385#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 386#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 387 388#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 389#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 390#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 391#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 392 393#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 394#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 395 396#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 397#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 398#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 399#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 400#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 401#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 402#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 403#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 404 405#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 406#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 407#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 408#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 409#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 410#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 411#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 412#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 413 414/* 415 * PCI state register -- note, this register is read only 416 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 417 * register is set. 418 */ 419#define BGE_PCISTATE_FORCE_RESET 0x00000001 420#define BGE_PCISTATE_INTR_STATE 0x00000002 421#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 422#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 423#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 424#define BGE_PCISTATE_WANT_EXPROM 0x00000020 425#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 426#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 427#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 428 429/* 430 * PCI Clock Control register -- note, this register is read only 431 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 432 * register is set. 433 */ 434#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 435#define BGE_PCICLOCKCTL_M66EN 0x00000080 436#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 437#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 438#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 439#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 440#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 441#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 442#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 443#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 444 445 446#ifndef PCIM_CMD_MWIEN 447#define PCIM_CMD_MWIEN 0x0010 448#endif 449#ifndef PCIM_CMD_INTxDIS 450#define PCIM_CMD_INTxDIS 0x0400 451#endif 452 453/* 454 * High priority mailbox registers 455 * Each mailbox is 64-bits wide, though we only use the 456 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 457 * first. The NIC will load the mailbox after the lower 32 bit word 458 * has been updated. 459 */ 460#define BGE_MBX_IRQ0_HI 0x0200 461#define BGE_MBX_IRQ0_LO 0x0204 462#define BGE_MBX_IRQ1_HI 0x0208 463#define BGE_MBX_IRQ1_LO 0x020C 464#define BGE_MBX_IRQ2_HI 0x0210 465#define BGE_MBX_IRQ2_LO 0x0214 466#define BGE_MBX_IRQ3_HI 0x0218 467#define BGE_MBX_IRQ3_LO 0x021C 468#define BGE_MBX_GEN0_HI 0x0220 469#define BGE_MBX_GEN0_LO 0x0224 470#define BGE_MBX_GEN1_HI 0x0228 471#define BGE_MBX_GEN1_LO 0x022C 472#define BGE_MBX_GEN2_HI 0x0230 473#define BGE_MBX_GEN2_LO 0x0234 474#define BGE_MBX_GEN3_HI 0x0228 475#define BGE_MBX_GEN3_LO 0x022C 476#define BGE_MBX_GEN4_HI 0x0240 477#define BGE_MBX_GEN4_LO 0x0244 478#define BGE_MBX_GEN5_HI 0x0248 479#define BGE_MBX_GEN5_LO 0x024C 480#define BGE_MBX_GEN6_HI 0x0250 481#define BGE_MBX_GEN6_LO 0x0254 482#define BGE_MBX_GEN7_HI 0x0258 483#define BGE_MBX_GEN7_LO 0x025C 484#define BGE_MBX_RELOAD_STATS_HI 0x0260 485#define BGE_MBX_RELOAD_STATS_LO 0x0264 486#define BGE_MBX_RX_STD_PROD_HI 0x0268 487#define BGE_MBX_RX_STD_PROD_LO 0x026C 488#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 489#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 490#define BGE_MBX_RX_MINI_PROD_HI 0x0278 491#define BGE_MBX_RX_MINI_PROD_LO 0x027C 492#define BGE_MBX_RX_CONS0_HI 0x0280 493#define BGE_MBX_RX_CONS0_LO 0x0284 494#define BGE_MBX_RX_CONS1_HI 0x0288 495#define BGE_MBX_RX_CONS1_LO 0x028C 496#define BGE_MBX_RX_CONS2_HI 0x0290 497#define BGE_MBX_RX_CONS2_LO 0x0294 498#define BGE_MBX_RX_CONS3_HI 0x0298 499#define BGE_MBX_RX_CONS3_LO 0x029C 500#define BGE_MBX_RX_CONS4_HI 0x02A0 501#define BGE_MBX_RX_CONS4_LO 0x02A4 502#define BGE_MBX_RX_CONS5_HI 0x02A8 503#define BGE_MBX_RX_CONS5_LO 0x02AC 504#define BGE_MBX_RX_CONS6_HI 0x02B0 505#define BGE_MBX_RX_CONS6_LO 0x02B4 506#define BGE_MBX_RX_CONS7_HI 0x02B8 507#define BGE_MBX_RX_CONS7_LO 0x02BC 508#define BGE_MBX_RX_CONS8_HI 0x02C0 509#define BGE_MBX_RX_CONS8_LO 0x02C4 510#define BGE_MBX_RX_CONS9_HI 0x02C8 511#define BGE_MBX_RX_CONS9_LO 0x02CC 512#define BGE_MBX_RX_CONS10_HI 0x02D0 513#define BGE_MBX_RX_CONS10_LO 0x02D4 514#define BGE_MBX_RX_CONS11_HI 0x02D8 515#define BGE_MBX_RX_CONS11_LO 0x02DC 516#define BGE_MBX_RX_CONS12_HI 0x02E0 517#define BGE_MBX_RX_CONS12_LO 0x02E4 518#define BGE_MBX_RX_CONS13_HI 0x02E8 519#define BGE_MBX_RX_CONS13_LO 0x02EC 520#define BGE_MBX_RX_CONS14_HI 0x02F0 521#define BGE_MBX_RX_CONS14_LO 0x02F4 522#define BGE_MBX_RX_CONS15_HI 0x02F8 523#define BGE_MBX_RX_CONS15_LO 0x02FC 524#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 525#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 526#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 527#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 528#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 529#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 530#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 531#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 532#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 533#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 534#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 535#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 536#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 537#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 538#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 539#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 540#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 541#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 542#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 543#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 544#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 545#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 546#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 547#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 548#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 549#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 550#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 551#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 552#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 553#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 554#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 555#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 556#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 557#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 558#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 559#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 560#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 561#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 562#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 563#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 564#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 565#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 566#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 567#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 568#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 569#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 570#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 571#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 572#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 573#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 574#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 575#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 576#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 577#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 578#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 579#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 580#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 581#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 582#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 583#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 584#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 585#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 586#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 587#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 588 589#define BGE_TX_RINGS_MAX 4 590#define BGE_TX_RINGS_EXTSSRAM_MAX 16 591#define BGE_RX_RINGS_MAX 16 592#define BGE_RX_RINGS_MAX_5717 17 593 594/* Ethernet MAC control registers */ 595#define BGE_MAC_MODE 0x0400 596#define BGE_MAC_STS 0x0404 597#define BGE_MAC_EVT_ENB 0x0408 598#define BGE_MAC_LED_CTL 0x040C 599#define BGE_MAC_ADDR1_LO 0x0410 600#define BGE_MAC_ADDR1_HI 0x0414 601#define BGE_MAC_ADDR2_LO 0x0418 602#define BGE_MAC_ADDR2_HI 0x041C 603#define BGE_MAC_ADDR3_LO 0x0420 604#define BGE_MAC_ADDR3_HI 0x0424 605#define BGE_MAC_ADDR4_LO 0x0428 606#define BGE_MAC_ADDR4_HI 0x042C 607#define BGE_WOL_PATPTR 0x0430 608#define BGE_WOL_PATCFG 0x0434 609#define BGE_TX_RANDOM_BACKOFF 0x0438 610#define BGE_RX_MTU 0x043C 611#define BGE_GBIT_PCS_TEST 0x0440 612#define BGE_TX_TBI_AUTONEG 0x0444 613#define BGE_RX_TBI_AUTONEG 0x0448 614#define BGE_MI_COMM 0x044C 615#define BGE_MI_STS 0x0450 616#define BGE_MI_MODE 0x0454 617#define BGE_AUTOPOLL_STS 0x0458 618#define BGE_TX_MODE 0x045C 619#define BGE_TX_STS 0x0460 620#define BGE_TX_LENGTHS 0x0464 621#define BGE_RX_MODE 0x0468 622#define BGE_RX_STS 0x046C 623#define BGE_MAR0 0x0470 624#define BGE_MAR1 0x0474 625#define BGE_MAR2 0x0478 626#define BGE_MAR3 0x047C 627#define BGE_RX_BD_RULES_CTL0 0x0480 628#define BGE_RX_BD_RULES_MASKVAL0 0x0484 629#define BGE_RX_BD_RULES_CTL1 0x0488 630#define BGE_RX_BD_RULES_MASKVAL1 0x048C 631#define BGE_RX_BD_RULES_CTL2 0x0490 632#define BGE_RX_BD_RULES_MASKVAL2 0x0494 633#define BGE_RX_BD_RULES_CTL3 0x0498 634#define BGE_RX_BD_RULES_MASKVAL3 0x049C 635#define BGE_RX_BD_RULES_CTL4 0x04A0 636#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 637#define BGE_RX_BD_RULES_CTL5 0x04A8 638#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 639#define BGE_RX_BD_RULES_CTL6 0x04B0 640#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 641#define BGE_RX_BD_RULES_CTL7 0x04B8 642#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 643#define BGE_RX_BD_RULES_CTL8 0x04C0 644#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 645#define BGE_RX_BD_RULES_CTL9 0x04C8 646#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 647#define BGE_RX_BD_RULES_CTL10 0x04D0 648#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 649#define BGE_RX_BD_RULES_CTL11 0x04D8 650#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 651#define BGE_RX_BD_RULES_CTL12 0x04E0 652#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 653#define BGE_RX_BD_RULES_CTL13 0x04E8 654#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 655#define BGE_RX_BD_RULES_CTL14 0x04F0 656#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 657#define BGE_RX_BD_RULES_CTL15 0x04F8 658#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 659#define BGE_RX_RULES_CFG 0x0500 660#define BGE_MAX_RX_FRAME_LOWAT 0x0504 661#define BGE_SERDES_CFG 0x0590 662#define BGE_SERDES_STS 0x0594 663#define BGE_SGDIG_CFG 0x05B0 664#define BGE_SGDIG_STS 0x05B4 665#define BGE_TX_MAC_STATS_OCTETS 0x0800 666#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 667#define BGE_TX_MAC_STATS_COLLS 0x0808 668#define BGE_TX_MAC_STATS_XON_SENT 0x080C 669#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 670#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 671#define BGE_TX_MAC_STATS_ERRORS 0x0818 672#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 673#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 674#define BGE_TX_MAC_STATS_DEFERRED 0x0824 675#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 676#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 677#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 678#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 679#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 680#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 681#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 682#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 683#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 684#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 685#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 686#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 687#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 688#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 689#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 690#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 691#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 692#define BGE_TX_MAC_STATS_UCAST 0x086C 693#define BGE_TX_MAC_STATS_MCAST 0x0870 694#define BGE_TX_MAC_STATS_BCAST 0x0874 695#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 696#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 697#define BGE_RX_MAC_STATS_OCTESTS 0x0880 698#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 699#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 700#define BGE_RX_MAC_STATS_UCAST 0x088C 701#define BGE_RX_MAC_STATS_MCAST 0x0890 702#define BGE_RX_MAC_STATS_BCAST 0x0894 703#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 704#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 705#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 706#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 707#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 708#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 709#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 710#define BGE_RX_MAC_STATS_JABBERS 0x08B4 711#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 712 713/* Ethernet MAC Mode register */ 714#define BGE_MACMODE_RESET 0x00000001 715#define BGE_MACMODE_HALF_DUPLEX 0x00000002 716#define BGE_MACMODE_PORTMODE 0x0000000C 717#define BGE_MACMODE_LOOPBACK 0x00000010 718#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 719#define BGE_MACMODE_TX_BURST_ENB 0x00000100 720#define BGE_MACMODE_MAX_DEFER 0x00000200 721#define BGE_MACMODE_LINK_POLARITY 0x00000400 722#define BGE_MACMODE_RX_STATS_ENB 0x00000800 723#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 724#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 725#define BGE_MACMODE_TX_STATS_ENB 0x00004000 726#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 727#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 728#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 729#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 730#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 731#define BGE_MACMODE_MIP_ENB 0x00100000 732#define BGE_MACMODE_TXDMA_ENB 0x00200000 733#define BGE_MACMODE_RXDMA_ENB 0x00400000 734#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 735 736#define BGE_PORTMODE_NONE 0x00000000 737#define BGE_PORTMODE_MII 0x00000004 738#define BGE_PORTMODE_GMII 0x00000008 739#define BGE_PORTMODE_TBI 0x0000000C 740 741/* MAC Status register */ 742#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 743#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 744#define BGE_MACSTAT_RX_CFG 0x00000004 745#define BGE_MACSTAT_CFG_CHANGED 0x00000008 746#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 747#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 748#define BGE_MACSTAT_LINK_CHANGED 0x00001000 749#define BGE_MACSTAT_MI_COMPLETE 0x00400000 750#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 751#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 752#define BGE_MACSTAT_ODI_ERROR 0x02000000 753#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 754#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 755 756/* MAC Event Enable Register */ 757#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 758#define BGE_EVTENB_LINK_CHANGED 0x00001000 759#define BGE_EVTENB_MI_COMPLETE 0x00400000 760#define BGE_EVTENB_MI_INTERRUPT 0x00800000 761#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 762#define BGE_EVTENB_ODI_ERROR 0x02000000 763#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 764#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 765 766/* LED Control Register */ 767#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 768#define BGE_LEDCTL_1000MBPS_LED 0x00000002 769#define BGE_LEDCTL_100MBPS_LED 0x00000004 770#define BGE_LEDCTL_10MBPS_LED 0x00000008 771#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 772#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 773#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 774#define BGE_LEDCTL_1000MBPS_STS 0x00000080 775#define BGE_LEDCTL_100MBPS_STS 0x00000100 776#define BGE_LEDCTL_10MBPS_STS 0x00000200 777#define BGE_LEDCTL_TRADLED_STS 0x00000400 778#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 779#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 780 781/* TX backoff seed register */ 782#define BGE_TX_BACKOFF_SEED_MASK 0x3F 783 784/* Autopoll status register */ 785#define BGE_AUTOPOLLSTS_ERROR 0x00000001 786 787/* Transmit MAC mode register */ 788#define BGE_TXMODE_RESET 0x00000001 789#define BGE_TXMODE_ENABLE 0x00000002 790#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 791#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 792#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 793#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 794 795/* Transmit MAC status register */ 796#define BGE_TXSTAT_RX_XOFFED 0x00000001 797#define BGE_TXSTAT_SENT_XOFF 0x00000002 798#define BGE_TXSTAT_SENT_XON 0x00000004 799#define BGE_TXSTAT_LINK_UP 0x00000008 800#define BGE_TXSTAT_ODI_UFLOW 0x00000010 801#define BGE_TXSTAT_ODI_OFLOW 0x00000020 802 803/* Transmit MAC lengths register */ 804#define BGE_TXLEN_SLOTTIME 0x000000FF 805#define BGE_TXLEN_IPG 0x00000F00 806#define BGE_TXLEN_CRS 0x00003000 807 808/* Receive MAC mode register */ 809#define BGE_RXMODE_RESET 0x00000001 810#define BGE_RXMODE_ENABLE 0x00000002 811#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 812#define BGE_RXMODE_RX_GIANTS 0x00000020 813#define BGE_RXMODE_RX_RUNTS 0x00000040 814#define BGE_RXMODE_8022_LENCHECK 0x00000080 815#define BGE_RXMODE_RX_PROMISC 0x00000100 816#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 817#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 818 819/* Receive MAC status register */ 820#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 821#define BGE_RXSTAT_RCVD_XOFF 0x00000002 822#define BGE_RXSTAT_RCVD_XON 0x00000004 823 824/* Receive Rules Control register */ 825#define BGE_RXRULECTL_OFFSET 0x000000FF 826#define BGE_RXRULECTL_CLASS 0x00001F00 827#define BGE_RXRULECTL_HDRTYPE 0x0000E000 828#define BGE_RXRULECTL_COMPARE_OP 0x00030000 829#define BGE_RXRULECTL_MAP 0x01000000 830#define BGE_RXRULECTL_DISCARD 0x02000000 831#define BGE_RXRULECTL_MASK 0x04000000 832#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 833#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 834#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 835#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 836 837/* Receive Rules Mask register */ 838#define BGE_RXRULEMASK_VALUE 0x0000FFFF 839#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 840 841/* SERDES configuration register */ 842#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 843#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 844#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 845#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 846#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 847#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 848#define BGE_SERDESCFG_TXMODE 0x00001000 849#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 850#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 851#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 852#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 853#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 854#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 855#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 856#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 857#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 858 859/* SERDES status register */ 860#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 861#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 862 863/* SGDIG config (not documented) */ 864#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 865#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 866#define BGE_SGDIGCFG_SEND 0x40000000 867#define BGE_SGDIGCFG_AUTO 0x80000000 868 869/* SGDIG status (not documented) */ 870#define BGE_SGDIGSTS_DONE 0x00000002 871#define BGE_SGDIGSTS_IS_SERDES 0x00000100 872#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 873#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 874 875 876/* MI communication register */ 877#define BGE_MICOMM_DATA 0x0000FFFF 878#define BGE_MICOMM_REG 0x001F0000 879#define BGE_MICOMM_PHY 0x03E00000 880#define BGE_MICOMM_CMD 0x0C000000 881#define BGE_MICOMM_READFAIL 0x10000000 882#define BGE_MICOMM_BUSY 0x20000000 883 884#define BGE_MIREG(x) ((x & 0x1F) << 16) 885#define BGE_MIPHY(x) ((x & 0x1F) << 21) 886#define BGE_MICMD_WRITE 0x04000000 887#define BGE_MICMD_READ 0x08000000 888 889/* MI status register */ 890#define BGE_MISTS_LINK 0x00000001 891#define BGE_MISTS_10MBPS 0x00000002 892 893#define BGE_MIMODE_CLK_10MHZ 0x00000001 894#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 895#define BGE_MIMODE_AUTOPOLL 0x00000010 896#define BGE_MIMODE_CLKCNT 0x001F0000 897#define BGE_MIMODE_500KHZ_CONST 0x00008000 898#define BGE_MIMODE_BASE 0x000C0000 899 900 901/* 902 * Send data initiator control registers. 903 */ 904#define BGE_SDI_MODE 0x0C00 905#define BGE_SDI_STATUS 0x0C04 906#define BGE_SDI_STATS_CTL 0x0C08 907#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 908#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 909#define BGE_ISO_PKT_TX 0x0C20 910#define BGE_LOCSTATS_COS0 0x0C80 911#define BGE_LOCSTATS_COS1 0x0C84 912#define BGE_LOCSTATS_COS2 0x0C88 913#define BGE_LOCSTATS_COS3 0x0C8C 914#define BGE_LOCSTATS_COS4 0x0C90 915#define BGE_LOCSTATS_COS5 0x0C84 916#define BGE_LOCSTATS_COS6 0x0C98 917#define BGE_LOCSTATS_COS7 0x0C9C 918#define BGE_LOCSTATS_COS8 0x0CA0 919#define BGE_LOCSTATS_COS9 0x0CA4 920#define BGE_LOCSTATS_COS10 0x0CA8 921#define BGE_LOCSTATS_COS11 0x0CAC 922#define BGE_LOCSTATS_COS12 0x0CB0 923#define BGE_LOCSTATS_COS13 0x0CB4 924#define BGE_LOCSTATS_COS14 0x0CB8 925#define BGE_LOCSTATS_COS15 0x0CBC 926#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 927#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 928#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 929#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 930#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 931#define BGE_LOCSTATS_IRQS 0x0CD4 932#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 933#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 934 935/* Send Data Initiator mode register */ 936#define BGE_SDIMODE_RESET 0x00000001 937#define BGE_SDIMODE_ENABLE 0x00000002 938#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 939#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 940 941/* Send Data Initiator stats register */ 942#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 943 944/* Send Data Initiator stats control register */ 945#define BGE_SDISTATSCTL_ENABLE 0x00000001 946#define BGE_SDISTATSCTL_FASTER 0x00000002 947#define BGE_SDISTATSCTL_CLEAR 0x00000004 948#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 949#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 950 951/* 952 * Send Data Completion Control registers 953 */ 954#define BGE_SDC_MODE 0x1000 955#define BGE_SDC_STATUS 0x1004 956 957/* Send Data completion mode register */ 958#define BGE_SDCMODE_RESET 0x00000001 959#define BGE_SDCMODE_ENABLE 0x00000002 960#define BGE_SDCMODE_ATTN 0x00000004 961#define BGE_SDCMODE_CDELAY 0x00000010 962 963/* Send Data completion status register */ 964#define BGE_SDCSTAT_ATTN 0x00000004 965 966/* 967 * Send BD Ring Selector Control registers 968 */ 969#define BGE_SRS_MODE 0x1400 970#define BGE_SRS_STATUS 0x1404 971#define BGE_SRS_HWDIAG 0x1408 972#define BGE_SRS_LOC_NIC_CONS0 0x1440 973#define BGE_SRS_LOC_NIC_CONS1 0x1444 974#define BGE_SRS_LOC_NIC_CONS2 0x1448 975#define BGE_SRS_LOC_NIC_CONS3 0x144C 976#define BGE_SRS_LOC_NIC_CONS4 0x1450 977#define BGE_SRS_LOC_NIC_CONS5 0x1454 978#define BGE_SRS_LOC_NIC_CONS6 0x1458 979#define BGE_SRS_LOC_NIC_CONS7 0x145C 980#define BGE_SRS_LOC_NIC_CONS8 0x1460 981#define BGE_SRS_LOC_NIC_CONS9 0x1464 982#define BGE_SRS_LOC_NIC_CONS10 0x1468 983#define BGE_SRS_LOC_NIC_CONS11 0x146C 984#define BGE_SRS_LOC_NIC_CONS12 0x1470 985#define BGE_SRS_LOC_NIC_CONS13 0x1474 986#define BGE_SRS_LOC_NIC_CONS14 0x1478 987#define BGE_SRS_LOC_NIC_CONS15 0x147C 988 989/* Send BD Ring Selector Mode register */ 990#define BGE_SRSMODE_RESET 0x00000001 991#define BGE_SRSMODE_ENABLE 0x00000002 992#define BGE_SRSMODE_ATTN 0x00000004 993 994/* Send BD Ring Selector Status register */ 995#define BGE_SRSSTAT_ERROR 0x00000004 996 997/* Send BD Ring Selector HW Diagnostics register */ 998#define BGE_SRSHWDIAG_STATE 0x0000000F 999#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1000#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1001#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 1002 1003/* 1004 * Send BD Initiator Selector Control registers 1005 */ 1006#define BGE_SBDI_MODE 0x1800 1007#define BGE_SBDI_STATUS 0x1804 1008#define BGE_SBDI_LOC_NIC_PROD0 0x1808 1009#define BGE_SBDI_LOC_NIC_PROD1 0x180C 1010#define BGE_SBDI_LOC_NIC_PROD2 0x1810 1011#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1012#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1013#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1014#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1015#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1016#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1017#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1018#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1019#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1020#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1021#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1022#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1023#define BGE_SBDI_LOC_NIC_PROD15 0x1844 1024 1025/* Send BD Initiator Mode register */ 1026#define BGE_SBDIMODE_RESET 0x00000001 1027#define BGE_SBDIMODE_ENABLE 0x00000002 1028#define BGE_SBDIMODE_ATTN 0x00000004 1029 1030/* Send BD Initiator Status register */ 1031#define BGE_SBDISTAT_ERROR 0x00000004 1032 1033/* 1034 * Send BD Completion Control registers 1035 */ 1036#define BGE_SBDC_MODE 0x1C00 1037#define BGE_SBDC_STATUS 0x1C04 1038 1039/* Send BD Completion Control Mode register */ 1040#define BGE_SBDCMODE_RESET 0x00000001 1041#define BGE_SBDCMODE_ENABLE 0x00000002 1042#define BGE_SBDCMODE_ATTN 0x00000004 1043 1044/* Send BD Completion Control Status register */ 1045#define BGE_SBDCSTAT_ATTN 0x00000004 1046 1047/* 1048 * Receive List Placement Control registers 1049 */ 1050#define BGE_RXLP_MODE 0x2000 1051#define BGE_RXLP_STATUS 0x2004 1052#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1053#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1054#define BGE_RXLP_CFG 0x2010 1055#define BGE_RXLP_STATS_CTL 0x2014 1056#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1057#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1058#define BGE_RXLP_HEAD0 0x2100 1059#define BGE_RXLP_TAIL0 0x2104 1060#define BGE_RXLP_COUNT0 0x2108 1061#define BGE_RXLP_HEAD1 0x2110 1062#define BGE_RXLP_TAIL1 0x2114 1063#define BGE_RXLP_COUNT1 0x2118 1064#define BGE_RXLP_HEAD2 0x2120 1065#define BGE_RXLP_TAIL2 0x2124 1066#define BGE_RXLP_COUNT2 0x2128 1067#define BGE_RXLP_HEAD3 0x2130 1068#define BGE_RXLP_TAIL3 0x2134 1069#define BGE_RXLP_COUNT3 0x2138 1070#define BGE_RXLP_HEAD4 0x2140 1071#define BGE_RXLP_TAIL4 0x2144 1072#define BGE_RXLP_COUNT4 0x2148 1073#define BGE_RXLP_HEAD5 0x2150 1074#define BGE_RXLP_TAIL5 0x2154 1075#define BGE_RXLP_COUNT5 0x2158 1076#define BGE_RXLP_HEAD6 0x2160 1077#define BGE_RXLP_TAIL6 0x2164 1078#define BGE_RXLP_COUNT6 0x2168 1079#define BGE_RXLP_HEAD7 0x2170 1080#define BGE_RXLP_TAIL7 0x2174 1081#define BGE_RXLP_COUNT7 0x2178 1082#define BGE_RXLP_HEAD8 0x2180 1083#define BGE_RXLP_TAIL8 0x2184 1084#define BGE_RXLP_COUNT8 0x2188 1085#define BGE_RXLP_HEAD9 0x2190 1086#define BGE_RXLP_TAIL9 0x2194 1087#define BGE_RXLP_COUNT9 0x2198 1088#define BGE_RXLP_HEAD10 0x21A0 1089#define BGE_RXLP_TAIL10 0x21A4 1090#define BGE_RXLP_COUNT10 0x21A8 1091#define BGE_RXLP_HEAD11 0x21B0 1092#define BGE_RXLP_TAIL11 0x21B4 1093#define BGE_RXLP_COUNT11 0x21B8 1094#define BGE_RXLP_HEAD12 0x21C0 1095#define BGE_RXLP_TAIL12 0x21C4 1096#define BGE_RXLP_COUNT12 0x21C8 1097#define BGE_RXLP_HEAD13 0x21D0 1098#define BGE_RXLP_TAIL13 0x21D4 1099#define BGE_RXLP_COUNT13 0x21D8 1100#define BGE_RXLP_HEAD14 0x21E0 1101#define BGE_RXLP_TAIL14 0x21E4 1102#define BGE_RXLP_COUNT14 0x21E8 1103#define BGE_RXLP_HEAD15 0x21F0 1104#define BGE_RXLP_TAIL15 0x21F4 1105#define BGE_RXLP_COUNT15 0x21F8 1106#define BGE_RXLP_LOCSTAT_COS0 0x2200 1107#define BGE_RXLP_LOCSTAT_COS1 0x2204 1108#define BGE_RXLP_LOCSTAT_COS2 0x2208 1109#define BGE_RXLP_LOCSTAT_COS3 0x220C 1110#define BGE_RXLP_LOCSTAT_COS4 0x2210 1111#define BGE_RXLP_LOCSTAT_COS5 0x2214 1112#define BGE_RXLP_LOCSTAT_COS6 0x2218 1113#define BGE_RXLP_LOCSTAT_COS7 0x221C 1114#define BGE_RXLP_LOCSTAT_COS8 0x2220 1115#define BGE_RXLP_LOCSTAT_COS9 0x2224 1116#define BGE_RXLP_LOCSTAT_COS10 0x2228 1117#define BGE_RXLP_LOCSTAT_COS11 0x222C 1118#define BGE_RXLP_LOCSTAT_COS12 0x2230 1119#define BGE_RXLP_LOCSTAT_COS13 0x2234 1120#define BGE_RXLP_LOCSTAT_COS14 0x2238 1121#define BGE_RXLP_LOCSTAT_COS15 0x223C 1122#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1123#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1124#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1125#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1126#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1127#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1128#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1129 1130 1131/* Receive List Placement mode register */ 1132#define BGE_RXLPMODE_RESET 0x00000001 1133#define BGE_RXLPMODE_ENABLE 0x00000002 1134#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1135#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1136#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1137 1138/* Receive List Placement Status register */ 1139#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1140#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1141#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1142 1143/* 1144 * Receive Data and Receive BD Initiator Control Registers 1145 */ 1146#define BGE_RDBDI_MODE 0x2400 1147#define BGE_RDBDI_STATUS 0x2404 1148#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1149#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1150#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1151#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1152#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1153#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1154#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1155#define BGE_RX_STD_RCB_NICADDR 0x245C 1156#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1157#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1158#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1159#define BGE_RX_MINI_RCB_NICADDR 0x246C 1160#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1161#define BGE_RDBDI_STD_RX_CONS 0x2474 1162#define BGE_RDBDI_MINI_RX_CONS 0x2478 1163#define BGE_RDBDI_RETURN_PROD0 0x2480 1164#define BGE_RDBDI_RETURN_PROD1 0x2484 1165#define BGE_RDBDI_RETURN_PROD2 0x2488 1166#define BGE_RDBDI_RETURN_PROD3 0x248C 1167#define BGE_RDBDI_RETURN_PROD4 0x2490 1168#define BGE_RDBDI_RETURN_PROD5 0x2494 1169#define BGE_RDBDI_RETURN_PROD6 0x2498 1170#define BGE_RDBDI_RETURN_PROD7 0x249C 1171#define BGE_RDBDI_RETURN_PROD8 0x24A0 1172#define BGE_RDBDI_RETURN_PROD9 0x24A4 1173#define BGE_RDBDI_RETURN_PROD10 0x24A8 1174#define BGE_RDBDI_RETURN_PROD11 0x24AC 1175#define BGE_RDBDI_RETURN_PROD12 0x24B0 1176#define BGE_RDBDI_RETURN_PROD13 0x24B4 1177#define BGE_RDBDI_RETURN_PROD14 0x24B8 1178#define BGE_RDBDI_RETURN_PROD15 0x24BC 1179#define BGE_RDBDI_HWDIAG 0x24C0 1180 1181 1182/* Receive Data and Receive BD Initiator Mode register */ 1183#define BGE_RDBDIMODE_RESET 0x00000001 1184#define BGE_RDBDIMODE_ENABLE 0x00000002 1185#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1186#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1187#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1188 1189/* Receive Data and Receive BD Initiator Status register */ 1190#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1191#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1192#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1193 1194 1195/* 1196 * Receive Data Completion Control registers 1197 */ 1198#define BGE_RDC_MODE 0x2800 1199 1200/* Receive Data Completion Mode register */ 1201#define BGE_RDCMODE_RESET 0x00000001 1202#define BGE_RDCMODE_ENABLE 0x00000002 1203#define BGE_RDCMODE_ATTN 0x00000004 1204 1205/* 1206 * Receive BD Initiator Control registers 1207 */ 1208#define BGE_RBDI_MODE 0x2C00 1209#define BGE_RBDI_STATUS 0x2C04 1210#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1211#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1212#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1213#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1214#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1215#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1216 1217#define BGE_STD_REPLENISH_LWM 0x2D00 1218#define BGE_JMB_REPLENISH_LWM 0x2D04 1219 1220/* Receive BD Initiator Mode register */ 1221#define BGE_RBDIMODE_RESET 0x00000001 1222#define BGE_RBDIMODE_ENABLE 0x00000002 1223#define BGE_RBDIMODE_ATTN 0x00000004 1224 1225/* Receive BD Initiator Status register */ 1226#define BGE_RBDISTAT_ATTN 0x00000004 1227 1228/* 1229 * Receive BD Completion Control registers 1230 */ 1231#define BGE_RBDC_MODE 0x3000 1232#define BGE_RBDC_STATUS 0x3004 1233#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1234#define BGE_RBDC_STD_BD_PROD 0x300C 1235#define BGE_RBDC_MINI_BD_PROD 0x3010 1236 1237/* Receive BD completion mode register */ 1238#define BGE_RBDCMODE_RESET 0x00000001 1239#define BGE_RBDCMODE_ENABLE 0x00000002 1240#define BGE_RBDCMODE_ATTN 0x00000004 1241 1242/* Receive BD completion status register */ 1243#define BGE_RBDCSTAT_ERROR 0x00000004 1244 1245/* 1246 * Receive List Selector Control registers 1247 */ 1248#define BGE_RXLS_MODE 0x3400 1249#define BGE_RXLS_STATUS 0x3404 1250 1251/* Receive List Selector Mode register */ 1252#define BGE_RXLSMODE_RESET 0x00000001 1253#define BGE_RXLSMODE_ENABLE 0x00000002 1254#define BGE_RXLSMODE_ATTN 0x00000004 1255 1256/* Receive List Selector Status register */ 1257#define BGE_RXLSSTAT_ERROR 0x00000004 1258 1259#define BGE_CPMU_CTRL 0x3600 1260#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1261#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1262#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1263#define BGE_CPMU_HST_ACC 0x361C 1264#define BGE_CPMU_CLCK_STAT 0x3630 1265#define BGE_CPMU_MUTEX_REQ 0x365C 1266#define BGE_CPMU_MUTEX_GNT 0x3660 1267#define BGE_CPMU_PHY_STRAP 0x3664 1268 1269/* Central Power Management Unit (CPMU) register */ 1270#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1271#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1272#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1273#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1274 1275/* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1276#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1277#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1278 1279/* Link Speed 1000MB Power Mode Clock Policy register */ 1280#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1281#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1282#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1283 1284/* Link Aware Power Mode Clock Policy register */ 1285#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1286#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1287 1288#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1289#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1290 1291/* CPMU Clock Status register */ 1292#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1293#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1294#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1295#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1296 1297/* CPMU Mutex Request register */ 1298#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1299#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1300 1301/* CPMU GPHY Strap register */ 1302#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1303 1304/* 1305 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1306 */ 1307#define BGE_MBCF_MODE 0x3800 1308#define BGE_MBCF_STATUS 0x3804 1309 1310/* Mbuf Cluster Free mode register */ 1311#define BGE_MBCFMODE_RESET 0x00000001 1312#define BGE_MBCFMODE_ENABLE 0x00000002 1313#define BGE_MBCFMODE_ATTN 0x00000004 1314 1315/* Mbuf Cluster Free status register */ 1316#define BGE_MBCFSTAT_ERROR 0x00000004 1317 1318/* 1319 * Host Coalescing Control registers 1320 */ 1321#define BGE_HCC_MODE 0x3C00 1322#define BGE_HCC_STATUS 0x3C04 1323#define BGE_HCC_RX_COAL_TICKS 0x3C08 1324#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1325#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1326#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1327#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1328#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1329#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1330#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1331#define BGE_HCC_STATS_TICKS 0x3C28 1332#define BGE_HCC_STATS_ADDR_HI 0x3C30 1333#define BGE_HCC_STATS_ADDR_LO 0x3C34 1334#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1335#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1336#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1337#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1338#define BGE_FLOW_ATTN 0x3C48 1339#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1340#define BGE_HCC_STD_BD_CONS 0x3C54 1341#define BGE_HCC_MINI_BD_CONS 0x3C58 1342#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1343#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1344#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1345#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1346#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1347#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1348#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1349#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1350#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1351#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1352#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1353#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1354#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1355#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1356#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1357#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1358#define BGE_HCC_TX_BD_CONS0 0x3CC0 1359#define BGE_HCC_TX_BD_CONS1 0x3CC4 1360#define BGE_HCC_TX_BD_CONS2 0x3CC8 1361#define BGE_HCC_TX_BD_CONS3 0x3CCC 1362#define BGE_HCC_TX_BD_CONS4 0x3CD0 1363#define BGE_HCC_TX_BD_CONS5 0x3CD4 1364#define BGE_HCC_TX_BD_CONS6 0x3CD8 1365#define BGE_HCC_TX_BD_CONS7 0x3CDC 1366#define BGE_HCC_TX_BD_CONS8 0x3CE0 1367#define BGE_HCC_TX_BD_CONS9 0x3CE4 1368#define BGE_HCC_TX_BD_CONS10 0x3CE8 1369#define BGE_HCC_TX_BD_CONS11 0x3CEC 1370#define BGE_HCC_TX_BD_CONS12 0x3CF0 1371#define BGE_HCC_TX_BD_CONS13 0x3CF4 1372#define BGE_HCC_TX_BD_CONS14 0x3CF8 1373#define BGE_HCC_TX_BD_CONS15 0x3CFC 1374 1375 1376/* Host coalescing mode register */ 1377#define BGE_HCCMODE_RESET 0x00000001 1378#define BGE_HCCMODE_ENABLE 0x00000002 1379#define BGE_HCCMODE_ATTN 0x00000004 1380#define BGE_HCCMODE_COAL_NOW 0x00000008 1381#define BGE_HCCMODE_MSI_BITS 0x00000070 1382#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1383 1384#define BGE_STATBLKSZ_FULL 0x00000000 1385#define BGE_STATBLKSZ_64BYTE 0x00000080 1386#define BGE_STATBLKSZ_32BYTE 0x00000100 1387 1388/* Host coalescing status register */ 1389#define BGE_HCCSTAT_ERROR 0x00000004 1390 1391/* Flow attention register */ 1392#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1393#define BGE_FLOWATTN_MEMARB 0x00000080 1394#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1395#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1396#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1397#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1398#define BGE_FLOWATTN_RDBDI 0x00080000 1399#define BGE_FLOWATTN_RXLS 0x00100000 1400#define BGE_FLOWATTN_RXLP 0x00200000 1401#define BGE_FLOWATTN_RBDC 0x00400000 1402#define BGE_FLOWATTN_RBDI 0x00800000 1403#define BGE_FLOWATTN_SDC 0x08000000 1404#define BGE_FLOWATTN_SDI 0x10000000 1405#define BGE_FLOWATTN_SRS 0x20000000 1406#define BGE_FLOWATTN_SBDC 0x40000000 1407#define BGE_FLOWATTN_SBDI 0x80000000 1408 1409/* 1410 * Memory arbiter registers 1411 */ 1412#define BGE_MARB_MODE 0x4000 1413#define BGE_MARB_STATUS 0x4004 1414#define BGE_MARB_TRAPADDR_HI 0x4008 1415#define BGE_MARB_TRAPADDR_LO 0x400C 1416 1417/* Memory arbiter mode register */ 1418#define BGE_MARBMODE_RESET 0x00000001 1419#define BGE_MARBMODE_ENABLE 0x00000002 1420#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1421#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1422#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1423#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1424#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1425#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1426#define BGE_MARBMODE_PCI_TRAP 0x00000100 1427#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1428#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1429#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1430#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1431#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1432#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1433#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1434#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1435#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1436#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1437#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1438#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1439#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1440#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1441#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1442#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1443#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1444 1445/* Memory arbiter status register */ 1446#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1447#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1448#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1449#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1450#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1451#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1452#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1453#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1454#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1455#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1456#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1457#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1458#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1459#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1460#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1461#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1462#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1463#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1464#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1465#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1466#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1467#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1468#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1469#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1470 1471/* 1472 * Buffer manager control registers 1473 */ 1474#define BGE_BMAN_MODE 0x4400 1475#define BGE_BMAN_STATUS 0x4404 1476#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1477#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1478#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1479#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1480#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1481#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1482#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1483#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1484#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1485#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1486#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1487#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1488#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1489#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1490#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1491#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1492#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1493#define BGE_BMAN_HWDIAG_1 0x444C 1494#define BGE_BMAN_HWDIAG_2 0x4450 1495#define BGE_BMAN_HWDIAG_3 0x4454 1496 1497/* Buffer manager mode register */ 1498#define BGE_BMANMODE_RESET 0x00000001 1499#define BGE_BMANMODE_ENABLE 0x00000002 1500#define BGE_BMANMODE_ATTN 0x00000004 1501#define BGE_BMANMODE_TESTMODE 0x00000008 1502#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1503#define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 1504 1505/* Buffer manager status register */ 1506#define BGE_BMANSTAT_ERRO 0x00000004 1507#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1508 1509 1510/* 1511 * Read DMA Control registers 1512 */ 1513#define BGE_RDMA_MODE 0x4800 1514#define BGE_RDMA_STATUS 0x4804 1515#define BGE_RDMA_RSRVCTRL 0x4900 1516#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 1517 1518/* Read DMA mode register */ 1519#define BGE_RDMAMODE_RESET 0x00000001 1520#define BGE_RDMAMODE_ENABLE 0x00000002 1521#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1522#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1523#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1524#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1525#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1526#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1527#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1528#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1529#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1530#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1531#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1532#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1533#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1534#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1535#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1536#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1537#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1538 1539/* Read DMA status register */ 1540#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1541#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1542#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1543#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1544#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1545#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1546#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1547#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1548 1549/* Read DMA Reserved Control register */ 1550#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1551#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1552#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1553#define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1554#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1555#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1556#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1557 1558#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1559#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1560 1561/* 1562 * Write DMA control registers 1563 */ 1564#define BGE_WDMA_MODE 0x4C00 1565#define BGE_WDMA_STATUS 0x4C04 1566 1567/* Write DMA mode register */ 1568#define BGE_WDMAMODE_RESET 0x00000001 1569#define BGE_WDMAMODE_ENABLE 0x00000002 1570#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1571#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1572#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1573#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1574#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1575#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1576#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1577#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1578#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1579#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1580#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1581 1582/* Write DMA status register */ 1583#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1584#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1585#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1586#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1587#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1588#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1589#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1590#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1591 1592 1593/* 1594 * RX CPU registers 1595 */ 1596#define BGE_RXCPU_MODE 0x5000 1597#define BGE_RXCPU_STATUS 0x5004 1598#define BGE_RXCPU_PC 0x501C 1599 1600/* RX CPU mode register */ 1601#define BGE_RXCPUMODE_RESET 0x00000001 1602#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1603#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1604#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1605#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1606#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1607#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1608#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1609#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1610#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1611#define BGE_RXCPUMODE_HALTCPU 0x00000400 1612#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1613#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1614#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1615 1616/* RX CPU status register */ 1617#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1618#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1619#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1620#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1621#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1622#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1623#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1624#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1625#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1626#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1627#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1628#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1629#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1630#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1631#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1632#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1633#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1634 1635/* 1636 * V? CPU registers 1637 */ 1638#define BGE_VCPU_STATUS 0x5100 1639#define BGE_VCPU_EXT_CTRL 0x6890 1640 1641#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1642#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1643 1644#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1645#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1646 1647/* 1648 * TX CPU registers 1649 */ 1650#define BGE_TXCPU_MODE 0x5400 1651#define BGE_TXCPU_STATUS 0x5404 1652#define BGE_TXCPU_PC 0x541C 1653 1654/* TX CPU mode register */ 1655#define BGE_TXCPUMODE_RESET 0x00000001 1656#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1657#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1658#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1659#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1660#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1661#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1662#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1663#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1664#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1665#define BGE_TXCPUMODE_HALTCPU 0x00000400 1666#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1667#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1668 1669/* TX CPU status register */ 1670#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1671#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1672#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1673#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1674#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1675#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1676#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1677#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1678#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1679#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1680#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1681#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1682#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1683#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1684#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1685#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1686#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1687 1688 1689/* 1690 * Low priority mailbox registers 1691 */ 1692#define BGE_LPMBX_IRQ0_HI 0x5800 1693#define BGE_LPMBX_IRQ0_LO 0x5804 1694#define BGE_LPMBX_IRQ1_HI 0x5808 1695#define BGE_LPMBX_IRQ1_LO 0x580C 1696#define BGE_LPMBX_IRQ2_HI 0x5810 1697#define BGE_LPMBX_IRQ2_LO 0x5814 1698#define BGE_LPMBX_IRQ3_HI 0x5818 1699#define BGE_LPMBX_IRQ3_LO 0x581C 1700#define BGE_LPMBX_GEN0_HI 0x5820 1701#define BGE_LPMBX_GEN0_LO 0x5824 1702#define BGE_LPMBX_GEN1_HI 0x5828 1703#define BGE_LPMBX_GEN1_LO 0x582C 1704#define BGE_LPMBX_GEN2_HI 0x5830 1705#define BGE_LPMBX_GEN2_LO 0x5834 1706#define BGE_LPMBX_GEN3_HI 0x5828 1707#define BGE_LPMBX_GEN3_LO 0x582C 1708#define BGE_LPMBX_GEN4_HI 0x5840 1709#define BGE_LPMBX_GEN4_LO 0x5844 1710#define BGE_LPMBX_GEN5_HI 0x5848 1711#define BGE_LPMBX_GEN5_LO 0x584C 1712#define BGE_LPMBX_GEN6_HI 0x5850 1713#define BGE_LPMBX_GEN6_LO 0x5854 1714#define BGE_LPMBX_GEN7_HI 0x5858 1715#define BGE_LPMBX_GEN7_LO 0x585C 1716#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1717#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1718#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1719#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1720#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1721#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1722#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1723#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1724#define BGE_LPMBX_RX_CONS0_HI 0x5880 1725#define BGE_LPMBX_RX_CONS0_LO 0x5884 1726#define BGE_LPMBX_RX_CONS1_HI 0x5888 1727#define BGE_LPMBX_RX_CONS1_LO 0x588C 1728#define BGE_LPMBX_RX_CONS2_HI 0x5890 1729#define BGE_LPMBX_RX_CONS2_LO 0x5894 1730#define BGE_LPMBX_RX_CONS3_HI 0x5898 1731#define BGE_LPMBX_RX_CONS3_LO 0x589C 1732#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1733#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1734#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1735#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1736#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1737#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1738#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1739#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1740#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1741#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1742#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1743#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1744#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1745#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1746#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1747#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1748#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1749#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1750#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1751#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1752#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1753#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1754#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1755#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1756#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1757#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1758#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1759#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1760#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1761#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1762#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1763#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1764#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1765#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1766#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1767#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1768#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1769#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1770#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1771#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1772#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1773#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1774#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1775#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1776#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1777#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1778#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1779#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1780#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1781#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1782#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1783#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1784#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1785#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1786#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1787#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1788#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1789#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1790#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1791#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1792#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1793#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1794#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1795#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1796#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1797#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1798#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1799#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1800#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1801#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1802#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1803#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1804#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1805#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1806#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1807#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1808#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1809#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1810#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1811#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1812#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1813#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1814#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1815#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1816#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1817#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1818#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1819#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1820 1821/* 1822 * Flow throw Queue reset register 1823 */ 1824#define BGE_FTQ_RESET 0x5C00 1825 1826#define BGE_FTQRESET_DMAREAD 0x00000002 1827#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1828#define BGE_FTQRESET_DMADONE 0x00000010 1829#define BGE_FTQRESET_SBDC 0x00000020 1830#define BGE_FTQRESET_SDI 0x00000040 1831#define BGE_FTQRESET_WDMA 0x00000080 1832#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1833#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1834#define BGE_FTQRESET_SDC 0x00000400 1835#define BGE_FTQRESET_HCC 0x00000800 1836#define BGE_FTQRESET_TXFIFO 0x00001000 1837#define BGE_FTQRESET_MBC 0x00002000 1838#define BGE_FTQRESET_RBDC 0x00004000 1839#define BGE_FTQRESET_RXLP 0x00008000 1840#define BGE_FTQRESET_RDBDI 0x00010000 1841#define BGE_FTQRESET_RDC 0x00020000 1842#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1843 1844/* 1845 * Message Signaled Interrupt registers 1846 */ 1847#define BGE_MSI_MODE 0x6000 1848#define BGE_MSI_STATUS 0x6004 1849#define BGE_MSI_FIFOACCESS 0x6008 1850 1851/* MSI mode register */ 1852#define BGE_MSIMODE_RESET 0x00000001 1853#define BGE_MSIMODE_ENABLE 0x00000002 1854#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1855#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1856 1857/* MSI status register */ 1858#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1859#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1860#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1861#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1862#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1863 1864 1865/* 1866 * DMA Completion registers 1867 */ 1868#define BGE_DMAC_MODE 0x6400 1869 1870/* DMA Completion mode register */ 1871#define BGE_DMACMODE_RESET 0x00000001 1872#define BGE_DMACMODE_ENABLE 0x00000002 1873 1874 1875/* 1876 * General control registers. 1877 */ 1878#define BGE_MODE_CTL 0x6800 1879#define BGE_MISC_CFG 0x6804 1880#define BGE_MISC_LOCAL_CTL 0x6808 1881#define BGE_CPU_EVENT 0x6810 1882#define BGE_EE_ADDR 0x6838 1883#define BGE_EE_DATA 0x683C 1884#define BGE_EE_CTL 0x6840 1885#define BGE_MDI_CTL 0x6844 1886#define BGE_EE_DELAY 0x6848 1887#define BGE_FASTBOOT_PC 0x6894 1888 1889/* 1890 * NVRAM Control registers 1891 */ 1892#define BGE_NVRAM_CMD 0x7000 1893#define BGE_NVRAM_STAT 0x7004 1894#define BGE_NVRAM_WRDATA 0x7008 1895#define BGE_NVRAM_ADDR 0x700c 1896#define BGE_NVRAM_RDDATA 0x7010 1897#define BGE_NVRAM_CFG1 0x7014 1898#define BGE_NVRAM_CFG2 0x7018 1899#define BGE_NVRAM_CFG3 0x701c 1900#define BGE_NVRAM_SWARB 0x7020 1901#define BGE_NVRAM_ACCESS 0x7024 1902#define BGE_NVRAM_WRITE1 0x7028 1903 1904#define BGE_NVRAMCMD_RESET 0x00000001 1905#define BGE_NVRAMCMD_DONE 0x00000008 1906#define BGE_NVRAMCMD_START 0x00000010 1907#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1908#define BGE_NVRAMCMD_ERASE 0x00000040 1909#define BGE_NVRAMCMD_FIRST 0x00000080 1910#define BGE_NVRAMCMD_LAST 0x00000100 1911 1912#define BGE_NVRAM_READCMD \ 1913 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1914 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1915#define BGE_NVRAM_WRITECMD \ 1916 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1917 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1918 1919#define BGE_NVRAMSWARB_SET0 0x00000001 1920#define BGE_NVRAMSWARB_SET1 0x00000002 1921#define BGE_NVRAMSWARB_SET2 0x00000003 1922#define BGE_NVRAMSWARB_SET3 0x00000004 1923#define BGE_NVRAMSWARB_CLR0 0x00000010 1924#define BGE_NVRAMSWARB_CLR1 0x00000020 1925#define BGE_NVRAMSWARB_CLR2 0x00000040 1926#define BGE_NVRAMSWARB_CLR3 0x00000080 1927#define BGE_NVRAMSWARB_GNT0 0x00000100 1928#define BGE_NVRAMSWARB_GNT1 0x00000200 1929#define BGE_NVRAMSWARB_GNT2 0x00000400 1930#define BGE_NVRAMSWARB_GNT3 0x00000800 1931#define BGE_NVRAMSWARB_REQ0 0x00001000 1932#define BGE_NVRAMSWARB_REQ1 0x00002000 1933#define BGE_NVRAMSWARB_REQ2 0x00004000 1934#define BGE_NVRAMSWARB_REQ3 0x00008000 1935 1936#define BGE_NVRAMACC_ENABLE 0x00000001 1937#define BGE_NVRAMACC_WRENABLE 0x00000002 1938 1939/* Mode control register */ 1940#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1941#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1942#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1943#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1944#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1945#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1946#define BGE_MODECTL_NO_RX_CRC 0x00000400 1947#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1948#define BGE_MODECTL_NO_TX_INTR 0x00002000 1949#define BGE_MODECTL_NO_RX_INTR 0x00004000 1950#define BGE_MODECTL_FORCE_PCI32 0x00008000 1951#define BGE_MODECTL_STACKUP 0x00010000 1952#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1953#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1954#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1955#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1956#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1957#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1958#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1959#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1960#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1961#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1962 1963/* Misc. config register */ 1964#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1965#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1966#define BGE_MISCCFG_BOARD_ID 0x0001E000 1967#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1968#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1969#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1970#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 1971 1972#define BGE_32BITTIME_66MHZ (0x41 << 1) 1973 1974/* Misc. Local Control */ 1975#define BGE_MLC_INTR_STATE 0x00000001 1976#define BGE_MLC_INTR_CLR 0x00000002 1977#define BGE_MLC_INTR_SET 0x00000004 1978#define BGE_MLC_INTR_ONATTN 0x00000008 1979#define BGE_MLC_MISCIO_IN0 0x00000100 1980#define BGE_MLC_MISCIO_IN1 0x00000200 1981#define BGE_MLC_MISCIO_IN2 0x00000400 1982#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1983#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1984#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1985#define BGE_MLC_MISCIO_OUT0 0x00004000 1986#define BGE_MLC_MISCIO_OUT1 0x00008000 1987#define BGE_MLC_MISCIO_OUT2 0x00010000 1988#define BGE_MLC_EXTRAM_ENB 0x00020000 1989#define BGE_MLC_SRAM_SIZE 0x001C0000 1990#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1991#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1992#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1993#define BGE_MLC_AUTO_EEPROM 0x01000000 1994 1995#define BGE_SSRAMSIZE_256KB 0x00000000 1996#define BGE_SSRAMSIZE_512KB 0x00040000 1997#define BGE_SSRAMSIZE_1MB 0x00080000 1998#define BGE_SSRAMSIZE_2MB 0x000C0000 1999#define BGE_SSRAMSIZE_4MB 0x00100000 2000#define BGE_SSRAMSIZE_8MB 0x00140000 2001#define BGE_SSRAMSIZE_16M 0x00180000 2002 2003/* EEPROM address register */ 2004#define BGE_EEADDR_ADDRESS 0x0000FFFC 2005#define BGE_EEADDR_HALFCLK 0x01FF0000 2006#define BGE_EEADDR_START 0x02000000 2007#define BGE_EEADDR_DEVID 0x1C000000 2008#define BGE_EEADDR_RESET 0x20000000 2009#define BGE_EEADDR_DONE 0x40000000 2010#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 2011 2012#define BGE_EEDEVID(x) ((x & 7) << 26) 2013#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2014#define BGE_HALFCLK_384SCL 0x60 2015#define BGE_EE_READCMD \ 2016 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2017 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2018#define BGE_EE_WRCMD \ 2019 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2020 BGE_EEADDR_START|BGE_EEADDR_DONE) 2021 2022/* EEPROM Control register */ 2023#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2024#define BGE_EECTL_CLKOUT 0x00000002 2025#define BGE_EECTL_CLKIN 0x00000004 2026#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2027#define BGE_EECTL_DATAOUT 0x00000010 2028#define BGE_EECTL_DATAIN 0x00000020 2029 2030/* MDI (MII/GMII) access register */ 2031#define BGE_MDI_DATA 0x00000001 2032#define BGE_MDI_DIR 0x00000002 2033#define BGE_MDI_SEL 0x00000004 2034#define BGE_MDI_CLK 0x00000008 2035 2036#define BGE_MEMWIN_START 0x00008000 2037#define BGE_MEMWIN_END 0x0000FFFF 2038 2039 2040#define BGE_MEMWIN_READ(sc, x, val) \ 2041 do { \ 2042 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2043 (0xFFFF0000 & x), 4); \ 2044 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2045 } while(0) 2046 2047#define BGE_MEMWIN_WRITE(sc, x, val) \ 2048 do { \ 2049 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2050 (0xFFFF0000 & x), 4); \ 2051 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2052 } while(0) 2053 2054/* 2055 * This magic number is written to the firmware mailbox at 0xb50 2056 * before a software reset is issued. After the internal firmware 2057 * has completed its initialization it will write the opposite of 2058 * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location, 2059 * allowing the driver to synchronize with the firmware. 2060 */ 2061#define BGE_SRAM_FW_MB_MAGIC 0x4B657654 2062 2063typedef struct { 2064 uint32_t bge_addr_hi; 2065 uint32_t bge_addr_lo; 2066} bge_hostaddr; 2067 2068#define BGE_HOSTADDR(x, y) \ 2069 do { \ 2070 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 2071 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 2072 } while(0) 2073 2074#define BGE_ADDR_LO(y) \ 2075 ((uint64_t) (y) & 0xFFFFFFFF) 2076#define BGE_ADDR_HI(y) \ 2077 ((uint64_t) (y) >> 32) 2078 2079/* Ring control block structure */ 2080struct bge_rcb { 2081 bge_hostaddr bge_hostaddr; 2082 uint32_t bge_maxlen_flags; 2083 uint32_t bge_nicaddr; 2084}; 2085 2086#define RCB_WRITE_4(sc, rcb, offset, val) \ 2087 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 2088#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2089 2090#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2091#define BGE_RCB_FLAG_RING_DISABLED 0x0002 2092 2093struct bge_tx_bd { 2094 bge_hostaddr bge_addr; 2095#if BYTE_ORDER == LITTLE_ENDIAN 2096 uint16_t bge_flags; 2097 uint16_t bge_len; 2098 uint16_t bge_vlan_tag; 2099 uint16_t bge_mss; 2100#else 2101 uint16_t bge_len; 2102 uint16_t bge_flags; 2103 uint16_t bge_mss; 2104 uint16_t bge_vlan_tag; 2105#endif 2106}; 2107 2108#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2109#define BGE_TXBDFLAG_IP_CSUM 0x0002 2110#define BGE_TXBDFLAG_END 0x0004 2111#define BGE_TXBDFLAG_IP_FRAG 0x0008 2112#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ 2113#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2114#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */ 2115#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ 2116#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2117#define BGE_TXBDFLAG_COAL_NOW 0x0080 2118#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2119#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2120#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */ 2121#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */ 2122#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2123#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */ 2124#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */ 2125#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */ 2126#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2127#define BGE_TXBDFLAG_NO_CRC 0x8000 2128 2129#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2130/* Bits [1:0] of the MSS header length. */ 2131#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2132 2133#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2134 BGE_SEND_RING_1_TO_4 + \ 2135 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2136 2137struct bge_rx_bd { 2138 bge_hostaddr bge_addr; 2139#if BYTE_ORDER == LITTLE_ENDIAN 2140 uint16_t bge_len; 2141 uint16_t bge_idx; 2142 uint16_t bge_flags; 2143 uint16_t bge_type; 2144 uint16_t bge_tcp_udp_csum; 2145 uint16_t bge_ip_csum; 2146 uint16_t bge_vlan_tag; 2147 uint16_t bge_error_flag; 2148#else 2149 uint16_t bge_idx; 2150 uint16_t bge_len; 2151 uint16_t bge_type; 2152 uint16_t bge_flags; 2153 uint16_t bge_ip_csum; 2154 uint16_t bge_tcp_udp_csum; 2155 uint16_t bge_error_flag; 2156 uint16_t bge_vlan_tag; 2157#endif 2158 uint32_t bge_rsvd; 2159 uint32_t bge_opaque; 2160}; 2161 2162struct bge_extrx_bd { 2163 bge_hostaddr bge_addr1; 2164 bge_hostaddr bge_addr2; 2165 bge_hostaddr bge_addr3; 2166#if BYTE_ORDER == LITTLE_ENDIAN 2167 uint16_t bge_len2; 2168 uint16_t bge_len1; 2169 uint16_t bge_rsvd1; 2170 uint16_t bge_len3; 2171#else 2172 uint16_t bge_len1; 2173 uint16_t bge_len2; 2174 uint16_t bge_len3; 2175 uint16_t bge_rsvd1; 2176#endif 2177 bge_hostaddr bge_addr0; 2178#if BYTE_ORDER == LITTLE_ENDIAN 2179 uint16_t bge_len0; 2180 uint16_t bge_idx; 2181 uint16_t bge_flags; 2182 uint16_t bge_type; 2183 uint16_t bge_tcp_udp_csum; 2184 uint16_t bge_ip_csum; 2185 uint16_t bge_vlan_tag; 2186 uint16_t bge_error_flag; 2187#else 2188 uint16_t bge_idx; 2189 uint16_t bge_len0; 2190 uint16_t bge_type; 2191 uint16_t bge_flags; 2192 uint16_t bge_ip_csum; 2193 uint16_t bge_tcp_udp_csum; 2194 uint16_t bge_error_flag; 2195 uint16_t bge_vlan_tag; 2196#endif 2197 uint32_t bge_rsvd0; 2198 uint32_t bge_opaque; 2199}; 2200 2201#define BGE_RXBDFLAG_END 0x0004 2202#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2203#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2204#define BGE_RXBDFLAG_ERROR 0x0400 2205#define BGE_RXBDFLAG_MINI_RING 0x0800 2206#define BGE_RXBDFLAG_IP_CSUM 0x1000 2207#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2208#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2209#define BGE_RXBDFLAG_IPV6 0x8000 2210 2211#define BGE_RXERRFLAG_BAD_CRC 0x0001 2212#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2213#define BGE_RXERRFLAG_LINK_LOST 0x0004 2214#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2215#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2216#define BGE_RXERRFLAG_RUNT 0x0020 2217#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2218#define BGE_RXERRFLAG_GIANT 0x0080 2219#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 2220 2221struct bge_sts_idx { 2222#if BYTE_ORDER == LITTLE_ENDIAN 2223 uint16_t bge_rx_prod_idx; 2224 uint16_t bge_tx_cons_idx; 2225#else 2226 uint16_t bge_tx_cons_idx; 2227 uint16_t bge_rx_prod_idx; 2228#endif 2229}; 2230 2231struct bge_status_block { 2232 uint32_t bge_status; 2233 uint32_t bge_status_tag; 2234#if BYTE_ORDER == LITTLE_ENDIAN 2235 uint16_t bge_rx_jumbo_cons_idx; 2236 uint16_t bge_rx_std_cons_idx; 2237 uint16_t bge_rx_mini_cons_idx; 2238 uint16_t bge_rsvd1; 2239#else 2240 uint16_t bge_rx_std_cons_idx; 2241 uint16_t bge_rx_jumbo_cons_idx; 2242 uint16_t bge_rsvd1; 2243 uint16_t bge_rx_mini_cons_idx; 2244#endif 2245 struct bge_sts_idx bge_idx[16]; 2246}; 2247 2248#define BGE_STATFLAG_UPDATED 0x00000001 2249#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2250#define BGE_STATFLAG_ERROR 0x00000004 2251 2252 2253/* 2254 * Broadcom Vendor ID 2255 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2256 * even though they're now manufactured by Broadcom) 2257 */ 2258#define BCOM_VENDORID 0x14E4 2259#define BCOM_DEVICEID_BCM5700 0x1644 2260#define BCOM_DEVICEID_BCM5701 0x1645 2261#define BCOM_DEVICEID_BCM5702 0x1646 2262#define BCOM_DEVICEID_BCM5702X 0x16A6 2263#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2264#define BCOM_DEVICEID_BCM5703 0x1647 2265#define BCOM_DEVICEID_BCM5703X 0x16A7 2266#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2267#define BCOM_DEVICEID_BCM5704C 0x1648 2268#define BCOM_DEVICEID_BCM5704S 0x16A8 2269#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2270#define BCOM_DEVICEID_BCM5705 0x1653 2271#define BCOM_DEVICEID_BCM5705K 0x1654 2272#define BCOM_DEVICEID_BCM5705F 0x166E 2273#define BCOM_DEVICEID_BCM5705M 0x165D 2274#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2275#define BCOM_DEVICEID_BCM5714C 0x1668 2276#define BCOM_DEVICEID_BCM5714S 0x1669 2277#define BCOM_DEVICEID_BCM5715 0x1678 2278#define BCOM_DEVICEID_BCM5715S 0x1679 2279#define BCOM_DEVICEID_BCM5717 0x1655 2280#define BCOM_DEVICEID_BCM5718 0x1656 2281#define BCOM_DEVICEID_BCM5719 0x1657 2282#define BCOM_DEVICEID_BCM5720 0x1658 2283#define BCOM_DEVICEID_BCM5721 0x1659 2284#define BCOM_DEVICEID_BCM5722 0x165A 2285#define BCOM_DEVICEID_BCM5723 0x165B 2286#define BCOM_DEVICEID_BCM5750 0x1676 2287#define BCOM_DEVICEID_BCM5750M 0x167C 2288#define BCOM_DEVICEID_BCM5751 0x1677 2289#define BCOM_DEVICEID_BCM5751F 0x167E 2290#define BCOM_DEVICEID_BCM5751M 0x167D 2291#define BCOM_DEVICEID_BCM5752 0x1600 2292#define BCOM_DEVICEID_BCM5752M 0x1601 2293#define BCOM_DEVICEID_BCM5753 0x16F7 2294#define BCOM_DEVICEID_BCM5753F 0x16FE 2295#define BCOM_DEVICEID_BCM5753M 0x16FD 2296#define BCOM_DEVICEID_BCM5754 0x167A 2297#define BCOM_DEVICEID_BCM5754M 0x1672 2298#define BCOM_DEVICEID_BCM5755 0x167B 2299#define BCOM_DEVICEID_BCM5755M 0x1673 2300#define BCOM_DEVICEID_BCM5756 0x1674 2301#define BCOM_DEVICEID_BCM5761 0x1681 2302#define BCOM_DEVICEID_BCM5761E 0x1680 2303#define BCOM_DEVICEID_BCM5761S 0x1688 2304#define BCOM_DEVICEID_BCM5761SE 0x1689 2305#define BCOM_DEVICEID_BCM5764 0x1684 2306#define BCOM_DEVICEID_BCM5780 0x166A 2307#define BCOM_DEVICEID_BCM5780S 0x166B 2308#define BCOM_DEVICEID_BCM5781 0x16DD 2309#define BCOM_DEVICEID_BCM5782 0x1696 2310#define BCOM_DEVICEID_BCM5784 0x1698 2311#define BCOM_DEVICEID_BCM5785F 0x16a0 2312#define BCOM_DEVICEID_BCM5785G 0x1699 2313#define BCOM_DEVICEID_BCM5786 0x169A 2314#define BCOM_DEVICEID_BCM5787 0x169B 2315#define BCOM_DEVICEID_BCM5787M 0x1693 2316#define BCOM_DEVICEID_BCM5787F 0x167f 2317#define BCOM_DEVICEID_BCM5788 0x169C 2318#define BCOM_DEVICEID_BCM5789 0x169D 2319#define BCOM_DEVICEID_BCM5901 0x170D 2320#define BCOM_DEVICEID_BCM5901A2 0x170E 2321#define BCOM_DEVICEID_BCM5903M 0x16FF 2322#define BCOM_DEVICEID_BCM5906 0x1712 2323#define BCOM_DEVICEID_BCM5906M 0x1713 2324#define BCOM_DEVICEID_BCM57760 0x1690 2325#define BCOM_DEVICEID_BCM57761 0x16B0 2326#define BCOM_DEVICEID_BCM57765 0x16B4 2327#define BCOM_DEVICEID_BCM57780 0x1692 2328#define BCOM_DEVICEID_BCM57781 0x16B1 2329#define BCOM_DEVICEID_BCM57785 0x16B5 2330#define BCOM_DEVICEID_BCM57788 0x1691 2331#define BCOM_DEVICEID_BCM57790 0x1694 2332#define BCOM_DEVICEID_BCM57791 0x16B2 2333#define BCOM_DEVICEID_BCM57795 0x16B6 2334 2335/* 2336 * Alteon AceNIC PCI vendor/device ID. 2337 */ 2338#define ALTEON_VENDORID 0x12AE 2339#define ALTEON_DEVICEID_ACENIC 0x0001 2340#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2341#define ALTEON_DEVICEID_BCM5700 0x0003 2342#define ALTEON_DEVICEID_BCM5701 0x0004 2343 2344/* 2345 * 3Com 3c996 PCI vendor/device ID. 2346 */ 2347#define TC_VENDORID 0x10B7 2348#define TC_DEVICEID_3C996 0x0003 2349 2350/* 2351 * SysKonnect PCI vendor ID 2352 */ 2353#define SK_VENDORID 0x1148 2354#define SK_DEVICEID_ALTIMA 0x4400 2355#define SK_SUBSYSID_9D21 0x4421 2356#define SK_SUBSYSID_9D41 0x4441 2357 2358/* 2359 * Altima PCI vendor/device ID. 2360 */ 2361#define ALTIMA_VENDORID 0x173b 2362#define ALTIMA_DEVICE_AC1000 0x03e8 2363#define ALTIMA_DEVICE_AC1002 0x03e9 2364#define ALTIMA_DEVICE_AC9100 0x03ea 2365 2366/* 2367 * Dell PCI vendor ID 2368 */ 2369 2370#define DELL_VENDORID 0x1028 2371 2372/* 2373 * Apple PCI vendor ID. 2374 */ 2375#define APPLE_VENDORID 0x106b 2376#define APPLE_DEVICE_BCM5701 0x1645 2377 2378/* 2379 * Sun PCI vendor ID 2380 */ 2381#define SUN_VENDORID 0x108e 2382 2383/* 2384 * Fujitsu vendor/device IDs 2385 */ 2386#define FJTSU_VENDORID 0x10cf 2387#define FJTSU_DEVICEID_PW008GE5 0x11a1 2388#define FJTSU_DEVICEID_PW008GE4 0x11a2 2389#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */ 2390 2391/* 2392 * Offset of MAC address inside EEPROM. 2393 */ 2394#define BGE_EE_MAC_OFFSET 0x7C 2395#define BGE_EE_MAC_OFFSET_5906 0x10 2396#define BGE_EE_HWCFG_OFFSET 0xC8 2397 2398#define BGE_HWCFG_VOLTAGE 0x00000003 2399#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2400#define BGE_HWCFG_MEDIA 0x00000030 2401#define BGE_HWCFG_ASF 0x00000080 2402 2403#define BGE_VOLTAGE_1POINT3 0x00000000 2404#define BGE_VOLTAGE_1POINT8 0x00000001 2405 2406#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2407#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2408#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2409 2410#define BGE_MEDIA_UNSPEC 0x00000000 2411#define BGE_MEDIA_COPPER 0x00000010 2412#define BGE_MEDIA_FIBER 0x00000020 2413 2414#define BGE_TICKS_PER_SEC 1000000 2415 2416/* 2417 * Ring size constants. 2418 */ 2419#define BGE_EVENT_RING_CNT 256 2420#define BGE_CMD_RING_CNT 64 2421#define BGE_STD_RX_RING_CNT 512 2422#define BGE_JUMBO_RX_RING_CNT 256 2423#define BGE_MINI_RX_RING_CNT 1024 2424#define BGE_RETURN_RING_CNT 1024 2425 2426/* 5705 has smaller return ring size */ 2427 2428#define BGE_RETURN_RING_CNT_5705 512 2429 2430/* 2431 * Possible TX ring sizes. 2432 */ 2433#define BGE_TX_RING_CNT_128 128 2434#define BGE_TX_RING_BASE_128 0x3800 2435 2436#define BGE_TX_RING_CNT_256 256 2437#define BGE_TX_RING_BASE_256 0x3000 2438 2439#define BGE_TX_RING_CNT_512 512 2440#define BGE_TX_RING_BASE_512 0x2000 2441 2442#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2443#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2444 2445/* 2446 * Tigon III statistics counters. 2447 */ 2448/* Statistics maintained MAC Receive block. */ 2449struct bge_rx_mac_stats { 2450 bge_hostaddr ifHCInOctets; 2451 bge_hostaddr Reserved1; 2452 bge_hostaddr etherStatsFragments; 2453 bge_hostaddr ifHCInUcastPkts; 2454 bge_hostaddr ifHCInMulticastPkts; 2455 bge_hostaddr ifHCInBroadcastPkts; 2456 bge_hostaddr dot3StatsFCSErrors; 2457 bge_hostaddr dot3StatsAlignmentErrors; 2458 bge_hostaddr xonPauseFramesReceived; 2459 bge_hostaddr xoffPauseFramesReceived; 2460 bge_hostaddr macControlFramesReceived; 2461 bge_hostaddr xoffStateEntered; 2462 bge_hostaddr dot3StatsFramesTooLong; 2463 bge_hostaddr etherStatsJabbers; 2464 bge_hostaddr etherStatsUndersizePkts; 2465 bge_hostaddr inRangeLengthError; 2466 bge_hostaddr outRangeLengthError; 2467 bge_hostaddr etherStatsPkts64Octets; 2468 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2469 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2470 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2471 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2472 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2473 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2474 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2475 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2476 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2477}; 2478 2479 2480/* Statistics maintained MAC Transmit block. */ 2481struct bge_tx_mac_stats { 2482 bge_hostaddr ifHCOutOctets; 2483 bge_hostaddr Reserved2; 2484 bge_hostaddr etherStatsCollisions; 2485 bge_hostaddr outXonSent; 2486 bge_hostaddr outXoffSent; 2487 bge_hostaddr flowControlDone; 2488 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2489 bge_hostaddr dot3StatsSingleCollisionFrames; 2490 bge_hostaddr dot3StatsMultipleCollisionFrames; 2491 bge_hostaddr dot3StatsDeferredTransmissions; 2492 bge_hostaddr Reserved3; 2493 bge_hostaddr dot3StatsExcessiveCollisions; 2494 bge_hostaddr dot3StatsLateCollisions; 2495 bge_hostaddr dot3Collided2Times; 2496 bge_hostaddr dot3Collided3Times; 2497 bge_hostaddr dot3Collided4Times; 2498 bge_hostaddr dot3Collided5Times; 2499 bge_hostaddr dot3Collided6Times; 2500 bge_hostaddr dot3Collided7Times; 2501 bge_hostaddr dot3Collided8Times; 2502 bge_hostaddr dot3Collided9Times; 2503 bge_hostaddr dot3Collided10Times; 2504 bge_hostaddr dot3Collided11Times; 2505 bge_hostaddr dot3Collided12Times; 2506 bge_hostaddr dot3Collided13Times; 2507 bge_hostaddr dot3Collided14Times; 2508 bge_hostaddr dot3Collided15Times; 2509 bge_hostaddr ifHCOutUcastPkts; 2510 bge_hostaddr ifHCOutMulticastPkts; 2511 bge_hostaddr ifHCOutBroadcastPkts; 2512 bge_hostaddr dot3StatsCarrierSenseErrors; 2513 bge_hostaddr ifOutDiscards; 2514 bge_hostaddr ifOutErrors; 2515}; 2516 2517/* Stats counters access through registers */ 2518struct bge_mac_stats { 2519 /* TX MAC statistics */ 2520 uint64_t ifHCOutOctets; 2521 uint64_t Reserved0; 2522 uint64_t etherStatsCollisions; 2523 uint64_t outXonSent; 2524 uint64_t outXoffSent; 2525 uint64_t Reserved1; 2526 uint64_t dot3StatsInternalMacTransmitErrors; 2527 uint64_t dot3StatsSingleCollisionFrames; 2528 uint64_t dot3StatsMultipleCollisionFrames; 2529 uint64_t dot3StatsDeferredTransmissions; 2530 uint64_t Reserved2; 2531 uint64_t dot3StatsExcessiveCollisions; 2532 uint64_t dot3StatsLateCollisions; 2533 uint64_t Reserved3[14]; 2534 uint64_t ifHCOutUcastPkts; 2535 uint64_t ifHCOutMulticastPkts; 2536 uint64_t ifHCOutBroadcastPkts; 2537 uint64_t Reserved4[2]; 2538 /* RX MAC statistics */ 2539 uint64_t ifHCInOctets; 2540 uint64_t Reserved5; 2541 uint64_t etherStatsFragments; 2542 uint64_t ifHCInUcastPkts; 2543 uint64_t ifHCInMulticastPkts; 2544 uint64_t ifHCInBroadcastPkts; 2545 uint64_t dot3StatsFCSErrors; 2546 uint64_t dot3StatsAlignmentErrors; 2547 uint64_t xonPauseFramesReceived; 2548 uint64_t xoffPauseFramesReceived; 2549 uint64_t macControlFramesReceived; 2550 uint64_t xoffStateEntered; 2551 uint64_t dot3StatsFramesTooLong; 2552 uint64_t etherStatsJabbers; 2553 uint64_t etherStatsUndersizePkts; 2554 /* Receive List Placement control */ 2555 uint64_t FramesDroppedDueToFilters; 2556 uint64_t DmaWriteQueueFull; 2557 uint64_t DmaWriteHighPriQueueFull; 2558 uint64_t NoMoreRxBDs; 2559 uint64_t InputDiscards; 2560 uint64_t InputErrors; 2561 uint64_t RecvThresholdHit; 2562}; 2563 2564struct bge_stats { 2565 uint8_t Reserved0[256]; 2566 2567 /* Statistics maintained by Receive MAC. */ 2568 struct bge_rx_mac_stats rxstats; 2569 2570 bge_hostaddr Unused1[37]; 2571 2572 /* Statistics maintained by Transmit MAC. */ 2573 struct bge_tx_mac_stats txstats; 2574 2575 bge_hostaddr Unused2[31]; 2576 2577 /* Statistics maintained by Receive List Placement. */ 2578 bge_hostaddr COSIfHCInPkts[16]; 2579 bge_hostaddr COSFramesDroppedDueToFilters; 2580 bge_hostaddr nicDmaWriteQueueFull; 2581 bge_hostaddr nicDmaWriteHighPriQueueFull; 2582 bge_hostaddr nicNoMoreRxBDs; 2583 bge_hostaddr ifInDiscards; 2584 bge_hostaddr ifInErrors; 2585 bge_hostaddr nicRecvThresholdHit; 2586 2587 bge_hostaddr Unused3[9]; 2588 2589 /* Statistics maintained by Send Data Initiator. */ 2590 bge_hostaddr COSIfHCOutPkts[16]; 2591 bge_hostaddr nicDmaReadQueueFull; 2592 bge_hostaddr nicDmaReadHighPriQueueFull; 2593 bge_hostaddr nicSendDataCompQueueFull; 2594 2595 /* Statistics maintained by Host Coalescing. */ 2596 bge_hostaddr nicRingSetSendProdIndex; 2597 bge_hostaddr nicRingStatusUpdate; 2598 bge_hostaddr nicInterrupts; 2599 bge_hostaddr nicAvoidedInterrupts; 2600 bge_hostaddr nicSendThresholdHit; 2601 2602 uint8_t Reserved4[320]; 2603}; 2604 2605/* 2606 * Tigon general information block. This resides in host memory 2607 * and contains the status counters, ring control blocks and 2608 * producer pointers. 2609 */ 2610 2611struct bge_gib { 2612 struct bge_stats bge_stats; 2613 struct bge_rcb bge_tx_rcb[16]; 2614 struct bge_rcb bge_std_rx_rcb; 2615 struct bge_rcb bge_jumbo_rx_rcb; 2616 struct bge_rcb bge_mini_rx_rcb; 2617 struct bge_rcb bge_return_rcb; 2618}; 2619 2620#define BGE_FRAMELEN 1518 2621#define BGE_MAX_FRAMELEN 1536 2622#define BGE_JUMBO_FRAMELEN 9018 2623#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2624#define BGE_MIN_FRAMELEN 60 2625 2626/* 2627 * Other utility macros. 2628 */ 2629#define BGE_INC(x, y) (x) = (x + 1) % y 2630 2631/* 2632 * Register access macros. The Tigon always uses memory mapped register 2633 * accesses and all registers must be accessed with 32 bit operations. 2634 */ 2635 2636#define CSR_WRITE_4(sc, reg, val) \ 2637 bus_write_4(sc->bge_res, reg, val) 2638 2639#define CSR_READ_4(sc, reg) \ 2640 bus_read_4(sc->bge_res, reg) 2641 2642#define BGE_SETBIT(sc, reg, x) \ 2643 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2644#define BGE_CLRBIT(sc, reg, x) \ 2645 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2646 2647#define PCI_SETBIT(dev, reg, x, s) \ 2648 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2649#define PCI_CLRBIT(dev, reg, x, s) \ 2650 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2651 2652/* 2653 * Memory management stuff. 2654 */ 2655 2656#define BGE_NSEG_JUMBO 4 2657#define BGE_NSEG_NEW 32 2658#define BGE_TSOSEG_SZ 4096 2659 2660/* Maximum DMA address for controllers that have 40bit DMA address bug. */ 2661#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2662#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2663#else 2664#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2665#endif 2666 2667#ifdef PAE 2668#define BGE_DMA_BNDRY 0x80000000 2669#else 2670#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 2671#define BGE_DMA_BNDRY 0x100000000 2672#else 2673#define BGE_DMA_BNDRY 0 2674#endif 2675#endif 2676 2677/* 2678 * Ring structures. Most of these reside in host memory and we tell 2679 * the NIC where they are via the ring control blocks. The exceptions 2680 * are the tx and command rings, which live in NIC memory and which 2681 * we access via the shared memory window. 2682 */ 2683 2684struct bge_ring_data { 2685 struct bge_rx_bd *bge_rx_std_ring; 2686 bus_addr_t bge_rx_std_ring_paddr; 2687 struct bge_extrx_bd *bge_rx_jumbo_ring; 2688 bus_addr_t bge_rx_jumbo_ring_paddr; 2689 struct bge_rx_bd *bge_rx_return_ring; 2690 bus_addr_t bge_rx_return_ring_paddr; 2691 struct bge_tx_bd *bge_tx_ring; 2692 bus_addr_t bge_tx_ring_paddr; 2693 struct bge_status_block *bge_status_block; 2694 bus_addr_t bge_status_block_paddr; 2695 struct bge_stats *bge_stats; 2696 bus_addr_t bge_stats_paddr; 2697 struct bge_gib bge_info; 2698}; 2699 2700#define BGE_STD_RX_RING_SZ \ 2701 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2702#define BGE_JUMBO_RX_RING_SZ \ 2703 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2704#define BGE_TX_RING_SZ \ 2705 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2706#define BGE_RX_RTN_RING_SZ(x) \ 2707 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2708 2709#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2710 2711#define BGE_STATS_SZ sizeof (struct bge_stats) 2712 2713/* 2714 * Mbuf pointers. We need these to keep track of the virtual addresses 2715 * of our mbuf chains since we can only convert from physical to virtual, 2716 * not the other way around. 2717 */ 2718struct bge_chain_data { 2719 bus_dma_tag_t bge_parent_tag; 2720 bus_dma_tag_t bge_buffer_tag; 2721 bus_dma_tag_t bge_rx_std_ring_tag; 2722 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2723 bus_dma_tag_t bge_rx_return_ring_tag; 2724 bus_dma_tag_t bge_tx_ring_tag; 2725 bus_dma_tag_t bge_status_tag; 2726 bus_dma_tag_t bge_stats_tag; 2727 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */ 2728 bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */ 2729 bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */ 2730 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2731 bus_dmamap_t bge_rx_std_sparemap; 2732 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2733 bus_dmamap_t bge_rx_jumbo_sparemap; 2734 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2735 bus_dmamap_t bge_rx_std_ring_map; 2736 bus_dmamap_t bge_rx_jumbo_ring_map; 2737 bus_dmamap_t bge_tx_ring_map; 2738 bus_dmamap_t bge_rx_return_ring_map; 2739 bus_dmamap_t bge_status_map; 2740 bus_dmamap_t bge_stats_map; 2741 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2742 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2743 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2744 int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2745 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 2746}; 2747 2748struct bge_dmamap_arg { 2749 bus_addr_t bge_busaddr; 2750}; 2751 2752#define BGE_HWREV_TIGON 0x01 2753#define BGE_HWREV_TIGON_II 0x02 2754#define BGE_TIMEOUT 100000 2755#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2756 2757struct bge_bcom_hack { 2758 int reg; 2759 int val; 2760}; 2761 2762#define ASF_ENABLE 1 2763#define ASF_NEW_HANDSHAKE 2 2764#define ASF_STACKUP 4 2765 2766struct bge_softc { 2767 struct ifnet *bge_ifp; /* interface info */ 2768 device_t bge_dev; 2769 struct mtx bge_mtx; 2770 device_t bge_miibus; 2771 void *bge_intrhand; 2772 struct resource *bge_irq; 2773 struct resource *bge_res; 2774 struct ifmedia bge_ifmedia; /* TBI media info */ 2775 int bge_expcap; 2776 int bge_msicap; 2777 int bge_pcixcap; 2778 uint32_t bge_flags; 2779#define BGE_FLAG_TBI 0x00000001 2780#define BGE_FLAG_JUMBO 0x00000002 2781#define BGE_FLAG_JUMBO_STD 0x00000004 2782#define BGE_FLAG_EADDR 0x00000008 2783#define BGE_FLAG_MII_SERDES 0x00000010 2784#define BGE_FLAG_CPMU_PRESENT 0x00000020 2785#define BGE_FLAG_TAGGED_STATUS 0x00000040 2786#define BGE_FLAG_MSI 0x00000100 2787#define BGE_FLAG_PCIX 0x00000200 2788#define BGE_FLAG_PCIE 0x00000400 2789#define BGE_FLAG_TSO 0x00000800 2790#define BGE_FLAG_TSO3 0x00001000 2791#define BGE_FLAG_JUMBO_FRAME 0x00002000 2792#define BGE_FLAG_5700_FAMILY 0x00010000 2793#define BGE_FLAG_5705_PLUS 0x00020000 2794#define BGE_FLAG_5714_FAMILY 0x00040000 2795#define BGE_FLAG_575X_PLUS 0x00080000 2796#define BGE_FLAG_5755_PLUS 0x00100000 2797#define BGE_FLAG_5788 0x00200000 2798#define BGE_FLAG_5717_PLUS 0x00400000 2799#define BGE_FLAG_40BIT_BUG 0x01000000 2800#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2801#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2802#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2803#define BGE_FLAG_4K_RDMA_BUG 0x10000000 2804 uint32_t bge_phy_flags; 2805#define BGE_PHY_NO_WIRESPEED 0x00000001 2806#define BGE_PHY_ADC_BUG 0x00000002 2807#define BGE_PHY_5704_A0_BUG 0x00000004 2808#define BGE_PHY_JITTER_BUG 0x00000008 2809#define BGE_PHY_BER_BUG 0x00000010 2810#define BGE_PHY_ADJUST_TRIM 0x00000020 2811#define BGE_PHY_CRC_BUG 0x00000040 2812#define BGE_PHY_NO_3LED 0x00000080 2813 uint32_t bge_chipid; 2814 uint32_t bge_asicrev; 2815 uint32_t bge_chiprev; 2816 uint8_t bge_asf_mode; 2817 uint8_t bge_asf_count; 2818 struct bge_ring_data bge_ldata; /* rings */ 2819 struct bge_chain_data bge_cdata; /* mbufs */ 2820 uint16_t bge_tx_saved_considx; 2821 uint16_t bge_rx_saved_considx; 2822 uint16_t bge_ev_saved_considx; 2823 uint16_t bge_return_ring_cnt; 2824 uint16_t bge_std; /* current std ring head */ 2825 uint16_t bge_jumbo; /* current jumo ring head */ 2826 uint32_t bge_stat_ticks; 2827 uint32_t bge_rx_coal_ticks; 2828 uint32_t bge_tx_coal_ticks; 2829 uint32_t bge_tx_prodidx; 2830 uint32_t bge_rx_max_coal_bds; 2831 uint32_t bge_tx_max_coal_bds; 2832 uint32_t bge_mi_mode; 2833 int bge_if_flags; 2834 int bge_txcnt; 2835 int bge_link; /* link state */ 2836 int bge_link_evt; /* pending link event */ 2837 int bge_timer; 2838 int bge_forced_collapse; 2839 int bge_forced_udpcsum; 2840 int bge_csum_features; 2841 struct callout bge_stat_ch; 2842 uint32_t bge_rx_discards; 2843 uint32_t bge_tx_discards; 2844 uint32_t bge_tx_collisions; 2845#ifdef DEVICE_POLLING 2846 int rxcycles; 2847#endif /* DEVICE_POLLING */ 2848 struct bge_mac_stats bge_mac_stats; 2849 struct task bge_intr_task; 2850 struct taskqueue *bge_tq; 2851}; 2852 2853#define BGE_LOCK_INIT(_sc, _name) \ 2854 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2855#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2856#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2857#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2858#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2859