if_bgereg.h revision 220368
1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 220368 2011-04-05 17:41:54Z yongari $ 34 */ 35 36/* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 */ 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SOFTWARE_GENCOMM 0x00000B50 75#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81#define BGE_UNMAPPED 0x00001000 82#define BGE_UNMAPPED_END 0x00001FFF 83#define BGE_DMA_DESCRIPTORS 0x00002000 84#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85#define BGE_SEND_RING_5717 0x00004000 86#define BGE_SEND_RING_1_TO_4 0x00004000 87#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 88 89/* Firmware interface */ 90#define BGE_FW_DRV_ALIVE 0x00000001 91#define BGE_FW_PAUSE 0x00000002 92 93/* Mappings for internal memory configuration */ 94#define BGE_STD_RX_RINGS 0x00006000 95#define BGE_STD_RX_RINGS_END 0x00006FFF 96#define BGE_JUMBO_RX_RINGS 0x00007000 97#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 98#define BGE_BUFFPOOL_1 0x00008000 99#define BGE_BUFFPOOL_1_END 0x0000FFFF 100#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 101#define BGE_BUFFPOOL_2_END 0x00017FFF 102#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 103#define BGE_BUFFPOOL_3_END 0x0001FFFF 104#define BGE_STD_RX_RINGS_5717 0x00040000 105#define BGE_JUMBO_RX_RINGS_5717 0x00044400 106 107/* Mappings for external SSRAM configurations */ 108#define BGE_SEND_RING_5_TO_6 0x00006000 109#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 110#define BGE_SEND_RING_7_TO_8 0x00007000 111#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 112#define BGE_SEND_RING_9_TO_16 0x00008000 113#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 114#define BGE_EXT_STD_RX_RINGS 0x0000C000 115#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 116#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 117#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 118#define BGE_MINI_RX_RINGS 0x0000E000 119#define BGE_MINI_RX_RINGS_END 0x0000FFFF 120#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 121#define BGE_AVAIL_REGION1_END 0x00017FFF 122#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 123#define BGE_AVAIL_REGION2_END 0x0001FFFF 124#define BGE_EXT_SSRAM 0x00020000 125#define BGE_EXT_SSRAM_END 0x000FFFFF 126 127 128/* 129 * BCM570x register offsets. These are memory mapped registers 130 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 131 * Each register must be accessed using 32 bit operations. 132 * 133 * All registers are accessed through a 32K shared memory block. 134 * The first group of registers are actually copies of the PCI 135 * configuration space registers. 136 */ 137 138/* 139 * PCI registers defined in the PCI 2.2 spec. 140 */ 141#define BGE_PCI_VID 0x00 142#define BGE_PCI_DID 0x02 143#define BGE_PCI_CMD 0x04 144#define BGE_PCI_STS 0x06 145#define BGE_PCI_REV 0x08 146#define BGE_PCI_CLASS 0x09 147#define BGE_PCI_CACHESZ 0x0C 148#define BGE_PCI_LATTIMER 0x0D 149#define BGE_PCI_HDRTYPE 0x0E 150#define BGE_PCI_BIST 0x0F 151#define BGE_PCI_BAR0 0x10 152#define BGE_PCI_BAR1 0x14 153#define BGE_PCI_SUBSYS 0x2C 154#define BGE_PCI_SUBVID 0x2E 155#define BGE_PCI_ROMBASE 0x30 156#define BGE_PCI_CAPPTR 0x34 157#define BGE_PCI_INTLINE 0x3C 158#define BGE_PCI_INTPIN 0x3D 159#define BGE_PCI_MINGNT 0x3E 160#define BGE_PCI_MAXLAT 0x3F 161#define BGE_PCI_PCIXCAP 0x40 162#define BGE_PCI_NEXTPTR_PM 0x41 163#define BGE_PCI_PCIX_CMD 0x42 164#define BGE_PCI_PCIX_STS 0x44 165#define BGE_PCI_PWRMGMT_CAPID 0x48 166#define BGE_PCI_NEXTPTR_VPD 0x49 167#define BGE_PCI_PWRMGMT_CAPS 0x4A 168#define BGE_PCI_PWRMGMT_CMD 0x4C 169#define BGE_PCI_PWRMGMT_STS 0x4D 170#define BGE_PCI_PWRMGMT_DATA 0x4F 171#define BGE_PCI_VPD_CAPID 0x50 172#define BGE_PCI_NEXTPTR_MSI 0x51 173#define BGE_PCI_VPD_ADDR 0x52 174#define BGE_PCI_VPD_DATA 0x54 175#define BGE_PCI_MSI_CAPID 0x58 176#define BGE_PCI_NEXTPTR_NONE 0x59 177#define BGE_PCI_MSI_CTL 0x5A 178#define BGE_PCI_MSI_ADDR_HI 0x5C 179#define BGE_PCI_MSI_ADDR_LO 0x60 180#define BGE_PCI_MSI_DATA 0x64 181 182/* 183 * PCI Express definitions 184 * According to 185 * PCI Express base specification, REV. 1.0a 186 */ 187 188/* PCI Express device control, 16bits */ 189#define BGE_PCIE_DEVCTL 0x08 190#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 191#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 192#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 193#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 194#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 195#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 196#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 197 198/* PCI MSI. ??? */ 199#define BGE_PCIE_CAPID_REG 0xD0 200#define BGE_PCIE_CAPID 0x10 201 202/* 203 * PCI registers specific to the BCM570x family. 204 */ 205#define BGE_PCI_MISC_CTL 0x68 206#define BGE_PCI_DMA_RW_CTL 0x6C 207#define BGE_PCI_PCISTATE 0x70 208#define BGE_PCI_CLKCTL 0x74 209#define BGE_PCI_REG_BASEADDR 0x78 210#define BGE_PCI_MEMWIN_BASEADDR 0x7C 211#define BGE_PCI_REG_DATA 0x80 212#define BGE_PCI_MEMWIN_DATA 0x84 213#define BGE_PCI_MODECTL 0x88 214#define BGE_PCI_MISC_CFG 0x8C 215#define BGE_PCI_MISC_LOCALCTL 0x90 216#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 217#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 218#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 219#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 220#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 221#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 222#define BGE_PCI_ISR_MBX_HI 0xB0 223#define BGE_PCI_ISR_MBX_LO 0xB4 224#define BGE_PCI_PRODID_ASICREV 0xBC 225#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 226 227/* PCI Misc. Host control register */ 228#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 229#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 230#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 231#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 232#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 233#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 234#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 235#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 236#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 237#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 238#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 239 240#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 241#if BYTE_ORDER == LITTLE_ENDIAN 242#define BGE_DMA_SWAP_OPTIONS \ 243 BGE_MODECTL_WORDSWAP_NONFRAME| \ 244 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 245#else 246#define BGE_DMA_SWAP_OPTIONS \ 247 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 248 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 249#endif 250 251#define BGE_INIT \ 252 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 253 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 254 255#define BGE_CHIPID_TIGON_I 0x4000 256#define BGE_CHIPID_TIGON_II 0x6000 257#define BGE_CHIPID_BCM5700_A0 0x7000 258#define BGE_CHIPID_BCM5700_A1 0x7001 259#define BGE_CHIPID_BCM5700_B0 0x7100 260#define BGE_CHIPID_BCM5700_B1 0x7101 261#define BGE_CHIPID_BCM5700_B2 0x7102 262#define BGE_CHIPID_BCM5700_B3 0x7103 263#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 264#define BGE_CHIPID_BCM5700_C0 0x7200 265#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 266#define BGE_CHIPID_BCM5701_B0 0x0100 267#define BGE_CHIPID_BCM5701_B2 0x0102 268#define BGE_CHIPID_BCM5701_B5 0x0105 269#define BGE_CHIPID_BCM5703_A0 0x1000 270#define BGE_CHIPID_BCM5703_A1 0x1001 271#define BGE_CHIPID_BCM5703_A2 0x1002 272#define BGE_CHIPID_BCM5703_A3 0x1003 273#define BGE_CHIPID_BCM5703_B0 0x1100 274#define BGE_CHIPID_BCM5704_A0 0x2000 275#define BGE_CHIPID_BCM5704_A1 0x2001 276#define BGE_CHIPID_BCM5704_A2 0x2002 277#define BGE_CHIPID_BCM5704_A3 0x2003 278#define BGE_CHIPID_BCM5704_B0 0x2100 279#define BGE_CHIPID_BCM5705_A0 0x3000 280#define BGE_CHIPID_BCM5705_A1 0x3001 281#define BGE_CHIPID_BCM5705_A2 0x3002 282#define BGE_CHIPID_BCM5705_A3 0x3003 283#define BGE_CHIPID_BCM5750_A0 0x4000 284#define BGE_CHIPID_BCM5750_A1 0x4001 285#define BGE_CHIPID_BCM5750_A3 0x4000 286#define BGE_CHIPID_BCM5750_B0 0x4100 287#define BGE_CHIPID_BCM5750_B1 0x4101 288#define BGE_CHIPID_BCM5750_C0 0x4200 289#define BGE_CHIPID_BCM5750_C1 0x4201 290#define BGE_CHIPID_BCM5750_C2 0x4202 291#define BGE_CHIPID_BCM5714_A0 0x5000 292#define BGE_CHIPID_BCM5752_A0 0x6000 293#define BGE_CHIPID_BCM5752_A1 0x6001 294#define BGE_CHIPID_BCM5752_A2 0x6002 295#define BGE_CHIPID_BCM5714_B0 0x8000 296#define BGE_CHIPID_BCM5714_B3 0x8003 297#define BGE_CHIPID_BCM5715_A0 0x9000 298#define BGE_CHIPID_BCM5715_A1 0x9001 299#define BGE_CHIPID_BCM5715_A3 0x9003 300#define BGE_CHIPID_BCM5755_A0 0xa000 301#define BGE_CHIPID_BCM5755_A1 0xa001 302#define BGE_CHIPID_BCM5755_A2 0xa002 303#define BGE_CHIPID_BCM5722_A0 0xa200 304#define BGE_CHIPID_BCM5754_A0 0xb000 305#define BGE_CHIPID_BCM5754_A1 0xb001 306#define BGE_CHIPID_BCM5754_A2 0xb002 307#define BGE_CHIPID_BCM5761_A0 0x5761000 308#define BGE_CHIPID_BCM5761_A1 0x5761100 309#define BGE_CHIPID_BCM5784_A0 0x5784000 310#define BGE_CHIPID_BCM5784_A1 0x5784100 311#define BGE_CHIPID_BCM5787_A0 0xb000 312#define BGE_CHIPID_BCM5787_A1 0xb001 313#define BGE_CHIPID_BCM5787_A2 0xb002 314#define BGE_CHIPID_BCM5906_A0 0xc000 315#define BGE_CHIPID_BCM5906_A1 0xc001 316#define BGE_CHIPID_BCM5906_A2 0xc002 317#define BGE_CHIPID_BCM57780_A0 0x57780000 318#define BGE_CHIPID_BCM57780_A1 0x57780001 319#define BGE_CHIPID_BCM5717_A0 0x05717000 320#define BGE_CHIPID_BCM5717_B0 0x05717100 321 322/* shorthand one */ 323#define BGE_ASICREV(x) ((x) >> 12) 324#define BGE_ASICREV_BCM5701 0x00 325#define BGE_ASICREV_BCM5703 0x01 326#define BGE_ASICREV_BCM5704 0x02 327#define BGE_ASICREV_BCM5705 0x03 328#define BGE_ASICREV_BCM5750 0x04 329#define BGE_ASICREV_BCM5714_A0 0x05 330#define BGE_ASICREV_BCM5752 0x06 331#define BGE_ASICREV_BCM5700 0x07 332#define BGE_ASICREV_BCM5780 0x08 333#define BGE_ASICREV_BCM5714 0x09 334#define BGE_ASICREV_BCM5755 0x0a 335#define BGE_ASICREV_BCM5754 0x0b 336#define BGE_ASICREV_BCM5787 0x0b 337#define BGE_ASICREV_BCM5906 0x0c 338/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 339#define BGE_ASICREV_USE_PRODID_REG 0x0f 340/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 341#define BGE_ASICREV_BCM5717 0x5717 342#define BGE_ASICREV_BCM5761 0x5761 343#define BGE_ASICREV_BCM5784 0x5784 344#define BGE_ASICREV_BCM5785 0x5785 345#define BGE_ASICREV_BCM57780 0x57780 346 347/* chip revisions */ 348#define BGE_CHIPREV(x) ((x) >> 8) 349#define BGE_CHIPREV_5700_AX 0x70 350#define BGE_CHIPREV_5700_BX 0x71 351#define BGE_CHIPREV_5700_CX 0x72 352#define BGE_CHIPREV_5701_AX 0x00 353#define BGE_CHIPREV_5703_AX 0x10 354#define BGE_CHIPREV_5704_AX 0x20 355#define BGE_CHIPREV_5704_BX 0x21 356#define BGE_CHIPREV_5750_AX 0x40 357#define BGE_CHIPREV_5750_BX 0x41 358/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 359#define BGE_CHIPREV_5717_AX 0x57170 360#define BGE_CHIPREV_5717_BX 0x57171 361#define BGE_CHIPREV_5761_AX 0x57611 362#define BGE_CHIPREV_5784_AX 0x57841 363 364/* PCI DMA Read/Write Control register */ 365#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 366#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 367#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 368#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 369#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 370#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 371#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 372#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 373#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 374#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 375#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 376#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 377#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 378 379#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 380#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 381#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 382#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 383 384#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 385#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 386#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 387#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 388#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 389#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 390#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 391#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 392 393#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 394#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 395#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 396#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 397#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 398#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 399#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 400#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 401 402/* 403 * PCI state register -- note, this register is read only 404 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 405 * register is set. 406 */ 407#define BGE_PCISTATE_FORCE_RESET 0x00000001 408#define BGE_PCISTATE_INTR_STATE 0x00000002 409#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 410#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 411#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 412#define BGE_PCISTATE_WANT_EXPROM 0x00000020 413#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 414#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 415#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 416 417/* 418 * PCI Clock Control register -- note, this register is read only 419 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 420 * register is set. 421 */ 422#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 423#define BGE_PCICLOCKCTL_M66EN 0x00000080 424#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 425#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 426#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 427#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 428#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 429#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 430#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 431#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 432 433 434#ifndef PCIM_CMD_MWIEN 435#define PCIM_CMD_MWIEN 0x0010 436#endif 437#ifndef PCIM_CMD_INTxDIS 438#define PCIM_CMD_INTxDIS 0x0400 439#endif 440 441/* 442 * High priority mailbox registers 443 * Each mailbox is 64-bits wide, though we only use the 444 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 445 * first. The NIC will load the mailbox after the lower 32 bit word 446 * has been updated. 447 */ 448#define BGE_MBX_IRQ0_HI 0x0200 449#define BGE_MBX_IRQ0_LO 0x0204 450#define BGE_MBX_IRQ1_HI 0x0208 451#define BGE_MBX_IRQ1_LO 0x020C 452#define BGE_MBX_IRQ2_HI 0x0210 453#define BGE_MBX_IRQ2_LO 0x0214 454#define BGE_MBX_IRQ3_HI 0x0218 455#define BGE_MBX_IRQ3_LO 0x021C 456#define BGE_MBX_GEN0_HI 0x0220 457#define BGE_MBX_GEN0_LO 0x0224 458#define BGE_MBX_GEN1_HI 0x0228 459#define BGE_MBX_GEN1_LO 0x022C 460#define BGE_MBX_GEN2_HI 0x0230 461#define BGE_MBX_GEN2_LO 0x0234 462#define BGE_MBX_GEN3_HI 0x0228 463#define BGE_MBX_GEN3_LO 0x022C 464#define BGE_MBX_GEN4_HI 0x0240 465#define BGE_MBX_GEN4_LO 0x0244 466#define BGE_MBX_GEN5_HI 0x0248 467#define BGE_MBX_GEN5_LO 0x024C 468#define BGE_MBX_GEN6_HI 0x0250 469#define BGE_MBX_GEN6_LO 0x0254 470#define BGE_MBX_GEN7_HI 0x0258 471#define BGE_MBX_GEN7_LO 0x025C 472#define BGE_MBX_RELOAD_STATS_HI 0x0260 473#define BGE_MBX_RELOAD_STATS_LO 0x0264 474#define BGE_MBX_RX_STD_PROD_HI 0x0268 475#define BGE_MBX_RX_STD_PROD_LO 0x026C 476#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 477#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 478#define BGE_MBX_RX_MINI_PROD_HI 0x0278 479#define BGE_MBX_RX_MINI_PROD_LO 0x027C 480#define BGE_MBX_RX_CONS0_HI 0x0280 481#define BGE_MBX_RX_CONS0_LO 0x0284 482#define BGE_MBX_RX_CONS1_HI 0x0288 483#define BGE_MBX_RX_CONS1_LO 0x028C 484#define BGE_MBX_RX_CONS2_HI 0x0290 485#define BGE_MBX_RX_CONS2_LO 0x0294 486#define BGE_MBX_RX_CONS3_HI 0x0298 487#define BGE_MBX_RX_CONS3_LO 0x029C 488#define BGE_MBX_RX_CONS4_HI 0x02A0 489#define BGE_MBX_RX_CONS4_LO 0x02A4 490#define BGE_MBX_RX_CONS5_HI 0x02A8 491#define BGE_MBX_RX_CONS5_LO 0x02AC 492#define BGE_MBX_RX_CONS6_HI 0x02B0 493#define BGE_MBX_RX_CONS6_LO 0x02B4 494#define BGE_MBX_RX_CONS7_HI 0x02B8 495#define BGE_MBX_RX_CONS7_LO 0x02BC 496#define BGE_MBX_RX_CONS8_HI 0x02C0 497#define BGE_MBX_RX_CONS8_LO 0x02C4 498#define BGE_MBX_RX_CONS9_HI 0x02C8 499#define BGE_MBX_RX_CONS9_LO 0x02CC 500#define BGE_MBX_RX_CONS10_HI 0x02D0 501#define BGE_MBX_RX_CONS10_LO 0x02D4 502#define BGE_MBX_RX_CONS11_HI 0x02D8 503#define BGE_MBX_RX_CONS11_LO 0x02DC 504#define BGE_MBX_RX_CONS12_HI 0x02E0 505#define BGE_MBX_RX_CONS12_LO 0x02E4 506#define BGE_MBX_RX_CONS13_HI 0x02E8 507#define BGE_MBX_RX_CONS13_LO 0x02EC 508#define BGE_MBX_RX_CONS14_HI 0x02F0 509#define BGE_MBX_RX_CONS14_LO 0x02F4 510#define BGE_MBX_RX_CONS15_HI 0x02F8 511#define BGE_MBX_RX_CONS15_LO 0x02FC 512#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 513#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 514#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 515#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 516#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 517#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 518#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 519#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 520#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 521#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 522#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 523#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 524#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 525#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 526#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 527#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 528#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 529#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 530#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 531#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 532#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 533#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 534#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 535#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 536#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 537#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 538#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 539#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 540#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 541#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 542#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 543#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 544#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 545#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 546#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 547#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 548#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 549#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 550#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 551#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 552#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 553#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 554#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 555#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 556#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 557#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 558#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 559#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 560#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 561#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 562#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 563#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 564#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 565#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 566#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 567#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 568#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 569#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 570#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 571#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 572#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 573#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 574#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 575#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 576 577#define BGE_TX_RINGS_MAX 4 578#define BGE_TX_RINGS_EXTSSRAM_MAX 16 579#define BGE_RX_RINGS_MAX 16 580#define BGE_RX_RINGS_MAX_5717 17 581 582/* Ethernet MAC control registers */ 583#define BGE_MAC_MODE 0x0400 584#define BGE_MAC_STS 0x0404 585#define BGE_MAC_EVT_ENB 0x0408 586#define BGE_MAC_LED_CTL 0x040C 587#define BGE_MAC_ADDR1_LO 0x0410 588#define BGE_MAC_ADDR1_HI 0x0414 589#define BGE_MAC_ADDR2_LO 0x0418 590#define BGE_MAC_ADDR2_HI 0x041C 591#define BGE_MAC_ADDR3_LO 0x0420 592#define BGE_MAC_ADDR3_HI 0x0424 593#define BGE_MAC_ADDR4_LO 0x0428 594#define BGE_MAC_ADDR4_HI 0x042C 595#define BGE_WOL_PATPTR 0x0430 596#define BGE_WOL_PATCFG 0x0434 597#define BGE_TX_RANDOM_BACKOFF 0x0438 598#define BGE_RX_MTU 0x043C 599#define BGE_GBIT_PCS_TEST 0x0440 600#define BGE_TX_TBI_AUTONEG 0x0444 601#define BGE_RX_TBI_AUTONEG 0x0448 602#define BGE_MI_COMM 0x044C 603#define BGE_MI_STS 0x0450 604#define BGE_MI_MODE 0x0454 605#define BGE_AUTOPOLL_STS 0x0458 606#define BGE_TX_MODE 0x045C 607#define BGE_TX_STS 0x0460 608#define BGE_TX_LENGTHS 0x0464 609#define BGE_RX_MODE 0x0468 610#define BGE_RX_STS 0x046C 611#define BGE_MAR0 0x0470 612#define BGE_MAR1 0x0474 613#define BGE_MAR2 0x0478 614#define BGE_MAR3 0x047C 615#define BGE_RX_BD_RULES_CTL0 0x0480 616#define BGE_RX_BD_RULES_MASKVAL0 0x0484 617#define BGE_RX_BD_RULES_CTL1 0x0488 618#define BGE_RX_BD_RULES_MASKVAL1 0x048C 619#define BGE_RX_BD_RULES_CTL2 0x0490 620#define BGE_RX_BD_RULES_MASKVAL2 0x0494 621#define BGE_RX_BD_RULES_CTL3 0x0498 622#define BGE_RX_BD_RULES_MASKVAL3 0x049C 623#define BGE_RX_BD_RULES_CTL4 0x04A0 624#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 625#define BGE_RX_BD_RULES_CTL5 0x04A8 626#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 627#define BGE_RX_BD_RULES_CTL6 0x04B0 628#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 629#define BGE_RX_BD_RULES_CTL7 0x04B8 630#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 631#define BGE_RX_BD_RULES_CTL8 0x04C0 632#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 633#define BGE_RX_BD_RULES_CTL9 0x04C8 634#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 635#define BGE_RX_BD_RULES_CTL10 0x04D0 636#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 637#define BGE_RX_BD_RULES_CTL11 0x04D8 638#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 639#define BGE_RX_BD_RULES_CTL12 0x04E0 640#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 641#define BGE_RX_BD_RULES_CTL13 0x04E8 642#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 643#define BGE_RX_BD_RULES_CTL14 0x04F0 644#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 645#define BGE_RX_BD_RULES_CTL15 0x04F8 646#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 647#define BGE_RX_RULES_CFG 0x0500 648#define BGE_MAX_RX_FRAME_LOWAT 0x0504 649#define BGE_SERDES_CFG 0x0590 650#define BGE_SERDES_STS 0x0594 651#define BGE_SGDIG_CFG 0x05B0 652#define BGE_SGDIG_STS 0x05B4 653#define BGE_TX_MAC_STATS_OCTETS 0x0800 654#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 655#define BGE_TX_MAC_STATS_COLLS 0x0808 656#define BGE_TX_MAC_STATS_XON_SENT 0x080C 657#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 658#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 659#define BGE_TX_MAC_STATS_ERRORS 0x0818 660#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 661#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 662#define BGE_TX_MAC_STATS_DEFERRED 0x0824 663#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 664#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 665#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 666#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 667#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 668#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 669#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 670#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 671#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 672#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 673#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 674#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 675#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 676#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 677#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 678#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 679#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 680#define BGE_TX_MAC_STATS_UCAST 0x086C 681#define BGE_TX_MAC_STATS_MCAST 0x0870 682#define BGE_TX_MAC_STATS_BCAST 0x0874 683#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 684#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 685#define BGE_RX_MAC_STATS_OCTESTS 0x0880 686#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 687#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 688#define BGE_RX_MAC_STATS_UCAST 0x088C 689#define BGE_RX_MAC_STATS_MCAST 0x0890 690#define BGE_RX_MAC_STATS_BCAST 0x0894 691#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 692#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 693#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 694#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 695#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 696#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 697#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 698#define BGE_RX_MAC_STATS_JABBERS 0x08B4 699#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 700 701/* Ethernet MAC Mode register */ 702#define BGE_MACMODE_RESET 0x00000001 703#define BGE_MACMODE_HALF_DUPLEX 0x00000002 704#define BGE_MACMODE_PORTMODE 0x0000000C 705#define BGE_MACMODE_LOOPBACK 0x00000010 706#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 707#define BGE_MACMODE_TX_BURST_ENB 0x00000100 708#define BGE_MACMODE_MAX_DEFER 0x00000200 709#define BGE_MACMODE_LINK_POLARITY 0x00000400 710#define BGE_MACMODE_RX_STATS_ENB 0x00000800 711#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 712#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 713#define BGE_MACMODE_TX_STATS_ENB 0x00004000 714#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 715#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 716#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 717#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 718#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 719#define BGE_MACMODE_MIP_ENB 0x00100000 720#define BGE_MACMODE_TXDMA_ENB 0x00200000 721#define BGE_MACMODE_RXDMA_ENB 0x00400000 722#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 723 724#define BGE_PORTMODE_NONE 0x00000000 725#define BGE_PORTMODE_MII 0x00000004 726#define BGE_PORTMODE_GMII 0x00000008 727#define BGE_PORTMODE_TBI 0x0000000C 728 729/* MAC Status register */ 730#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 731#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 732#define BGE_MACSTAT_RX_CFG 0x00000004 733#define BGE_MACSTAT_CFG_CHANGED 0x00000008 734#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 735#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 736#define BGE_MACSTAT_LINK_CHANGED 0x00001000 737#define BGE_MACSTAT_MI_COMPLETE 0x00400000 738#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 739#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 740#define BGE_MACSTAT_ODI_ERROR 0x02000000 741#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 742#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 743 744/* MAC Event Enable Register */ 745#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 746#define BGE_EVTENB_LINK_CHANGED 0x00001000 747#define BGE_EVTENB_MI_COMPLETE 0x00400000 748#define BGE_EVTENB_MI_INTERRUPT 0x00800000 749#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 750#define BGE_EVTENB_ODI_ERROR 0x02000000 751#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 752#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 753 754/* LED Control Register */ 755#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 756#define BGE_LEDCTL_1000MBPS_LED 0x00000002 757#define BGE_LEDCTL_100MBPS_LED 0x00000004 758#define BGE_LEDCTL_10MBPS_LED 0x00000008 759#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 760#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 761#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 762#define BGE_LEDCTL_1000MBPS_STS 0x00000080 763#define BGE_LEDCTL_100MBPS_STS 0x00000100 764#define BGE_LEDCTL_10MBPS_STS 0x00000200 765#define BGE_LEDCTL_TRADLED_STS 0x00000400 766#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 767#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 768 769/* TX backoff seed register */ 770#define BGE_TX_BACKOFF_SEED_MASK 0x3F 771 772/* Autopoll status register */ 773#define BGE_AUTOPOLLSTS_ERROR 0x00000001 774 775/* Transmit MAC mode register */ 776#define BGE_TXMODE_RESET 0x00000001 777#define BGE_TXMODE_ENABLE 0x00000002 778#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 779#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 780#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 781#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 782 783/* Transmit MAC status register */ 784#define BGE_TXSTAT_RX_XOFFED 0x00000001 785#define BGE_TXSTAT_SENT_XOFF 0x00000002 786#define BGE_TXSTAT_SENT_XON 0x00000004 787#define BGE_TXSTAT_LINK_UP 0x00000008 788#define BGE_TXSTAT_ODI_UFLOW 0x00000010 789#define BGE_TXSTAT_ODI_OFLOW 0x00000020 790 791/* Transmit MAC lengths register */ 792#define BGE_TXLEN_SLOTTIME 0x000000FF 793#define BGE_TXLEN_IPG 0x00000F00 794#define BGE_TXLEN_CRS 0x00003000 795 796/* Receive MAC mode register */ 797#define BGE_RXMODE_RESET 0x00000001 798#define BGE_RXMODE_ENABLE 0x00000002 799#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 800#define BGE_RXMODE_RX_GIANTS 0x00000020 801#define BGE_RXMODE_RX_RUNTS 0x00000040 802#define BGE_RXMODE_8022_LENCHECK 0x00000080 803#define BGE_RXMODE_RX_PROMISC 0x00000100 804#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 805#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 806 807/* Receive MAC status register */ 808#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 809#define BGE_RXSTAT_RCVD_XOFF 0x00000002 810#define BGE_RXSTAT_RCVD_XON 0x00000004 811 812/* Receive Rules Control register */ 813#define BGE_RXRULECTL_OFFSET 0x000000FF 814#define BGE_RXRULECTL_CLASS 0x00001F00 815#define BGE_RXRULECTL_HDRTYPE 0x0000E000 816#define BGE_RXRULECTL_COMPARE_OP 0x00030000 817#define BGE_RXRULECTL_MAP 0x01000000 818#define BGE_RXRULECTL_DISCARD 0x02000000 819#define BGE_RXRULECTL_MASK 0x04000000 820#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 821#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 822#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 823#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 824 825/* Receive Rules Mask register */ 826#define BGE_RXRULEMASK_VALUE 0x0000FFFF 827#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 828 829/* SERDES configuration register */ 830#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 831#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 832#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 833#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 834#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 835#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 836#define BGE_SERDESCFG_TXMODE 0x00001000 837#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 838#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 839#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 840#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 841#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 842#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 843#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 844#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 845#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 846 847/* SERDES status register */ 848#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 849#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 850 851/* SGDIG config (not documented) */ 852#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 853#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 854#define BGE_SGDIGCFG_SEND 0x40000000 855#define BGE_SGDIGCFG_AUTO 0x80000000 856 857/* SGDIG status (not documented) */ 858#define BGE_SGDIGSTS_DONE 0x00000002 859#define BGE_SGDIGSTS_IS_SERDES 0x00000100 860#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 861#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 862 863 864/* MI communication register */ 865#define BGE_MICOMM_DATA 0x0000FFFF 866#define BGE_MICOMM_REG 0x001F0000 867#define BGE_MICOMM_PHY 0x03E00000 868#define BGE_MICOMM_CMD 0x0C000000 869#define BGE_MICOMM_READFAIL 0x10000000 870#define BGE_MICOMM_BUSY 0x20000000 871 872#define BGE_MIREG(x) ((x & 0x1F) << 16) 873#define BGE_MIPHY(x) ((x & 0x1F) << 21) 874#define BGE_MICMD_WRITE 0x04000000 875#define BGE_MICMD_READ 0x08000000 876 877/* MI status register */ 878#define BGE_MISTS_LINK 0x00000001 879#define BGE_MISTS_10MBPS 0x00000002 880 881#define BGE_MIMODE_CLK_10MHZ 0x00000001 882#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 883#define BGE_MIMODE_AUTOPOLL 0x00000010 884#define BGE_MIMODE_CLKCNT 0x001F0000 885#define BGE_MIMODE_500KHZ_CONST 0x00008000 886#define BGE_MIMODE_BASE 0x000C0000 887 888 889/* 890 * Send data initiator control registers. 891 */ 892#define BGE_SDI_MODE 0x0C00 893#define BGE_SDI_STATUS 0x0C04 894#define BGE_SDI_STATS_CTL 0x0C08 895#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 896#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 897#define BGE_ISO_PKT_TX 0x0C20 898#define BGE_LOCSTATS_COS0 0x0C80 899#define BGE_LOCSTATS_COS1 0x0C84 900#define BGE_LOCSTATS_COS2 0x0C88 901#define BGE_LOCSTATS_COS3 0x0C8C 902#define BGE_LOCSTATS_COS4 0x0C90 903#define BGE_LOCSTATS_COS5 0x0C84 904#define BGE_LOCSTATS_COS6 0x0C98 905#define BGE_LOCSTATS_COS7 0x0C9C 906#define BGE_LOCSTATS_COS8 0x0CA0 907#define BGE_LOCSTATS_COS9 0x0CA4 908#define BGE_LOCSTATS_COS10 0x0CA8 909#define BGE_LOCSTATS_COS11 0x0CAC 910#define BGE_LOCSTATS_COS12 0x0CB0 911#define BGE_LOCSTATS_COS13 0x0CB4 912#define BGE_LOCSTATS_COS14 0x0CB8 913#define BGE_LOCSTATS_COS15 0x0CBC 914#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 915#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 916#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 917#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 918#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 919#define BGE_LOCSTATS_IRQS 0x0CD4 920#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 921#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 922 923/* Send Data Initiator mode register */ 924#define BGE_SDIMODE_RESET 0x00000001 925#define BGE_SDIMODE_ENABLE 0x00000002 926#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 927#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 928 929/* Send Data Initiator stats register */ 930#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 931 932/* Send Data Initiator stats control register */ 933#define BGE_SDISTATSCTL_ENABLE 0x00000001 934#define BGE_SDISTATSCTL_FASTER 0x00000002 935#define BGE_SDISTATSCTL_CLEAR 0x00000004 936#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 937#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 938 939/* 940 * Send Data Completion Control registers 941 */ 942#define BGE_SDC_MODE 0x1000 943#define BGE_SDC_STATUS 0x1004 944 945/* Send Data completion mode register */ 946#define BGE_SDCMODE_RESET 0x00000001 947#define BGE_SDCMODE_ENABLE 0x00000002 948#define BGE_SDCMODE_ATTN 0x00000004 949#define BGE_SDCMODE_CDELAY 0x00000010 950 951/* Send Data completion status register */ 952#define BGE_SDCSTAT_ATTN 0x00000004 953 954/* 955 * Send BD Ring Selector Control registers 956 */ 957#define BGE_SRS_MODE 0x1400 958#define BGE_SRS_STATUS 0x1404 959#define BGE_SRS_HWDIAG 0x1408 960#define BGE_SRS_LOC_NIC_CONS0 0x1440 961#define BGE_SRS_LOC_NIC_CONS1 0x1444 962#define BGE_SRS_LOC_NIC_CONS2 0x1448 963#define BGE_SRS_LOC_NIC_CONS3 0x144C 964#define BGE_SRS_LOC_NIC_CONS4 0x1450 965#define BGE_SRS_LOC_NIC_CONS5 0x1454 966#define BGE_SRS_LOC_NIC_CONS6 0x1458 967#define BGE_SRS_LOC_NIC_CONS7 0x145C 968#define BGE_SRS_LOC_NIC_CONS8 0x1460 969#define BGE_SRS_LOC_NIC_CONS9 0x1464 970#define BGE_SRS_LOC_NIC_CONS10 0x1468 971#define BGE_SRS_LOC_NIC_CONS11 0x146C 972#define BGE_SRS_LOC_NIC_CONS12 0x1470 973#define BGE_SRS_LOC_NIC_CONS13 0x1474 974#define BGE_SRS_LOC_NIC_CONS14 0x1478 975#define BGE_SRS_LOC_NIC_CONS15 0x147C 976 977/* Send BD Ring Selector Mode register */ 978#define BGE_SRSMODE_RESET 0x00000001 979#define BGE_SRSMODE_ENABLE 0x00000002 980#define BGE_SRSMODE_ATTN 0x00000004 981 982/* Send BD Ring Selector Status register */ 983#define BGE_SRSSTAT_ERROR 0x00000004 984 985/* Send BD Ring Selector HW Diagnostics register */ 986#define BGE_SRSHWDIAG_STATE 0x0000000F 987#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 988#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 989#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 990 991/* 992 * Send BD Initiator Selector Control registers 993 */ 994#define BGE_SBDI_MODE 0x1800 995#define BGE_SBDI_STATUS 0x1804 996#define BGE_SBDI_LOC_NIC_PROD0 0x1808 997#define BGE_SBDI_LOC_NIC_PROD1 0x180C 998#define BGE_SBDI_LOC_NIC_PROD2 0x1810 999#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1000#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1001#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1002#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1003#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1004#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1005#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1006#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1007#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1008#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1009#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1010#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1011#define BGE_SBDI_LOC_NIC_PROD15 0x1844 1012 1013/* Send BD Initiator Mode register */ 1014#define BGE_SBDIMODE_RESET 0x00000001 1015#define BGE_SBDIMODE_ENABLE 0x00000002 1016#define BGE_SBDIMODE_ATTN 0x00000004 1017 1018/* Send BD Initiator Status register */ 1019#define BGE_SBDISTAT_ERROR 0x00000004 1020 1021/* 1022 * Send BD Completion Control registers 1023 */ 1024#define BGE_SBDC_MODE 0x1C00 1025#define BGE_SBDC_STATUS 0x1C04 1026 1027/* Send BD Completion Control Mode register */ 1028#define BGE_SBDCMODE_RESET 0x00000001 1029#define BGE_SBDCMODE_ENABLE 0x00000002 1030#define BGE_SBDCMODE_ATTN 0x00000004 1031 1032/* Send BD Completion Control Status register */ 1033#define BGE_SBDCSTAT_ATTN 0x00000004 1034 1035/* 1036 * Receive List Placement Control registers 1037 */ 1038#define BGE_RXLP_MODE 0x2000 1039#define BGE_RXLP_STATUS 0x2004 1040#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1041#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1042#define BGE_RXLP_CFG 0x2010 1043#define BGE_RXLP_STATS_CTL 0x2014 1044#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1045#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1046#define BGE_RXLP_HEAD0 0x2100 1047#define BGE_RXLP_TAIL0 0x2104 1048#define BGE_RXLP_COUNT0 0x2108 1049#define BGE_RXLP_HEAD1 0x2110 1050#define BGE_RXLP_TAIL1 0x2114 1051#define BGE_RXLP_COUNT1 0x2118 1052#define BGE_RXLP_HEAD2 0x2120 1053#define BGE_RXLP_TAIL2 0x2124 1054#define BGE_RXLP_COUNT2 0x2128 1055#define BGE_RXLP_HEAD3 0x2130 1056#define BGE_RXLP_TAIL3 0x2134 1057#define BGE_RXLP_COUNT3 0x2138 1058#define BGE_RXLP_HEAD4 0x2140 1059#define BGE_RXLP_TAIL4 0x2144 1060#define BGE_RXLP_COUNT4 0x2148 1061#define BGE_RXLP_HEAD5 0x2150 1062#define BGE_RXLP_TAIL5 0x2154 1063#define BGE_RXLP_COUNT5 0x2158 1064#define BGE_RXLP_HEAD6 0x2160 1065#define BGE_RXLP_TAIL6 0x2164 1066#define BGE_RXLP_COUNT6 0x2168 1067#define BGE_RXLP_HEAD7 0x2170 1068#define BGE_RXLP_TAIL7 0x2174 1069#define BGE_RXLP_COUNT7 0x2178 1070#define BGE_RXLP_HEAD8 0x2180 1071#define BGE_RXLP_TAIL8 0x2184 1072#define BGE_RXLP_COUNT8 0x2188 1073#define BGE_RXLP_HEAD9 0x2190 1074#define BGE_RXLP_TAIL9 0x2194 1075#define BGE_RXLP_COUNT9 0x2198 1076#define BGE_RXLP_HEAD10 0x21A0 1077#define BGE_RXLP_TAIL10 0x21A4 1078#define BGE_RXLP_COUNT10 0x21A8 1079#define BGE_RXLP_HEAD11 0x21B0 1080#define BGE_RXLP_TAIL11 0x21B4 1081#define BGE_RXLP_COUNT11 0x21B8 1082#define BGE_RXLP_HEAD12 0x21C0 1083#define BGE_RXLP_TAIL12 0x21C4 1084#define BGE_RXLP_COUNT12 0x21C8 1085#define BGE_RXLP_HEAD13 0x21D0 1086#define BGE_RXLP_TAIL13 0x21D4 1087#define BGE_RXLP_COUNT13 0x21D8 1088#define BGE_RXLP_HEAD14 0x21E0 1089#define BGE_RXLP_TAIL14 0x21E4 1090#define BGE_RXLP_COUNT14 0x21E8 1091#define BGE_RXLP_HEAD15 0x21F0 1092#define BGE_RXLP_TAIL15 0x21F4 1093#define BGE_RXLP_COUNT15 0x21F8 1094#define BGE_RXLP_LOCSTAT_COS0 0x2200 1095#define BGE_RXLP_LOCSTAT_COS1 0x2204 1096#define BGE_RXLP_LOCSTAT_COS2 0x2208 1097#define BGE_RXLP_LOCSTAT_COS3 0x220C 1098#define BGE_RXLP_LOCSTAT_COS4 0x2210 1099#define BGE_RXLP_LOCSTAT_COS5 0x2214 1100#define BGE_RXLP_LOCSTAT_COS6 0x2218 1101#define BGE_RXLP_LOCSTAT_COS7 0x221C 1102#define BGE_RXLP_LOCSTAT_COS8 0x2220 1103#define BGE_RXLP_LOCSTAT_COS9 0x2224 1104#define BGE_RXLP_LOCSTAT_COS10 0x2228 1105#define BGE_RXLP_LOCSTAT_COS11 0x222C 1106#define BGE_RXLP_LOCSTAT_COS12 0x2230 1107#define BGE_RXLP_LOCSTAT_COS13 0x2234 1108#define BGE_RXLP_LOCSTAT_COS14 0x2238 1109#define BGE_RXLP_LOCSTAT_COS15 0x223C 1110#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1111#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1112#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1113#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1114#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1115#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1116#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1117 1118 1119/* Receive List Placement mode register */ 1120#define BGE_RXLPMODE_RESET 0x00000001 1121#define BGE_RXLPMODE_ENABLE 0x00000002 1122#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1123#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1124#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1125 1126/* Receive List Placement Status register */ 1127#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1128#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1129#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1130 1131/* 1132 * Receive Data and Receive BD Initiator Control Registers 1133 */ 1134#define BGE_RDBDI_MODE 0x2400 1135#define BGE_RDBDI_STATUS 0x2404 1136#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1137#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1138#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1139#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1140#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1141#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1142#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1143#define BGE_RX_STD_RCB_NICADDR 0x245C 1144#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1145#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1146#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1147#define BGE_RX_MINI_RCB_NICADDR 0x246C 1148#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1149#define BGE_RDBDI_STD_RX_CONS 0x2474 1150#define BGE_RDBDI_MINI_RX_CONS 0x2478 1151#define BGE_RDBDI_RETURN_PROD0 0x2480 1152#define BGE_RDBDI_RETURN_PROD1 0x2484 1153#define BGE_RDBDI_RETURN_PROD2 0x2488 1154#define BGE_RDBDI_RETURN_PROD3 0x248C 1155#define BGE_RDBDI_RETURN_PROD4 0x2490 1156#define BGE_RDBDI_RETURN_PROD5 0x2494 1157#define BGE_RDBDI_RETURN_PROD6 0x2498 1158#define BGE_RDBDI_RETURN_PROD7 0x249C 1159#define BGE_RDBDI_RETURN_PROD8 0x24A0 1160#define BGE_RDBDI_RETURN_PROD9 0x24A4 1161#define BGE_RDBDI_RETURN_PROD10 0x24A8 1162#define BGE_RDBDI_RETURN_PROD11 0x24AC 1163#define BGE_RDBDI_RETURN_PROD12 0x24B0 1164#define BGE_RDBDI_RETURN_PROD13 0x24B4 1165#define BGE_RDBDI_RETURN_PROD14 0x24B8 1166#define BGE_RDBDI_RETURN_PROD15 0x24BC 1167#define BGE_RDBDI_HWDIAG 0x24C0 1168 1169 1170/* Receive Data and Receive BD Initiator Mode register */ 1171#define BGE_RDBDIMODE_RESET 0x00000001 1172#define BGE_RDBDIMODE_ENABLE 0x00000002 1173#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1174#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1175#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1176 1177/* Receive Data and Receive BD Initiator Status register */ 1178#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1179#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1180#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1181 1182 1183/* 1184 * Receive Data Completion Control registers 1185 */ 1186#define BGE_RDC_MODE 0x2800 1187 1188/* Receive Data Completion Mode register */ 1189#define BGE_RDCMODE_RESET 0x00000001 1190#define BGE_RDCMODE_ENABLE 0x00000002 1191#define BGE_RDCMODE_ATTN 0x00000004 1192 1193/* 1194 * Receive BD Initiator Control registers 1195 */ 1196#define BGE_RBDI_MODE 0x2C00 1197#define BGE_RBDI_STATUS 0x2C04 1198#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1199#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1200#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1201#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1202#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1203#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1204 1205#define BGE_STD_REPLENISH_LWM 0x2D00 1206#define BGE_JMB_REPLENISH_LWM 0x2D04 1207 1208/* Receive BD Initiator Mode register */ 1209#define BGE_RBDIMODE_RESET 0x00000001 1210#define BGE_RBDIMODE_ENABLE 0x00000002 1211#define BGE_RBDIMODE_ATTN 0x00000004 1212 1213/* Receive BD Initiator Status register */ 1214#define BGE_RBDISTAT_ATTN 0x00000004 1215 1216/* 1217 * Receive BD Completion Control registers 1218 */ 1219#define BGE_RBDC_MODE 0x3000 1220#define BGE_RBDC_STATUS 0x3004 1221#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1222#define BGE_RBDC_STD_BD_PROD 0x300C 1223#define BGE_RBDC_MINI_BD_PROD 0x3010 1224 1225/* Receive BD completion mode register */ 1226#define BGE_RBDCMODE_RESET 0x00000001 1227#define BGE_RBDCMODE_ENABLE 0x00000002 1228#define BGE_RBDCMODE_ATTN 0x00000004 1229 1230/* Receive BD completion status register */ 1231#define BGE_RBDCSTAT_ERROR 0x00000004 1232 1233/* 1234 * Receive List Selector Control registers 1235 */ 1236#define BGE_RXLS_MODE 0x3400 1237#define BGE_RXLS_STATUS 0x3404 1238 1239/* Receive List Selector Mode register */ 1240#define BGE_RXLSMODE_RESET 0x00000001 1241#define BGE_RXLSMODE_ENABLE 0x00000002 1242#define BGE_RXLSMODE_ATTN 0x00000004 1243 1244/* Receive List Selector Status register */ 1245#define BGE_RXLSSTAT_ERROR 0x00000004 1246 1247#define BGE_CPMU_CTRL 0x3600 1248#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1249#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1250#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1251#define BGE_CPMU_HST_ACC 0x361C 1252#define BGE_CPMU_CLCK_STAT 0x3630 1253#define BGE_CPMU_MUTEX_REQ 0x365C 1254#define BGE_CPMU_MUTEX_GNT 0x3660 1255#define BGE_CPMU_PHY_STRAP 0x3664 1256 1257/* Central Power Management Unit (CPMU) register */ 1258#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1259#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1260#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1261#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1262 1263/* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1264#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1265#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1266 1267/* Link Speed 1000MB Power Mode Clock Policy register */ 1268#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1269#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1270#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1271 1272/* Link Aware Power Mode Clock Policy register */ 1273#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1274#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1275 1276#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1277#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1278 1279/* CPMU Clock Status register */ 1280#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1281#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1282#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1283#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1284 1285/* CPMU Mutex Request register */ 1286#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1287#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1288 1289/* CPMU GPHY Strap register */ 1290#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1291 1292/* 1293 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1294 */ 1295#define BGE_MBCF_MODE 0x3800 1296#define BGE_MBCF_STATUS 0x3804 1297 1298/* Mbuf Cluster Free mode register */ 1299#define BGE_MBCFMODE_RESET 0x00000001 1300#define BGE_MBCFMODE_ENABLE 0x00000002 1301#define BGE_MBCFMODE_ATTN 0x00000004 1302 1303/* Mbuf Cluster Free status register */ 1304#define BGE_MBCFSTAT_ERROR 0x00000004 1305 1306/* 1307 * Host Coalescing Control registers 1308 */ 1309#define BGE_HCC_MODE 0x3C00 1310#define BGE_HCC_STATUS 0x3C04 1311#define BGE_HCC_RX_COAL_TICKS 0x3C08 1312#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1313#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1314#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1315#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1316#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1317#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1318#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1319#define BGE_HCC_STATS_TICKS 0x3C28 1320#define BGE_HCC_STATS_ADDR_HI 0x3C30 1321#define BGE_HCC_STATS_ADDR_LO 0x3C34 1322#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1323#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1324#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1325#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1326#define BGE_FLOW_ATTN 0x3C48 1327#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1328#define BGE_HCC_STD_BD_CONS 0x3C54 1329#define BGE_HCC_MINI_BD_CONS 0x3C58 1330#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1331#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1332#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1333#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1334#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1335#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1336#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1337#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1338#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1339#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1340#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1341#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1342#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1343#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1344#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1345#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1346#define BGE_HCC_TX_BD_CONS0 0x3CC0 1347#define BGE_HCC_TX_BD_CONS1 0x3CC4 1348#define BGE_HCC_TX_BD_CONS2 0x3CC8 1349#define BGE_HCC_TX_BD_CONS3 0x3CCC 1350#define BGE_HCC_TX_BD_CONS4 0x3CD0 1351#define BGE_HCC_TX_BD_CONS5 0x3CD4 1352#define BGE_HCC_TX_BD_CONS6 0x3CD8 1353#define BGE_HCC_TX_BD_CONS7 0x3CDC 1354#define BGE_HCC_TX_BD_CONS8 0x3CE0 1355#define BGE_HCC_TX_BD_CONS9 0x3CE4 1356#define BGE_HCC_TX_BD_CONS10 0x3CE8 1357#define BGE_HCC_TX_BD_CONS11 0x3CEC 1358#define BGE_HCC_TX_BD_CONS12 0x3CF0 1359#define BGE_HCC_TX_BD_CONS13 0x3CF4 1360#define BGE_HCC_TX_BD_CONS14 0x3CF8 1361#define BGE_HCC_TX_BD_CONS15 0x3CFC 1362 1363 1364/* Host coalescing mode register */ 1365#define BGE_HCCMODE_RESET 0x00000001 1366#define BGE_HCCMODE_ENABLE 0x00000002 1367#define BGE_HCCMODE_ATTN 0x00000004 1368#define BGE_HCCMODE_COAL_NOW 0x00000008 1369#define BGE_HCCMODE_MSI_BITS 0x00000070 1370#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1371 1372#define BGE_STATBLKSZ_FULL 0x00000000 1373#define BGE_STATBLKSZ_64BYTE 0x00000080 1374#define BGE_STATBLKSZ_32BYTE 0x00000100 1375 1376/* Host coalescing status register */ 1377#define BGE_HCCSTAT_ERROR 0x00000004 1378 1379/* Flow attention register */ 1380#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1381#define BGE_FLOWATTN_MEMARB 0x00000080 1382#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1383#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1384#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1385#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1386#define BGE_FLOWATTN_RDBDI 0x00080000 1387#define BGE_FLOWATTN_RXLS 0x00100000 1388#define BGE_FLOWATTN_RXLP 0x00200000 1389#define BGE_FLOWATTN_RBDC 0x00400000 1390#define BGE_FLOWATTN_RBDI 0x00800000 1391#define BGE_FLOWATTN_SDC 0x08000000 1392#define BGE_FLOWATTN_SDI 0x10000000 1393#define BGE_FLOWATTN_SRS 0x20000000 1394#define BGE_FLOWATTN_SBDC 0x40000000 1395#define BGE_FLOWATTN_SBDI 0x80000000 1396 1397/* 1398 * Memory arbiter registers 1399 */ 1400#define BGE_MARB_MODE 0x4000 1401#define BGE_MARB_STATUS 0x4004 1402#define BGE_MARB_TRAPADDR_HI 0x4008 1403#define BGE_MARB_TRAPADDR_LO 0x400C 1404 1405/* Memory arbiter mode register */ 1406#define BGE_MARBMODE_RESET 0x00000001 1407#define BGE_MARBMODE_ENABLE 0x00000002 1408#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1409#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1410#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1411#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1412#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1413#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1414#define BGE_MARBMODE_PCI_TRAP 0x00000100 1415#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1416#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1417#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1418#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1419#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1420#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1421#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1422#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1423#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1424#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1425#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1426#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1427#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1428#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1429#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1430#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1431#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1432 1433/* Memory arbiter status register */ 1434#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1435#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1436#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1437#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1438#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1439#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1440#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1441#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1442#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1443#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1444#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1445#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1446#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1447#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1448#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1449#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1450#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1451#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1452#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1453#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1454#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1455#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1456#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1457#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1458 1459/* 1460 * Buffer manager control registers 1461 */ 1462#define BGE_BMAN_MODE 0x4400 1463#define BGE_BMAN_STATUS 0x4404 1464#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1465#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1466#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1467#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1468#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1469#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1470#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1471#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1472#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1473#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1474#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1475#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1476#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1477#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1478#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1479#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1480#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1481#define BGE_BMAN_HWDIAG_1 0x444C 1482#define BGE_BMAN_HWDIAG_2 0x4450 1483#define BGE_BMAN_HWDIAG_3 0x4454 1484 1485/* Buffer manager mode register */ 1486#define BGE_BMANMODE_RESET 0x00000001 1487#define BGE_BMANMODE_ENABLE 0x00000002 1488#define BGE_BMANMODE_ATTN 0x00000004 1489#define BGE_BMANMODE_TESTMODE 0x00000008 1490#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1491 1492/* Buffer manager status register */ 1493#define BGE_BMANSTAT_ERRO 0x00000004 1494#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1495 1496 1497/* 1498 * Read DMA Control registers 1499 */ 1500#define BGE_RDMA_MODE 0x4800 1501#define BGE_RDMA_STATUS 0x4804 1502#define BGE_RDMA_RSRVCTRL 0x4900 1503 1504/* Read DMA mode register */ 1505#define BGE_RDMAMODE_RESET 0x00000001 1506#define BGE_RDMAMODE_ENABLE 0x00000002 1507#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1508#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1509#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1510#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1511#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1512#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1513#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1514#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1515#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1516#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1517#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1518#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1519#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1520#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1521#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1522#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1523#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1524 1525/* Read DMA status register */ 1526#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1527#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1528#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1529#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1530#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1531#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1532#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1533#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1534 1535/* Read DMA Reserved Control register */ 1536#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1537 1538/* 1539 * Write DMA control registers 1540 */ 1541#define BGE_WDMA_MODE 0x4C00 1542#define BGE_WDMA_STATUS 0x4C04 1543 1544/* Write DMA mode register */ 1545#define BGE_WDMAMODE_RESET 0x00000001 1546#define BGE_WDMAMODE_ENABLE 0x00000002 1547#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1548#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1549#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1550#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1551#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1552#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1553#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1554#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1555#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1556#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1557#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1558 1559/* Write DMA status register */ 1560#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1561#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1562#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1563#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1564#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1565#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1566#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1567#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1568 1569 1570/* 1571 * RX CPU registers 1572 */ 1573#define BGE_RXCPU_MODE 0x5000 1574#define BGE_RXCPU_STATUS 0x5004 1575#define BGE_RXCPU_PC 0x501C 1576 1577/* RX CPU mode register */ 1578#define BGE_RXCPUMODE_RESET 0x00000001 1579#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1580#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1581#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1582#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1583#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1584#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1585#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1586#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1587#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1588#define BGE_RXCPUMODE_HALTCPU 0x00000400 1589#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1590#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1591#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1592 1593/* RX CPU status register */ 1594#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1595#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1596#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1597#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1598#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1599#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1600#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1601#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1602#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1603#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1604#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1605#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1606#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1607#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1608#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1609#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1610#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1611 1612/* 1613 * V? CPU registers 1614 */ 1615#define BGE_VCPU_STATUS 0x5100 1616#define BGE_VCPU_EXT_CTRL 0x6890 1617 1618#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1619#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1620 1621#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1622#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1623 1624/* 1625 * TX CPU registers 1626 */ 1627#define BGE_TXCPU_MODE 0x5400 1628#define BGE_TXCPU_STATUS 0x5404 1629#define BGE_TXCPU_PC 0x541C 1630 1631/* TX CPU mode register */ 1632#define BGE_TXCPUMODE_RESET 0x00000001 1633#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1634#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1635#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1636#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1637#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1638#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1639#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1640#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1641#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1642#define BGE_TXCPUMODE_HALTCPU 0x00000400 1643#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1644#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1645 1646/* TX CPU status register */ 1647#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1648#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1649#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1650#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1651#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1652#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1653#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1654#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1655#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1656#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1657#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1658#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1659#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1660#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1661#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1662#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1663#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1664 1665 1666/* 1667 * Low priority mailbox registers 1668 */ 1669#define BGE_LPMBX_IRQ0_HI 0x5800 1670#define BGE_LPMBX_IRQ0_LO 0x5804 1671#define BGE_LPMBX_IRQ1_HI 0x5808 1672#define BGE_LPMBX_IRQ1_LO 0x580C 1673#define BGE_LPMBX_IRQ2_HI 0x5810 1674#define BGE_LPMBX_IRQ2_LO 0x5814 1675#define BGE_LPMBX_IRQ3_HI 0x5818 1676#define BGE_LPMBX_IRQ3_LO 0x581C 1677#define BGE_LPMBX_GEN0_HI 0x5820 1678#define BGE_LPMBX_GEN0_LO 0x5824 1679#define BGE_LPMBX_GEN1_HI 0x5828 1680#define BGE_LPMBX_GEN1_LO 0x582C 1681#define BGE_LPMBX_GEN2_HI 0x5830 1682#define BGE_LPMBX_GEN2_LO 0x5834 1683#define BGE_LPMBX_GEN3_HI 0x5828 1684#define BGE_LPMBX_GEN3_LO 0x582C 1685#define BGE_LPMBX_GEN4_HI 0x5840 1686#define BGE_LPMBX_GEN4_LO 0x5844 1687#define BGE_LPMBX_GEN5_HI 0x5848 1688#define BGE_LPMBX_GEN5_LO 0x584C 1689#define BGE_LPMBX_GEN6_HI 0x5850 1690#define BGE_LPMBX_GEN6_LO 0x5854 1691#define BGE_LPMBX_GEN7_HI 0x5858 1692#define BGE_LPMBX_GEN7_LO 0x585C 1693#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1694#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1695#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1696#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1697#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1698#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1699#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1700#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1701#define BGE_LPMBX_RX_CONS0_HI 0x5880 1702#define BGE_LPMBX_RX_CONS0_LO 0x5884 1703#define BGE_LPMBX_RX_CONS1_HI 0x5888 1704#define BGE_LPMBX_RX_CONS1_LO 0x588C 1705#define BGE_LPMBX_RX_CONS2_HI 0x5890 1706#define BGE_LPMBX_RX_CONS2_LO 0x5894 1707#define BGE_LPMBX_RX_CONS3_HI 0x5898 1708#define BGE_LPMBX_RX_CONS3_LO 0x589C 1709#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1710#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1711#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1712#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1713#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1714#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1715#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1716#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1717#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1718#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1719#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1720#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1721#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1722#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1723#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1724#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1725#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1726#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1727#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1728#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1729#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1730#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1731#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1732#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1733#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1734#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1735#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1736#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1737#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1738#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1739#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1740#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1741#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1742#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1743#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1744#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1745#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1746#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1747#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1748#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1749#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1750#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1751#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1752#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1753#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1754#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1755#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1756#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1757#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1758#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1759#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1760#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1761#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1762#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1763#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1764#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1765#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1766#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1767#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1768#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1769#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1770#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1771#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1772#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1773#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1774#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1775#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1776#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1777#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1778#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1779#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1780#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1781#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1782#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1783#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1784#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1785#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1786#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1787#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1788#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1789#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1790#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1791#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1792#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1793#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1794#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1795#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1796#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1797 1798/* 1799 * Flow throw Queue reset register 1800 */ 1801#define BGE_FTQ_RESET 0x5C00 1802 1803#define BGE_FTQRESET_DMAREAD 0x00000002 1804#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1805#define BGE_FTQRESET_DMADONE 0x00000010 1806#define BGE_FTQRESET_SBDC 0x00000020 1807#define BGE_FTQRESET_SDI 0x00000040 1808#define BGE_FTQRESET_WDMA 0x00000080 1809#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1810#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1811#define BGE_FTQRESET_SDC 0x00000400 1812#define BGE_FTQRESET_HCC 0x00000800 1813#define BGE_FTQRESET_TXFIFO 0x00001000 1814#define BGE_FTQRESET_MBC 0x00002000 1815#define BGE_FTQRESET_RBDC 0x00004000 1816#define BGE_FTQRESET_RXLP 0x00008000 1817#define BGE_FTQRESET_RDBDI 0x00010000 1818#define BGE_FTQRESET_RDC 0x00020000 1819#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1820 1821/* 1822 * Message Signaled Interrupt registers 1823 */ 1824#define BGE_MSI_MODE 0x6000 1825#define BGE_MSI_STATUS 0x6004 1826#define BGE_MSI_FIFOACCESS 0x6008 1827 1828/* MSI mode register */ 1829#define BGE_MSIMODE_RESET 0x00000001 1830#define BGE_MSIMODE_ENABLE 0x00000002 1831#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1832#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1833 1834/* MSI status register */ 1835#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1836#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1837#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1838#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1839#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1840 1841 1842/* 1843 * DMA Completion registers 1844 */ 1845#define BGE_DMAC_MODE 0x6400 1846 1847/* DMA Completion mode register */ 1848#define BGE_DMACMODE_RESET 0x00000001 1849#define BGE_DMACMODE_ENABLE 0x00000002 1850 1851 1852/* 1853 * General control registers. 1854 */ 1855#define BGE_MODE_CTL 0x6800 1856#define BGE_MISC_CFG 0x6804 1857#define BGE_MISC_LOCAL_CTL 0x6808 1858#define BGE_CPU_EVENT 0x6810 1859#define BGE_EE_ADDR 0x6838 1860#define BGE_EE_DATA 0x683C 1861#define BGE_EE_CTL 0x6840 1862#define BGE_MDI_CTL 0x6844 1863#define BGE_EE_DELAY 0x6848 1864#define BGE_FASTBOOT_PC 0x6894 1865 1866/* 1867 * NVRAM Control registers 1868 */ 1869#define BGE_NVRAM_CMD 0x7000 1870#define BGE_NVRAM_STAT 0x7004 1871#define BGE_NVRAM_WRDATA 0x7008 1872#define BGE_NVRAM_ADDR 0x700c 1873#define BGE_NVRAM_RDDATA 0x7010 1874#define BGE_NVRAM_CFG1 0x7014 1875#define BGE_NVRAM_CFG2 0x7018 1876#define BGE_NVRAM_CFG3 0x701c 1877#define BGE_NVRAM_SWARB 0x7020 1878#define BGE_NVRAM_ACCESS 0x7024 1879#define BGE_NVRAM_WRITE1 0x7028 1880 1881#define BGE_NVRAMCMD_RESET 0x00000001 1882#define BGE_NVRAMCMD_DONE 0x00000008 1883#define BGE_NVRAMCMD_START 0x00000010 1884#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1885#define BGE_NVRAMCMD_ERASE 0x00000040 1886#define BGE_NVRAMCMD_FIRST 0x00000080 1887#define BGE_NVRAMCMD_LAST 0x00000100 1888 1889#define BGE_NVRAM_READCMD \ 1890 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1891 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1892#define BGE_NVRAM_WRITECMD \ 1893 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1894 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1895 1896#define BGE_NVRAMSWARB_SET0 0x00000001 1897#define BGE_NVRAMSWARB_SET1 0x00000002 1898#define BGE_NVRAMSWARB_SET2 0x00000003 1899#define BGE_NVRAMSWARB_SET3 0x00000004 1900#define BGE_NVRAMSWARB_CLR0 0x00000010 1901#define BGE_NVRAMSWARB_CLR1 0x00000020 1902#define BGE_NVRAMSWARB_CLR2 0x00000040 1903#define BGE_NVRAMSWARB_CLR3 0x00000080 1904#define BGE_NVRAMSWARB_GNT0 0x00000100 1905#define BGE_NVRAMSWARB_GNT1 0x00000200 1906#define BGE_NVRAMSWARB_GNT2 0x00000400 1907#define BGE_NVRAMSWARB_GNT3 0x00000800 1908#define BGE_NVRAMSWARB_REQ0 0x00001000 1909#define BGE_NVRAMSWARB_REQ1 0x00002000 1910#define BGE_NVRAMSWARB_REQ2 0x00004000 1911#define BGE_NVRAMSWARB_REQ3 0x00008000 1912 1913#define BGE_NVRAMACC_ENABLE 0x00000001 1914#define BGE_NVRAMACC_WRENABLE 0x00000002 1915 1916/* Mode control register */ 1917#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1918#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1919#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1920#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1921#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1922#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1923#define BGE_MODECTL_NO_RX_CRC 0x00000400 1924#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1925#define BGE_MODECTL_NO_TX_INTR 0x00002000 1926#define BGE_MODECTL_NO_RX_INTR 0x00004000 1927#define BGE_MODECTL_FORCE_PCI32 0x00008000 1928#define BGE_MODECTL_STACKUP 0x00010000 1929#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1930#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1931#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1932#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1933#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1934#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1935#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1936#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1937#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1938#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1939 1940/* Misc. config register */ 1941#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1942#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1943#define BGE_MISCCFG_BOARD_ID 0x0001E000 1944#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1945#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1946#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1947#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 1948 1949#define BGE_32BITTIME_66MHZ (0x41 << 1) 1950 1951/* Misc. Local Control */ 1952#define BGE_MLC_INTR_STATE 0x00000001 1953#define BGE_MLC_INTR_CLR 0x00000002 1954#define BGE_MLC_INTR_SET 0x00000004 1955#define BGE_MLC_INTR_ONATTN 0x00000008 1956#define BGE_MLC_MISCIO_IN0 0x00000100 1957#define BGE_MLC_MISCIO_IN1 0x00000200 1958#define BGE_MLC_MISCIO_IN2 0x00000400 1959#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1960#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1961#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1962#define BGE_MLC_MISCIO_OUT0 0x00004000 1963#define BGE_MLC_MISCIO_OUT1 0x00008000 1964#define BGE_MLC_MISCIO_OUT2 0x00010000 1965#define BGE_MLC_EXTRAM_ENB 0x00020000 1966#define BGE_MLC_SRAM_SIZE 0x001C0000 1967#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1968#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1969#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1970#define BGE_MLC_AUTO_EEPROM 0x01000000 1971 1972#define BGE_SSRAMSIZE_256KB 0x00000000 1973#define BGE_SSRAMSIZE_512KB 0x00040000 1974#define BGE_SSRAMSIZE_1MB 0x00080000 1975#define BGE_SSRAMSIZE_2MB 0x000C0000 1976#define BGE_SSRAMSIZE_4MB 0x00100000 1977#define BGE_SSRAMSIZE_8MB 0x00140000 1978#define BGE_SSRAMSIZE_16M 0x00180000 1979 1980/* EEPROM address register */ 1981#define BGE_EEADDR_ADDRESS 0x0000FFFC 1982#define BGE_EEADDR_HALFCLK 0x01FF0000 1983#define BGE_EEADDR_START 0x02000000 1984#define BGE_EEADDR_DEVID 0x1C000000 1985#define BGE_EEADDR_RESET 0x20000000 1986#define BGE_EEADDR_DONE 0x40000000 1987#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1988 1989#define BGE_EEDEVID(x) ((x & 7) << 26) 1990#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1991#define BGE_HALFCLK_384SCL 0x60 1992#define BGE_EE_READCMD \ 1993 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1994 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1995#define BGE_EE_WRCMD \ 1996 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1997 BGE_EEADDR_START|BGE_EEADDR_DONE) 1998 1999/* EEPROM Control register */ 2000#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2001#define BGE_EECTL_CLKOUT 0x00000002 2002#define BGE_EECTL_CLKIN 0x00000004 2003#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2004#define BGE_EECTL_DATAOUT 0x00000010 2005#define BGE_EECTL_DATAIN 0x00000020 2006 2007/* MDI (MII/GMII) access register */ 2008#define BGE_MDI_DATA 0x00000001 2009#define BGE_MDI_DIR 0x00000002 2010#define BGE_MDI_SEL 0x00000004 2011#define BGE_MDI_CLK 0x00000008 2012 2013#define BGE_MEMWIN_START 0x00008000 2014#define BGE_MEMWIN_END 0x0000FFFF 2015 2016 2017#define BGE_MEMWIN_READ(sc, x, val) \ 2018 do { \ 2019 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2020 (0xFFFF0000 & x), 4); \ 2021 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2022 } while(0) 2023 2024#define BGE_MEMWIN_WRITE(sc, x, val) \ 2025 do { \ 2026 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2027 (0xFFFF0000 & x), 4); \ 2028 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2029 } while(0) 2030 2031/* 2032 * This magic number is written to the firmware mailbox at 0xb50 2033 * before a software reset is issued. After the internal firmware 2034 * has completed its initialization it will write the opposite of 2035 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 2036 * driver to synchronize with the firmware. 2037 */ 2038#define BGE_MAGIC_NUMBER 0x4B657654 2039 2040typedef struct { 2041 uint32_t bge_addr_hi; 2042 uint32_t bge_addr_lo; 2043} bge_hostaddr; 2044 2045#define BGE_HOSTADDR(x, y) \ 2046 do { \ 2047 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 2048 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 2049 } while(0) 2050 2051#define BGE_ADDR_LO(y) \ 2052 ((uint64_t) (y) & 0xFFFFFFFF) 2053#define BGE_ADDR_HI(y) \ 2054 ((uint64_t) (y) >> 32) 2055 2056/* Ring control block structure */ 2057struct bge_rcb { 2058 bge_hostaddr bge_hostaddr; 2059 uint32_t bge_maxlen_flags; 2060 uint32_t bge_nicaddr; 2061}; 2062 2063#define RCB_WRITE_4(sc, rcb, offset, val) \ 2064 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 2065#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2066 2067#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2068#define BGE_RCB_FLAG_RING_DISABLED 0x0002 2069 2070struct bge_tx_bd { 2071 bge_hostaddr bge_addr; 2072#if BYTE_ORDER == LITTLE_ENDIAN 2073 uint16_t bge_flags; 2074 uint16_t bge_len; 2075 uint16_t bge_vlan_tag; 2076 uint16_t bge_mss; 2077#else 2078 uint16_t bge_len; 2079 uint16_t bge_flags; 2080 uint16_t bge_mss; 2081 uint16_t bge_vlan_tag; 2082#endif 2083}; 2084 2085#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2086#define BGE_TXBDFLAG_IP_CSUM 0x0002 2087#define BGE_TXBDFLAG_END 0x0004 2088#define BGE_TXBDFLAG_IP_FRAG 0x0008 2089#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ 2090#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2091#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */ 2092#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ 2093#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2094#define BGE_TXBDFLAG_COAL_NOW 0x0080 2095#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2096#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2097#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */ 2098#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */ 2099#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2100#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */ 2101#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */ 2102#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */ 2103#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2104#define BGE_TXBDFLAG_NO_CRC 0x8000 2105 2106#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2107/* Bits [1:0] of the MSS header length. */ 2108#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2109 2110#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2111 BGE_SEND_RING_1_TO_4 + \ 2112 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2113 2114struct bge_rx_bd { 2115 bge_hostaddr bge_addr; 2116#if BYTE_ORDER == LITTLE_ENDIAN 2117 uint16_t bge_len; 2118 uint16_t bge_idx; 2119 uint16_t bge_flags; 2120 uint16_t bge_type; 2121 uint16_t bge_tcp_udp_csum; 2122 uint16_t bge_ip_csum; 2123 uint16_t bge_vlan_tag; 2124 uint16_t bge_error_flag; 2125#else 2126 uint16_t bge_idx; 2127 uint16_t bge_len; 2128 uint16_t bge_type; 2129 uint16_t bge_flags; 2130 uint16_t bge_ip_csum; 2131 uint16_t bge_tcp_udp_csum; 2132 uint16_t bge_error_flag; 2133 uint16_t bge_vlan_tag; 2134#endif 2135 uint32_t bge_rsvd; 2136 uint32_t bge_opaque; 2137}; 2138 2139struct bge_extrx_bd { 2140 bge_hostaddr bge_addr1; 2141 bge_hostaddr bge_addr2; 2142 bge_hostaddr bge_addr3; 2143#if BYTE_ORDER == LITTLE_ENDIAN 2144 uint16_t bge_len2; 2145 uint16_t bge_len1; 2146 uint16_t bge_rsvd1; 2147 uint16_t bge_len3; 2148#else 2149 uint16_t bge_len1; 2150 uint16_t bge_len2; 2151 uint16_t bge_len3; 2152 uint16_t bge_rsvd1; 2153#endif 2154 bge_hostaddr bge_addr0; 2155#if BYTE_ORDER == LITTLE_ENDIAN 2156 uint16_t bge_len0; 2157 uint16_t bge_idx; 2158 uint16_t bge_flags; 2159 uint16_t bge_type; 2160 uint16_t bge_tcp_udp_csum; 2161 uint16_t bge_ip_csum; 2162 uint16_t bge_vlan_tag; 2163 uint16_t bge_error_flag; 2164#else 2165 uint16_t bge_idx; 2166 uint16_t bge_len0; 2167 uint16_t bge_type; 2168 uint16_t bge_flags; 2169 uint16_t bge_ip_csum; 2170 uint16_t bge_tcp_udp_csum; 2171 uint16_t bge_error_flag; 2172 uint16_t bge_vlan_tag; 2173#endif 2174 uint32_t bge_rsvd0; 2175 uint32_t bge_opaque; 2176}; 2177 2178#define BGE_RXBDFLAG_END 0x0004 2179#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2180#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2181#define BGE_RXBDFLAG_ERROR 0x0400 2182#define BGE_RXBDFLAG_MINI_RING 0x0800 2183#define BGE_RXBDFLAG_IP_CSUM 0x1000 2184#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2185#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2186#define BGE_RXBDFLAG_IPV6 0x8000 2187 2188#define BGE_RXERRFLAG_BAD_CRC 0x0001 2189#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2190#define BGE_RXERRFLAG_LINK_LOST 0x0004 2191#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2192#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2193#define BGE_RXERRFLAG_RUNT 0x0020 2194#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2195#define BGE_RXERRFLAG_GIANT 0x0080 2196#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 2197 2198struct bge_sts_idx { 2199#if BYTE_ORDER == LITTLE_ENDIAN 2200 uint16_t bge_rx_prod_idx; 2201 uint16_t bge_tx_cons_idx; 2202#else 2203 uint16_t bge_tx_cons_idx; 2204 uint16_t bge_rx_prod_idx; 2205#endif 2206}; 2207 2208struct bge_status_block { 2209 uint32_t bge_status; 2210 uint32_t bge_status_tag; 2211#if BYTE_ORDER == LITTLE_ENDIAN 2212 uint16_t bge_rx_jumbo_cons_idx; 2213 uint16_t bge_rx_std_cons_idx; 2214 uint16_t bge_rx_mini_cons_idx; 2215 uint16_t bge_rsvd1; 2216#else 2217 uint16_t bge_rx_std_cons_idx; 2218 uint16_t bge_rx_jumbo_cons_idx; 2219 uint16_t bge_rsvd1; 2220 uint16_t bge_rx_mini_cons_idx; 2221#endif 2222 struct bge_sts_idx bge_idx[16]; 2223}; 2224 2225#define BGE_STATFLAG_UPDATED 0x00000001 2226#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2227#define BGE_STATFLAG_ERROR 0x00000004 2228 2229 2230/* 2231 * Broadcom Vendor ID 2232 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2233 * even though they're now manufactured by Broadcom) 2234 */ 2235#define BCOM_VENDORID 0x14E4 2236#define BCOM_DEVICEID_BCM5700 0x1644 2237#define BCOM_DEVICEID_BCM5701 0x1645 2238#define BCOM_DEVICEID_BCM5702 0x1646 2239#define BCOM_DEVICEID_BCM5702X 0x16A6 2240#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2241#define BCOM_DEVICEID_BCM5703 0x1647 2242#define BCOM_DEVICEID_BCM5703X 0x16A7 2243#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2244#define BCOM_DEVICEID_BCM5704C 0x1648 2245#define BCOM_DEVICEID_BCM5704S 0x16A8 2246#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2247#define BCOM_DEVICEID_BCM5705 0x1653 2248#define BCOM_DEVICEID_BCM5705K 0x1654 2249#define BCOM_DEVICEID_BCM5705F 0x166E 2250#define BCOM_DEVICEID_BCM5705M 0x165D 2251#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2252#define BCOM_DEVICEID_BCM5714C 0x1668 2253#define BCOM_DEVICEID_BCM5714S 0x1669 2254#define BCOM_DEVICEID_BCM5715 0x1678 2255#define BCOM_DEVICEID_BCM5715S 0x1679 2256#define BCOM_DEVICEID_BCM5717 0x1655 2257#define BCOM_DEVICEID_BCM5718 0x1656 2258#define BCOM_DEVICEID_BCM5720 0x1658 2259#define BCOM_DEVICEID_BCM5721 0x1659 2260#define BCOM_DEVICEID_BCM5722 0x165A 2261#define BCOM_DEVICEID_BCM5723 0x165B 2262#define BCOM_DEVICEID_BCM5750 0x1676 2263#define BCOM_DEVICEID_BCM5750M 0x167C 2264#define BCOM_DEVICEID_BCM5751 0x1677 2265#define BCOM_DEVICEID_BCM5751F 0x167E 2266#define BCOM_DEVICEID_BCM5751M 0x167D 2267#define BCOM_DEVICEID_BCM5752 0x1600 2268#define BCOM_DEVICEID_BCM5752M 0x1601 2269#define BCOM_DEVICEID_BCM5753 0x16F7 2270#define BCOM_DEVICEID_BCM5753F 0x16FE 2271#define BCOM_DEVICEID_BCM5753M 0x16FD 2272#define BCOM_DEVICEID_BCM5754 0x167A 2273#define BCOM_DEVICEID_BCM5754M 0x1672 2274#define BCOM_DEVICEID_BCM5755 0x167B 2275#define BCOM_DEVICEID_BCM5755M 0x1673 2276#define BCOM_DEVICEID_BCM5756 0x1674 2277#define BCOM_DEVICEID_BCM5761 0x1681 2278#define BCOM_DEVICEID_BCM5761E 0x1680 2279#define BCOM_DEVICEID_BCM5761S 0x1688 2280#define BCOM_DEVICEID_BCM5761SE 0x1689 2281#define BCOM_DEVICEID_BCM5764 0x1684 2282#define BCOM_DEVICEID_BCM5780 0x166A 2283#define BCOM_DEVICEID_BCM5780S 0x166B 2284#define BCOM_DEVICEID_BCM5781 0x16DD 2285#define BCOM_DEVICEID_BCM5782 0x1696 2286#define BCOM_DEVICEID_BCM5784 0x1698 2287#define BCOM_DEVICEID_BCM5785F 0x16a0 2288#define BCOM_DEVICEID_BCM5785G 0x1699 2289#define BCOM_DEVICEID_BCM5786 0x169A 2290#define BCOM_DEVICEID_BCM5787 0x169B 2291#define BCOM_DEVICEID_BCM5787M 0x1693 2292#define BCOM_DEVICEID_BCM5787F 0x167f 2293#define BCOM_DEVICEID_BCM5788 0x169C 2294#define BCOM_DEVICEID_BCM5789 0x169D 2295#define BCOM_DEVICEID_BCM5901 0x170D 2296#define BCOM_DEVICEID_BCM5901A2 0x170E 2297#define BCOM_DEVICEID_BCM5903M 0x16FF 2298#define BCOM_DEVICEID_BCM5906 0x1712 2299#define BCOM_DEVICEID_BCM5906M 0x1713 2300#define BCOM_DEVICEID_BCM57760 0x1690 2301#define BCOM_DEVICEID_BCM57780 0x1692 2302#define BCOM_DEVICEID_BCM57788 0x1691 2303#define BCOM_DEVICEID_BCM57790 0x1694 2304 2305/* 2306 * Alteon AceNIC PCI vendor/device ID. 2307 */ 2308#define ALTEON_VENDORID 0x12AE 2309#define ALTEON_DEVICEID_ACENIC 0x0001 2310#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2311#define ALTEON_DEVICEID_BCM5700 0x0003 2312#define ALTEON_DEVICEID_BCM5701 0x0004 2313 2314/* 2315 * 3Com 3c996 PCI vendor/device ID. 2316 */ 2317#define TC_VENDORID 0x10B7 2318#define TC_DEVICEID_3C996 0x0003 2319 2320/* 2321 * SysKonnect PCI vendor ID 2322 */ 2323#define SK_VENDORID 0x1148 2324#define SK_DEVICEID_ALTIMA 0x4400 2325#define SK_SUBSYSID_9D21 0x4421 2326#define SK_SUBSYSID_9D41 0x4441 2327 2328/* 2329 * Altima PCI vendor/device ID. 2330 */ 2331#define ALTIMA_VENDORID 0x173b 2332#define ALTIMA_DEVICE_AC1000 0x03e8 2333#define ALTIMA_DEVICE_AC1002 0x03e9 2334#define ALTIMA_DEVICE_AC9100 0x03ea 2335 2336/* 2337 * Dell PCI vendor ID 2338 */ 2339 2340#define DELL_VENDORID 0x1028 2341 2342/* 2343 * Apple PCI vendor ID. 2344 */ 2345#define APPLE_VENDORID 0x106b 2346#define APPLE_DEVICE_BCM5701 0x1645 2347 2348/* 2349 * Sun PCI vendor ID 2350 */ 2351#define SUN_VENDORID 0x108e 2352 2353/* 2354 * Fujitsu vendor/device IDs 2355 */ 2356#define FJTSU_VENDORID 0x10cf 2357#define FJTSU_DEVICEID_PW008GE5 0x11a1 2358#define FJTSU_DEVICEID_PW008GE4 0x11a2 2359#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */ 2360 2361/* 2362 * Offset of MAC address inside EEPROM. 2363 */ 2364#define BGE_EE_MAC_OFFSET 0x7C 2365#define BGE_EE_MAC_OFFSET_5906 0x10 2366#define BGE_EE_HWCFG_OFFSET 0xC8 2367 2368#define BGE_HWCFG_VOLTAGE 0x00000003 2369#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2370#define BGE_HWCFG_MEDIA 0x00000030 2371#define BGE_HWCFG_ASF 0x00000080 2372 2373#define BGE_VOLTAGE_1POINT3 0x00000000 2374#define BGE_VOLTAGE_1POINT8 0x00000001 2375 2376#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2377#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2378#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2379 2380#define BGE_MEDIA_UNSPEC 0x00000000 2381#define BGE_MEDIA_COPPER 0x00000010 2382#define BGE_MEDIA_FIBER 0x00000020 2383 2384#define BGE_TICKS_PER_SEC 1000000 2385 2386/* 2387 * Ring size constants. 2388 */ 2389#define BGE_EVENT_RING_CNT 256 2390#define BGE_CMD_RING_CNT 64 2391#define BGE_STD_RX_RING_CNT 512 2392#define BGE_JUMBO_RX_RING_CNT 256 2393#define BGE_MINI_RX_RING_CNT 1024 2394#define BGE_RETURN_RING_CNT 1024 2395 2396/* 5705 has smaller return ring size */ 2397 2398#define BGE_RETURN_RING_CNT_5705 512 2399 2400/* 2401 * Possible TX ring sizes. 2402 */ 2403#define BGE_TX_RING_CNT_128 128 2404#define BGE_TX_RING_BASE_128 0x3800 2405 2406#define BGE_TX_RING_CNT_256 256 2407#define BGE_TX_RING_BASE_256 0x3000 2408 2409#define BGE_TX_RING_CNT_512 512 2410#define BGE_TX_RING_BASE_512 0x2000 2411 2412#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2413#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2414 2415/* 2416 * Tigon III statistics counters. 2417 */ 2418/* Statistics maintained MAC Receive block. */ 2419struct bge_rx_mac_stats { 2420 bge_hostaddr ifHCInOctets; 2421 bge_hostaddr Reserved1; 2422 bge_hostaddr etherStatsFragments; 2423 bge_hostaddr ifHCInUcastPkts; 2424 bge_hostaddr ifHCInMulticastPkts; 2425 bge_hostaddr ifHCInBroadcastPkts; 2426 bge_hostaddr dot3StatsFCSErrors; 2427 bge_hostaddr dot3StatsAlignmentErrors; 2428 bge_hostaddr xonPauseFramesReceived; 2429 bge_hostaddr xoffPauseFramesReceived; 2430 bge_hostaddr macControlFramesReceived; 2431 bge_hostaddr xoffStateEntered; 2432 bge_hostaddr dot3StatsFramesTooLong; 2433 bge_hostaddr etherStatsJabbers; 2434 bge_hostaddr etherStatsUndersizePkts; 2435 bge_hostaddr inRangeLengthError; 2436 bge_hostaddr outRangeLengthError; 2437 bge_hostaddr etherStatsPkts64Octets; 2438 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2439 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2440 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2441 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2442 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2443 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2444 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2445 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2446 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2447}; 2448 2449 2450/* Statistics maintained MAC Transmit block. */ 2451struct bge_tx_mac_stats { 2452 bge_hostaddr ifHCOutOctets; 2453 bge_hostaddr Reserved2; 2454 bge_hostaddr etherStatsCollisions; 2455 bge_hostaddr outXonSent; 2456 bge_hostaddr outXoffSent; 2457 bge_hostaddr flowControlDone; 2458 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2459 bge_hostaddr dot3StatsSingleCollisionFrames; 2460 bge_hostaddr dot3StatsMultipleCollisionFrames; 2461 bge_hostaddr dot3StatsDeferredTransmissions; 2462 bge_hostaddr Reserved3; 2463 bge_hostaddr dot3StatsExcessiveCollisions; 2464 bge_hostaddr dot3StatsLateCollisions; 2465 bge_hostaddr dot3Collided2Times; 2466 bge_hostaddr dot3Collided3Times; 2467 bge_hostaddr dot3Collided4Times; 2468 bge_hostaddr dot3Collided5Times; 2469 bge_hostaddr dot3Collided6Times; 2470 bge_hostaddr dot3Collided7Times; 2471 bge_hostaddr dot3Collided8Times; 2472 bge_hostaddr dot3Collided9Times; 2473 bge_hostaddr dot3Collided10Times; 2474 bge_hostaddr dot3Collided11Times; 2475 bge_hostaddr dot3Collided12Times; 2476 bge_hostaddr dot3Collided13Times; 2477 bge_hostaddr dot3Collided14Times; 2478 bge_hostaddr dot3Collided15Times; 2479 bge_hostaddr ifHCOutUcastPkts; 2480 bge_hostaddr ifHCOutMulticastPkts; 2481 bge_hostaddr ifHCOutBroadcastPkts; 2482 bge_hostaddr dot3StatsCarrierSenseErrors; 2483 bge_hostaddr ifOutDiscards; 2484 bge_hostaddr ifOutErrors; 2485}; 2486 2487/* Stats counters access through registers */ 2488struct bge_mac_stats { 2489 /* TX MAC statistics */ 2490 uint64_t ifHCOutOctets; 2491 uint64_t Reserved0; 2492 uint64_t etherStatsCollisions; 2493 uint64_t outXonSent; 2494 uint64_t outXoffSent; 2495 uint64_t Reserved1; 2496 uint64_t dot3StatsInternalMacTransmitErrors; 2497 uint64_t dot3StatsSingleCollisionFrames; 2498 uint64_t dot3StatsMultipleCollisionFrames; 2499 uint64_t dot3StatsDeferredTransmissions; 2500 uint64_t Reserved2; 2501 uint64_t dot3StatsExcessiveCollisions; 2502 uint64_t dot3StatsLateCollisions; 2503 uint64_t Reserved3[14]; 2504 uint64_t ifHCOutUcastPkts; 2505 uint64_t ifHCOutMulticastPkts; 2506 uint64_t ifHCOutBroadcastPkts; 2507 uint64_t Reserved4[2]; 2508 /* RX MAC statistics */ 2509 uint64_t ifHCInOctets; 2510 uint64_t Reserved5; 2511 uint64_t etherStatsFragments; 2512 uint64_t ifHCInUcastPkts; 2513 uint64_t ifHCInMulticastPkts; 2514 uint64_t ifHCInBroadcastPkts; 2515 uint64_t dot3StatsFCSErrors; 2516 uint64_t dot3StatsAlignmentErrors; 2517 uint64_t xonPauseFramesReceived; 2518 uint64_t xoffPauseFramesReceived; 2519 uint64_t macControlFramesReceived; 2520 uint64_t xoffStateEntered; 2521 uint64_t dot3StatsFramesTooLong; 2522 uint64_t etherStatsJabbers; 2523 uint64_t etherStatsUndersizePkts; 2524 /* Receive List Placement control */ 2525 uint64_t FramesDroppedDueToFilters; 2526 uint64_t DmaWriteQueueFull; 2527 uint64_t DmaWriteHighPriQueueFull; 2528 uint64_t NoMoreRxBDs; 2529 uint64_t InputDiscards; 2530 uint64_t InputErrors; 2531 uint64_t RecvThresholdHit; 2532}; 2533 2534struct bge_stats { 2535 uint8_t Reserved0[256]; 2536 2537 /* Statistics maintained by Receive MAC. */ 2538 struct bge_rx_mac_stats rxstats; 2539 2540 bge_hostaddr Unused1[37]; 2541 2542 /* Statistics maintained by Transmit MAC. */ 2543 struct bge_tx_mac_stats txstats; 2544 2545 bge_hostaddr Unused2[31]; 2546 2547 /* Statistics maintained by Receive List Placement. */ 2548 bge_hostaddr COSIfHCInPkts[16]; 2549 bge_hostaddr COSFramesDroppedDueToFilters; 2550 bge_hostaddr nicDmaWriteQueueFull; 2551 bge_hostaddr nicDmaWriteHighPriQueueFull; 2552 bge_hostaddr nicNoMoreRxBDs; 2553 bge_hostaddr ifInDiscards; 2554 bge_hostaddr ifInErrors; 2555 bge_hostaddr nicRecvThresholdHit; 2556 2557 bge_hostaddr Unused3[9]; 2558 2559 /* Statistics maintained by Send Data Initiator. */ 2560 bge_hostaddr COSIfHCOutPkts[16]; 2561 bge_hostaddr nicDmaReadQueueFull; 2562 bge_hostaddr nicDmaReadHighPriQueueFull; 2563 bge_hostaddr nicSendDataCompQueueFull; 2564 2565 /* Statistics maintained by Host Coalescing. */ 2566 bge_hostaddr nicRingSetSendProdIndex; 2567 bge_hostaddr nicRingStatusUpdate; 2568 bge_hostaddr nicInterrupts; 2569 bge_hostaddr nicAvoidedInterrupts; 2570 bge_hostaddr nicSendThresholdHit; 2571 2572 uint8_t Reserved4[320]; 2573}; 2574 2575/* 2576 * Tigon general information block. This resides in host memory 2577 * and contains the status counters, ring control blocks and 2578 * producer pointers. 2579 */ 2580 2581struct bge_gib { 2582 struct bge_stats bge_stats; 2583 struct bge_rcb bge_tx_rcb[16]; 2584 struct bge_rcb bge_std_rx_rcb; 2585 struct bge_rcb bge_jumbo_rx_rcb; 2586 struct bge_rcb bge_mini_rx_rcb; 2587 struct bge_rcb bge_return_rcb; 2588}; 2589 2590#define BGE_FRAMELEN 1518 2591#define BGE_MAX_FRAMELEN 1536 2592#define BGE_JUMBO_FRAMELEN 9018 2593#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2594#define BGE_MIN_FRAMELEN 60 2595 2596/* 2597 * Other utility macros. 2598 */ 2599#define BGE_INC(x, y) (x) = (x + 1) % y 2600 2601/* 2602 * Register access macros. The Tigon always uses memory mapped register 2603 * accesses and all registers must be accessed with 32 bit operations. 2604 */ 2605 2606#define CSR_WRITE_4(sc, reg, val) \ 2607 bus_write_4(sc->bge_res, reg, val) 2608 2609#define CSR_READ_4(sc, reg) \ 2610 bus_read_4(sc->bge_res, reg) 2611 2612#define BGE_SETBIT(sc, reg, x) \ 2613 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2614#define BGE_CLRBIT(sc, reg, x) \ 2615 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2616 2617#define PCI_SETBIT(dev, reg, x, s) \ 2618 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2619#define PCI_CLRBIT(dev, reg, x, s) \ 2620 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2621 2622/* 2623 * Memory management stuff. 2624 */ 2625 2626#define BGE_NSEG_JUMBO 4 2627#define BGE_NSEG_NEW 32 2628#define BGE_TSOSEG_SZ 4096 2629 2630/* Maximum DMA address for controllers that have 40bit DMA address bug. */ 2631#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2632#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2633#else 2634#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2635#endif 2636 2637#ifdef PAE 2638#define BGE_DMA_BNDRY 0x80000000 2639#else 2640#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 2641#define BGE_DMA_BNDRY 0x100000000 2642#else 2643#define BGE_DMA_BNDRY 0 2644#endif 2645#endif 2646 2647/* 2648 * Ring structures. Most of these reside in host memory and we tell 2649 * the NIC where they are via the ring control blocks. The exceptions 2650 * are the tx and command rings, which live in NIC memory and which 2651 * we access via the shared memory window. 2652 */ 2653 2654struct bge_ring_data { 2655 struct bge_rx_bd *bge_rx_std_ring; 2656 bus_addr_t bge_rx_std_ring_paddr; 2657 struct bge_extrx_bd *bge_rx_jumbo_ring; 2658 bus_addr_t bge_rx_jumbo_ring_paddr; 2659 struct bge_rx_bd *bge_rx_return_ring; 2660 bus_addr_t bge_rx_return_ring_paddr; 2661 struct bge_tx_bd *bge_tx_ring; 2662 bus_addr_t bge_tx_ring_paddr; 2663 struct bge_status_block *bge_status_block; 2664 bus_addr_t bge_status_block_paddr; 2665 struct bge_stats *bge_stats; 2666 bus_addr_t bge_stats_paddr; 2667 struct bge_gib bge_info; 2668}; 2669 2670#define BGE_STD_RX_RING_SZ \ 2671 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2672#define BGE_JUMBO_RX_RING_SZ \ 2673 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2674#define BGE_TX_RING_SZ \ 2675 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2676#define BGE_RX_RTN_RING_SZ(x) \ 2677 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2678 2679#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2680 2681#define BGE_STATS_SZ sizeof (struct bge_stats) 2682 2683/* 2684 * Mbuf pointers. We need these to keep track of the virtual addresses 2685 * of our mbuf chains since we can only convert from physical to virtual, 2686 * not the other way around. 2687 */ 2688struct bge_chain_data { 2689 bus_dma_tag_t bge_parent_tag; 2690 bus_dma_tag_t bge_buffer_tag; 2691 bus_dma_tag_t bge_rx_std_ring_tag; 2692 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2693 bus_dma_tag_t bge_rx_return_ring_tag; 2694 bus_dma_tag_t bge_tx_ring_tag; 2695 bus_dma_tag_t bge_status_tag; 2696 bus_dma_tag_t bge_stats_tag; 2697 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */ 2698 bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */ 2699 bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */ 2700 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2701 bus_dmamap_t bge_rx_std_sparemap; 2702 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2703 bus_dmamap_t bge_rx_jumbo_sparemap; 2704 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2705 bus_dmamap_t bge_rx_std_ring_map; 2706 bus_dmamap_t bge_rx_jumbo_ring_map; 2707 bus_dmamap_t bge_tx_ring_map; 2708 bus_dmamap_t bge_rx_return_ring_map; 2709 bus_dmamap_t bge_status_map; 2710 bus_dmamap_t bge_stats_map; 2711 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2712 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2713 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2714 int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2715 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 2716}; 2717 2718struct bge_dmamap_arg { 2719 bus_addr_t bge_busaddr; 2720}; 2721 2722#define BGE_HWREV_TIGON 0x01 2723#define BGE_HWREV_TIGON_II 0x02 2724#define BGE_TIMEOUT 100000 2725#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2726 2727struct bge_bcom_hack { 2728 int reg; 2729 int val; 2730}; 2731 2732#define ASF_ENABLE 1 2733#define ASF_NEW_HANDSHAKE 2 2734#define ASF_STACKUP 4 2735 2736struct bge_softc { 2737 struct ifnet *bge_ifp; /* interface info */ 2738 device_t bge_dev; 2739 struct mtx bge_mtx; 2740 device_t bge_miibus; 2741 void *bge_intrhand; 2742 struct resource *bge_irq; 2743 struct resource *bge_res; 2744 struct ifmedia bge_ifmedia; /* TBI media info */ 2745 int bge_expcap; 2746 int bge_msicap; 2747 int bge_pcixcap; 2748 uint32_t bge_flags; 2749#define BGE_FLAG_TBI 0x00000001 2750#define BGE_FLAG_JUMBO 0x00000002 2751#define BGE_FLAG_JUMBO_STD 0x00000004 2752#define BGE_FLAG_EADDR 0x00000008 2753#define BGE_FLAG_MII_SERDES 0x00000010 2754#define BGE_FLAG_CPMU_PRESENT 0x00000020 2755#define BGE_FLAG_TAGGED_STATUS 0x00000040 2756#define BGE_FLAG_MSI 0x00000100 2757#define BGE_FLAG_PCIX 0x00000200 2758#define BGE_FLAG_PCIE 0x00000400 2759#define BGE_FLAG_TSO 0x00000800 2760#define BGE_FLAG_TSO3 0x00001000 2761#define BGE_FLAG_JUMBO_FRAME 0x00002000 2762#define BGE_FLAG_5700_FAMILY 0x00010000 2763#define BGE_FLAG_5705_PLUS 0x00020000 2764#define BGE_FLAG_5714_FAMILY 0x00040000 2765#define BGE_FLAG_575X_PLUS 0x00080000 2766#define BGE_FLAG_5755_PLUS 0x00100000 2767#define BGE_FLAG_5788 0x00200000 2768#define BGE_FLAG_5717_PLUS 0x00400000 2769#define BGE_FLAG_40BIT_BUG 0x01000000 2770#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2771#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2772#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2773 uint32_t bge_phy_flags; 2774#define BGE_PHY_WIRESPEED 0x00000001 2775#define BGE_PHY_ADC_BUG 0x00000002 2776#define BGE_PHY_5704_A0_BUG 0x00000004 2777#define BGE_PHY_JITTER_BUG 0x00000008 2778#define BGE_PHY_BER_BUG 0x00000010 2779#define BGE_PHY_ADJUST_TRIM 0x00000020 2780#define BGE_PHY_CRC_BUG 0x00000040 2781#define BGE_PHY_NO_3LED 0x00000080 2782 uint32_t bge_chipid; 2783 uint32_t bge_asicrev; 2784 uint32_t bge_chiprev; 2785 uint8_t bge_asf_mode; 2786 uint8_t bge_asf_count; 2787 struct bge_ring_data bge_ldata; /* rings */ 2788 struct bge_chain_data bge_cdata; /* mbufs */ 2789 uint16_t bge_tx_saved_considx; 2790 uint16_t bge_rx_saved_considx; 2791 uint16_t bge_ev_saved_considx; 2792 uint16_t bge_return_ring_cnt; 2793 uint16_t bge_std; /* current std ring head */ 2794 uint16_t bge_jumbo; /* current jumo ring head */ 2795 uint32_t bge_stat_ticks; 2796 uint32_t bge_rx_coal_ticks; 2797 uint32_t bge_tx_coal_ticks; 2798 uint32_t bge_tx_prodidx; 2799 uint32_t bge_rx_max_coal_bds; 2800 uint32_t bge_tx_max_coal_bds; 2801 uint32_t bge_mi_mode; 2802 int bge_if_flags; 2803 int bge_txcnt; 2804 int bge_link; /* link state */ 2805 int bge_link_evt; /* pending link event */ 2806 int bge_timer; 2807 int bge_forced_collapse; 2808 int bge_forced_udpcsum; 2809 int bge_csum_features; 2810 struct callout bge_stat_ch; 2811 uint32_t bge_rx_discards; 2812 uint32_t bge_tx_discards; 2813 uint32_t bge_tx_collisions; 2814#ifdef DEVICE_POLLING 2815 int rxcycles; 2816#endif /* DEVICE_POLLING */ 2817 struct bge_mac_stats bge_mac_stats; 2818 struct task bge_intr_task; 2819 struct taskqueue *bge_tq; 2820}; 2821 2822#define BGE_LOCK_INIT(_sc, _name) \ 2823 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2824#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2825#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2826#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2827#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2828