if_bgereg.h revision 155180
1101099Srwatson/*- 2166533Srwatson * Copyright (c) 2001 Wind River Systems 3140628Srwatson * Copyright (c) 1997, 1998, 1999, 2001 4172930Srwatson * Bill Paul <wpaul@windriver.com>. All rights reserved. 5101099Srwatson * 6101099Srwatson * Redistribution and use in source and binary forms, with or without 7101099Srwatson * modification, are permitted provided that the following conditions 8101099Srwatson * are met: 9140628Srwatson * 1. Redistributions of source code must retain the above copyright 10140628Srwatson * notice, this list of conditions and the following disclaimer. 11140628Srwatson * 2. Redistributions in binary form must reproduce the above copyright 12140628Srwatson * notice, this list of conditions and the following disclaimer in the 13101099Srwatson * documentation and/or other materials provided with the distribution. 14172930Srwatson * 3. All advertising materials mentioning features or use of this software 15172930Srwatson * must display the following acknowledgement: 16172930Srwatson * This product includes software developed by Bill Paul. 17101099Srwatson * 4. Neither the name of the author nor the names of any co-contributors 18101099Srwatson * may be used to endorse or promote products derived from this software 19101099Srwatson * without specific prior written permission. 20101099Srwatson * 21101099Srwatson * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22101099Srwatson * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23101099Srwatson * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24101099Srwatson * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25101099Srwatson * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26101099Srwatson * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27101099Srwatson * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28101099Srwatson * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29101099Srwatson * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30101099Srwatson * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31101099Srwatson * THE POSSIBILITY OF SUCH DAMAGE. 32101099Srwatson * 33101099Srwatson * $FreeBSD: head/sys/dev/bge/if_bgereg.h 155180 2006-02-01 14:26:35Z oleg $ 34101099Srwatson */ 35101099Srwatson 36101099Srwatson/* 37101099Srwatson * BCM570x memory map. The internal memory layout varies somewhat 38101099Srwatson * depending on whether or not we have external SSRAM attached. 39101099Srwatson * The BCM5700 can have up to 16MB of external memory. The BCM5701 40101099Srwatson * is apparently not designed to use external SSRAM. The mappings 41101099Srwatson * up to the first 4 send rings are the same for both internal and 42101099Srwatson * external memory configurations. Note that mini RX ring space is 43168951Srwatson * only available with external SSRAM configurations, which means 44101099Srwatson * the mini RX ring is not supported on the BCM5701. 45101099Srwatson * 46101099Srwatson * The NIC's memory can be accessed by the host in one of 3 ways: 47101099Srwatson * 48101099Srwatson * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49105988Srwatson * registers in PCI config space can be used to read any 32-bit 50101099Srwatson * address within the NIC's memory. 51164184Strhodes * 52103183Sbde * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53145076Scsjp * space can be used in conjunction with the memory window in the 54101099Srwatson * device register space at offset 0x8000 to read any 32K chunk 55168951Srwatson * of NIC memory. 56101099Srwatson * 57115497Srwatson * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58101099Srwatson * set, the device I/O mapping consumes 32MB of host address space, 59101099Srwatson * allowing all of the registers and internal NIC memory to be 60101099Srwatson * accessed directly. NIC memory addresses are offset by 0x01000000. 61105696Srwatson * Flat mode consumes so much host address space that it is not 62101099Srwatson * recommended. 63101099Srwatson */ 64101099Srwatson#define BGE_PAGE_ZERO 0x00000000 65101099Srwatson#define BGE_PAGE_ZERO_END 0x000000FF 66101099Srwatson#define BGE_SEND_RING_RCB 0x00000100 67150340Sphk#define BGE_SEND_RING_RCB_END 0x000001FF 68101099Srwatson#define BGE_RX_RETURN_RING_RCB 0x00000200 69140628Srwatson#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70140628Srwatson#define BGE_STATS_BLOCK 0x00000300 71140628Srwatson#define BGE_STATS_BLOCK_END 0x00000AFF 72101099Srwatson#define BGE_STATUS_BLOCK 0x00000B00 73101099Srwatson#define BGE_STATUS_BLOCK_END 0x00000B4F 74101099Srwatson#define BGE_SOFTWARE_GENCOMM 0x00000B50 75101099Srwatson#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76101099Srwatson#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77101099Srwatson#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 78101099Srwatson#define BGE_UNMAPPED 0x00001000 79101099Srwatson#define BGE_UNMAPPED_END 0x00001FFF 80101099Srwatson#define BGE_DMA_DESCRIPTORS 0x00002000 81122875Srwatson#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 82101099Srwatson#define BGE_SEND_RING_1_TO_4 0x00004000 83101099Srwatson#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 84122879Srwatson 85101099Srwatson/* Mappings for internal memory configuration */ 86101099Srwatson#define BGE_STD_RX_RINGS 0x00006000 87165469Srwatson#define BGE_STD_RX_RINGS_END 0x00006FFF 88101099Srwatson#define BGE_JUMBO_RX_RINGS 0x00007000 89101099Srwatson#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 90101099Srwatson#define BGE_BUFFPOOL_1 0x00008000 91101099Srwatson#define BGE_BUFFPOOL_1_END 0x0000FFFF 92101099Srwatson#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 93101099Srwatson#define BGE_BUFFPOOL_2_END 0x00017FFF 94101099Srwatson#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 95172955Srwatson#define BGE_BUFFPOOL_3_END 0x0001FFFF 96105988Srwatson 97172955Srwatson/* Mappings for external SSRAM configurations */ 98105988Srwatson#define BGE_SEND_RING_5_TO_6 0x00006000 99172955Srwatson#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 100172955Srwatson#define BGE_SEND_RING_7_TO_8 0x00007000 101172955Srwatson#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 102172955Srwatson#define BGE_SEND_RING_9_TO_16 0x00008000 103101099Srwatson#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 104101099Srwatson#define BGE_EXT_STD_RX_RINGS 0x0000C000 105101099Srwatson#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 106101099Srwatson#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 107101099Srwatson#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 108101099Srwatson#define BGE_MINI_RX_RINGS 0x0000E000 109101099Srwatson#define BGE_MINI_RX_RINGS_END 0x0000FFFF 110101099Srwatson#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 111101099Srwatson#define BGE_AVAIL_REGION1_END 0x00017FFF 112101099Srwatson#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 113101099Srwatson#define BGE_AVAIL_REGION2_END 0x0001FFFF 114101099Srwatson#define BGE_EXT_SSRAM 0x00020000 115101099Srwatson#define BGE_EXT_SSRAM_END 0x000FFFFF 116101099Srwatson 117101099Srwatson 118101099Srwatson/* 119105643Srwatson * BCM570x register offsets. These are memory mapped registers 120105643Srwatson * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 121105643Srwatson * Each register must be accessed using 32 bit operations. 122105643Srwatson * 123105606Srwatson * All registers are accessed through a 32K shared memory block. 124181217Srwatson * The first group of registers are actually copies of the PCI 125181217Srwatson * configuration space registers. 126105606Srwatson */ 127105606Srwatson 128153927Scsjp/* 129153927Scsjp * PCI registers defined in the PCI 2.2 spec. 130153927Scsjp */ 131153927Scsjp#define BGE_PCI_VID 0x00 132153927Scsjp#define BGE_PCI_DID 0x02 133105637Srwatson#define BGE_PCI_CMD 0x04 134101099Srwatson#define BGE_PCI_STS 0x06 135105637Srwatson#define BGE_PCI_REV 0x08 136105637Srwatson#define BGE_PCI_CLASS 0x09 137101099Srwatson#define BGE_PCI_CACHESZ 0x0C 138172955Srwatson#define BGE_PCI_LATTIMER 0x0D 139172955Srwatson#define BGE_PCI_HDRTYPE 0x0E 140172955Srwatson#define BGE_PCI_BIST 0x0F 141101099Srwatson#define BGE_PCI_BAR0 0x10 142122879Srwatson#define BGE_PCI_BAR1 0x14 143101099Srwatson#define BGE_PCI_SUBSYS 0x2C 144105643Srwatson#define BGE_PCI_SUBVID 0x2E 145105643Srwatson#define BGE_PCI_ROMBASE 0x30 146105643Srwatson#define BGE_PCI_CAPPTR 0x34 147105643Srwatson#define BGE_PCI_INTLINE 0x3C 148105643Srwatson#define BGE_PCI_INTPIN 0x3D 149105643Srwatson#define BGE_PCI_MINGNT 0x3E 150105643Srwatson#define BGE_PCI_MAXLAT 0x3F 151105643Srwatson#define BGE_PCI_PCIXCAP 0x40 152105643Srwatson#define BGE_PCI_NEXTPTR_PM 0x41 153105643Srwatson#define BGE_PCI_PCIX_CMD 0x42 154101099Srwatson#define BGE_PCI_PCIX_STS 0x44 155104514Srwatson#define BGE_PCI_PWRMGMT_CAPID 0x48 156101099Srwatson#define BGE_PCI_NEXTPTR_VPD 0x49 157101099Srwatson#define BGE_PCI_PWRMGMT_CAPS 0x4A 158122879Srwatson#define BGE_PCI_PWRMGMT_CMD 0x4C 159101099Srwatson#define BGE_PCI_PWRMGMT_STS 0x4D 160101099Srwatson#define BGE_PCI_PWRMGMT_DATA 0x4F 161101099Srwatson#define BGE_PCI_VPD_CAPID 0x50 162172955Srwatson#define BGE_PCI_NEXTPTR_MSI 0x51 163101099Srwatson#define BGE_PCI_VPD_ADDR 0x52 164101099Srwatson#define BGE_PCI_VPD_DATA 0x54 165172955Srwatson#define BGE_PCI_MSI_CAPID 0x58 166172955Srwatson#define BGE_PCI_NEXTPTR_NONE 0x59 167101099Srwatson#define BGE_PCI_MSI_CTL 0x5A 168101099Srwatson#define BGE_PCI_MSI_ADDR_HI 0x5C 169101099Srwatson#define BGE_PCI_MSI_ADDR_LO 0x60 170101099Srwatson#define BGE_PCI_MSI_DATA 0x64 171101099Srwatson 172172955Srwatson/* PCI MSI. ??? */ 173105634Srwatson#define BGE_PCIE_CAPID_REG 0xD0 174105634Srwatson#define BGE_PCIE_CAPID 0x10 175172955Srwatson 176105634Srwatson/* 177105634Srwatson * PCI registers specific to the BCM570x family. 178105634Srwatson */ 179105634Srwatson#define BGE_PCI_MISC_CTL 0x68 180105634Srwatson#define BGE_PCI_DMA_RW_CTL 0x6C 181172955Srwatson#define BGE_PCI_PCISTATE 0x70 182101099Srwatson#define BGE_PCI_CLKCTL 0x74 183105643Srwatson#define BGE_PCI_REG_BASEADDR 0x78 184101099Srwatson#define BGE_PCI_MEMWIN_BASEADDR 0x7C 185105736Srwatson#define BGE_PCI_REG_DATA 0x80 186101099Srwatson#define BGE_PCI_MEMWIN_DATA 0x84 187101099Srwatson#define BGE_PCI_MODECTL 0x88 188101099Srwatson#define BGE_PCI_MISC_CFG 0x8C 189101099Srwatson#define BGE_PCI_MISC_LOCALCTL 0x90 190101099Srwatson#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 191101099Srwatson#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 192101099Srwatson#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 193101099Srwatson#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 194101099Srwatson#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 195101099Srwatson#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 196101099Srwatson#define BGE_PCI_ISR_MBX_HI 0xB0 197101099Srwatson#define BGE_PCI_ISR_MBX_LO 0xB4 198101099Srwatson 199101099Srwatson/* PCI Misc. Host control register */ 200101099Srwatson#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 201172955Srwatson#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 202101099Srwatson#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 203101099Srwatson#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 204101099Srwatson#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 205101099Srwatson#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 206101099Srwatson#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 207101099Srwatson#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 208101099Srwatson#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 209101099Srwatson 210101099Srwatson#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 211101099Srwatson#if BYTE_ORDER == LITTLE_ENDIAN 212101099Srwatson#define BGE_DMA_SWAP_OPTIONS \ 213101099Srwatson BGE_MODECTL_WORDSWAP_NONFRAME| \ 214105643Srwatson BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 215105643Srwatson#else 216105643Srwatson#define BGE_DMA_SWAP_OPTIONS \ 217105643Srwatson BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 218105643Srwatson BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 219101099Srwatson#endif 220101099Srwatson 221101099Srwatson#define BGE_INIT \ 222172955Srwatson (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 223101099Srwatson BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 224101099Srwatson 225101099Srwatson#define BGE_CHIPID_TIGON_I 0x40000000 226172955Srwatson#define BGE_CHIPID_TIGON_II 0x60000000 227101099Srwatson#define BGE_CHIPID_BCM5700_B0 0x71000000 228101099Srwatson#define BGE_CHIPID_BCM5700_B1 0x71020000 229101099Srwatson#define BGE_CHIPID_BCM5700_B2 0x71030000 230101099Srwatson#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 231101099Srwatson#define BGE_CHIPID_BCM5700_C0 0x72000000 232101099Srwatson#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 233172955Srwatson#define BGE_CHIPID_BCM5701_B0 0x01000000 234105988Srwatson#define BGE_CHIPID_BCM5701_B2 0x01020000 235105988Srwatson#define BGE_CHIPID_BCM5701_B5 0x01050000 236105988Srwatson#define BGE_CHIPID_BCM5703_A0 0x10000000 237172955Srwatson#define BGE_CHIPID_BCM5703_A1 0x10010000 238172955Srwatson#define BGE_CHIPID_BCM5703_A2 0x10020000 239172955Srwatson#define BGE_CHIPID_BCM5704_A0 0x20000000 240105988Srwatson#define BGE_CHIPID_BCM5704_A1 0x20010000 241105988Srwatson#define BGE_CHIPID_BCM5704_A2 0x20020000 242105988Srwatson#define BGE_CHIPID_BCM5705_A0 0x30000000 243105988Srwatson#define BGE_CHIPID_BCM5705_A1 0x30010000 244105988Srwatson#define BGE_CHIPID_BCM5705_A2 0x30020000 245105988Srwatson#define BGE_CHIPID_BCM5705_A3 0x30030000 246172955Srwatson#define BGE_CHIPID_BCM5750_A0 0x40000000 247101099Srwatson#define BGE_CHIPID_BCM5750_A1 0x40010000 248101099Srwatson#define BGE_CHIPID_BCM5714_A0 0x50000000 249172955Srwatson 250101099Srwatson/* shorthand one */ 251172955Srwatson#define BGE_ASICREV(x) ((x) >> 28) 252101099Srwatson#define BGE_ASICREV_BCM5700 0x07 253101099Srwatson#define BGE_ASICREV_BCM5701 0x00 254101099Srwatson#define BGE_ASICREV_BCM5703 0x01 255101099Srwatson#define BGE_ASICREV_BCM5704 0x02 256172955Srwatson#define BGE_ASICREV_BCM5705 0x03 257101099Srwatson#define BGE_ASICREV_BCM5750 0x04 258101099Srwatson#define BGE_ASICREV_BCM5714 0x05 259132232Srwatson#define BGE_ASICREV_BCM5752 0x06 260172955Srwatson 261103750Srwatson/* chip revisions */ 262172955Srwatson#define BGE_CHIPREV(x) ((x) >> 24) 263101099Srwatson#define BGE_CHIPREV_5700_AX 0x70 264172955Srwatson#define BGE_CHIPREV_5700_BX 0x71 265132232Srwatson#define BGE_CHIPREV_5700_CX 0x72 266172955Srwatson#define BGE_CHIPREV_5701_AX 0x00 267101099Srwatson 268101099Srwatson/* PCI DMA Read/Write Control register */ 269101099Srwatson#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 270101099Srwatson#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 271101099Srwatson#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 272101099Srwatson#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 273172955Srwatson#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 274101099Srwatson# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 275132232Srwatson#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 276172955Srwatson# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 277132232Srwatson#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 278172955Srwatson#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 279101099Srwatson#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 280172955Srwatson# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 281101099Srwatson#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 282101099Srwatson# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 283101099Srwatson 284172955Srwatson#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 285101099Srwatson#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 286101099Srwatson#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 287101099Srwatson#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 288101099Srwatson#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 289101099Srwatson#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 290101099Srwatson#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 291101099Srwatson#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 292101099Srwatson 293101099Srwatson#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 294101099Srwatson#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 295172955Srwatson#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 296101099Srwatson#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 297101099Srwatson#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 298132232Srwatson#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 299172955Srwatson#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 300132232Srwatson#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 301172955Srwatson 302101099Srwatson/* 303172955Srwatson * PCI state register -- note, this register is read only 304101099Srwatson * unless the PCISTATE_WR bit of the PCI Misc. Host Control 305101099Srwatson * register is set. 306101099Srwatson */ 307172955Srwatson#define BGE_PCISTATE_FORCE_RESET 0x00000001 308105634Srwatson#define BGE_PCISTATE_INTR_STATE 0x00000002 309105634Srwatson#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 310172955Srwatson#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 311172955Srwatson#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 312105634Srwatson#define BGE_PCISTATE_WANT_EXPROM 0x00000020 313172955Srwatson#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 314105634Srwatson#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 315172955Srwatson#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 316172955Srwatson 317105634Srwatson/* 318172955Srwatson * PCI Clock Control register -- note, this register is read only 319105637Srwatson * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 320105634Srwatson * register is set. 321105634Srwatson */ 322105634Srwatson#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 323105634Srwatson#define BGE_PCICLOCKCTL_M66EN 0x00000080 324105634Srwatson#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 325105634Srwatson#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 326172955Srwatson#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 327105634Srwatson#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 328105634Srwatson#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 329172955Srwatson#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 330172955Srwatson#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 331105634Srwatson#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 332132232Srwatson 333172955Srwatson 334105634Srwatson#ifndef PCIM_CMD_MWIEN 335105634Srwatson#define PCIM_CMD_MWIEN 0x0010 336105634Srwatson#endif 337172955Srwatson 338172955Srwatson/* 339105634Srwatson * High priority mailbox registers 340105634Srwatson * Each mailbox is 64-bits wide, though we only use the 341105634Srwatson * lower 32 bits. To write a 64-bit value, write the upper 32 bits 342172955Srwatson * first. The NIC will load the mailbox after the lower 32 bit word 343172955Srwatson * has been updated. 344105634Srwatson */ 345105634Srwatson#define BGE_MBX_IRQ0_HI 0x0200 346105634Srwatson#define BGE_MBX_IRQ0_LO 0x0204 347105634Srwatson#define BGE_MBX_IRQ1_HI 0x0208 348105634Srwatson#define BGE_MBX_IRQ1_LO 0x020C 349105634Srwatson#define BGE_MBX_IRQ2_HI 0x0210 350106091Srwatson#define BGE_MBX_IRQ2_LO 0x0214 351172955Srwatson#define BGE_MBX_IRQ3_HI 0x0218 352105988Srwatson#define BGE_MBX_IRQ3_LO 0x021C 353105988Srwatson#define BGE_MBX_GEN0_HI 0x0220 354172955Srwatson#define BGE_MBX_GEN0_LO 0x0224 355172955Srwatson#define BGE_MBX_GEN1_HI 0x0228 356105988Srwatson#define BGE_MBX_GEN1_LO 0x022C 357172955Srwatson#define BGE_MBX_GEN2_HI 0x0230 358105988Srwatson#define BGE_MBX_GEN2_LO 0x0234 359105988Srwatson#define BGE_MBX_GEN3_HI 0x0228 360105634Srwatson#define BGE_MBX_GEN3_LO 0x022C 361172955Srwatson#define BGE_MBX_GEN4_HI 0x0240 362101099Srwatson#define BGE_MBX_GEN4_LO 0x0244 363101099Srwatson#define BGE_MBX_GEN5_HI 0x0248 364172955Srwatson#define BGE_MBX_GEN5_LO 0x024C 365172955Srwatson#define BGE_MBX_GEN6_HI 0x0250 366101099Srwatson#define BGE_MBX_GEN6_LO 0x0254 367101099Srwatson#define BGE_MBX_GEN7_HI 0x0258 368101099Srwatson#define BGE_MBX_GEN7_LO 0x025C 369101099Srwatson#define BGE_MBX_RELOAD_STATS_HI 0x0260 370101099Srwatson#define BGE_MBX_RELOAD_STATS_LO 0x0264 371101099Srwatson#define BGE_MBX_RX_STD_PROD_HI 0x0268 372172955Srwatson#define BGE_MBX_RX_STD_PROD_LO 0x026C 373105643Srwatson#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 374172955Srwatson#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 375101099Srwatson#define BGE_MBX_RX_MINI_PROD_HI 0x0278 376101099Srwatson#define BGE_MBX_RX_MINI_PROD_LO 0x027C 377101099Srwatson#define BGE_MBX_RX_CONS0_HI 0x0280 378101099Srwatson#define BGE_MBX_RX_CONS0_LO 0x0284 379101099Srwatson#define BGE_MBX_RX_CONS1_HI 0x0288 380101099Srwatson#define BGE_MBX_RX_CONS1_LO 0x028C 381101099Srwatson#define BGE_MBX_RX_CONS2_HI 0x0290 382172955Srwatson#define BGE_MBX_RX_CONS2_LO 0x0294 383101099Srwatson#define BGE_MBX_RX_CONS3_HI 0x0298 384101099Srwatson#define BGE_MBX_RX_CONS3_LO 0x029C 385101099Srwatson#define BGE_MBX_RX_CONS4_HI 0x02A0 386172955Srwatson#define BGE_MBX_RX_CONS4_LO 0x02A4 387172955Srwatson#define BGE_MBX_RX_CONS5_HI 0x02A8 388101099Srwatson#define BGE_MBX_RX_CONS5_LO 0x02AC 389101099Srwatson#define BGE_MBX_RX_CONS6_HI 0x02B0 390101099Srwatson#define BGE_MBX_RX_CONS6_LO 0x02B4 391101099Srwatson#define BGE_MBX_RX_CONS7_HI 0x02B8 392101099Srwatson#define BGE_MBX_RX_CONS7_LO 0x02BC 393101099Srwatson#define BGE_MBX_RX_CONS8_HI 0x02C0 394172955Srwatson#define BGE_MBX_RX_CONS8_LO 0x02C4 395105643Srwatson#define BGE_MBX_RX_CONS9_HI 0x02C8 396172955Srwatson#define BGE_MBX_RX_CONS9_LO 0x02CC 397101099Srwatson#define BGE_MBX_RX_CONS10_HI 0x02D0 398101099Srwatson#define BGE_MBX_RX_CONS10_LO 0x02D4 399101099Srwatson#define BGE_MBX_RX_CONS11_HI 0x02D8 400101099Srwatson#define BGE_MBX_RX_CONS11_LO 0x02DC 401101099Srwatson#define BGE_MBX_RX_CONS12_HI 0x02E0 402101099Srwatson#define BGE_MBX_RX_CONS12_LO 0x02E4 403101099Srwatson#define BGE_MBX_RX_CONS13_HI 0x02E8 404172955Srwatson#define BGE_MBX_RX_CONS13_LO 0x02EC 405101099Srwatson#define BGE_MBX_RX_CONS14_HI 0x02F0 406101099Srwatson#define BGE_MBX_RX_CONS14_LO 0x02F4 407101099Srwatson#define BGE_MBX_RX_CONS15_HI 0x02F8 408101099Srwatson#define BGE_MBX_RX_CONS15_LO 0x02FC 409101099Srwatson#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 410101099Srwatson#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 411172955Srwatson#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 412105643Srwatson#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 413172955Srwatson#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 414101099Srwatson#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 415101099Srwatson#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 416101099Srwatson#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 417101099Srwatson#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 418101099Srwatson#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 419101099Srwatson#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 420172955Srwatson#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 421172955Srwatson#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 422101099Srwatson#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 423101099Srwatson#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 424172955Srwatson#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 425172955Srwatson#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 426101099Srwatson#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 427101099Srwatson#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 428101099Srwatson#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 429101099Srwatson#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 430101099Srwatson#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 431101099Srwatson#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 432101099Srwatson#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 433172955Srwatson#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 434172955Srwatson#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 435172955Srwatson#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 436101099Srwatson#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 437101099Srwatson#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 438172955Srwatson#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 439172955Srwatson#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 440105643Srwatson#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 441172955Srwatson#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 442172955Srwatson#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 443172955Srwatson#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 444172955Srwatson#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 445105643Srwatson#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 446172955Srwatson#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 447172955Srwatson#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 448172955Srwatson#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 449101099Srwatson#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 450101099Srwatson#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 451101099Srwatson#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 452172955Srwatson#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 453105643Srwatson#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 454101099Srwatson#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 455101099Srwatson#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 456172955Srwatson#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 457172955Srwatson#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 458105643Srwatson#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 459172955Srwatson#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 460172955Srwatson#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 461172955Srwatson#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 462101099Srwatson#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 463101099Srwatson#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 464101099Srwatson#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 465172955Srwatson#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 466101099Srwatson#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 467105643Srwatson#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 468101099Srwatson#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 469172955Srwatson#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 470101099Srwatson#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 471101099Srwatson#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 472101099Srwatson#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 473101099Srwatson 474101099Srwatson#define BGE_TX_RINGS_MAX 4 475101099Srwatson#define BGE_TX_RINGS_EXTSSRAM_MAX 16 476101099Srwatson#define BGE_RX_RINGS_MAX 16 477172955Srwatson 478101099Srwatson/* Ethernet MAC control registers */ 479101099Srwatson#define BGE_MAC_MODE 0x0400 480132232Srwatson#define BGE_MAC_STS 0x0404 481172955Srwatson#define BGE_MAC_EVT_ENB 0x0408 482101099Srwatson#define BGE_MAC_LED_CTL 0x040C 483132232Srwatson#define BGE_MAC_ADDR1_LO 0x0410 484132232Srwatson#define BGE_MAC_ADDR1_HI 0x0414 485101099Srwatson#define BGE_MAC_ADDR2_LO 0x0418 486101099Srwatson#define BGE_MAC_ADDR2_HI 0x041C 487105656Srwatson#define BGE_MAC_ADDR3_LO 0x0420 488172955Srwatson#define BGE_MAC_ADDR3_HI 0x0424 489105656Srwatson#define BGE_MAC_ADDR4_LO 0x0428 490105656Srwatson#define BGE_MAC_ADDR4_HI 0x042C 491132232Srwatson#define BGE_WOL_PATPTR 0x0430 492172955Srwatson#define BGE_WOL_PATCFG 0x0434 493105656Srwatson#define BGE_TX_RANDOM_BACKOFF 0x0438 494172955Srwatson#define BGE_RX_MTU 0x043C 495105656Srwatson#define BGE_GBIT_PCS_TEST 0x0440 496105656Srwatson#define BGE_TX_TBI_AUTONEG 0x0444 497101099Srwatson#define BGE_RX_TBI_AUTONEG 0x0448 498101099Srwatson#define BGE_MI_COMM 0x044C 499101099Srwatson#define BGE_MI_STS 0x0450 500101099Srwatson#define BGE_MI_MODE 0x0454 501172955Srwatson#define BGE_AUTOPOLL_STS 0x0458 502101099Srwatson#define BGE_TX_MODE 0x045C 503101099Srwatson#define BGE_TX_STS 0x0460 504122879Srwatson#define BGE_TX_LENGTHS 0x0464 505122879Srwatson#define BGE_RX_MODE 0x0468 506101099Srwatson#define BGE_RX_STS 0x046C 507101099Srwatson#define BGE_MAR0 0x0470 508101099Srwatson#define BGE_MAR1 0x0474 509101099Srwatson#define BGE_MAR2 0x0478 510101099Srwatson#define BGE_MAR3 0x047C 511101099Srwatson#define BGE_RX_BD_RULES_CTL0 0x0480 512172955Srwatson#define BGE_RX_BD_RULES_MASKVAL0 0x0484 513101099Srwatson#define BGE_RX_BD_RULES_CTL1 0x0488 514101099Srwatson#define BGE_RX_BD_RULES_MASKVAL1 0x048C 515132781Skan#define BGE_RX_BD_RULES_CTL2 0x0490 516101099Srwatson#define BGE_RX_BD_RULES_MASKVAL2 0x0494 517101099Srwatson#define BGE_RX_BD_RULES_CTL3 0x0498 518101099Srwatson#define BGE_RX_BD_RULES_MASKVAL3 0x049C 519172955Srwatson#define BGE_RX_BD_RULES_CTL4 0x04A0 520101099Srwatson#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 521101099Srwatson#define BGE_RX_BD_RULES_CTL5 0x04A8 522132781Skan#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 523101099Srwatson#define BGE_RX_BD_RULES_CTL6 0x04B0 524101099Srwatson#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 525101099Srwatson#define BGE_RX_BD_RULES_CTL7 0x04B8 526101099Srwatson#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 527101099Srwatson#define BGE_RX_BD_RULES_CTL8 0x04C0 528101099Srwatson#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 529101099Srwatson#define BGE_RX_BD_RULES_CTL9 0x04C8 530172955Srwatson#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 531101099Srwatson#define BGE_RX_BD_RULES_CTL10 0x04D0 532101099Srwatson#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 533101099Srwatson#define BGE_RX_BD_RULES_CTL11 0x04D8 534132781Skan#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 535101099Srwatson#define BGE_RX_BD_RULES_CTL12 0x04E0 536101099Srwatson#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 537105696Srwatson#define BGE_RX_BD_RULES_CTL13 0x04E8 538172955Srwatson#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 539172955Srwatson#define BGE_RX_BD_RULES_CTL14 0x04F0 540172955Srwatson#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 541105696Srwatson#define BGE_RX_BD_RULES_CTL15 0x04F8 542115497Srwatson#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 543172955Srwatson#define BGE_RX_RULES_CFG 0x0500 544105696Srwatson#define BGE_SERDES_CFG 0x0590 545115497Srwatson#define BGE_SERDES_STS 0x0594 546105696Srwatson#define BGE_SGDIG_CFG 0x05B0 547105696Srwatson#define BGE_SGDIG_STS 0x05B4 548105696Srwatson#define BGE_RX_STATS 0x0800 549115497Srwatson#define BGE_TX_STATS 0x0880 550105696Srwatson 551105696Srwatson/* Ethernet MAC Mode register */ 552115497Srwatson#define BGE_MACMODE_RESET 0x00000001 553105696Srwatson#define BGE_MACMODE_HALF_DUPLEX 0x00000002 554105696Srwatson#define BGE_MACMODE_PORTMODE 0x0000000C 555115497Srwatson#define BGE_MACMODE_LOOPBACK 0x00000010 556105696Srwatson#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 557105696Srwatson#define BGE_MACMODE_TX_BURST_ENB 0x00000100 558115497Srwatson#define BGE_MACMODE_MAX_DEFER 0x00000200 559115497Srwatson#define BGE_MACMODE_LINK_POLARITY 0x00000400 560115497Srwatson#define BGE_MACMODE_RX_STATS_ENB 0x00000800 561115497Srwatson#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 562115497Srwatson#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 563115497Srwatson#define BGE_MACMODE_TX_STATS_ENB 0x00004000 564115497Srwatson#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 565115497Srwatson#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 566115497Srwatson#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 567115497Srwatson#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 568115497Srwatson#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 569115497Srwatson#define BGE_MACMODE_MIP_ENB 0x00100000 570115497Srwatson#define BGE_MACMODE_TXDMA_ENB 0x00200000 571115497Srwatson#define BGE_MACMODE_RXDMA_ENB 0x00400000 572115497Srwatson#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 573115497Srwatson 574115497Srwatson#define BGE_PORTMODE_NONE 0x00000000 575105696Srwatson#define BGE_PORTMODE_MII 0x00000004 576115497Srwatson#define BGE_PORTMODE_GMII 0x00000008 577105696Srwatson#define BGE_PORTMODE_TBI 0x0000000C 578105696Srwatson 579172955Srwatson/* MAC Status register */ 580105696Srwatson#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 581105696Srwatson#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 582105696Srwatson#define BGE_MACSTAT_RX_CFG 0x00000004 583105696Srwatson#define BGE_MACSTAT_CFG_CHANGED 0x00000008 584115497Srwatson#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 585172955Srwatson#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 586172955Srwatson#define BGE_MACSTAT_LINK_CHANGED 0x00001000 587172955Srwatson#define BGE_MACSTAT_MI_COMPLETE 0x00400000 588172955Srwatson#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 589172955Srwatson#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 590115497Srwatson#define BGE_MACSTAT_ODI_ERROR 0x02000000 591101099Srwatson#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 592172955Srwatson#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 593101099Srwatson 594105696Srwatson/* MAC Event Enable Register */ 595172955Srwatson#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 596172955Srwatson#define BGE_EVTENB_LINK_CHANGED 0x00001000 597105696Srwatson#define BGE_EVTENB_MI_COMPLETE 0x00400000 598105696Srwatson#define BGE_EVTENB_MI_INTERRUPT 0x00800000 599105696Srwatson#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 600172955Srwatson#define BGE_EVTENB_ODI_ERROR 0x02000000 601116701Srwatson#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 602105696Srwatson#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 603105696Srwatson 604172955Srwatson/* LED Control Register */ 605105696Srwatson#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 606105696Srwatson#define BGE_LEDCTL_1000MBPS_LED 0x00000002 607116701Srwatson#define BGE_LEDCTL_100MBPS_LED 0x00000004 608105696Srwatson#define BGE_LEDCTL_10MBPS_LED 0x00000008 609105696Srwatson#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 610172955Srwatson#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 611105696Srwatson#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 612105696Srwatson#define BGE_LEDCTL_1000MBPS_STS 0x00000080 613116701Srwatson#define BGE_LEDCTL_100MBPS_STS 0x00000100 614105696Srwatson#define BGE_LEDCTL_10MBPS_STS 0x00000200 615105696Srwatson#define BGE_LEDCTL_TRADLED_STS 0x00000400 616105696Srwatson#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 617105696Srwatson#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 618105696Srwatson 619105696Srwatson/* TX backoff seed register */ 620105696Srwatson#define BGE_TX_BACKOFF_SEED_MASK 0x3F 621172955Srwatson 622116701Srwatson/* Autopoll status register */ 623105696Srwatson#define BGE_AUTOPOLLSTS_ERROR 0x00000001 624172955Srwatson 625101099Srwatson/* Transmit MAC mode register */ 626105696Srwatson#define BGE_TXMODE_RESET 0x00000001 627105696Srwatson#define BGE_TXMODE_ENABLE 0x00000002 628105696Srwatson#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 629105696Srwatson#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 630105696Srwatson#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 631172955Srwatson 632172955Srwatson/* Transmit MAC status register */ 633105696Srwatson#define BGE_TXSTAT_RX_XOFFED 0x00000001 634105696Srwatson#define BGE_TXSTAT_SENT_XOFF 0x00000002 635105696Srwatson#define BGE_TXSTAT_SENT_XON 0x00000004 636172955Srwatson#define BGE_TXSTAT_LINK_UP 0x00000008 637101099Srwatson#define BGE_TXSTAT_ODI_UFLOW 0x00000010 638115395Srwatson#define BGE_TXSTAT_ODI_OFLOW 0x00000020 639115395Srwatson 640105696Srwatson/* Transmit MAC lengths register */ 641181217Srwatson#define BGE_TXLEN_SLOTTIME 0x000000FF 642105696Srwatson#define BGE_TXLEN_IPG 0x00000F00 643105696Srwatson#define BGE_TXLEN_CRS 0x00003000 644181217Srwatson 645105696Srwatson/* Receive MAC mode register */ 646105696Srwatson#define BGE_RXMODE_RESET 0x00000001 647105696Srwatson#define BGE_RXMODE_ENABLE 0x00000002 648105696Srwatson#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 649105696Srwatson#define BGE_RXMODE_RX_GIANTS 0x00000020 650105696Srwatson#define BGE_RXMODE_RX_RUNTS 0x00000040 651105696Srwatson#define BGE_RXMODE_8022_LENCHECK 0x00000080 652115395Srwatson#define BGE_RXMODE_RX_PROMISC 0x00000100 653105696Srwatson#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 654115395Srwatson#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 655115395Srwatson 656115395Srwatson/* Receive MAC status register */ 657115395Srwatson#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 658115395Srwatson#define BGE_RXSTAT_RCVD_XOFF 0x00000002 659115395Srwatson#define BGE_RXSTAT_RCVD_XON 0x00000004 660105696Srwatson 661115395Srwatson/* Receive Rules Control register */ 662115395Srwatson#define BGE_RXRULECTL_OFFSET 0x000000FF 663115395Srwatson#define BGE_RXRULECTL_CLASS 0x00001F00 664105696Srwatson#define BGE_RXRULECTL_HDRTYPE 0x0000E000 665115395Srwatson#define BGE_RXRULECTL_COMPARE_OP 0x00030000 666181217Srwatson#define BGE_RXRULECTL_MAP 0x01000000 667181217Srwatson#define BGE_RXRULECTL_DISCARD 0x02000000 668115395Srwatson#define BGE_RXRULECTL_MASK 0x04000000 669115395Srwatson#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 670115395Srwatson#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 671115395Srwatson#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 672115395Srwatson#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 673105696Srwatson 674115395Srwatson/* Receive Rules Mask register */ 675115395Srwatson#define BGE_RXRULEMASK_VALUE 0x0000FFFF 676115395Srwatson#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 677105696Srwatson 678115395Srwatson/* SERDES configuration register */ 679105696Srwatson#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 680115395Srwatson#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 681105696Srwatson#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 682105696Srwatson#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 683105696Srwatson#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 684105696Srwatson#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 685105696Srwatson#define BGE_SERDESCFG_TXMODE 0x00001000 686105696Srwatson#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 687105696Srwatson#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 688181217Srwatson#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 689181217Srwatson#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 690105696Srwatson#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 691105696Srwatson#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 692172955Srwatson#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 693105696Srwatson#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 694132232Srwatson#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 695101099Srwatson 696101099Srwatson/* SERDES status register */ 697132232Srwatson#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 698132232Srwatson#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 699132232Srwatson 700115395Srwatson/* SGDIG config (not documented) */ 701115395Srwatson#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 702115395Srwatson#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 703115395Srwatson#define BGE_SGDIGCFG_SEND 0x40000000 704105696Srwatson#define BGE_SGDIGCFG_AUTO 0x80000000 705115395Srwatson 706115395Srwatson/* SGDIG status (not documented) */ 707105696Srwatson#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 708115395Srwatson#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 709105696Srwatson#define BGE_SGDIGSTS_DONE 0x00000002 710115395Srwatson 711115395Srwatson 712115395Srwatson/* MI communication register */ 713105696Srwatson#define BGE_MICOMM_DATA 0x0000FFFF 714115395Srwatson#define BGE_MICOMM_REG 0x001F0000 715105696Srwatson#define BGE_MICOMM_PHY 0x03E00000 716105696Srwatson#define BGE_MICOMM_CMD 0x0C000000 717172955Srwatson#define BGE_MICOMM_READFAIL 0x10000000 718101099Srwatson#define BGE_MICOMM_BUSY 0x20000000 719172955Srwatson 720132232Srwatson#define BGE_MIREG(x) ((x & 0x1F) << 16) 721172955Srwatson#define BGE_MIPHY(x) ((x & 0x1F) << 21) 722105696Srwatson#define BGE_MICMD_WRITE 0x04000000 723105696Srwatson#define BGE_MICMD_READ 0x08000000 724172955Srwatson 725105696Srwatson/* MI status register */ 726105696Srwatson#define BGE_MISTS_LINK 0x00000001 727105696Srwatson#define BGE_MISTS_10MBPS 0x00000002 728172955Srwatson 729105696Srwatson#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 730105696Srwatson#define BGE_MIMODE_AUTOPOLL 0x00000010 731172955Srwatson#define BGE_MIMODE_CLKCNT 0x001F0000 732105696Srwatson 733105696Srwatson 734172955Srwatson/* 735105696Srwatson * Send data initiator control registers. 736105696Srwatson */ 737172955Srwatson#define BGE_SDI_MODE 0x0C00 738101099Srwatson#define BGE_SDI_STATUS 0x0C04 739101099Srwatson#define BGE_SDI_STATS_CTL 0x0C08 740101099Srwatson#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 741105696Srwatson#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 742105696Srwatson#define BGE_LOCSTATS_COS0 0x0C80 743101099Srwatson#define BGE_LOCSTATS_COS1 0x0C84 744105696Srwatson#define BGE_LOCSTATS_COS2 0x0C88 745172955Srwatson#define BGE_LOCSTATS_COS3 0x0C8C 746105696Srwatson#define BGE_LOCSTATS_COS4 0x0C90 747105696Srwatson#define BGE_LOCSTATS_COS5 0x0C84 748172955Srwatson#define BGE_LOCSTATS_COS6 0x0C98 749105696Srwatson#define BGE_LOCSTATS_COS7 0x0C9C 750105696Srwatson#define BGE_LOCSTATS_COS8 0x0CA0 751105696Srwatson#define BGE_LOCSTATS_COS9 0x0CA4 752105696Srwatson#define BGE_LOCSTATS_COS10 0x0CA8 753105696Srwatson#define BGE_LOCSTATS_COS11 0x0CAC 754105696Srwatson#define BGE_LOCSTATS_COS12 0x0CB0 755105696Srwatson#define BGE_LOCSTATS_COS13 0x0CB4 756172955Srwatson#define BGE_LOCSTATS_COS14 0x0CB8 757105696Srwatson#define BGE_LOCSTATS_COS15 0x0CBC 758105696Srwatson#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 759105696Srwatson#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 760172955Srwatson#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 761172955Srwatson#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 762105696Srwatson#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 763101099Srwatson#define BGE_LOCSTATS_IRQS 0x0CD4 764101099Srwatson#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 765101099Srwatson#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 766105696Srwatson 767172955Srwatson/* Send Data Initiator mode register */ 768105696Srwatson#define BGE_SDIMODE_RESET 0x00000001 769105696Srwatson#define BGE_SDIMODE_ENABLE 0x00000002 770105696Srwatson#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 771105696Srwatson 772105696Srwatson/* Send Data Initiator stats register */ 773101099Srwatson#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 774173138Srwatson 775173138Srwatson/* Send Data Initiator stats control register */ 776101099Srwatson#define BGE_SDISTATSCTL_ENABLE 0x00000001 777173138Srwatson#define BGE_SDISTATSCTL_FASTER 0x00000002 778173138Srwatson#define BGE_SDISTATSCTL_CLEAR 0x00000004 779173138Srwatson#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 780101099Srwatson#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 781173138Srwatson 782101099Srwatson/* 783173138Srwatson * Send Data Completion Control registers 784173138Srwatson */ 785101099Srwatson#define BGE_SDC_MODE 0x1000 786173138Srwatson#define BGE_SDC_STATUS 0x1004 787173138Srwatson 788101099Srwatson/* Send Data completion mode register */ 789173138Srwatson#define BGE_SDCMODE_RESET 0x00000001 790173138Srwatson#define BGE_SDCMODE_ENABLE 0x00000002 791173138Srwatson#define BGE_SDCMODE_ATTN 0x00000004 792101099Srwatson 793101099Srwatson/* Send Data completion status register */ 794101099Srwatson#define BGE_SDCSTAT_ATTN 0x00000004 795173138Srwatson 796173138Srwatson/* 797104535Srwatson * Send BD Ring Selector Control registers 798104535Srwatson */ 799104535Srwatson#define BGE_SRS_MODE 0x1400 800122524Srwatson#define BGE_SRS_STATUS 0x1404 801173138Srwatson#define BGE_SRS_HWDIAG 0x1408 802104535Srwatson#define BGE_SRS_LOC_NIC_CONS0 0x1440 803172955Srwatson#define BGE_SRS_LOC_NIC_CONS1 0x1444 804104535Srwatson#define BGE_SRS_LOC_NIC_CONS2 0x1448 805104535Srwatson#define BGE_SRS_LOC_NIC_CONS3 0x144C 806104535Srwatson#define BGE_SRS_LOC_NIC_CONS4 0x1450 807173138Srwatson#define BGE_SRS_LOC_NIC_CONS5 0x1454 808173138Srwatson#define BGE_SRS_LOC_NIC_CONS6 0x1458 809101099Srwatson#define BGE_SRS_LOC_NIC_CONS7 0x145C 810101099Srwatson#define BGE_SRS_LOC_NIC_CONS8 0x1460 811101099Srwatson#define BGE_SRS_LOC_NIC_CONS9 0x1464 812173138Srwatson#define BGE_SRS_LOC_NIC_CONS10 0x1468 813173138Srwatson#define BGE_SRS_LOC_NIC_CONS11 0x146C 814172955Srwatson#define BGE_SRS_LOC_NIC_CONS12 0x1470 815172955Srwatson#define BGE_SRS_LOC_NIC_CONS13 0x1474 816101099Srwatson#define BGE_SRS_LOC_NIC_CONS14 0x1478 817101099Srwatson#define BGE_SRS_LOC_NIC_CONS15 0x147C 818173138Srwatson 819173138Srwatson/* Send BD Ring Selector Mode register */ 820101099Srwatson#define BGE_SRSMODE_RESET 0x00000001 821173138Srwatson#define BGE_SRSMODE_ENABLE 0x00000002 822173138Srwatson#define BGE_SRSMODE_ATTN 0x00000004 823101099Srwatson 824173138Srwatson/* Send BD Ring Selector Status register */ 825173138Srwatson#define BGE_SRSSTAT_ERROR 0x00000004 826101099Srwatson 827173138Srwatson/* Send BD Ring Selector HW Diagnostics register */ 828173138Srwatson#define BGE_SRSHWDIAG_STATE 0x0000000F 829173138Srwatson#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 830173138Srwatson#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 831173138Srwatson#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 832173138Srwatson 833173138Srwatson/* 834101099Srwatson * Send BD Initiator Selector Control registers 835173138Srwatson */ 836173138Srwatson#define BGE_SBDI_MODE 0x1800 837173138Srwatson#define BGE_SBDI_STATUS 0x1804 838173138Srwatson#define BGE_SBDI_LOC_NIC_PROD0 0x1808 839173138Srwatson#define BGE_SBDI_LOC_NIC_PROD1 0x180C 840173138Srwatson#define BGE_SBDI_LOC_NIC_PROD2 0x1810 841173138Srwatson#define BGE_SBDI_LOC_NIC_PROD3 0x1814 842173138Srwatson#define BGE_SBDI_LOC_NIC_PROD4 0x1818 843173138Srwatson#define BGE_SBDI_LOC_NIC_PROD5 0x181C 844173138Srwatson#define BGE_SBDI_LOC_NIC_PROD6 0x1820 845173138Srwatson#define BGE_SBDI_LOC_NIC_PROD7 0x1824 846173138Srwatson#define BGE_SBDI_LOC_NIC_PROD8 0x1828 847173138Srwatson#define BGE_SBDI_LOC_NIC_PROD9 0x182C 848101099Srwatson#define BGE_SBDI_LOC_NIC_PROD10 0x1830 849173138Srwatson#define BGE_SBDI_LOC_NIC_PROD11 0x1834 850173138Srwatson#define BGE_SBDI_LOC_NIC_PROD12 0x1838 851173138Srwatson#define BGE_SBDI_LOC_NIC_PROD13 0x183C 852173138Srwatson#define BGE_SBDI_LOC_NIC_PROD14 0x1840 853173138Srwatson#define BGE_SBDI_LOC_NIC_PROD15 0x1844 854173138Srwatson 855173138Srwatson/* Send BD Initiator Mode register */ 856101099Srwatson#define BGE_SBDIMODE_RESET 0x00000001 857173138Srwatson#define BGE_SBDIMODE_ENABLE 0x00000002 858173138Srwatson#define BGE_SBDIMODE_ATTN 0x00000004 859173138Srwatson 860173138Srwatson/* Send BD Initiator Status register */ 861173138Srwatson#define BGE_SBDISTAT_ERROR 0x00000004 862173138Srwatson 863173138Srwatson/* 864101099Srwatson * Send BD Completion Control registers 865173138Srwatson */ 866173138Srwatson#define BGE_SBDC_MODE 0x1C00 867173138Srwatson#define BGE_SBDC_STATUS 0x1C04 868173138Srwatson 869173138Srwatson/* Send BD Completion Control Mode register */ 870173138Srwatson#define BGE_SBDCMODE_RESET 0x00000001 871173138Srwatson#define BGE_SBDCMODE_ENABLE 0x00000002 872173138Srwatson#define BGE_SBDCMODE_ATTN 0x00000004 873173138Srwatson 874105988Srwatson/* Send BD Completion Control Status register */ 875101099Srwatson#define BGE_SBDCSTAT_ATTN 0x00000004 876101099Srwatson 877101099Srwatson/* 878101099Srwatson * Receive List Placement Control registers 879105988Srwatson */ 880173138Srwatson#define BGE_RXLP_MODE 0x2000 881105988Srwatson#define BGE_RXLP_STATUS 0x2004 882173138Srwatson#define BGE_RXLP_SEL_LIST_LOCK 0x2008 883105988Srwatson#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 884173138Srwatson#define BGE_RXLP_CFG 0x2010 885105988Srwatson#define BGE_RXLP_STATS_CTL 0x2014 886105988Srwatson#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 887173138Srwatson#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 888173138Srwatson#define BGE_RXLP_HEAD0 0x2100 889105988Srwatson#define BGE_RXLP_TAIL0 0x2104 890173138Srwatson#define BGE_RXLP_COUNT0 0x2108 891173138Srwatson#define BGE_RXLP_HEAD1 0x2110 892173138Srwatson#define BGE_RXLP_TAIL1 0x2114 893105988Srwatson#define BGE_RXLP_COUNT1 0x2118 894173138Srwatson#define BGE_RXLP_HEAD2 0x2120 895122875Srwatson#define BGE_RXLP_TAIL2 0x2124 896122875Srwatson#define BGE_RXLP_COUNT2 0x2128 897122875Srwatson#define BGE_RXLP_HEAD3 0x2130 898173138Srwatson#define BGE_RXLP_TAIL3 0x2134 899101099Srwatson#define BGE_RXLP_COUNT3 0x2138 900101099Srwatson#define BGE_RXLP_HEAD4 0x2140 901101099Srwatson#define BGE_RXLP_TAIL4 0x2144 902173138Srwatson#define BGE_RXLP_COUNT4 0x2148 903173138Srwatson#define BGE_RXLP_HEAD5 0x2150 904101099Srwatson#define BGE_RXLP_TAIL5 0x2154 905173138Srwatson#define BGE_RXLP_COUNT5 0x2158 906101099Srwatson#define BGE_RXLP_HEAD6 0x2160 907101099Srwatson#define BGE_RXLP_TAIL6 0x2164 908101099Srwatson#define BGE_RXLP_COUNT6 0x2168 909173138Srwatson#define BGE_RXLP_HEAD7 0x2170 910173138Srwatson#define BGE_RXLP_TAIL7 0x2174 911101099Srwatson#define BGE_RXLP_COUNT7 0x2178 912173138Srwatson#define BGE_RXLP_HEAD8 0x2180 913173138Srwatson#define BGE_RXLP_TAIL8 0x2184 914101099Srwatson#define BGE_RXLP_COUNT8 0x2188 915173138Srwatson#define BGE_RXLP_HEAD9 0x2190 916173138Srwatson#define BGE_RXLP_TAIL9 0x2194 917173138Srwatson#define BGE_RXLP_COUNT9 0x2198 918173138Srwatson#define BGE_RXLP_HEAD10 0x21A0 919173138Srwatson#define BGE_RXLP_TAIL10 0x21A4 920173138Srwatson#define BGE_RXLP_COUNT10 0x21A8 921173138Srwatson#define BGE_RXLP_HEAD11 0x21B0 922173138Srwatson#define BGE_RXLP_TAIL11 0x21B4 923173138Srwatson#define BGE_RXLP_COUNT11 0x21B8 924173138Srwatson#define BGE_RXLP_HEAD12 0x21C0 925173138Srwatson#define BGE_RXLP_TAIL12 0x21C4 926173138Srwatson#define BGE_RXLP_COUNT12 0x21C8 927173138Srwatson#define BGE_RXLP_HEAD13 0x21D0 928101099Srwatson#define BGE_RXLP_TAIL13 0x21D4 929101099Srwatson#define BGE_RXLP_COUNT13 0x21D8 930101099Srwatson#define BGE_RXLP_HEAD14 0x21E0 931173138Srwatson#define BGE_RXLP_TAIL14 0x21E4 932173138Srwatson#define BGE_RXLP_COUNT14 0x21E8 933101099Srwatson#define BGE_RXLP_HEAD15 0x21F0 934173138Srwatson#define BGE_RXLP_TAIL15 0x21F4 935101099Srwatson#define BGE_RXLP_COUNT15 0x21F8 936173138Srwatson#define BGE_RXLP_LOCSTAT_COS0 0x2200 937101099Srwatson#define BGE_RXLP_LOCSTAT_COS1 0x2204 938173138Srwatson#define BGE_RXLP_LOCSTAT_COS2 0x2208 939101099Srwatson#define BGE_RXLP_LOCSTAT_COS3 0x220C 940101099Srwatson#define BGE_RXLP_LOCSTAT_COS4 0x2210 941101099Srwatson#define BGE_RXLP_LOCSTAT_COS5 0x2214 942173138Srwatson#define BGE_RXLP_LOCSTAT_COS6 0x2218 943173138Srwatson#define BGE_RXLP_LOCSTAT_COS7 0x221C 944173138Srwatson#define BGE_RXLP_LOCSTAT_COS8 0x2220 945145855Srwatson#define BGE_RXLP_LOCSTAT_COS9 0x2224 946145855Srwatson#define BGE_RXLP_LOCSTAT_COS10 0x2228 947145855Srwatson#define BGE_RXLP_LOCSTAT_COS11 0x222C 948145855Srwatson#define BGE_RXLP_LOCSTAT_COS12 0x2230 949173138Srwatson#define BGE_RXLP_LOCSTAT_COS13 0x2234 950145855Srwatson#define BGE_RXLP_LOCSTAT_COS14 0x2238 951172955Srwatson#define BGE_RXLP_LOCSTAT_COS15 0x223C 952145855Srwatson#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 953145855Srwatson#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 954145855Srwatson#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 955173138Srwatson#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 956173138Srwatson#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 957101099Srwatson#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 958101099Srwatson#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 959101099Srwatson 960173138Srwatson 961173138Srwatson/* Receive List Placement mode register */ 962101099Srwatson#define BGE_RXLPMODE_RESET 0x00000001 963172955Srwatson#define BGE_RXLPMODE_ENABLE 0x00000002 964101099Srwatson#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 965101099Srwatson#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 966101099Srwatson#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 967173138Srwatson 968173138Srwatson/* Receive List Placement Status register */ 969173138Srwatson#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 970101099Srwatson#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 971101099Srwatson#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 972101099Srwatson 973173138Srwatson/* 974173138Srwatson * Receive Data and Receive BD Initiator Control Registers 975101099Srwatson */ 976172955Srwatson#define BGE_RDBDI_MODE 0x2400 977101099Srwatson#define BGE_RDBDI_STATUS 0x2404 978101099Srwatson#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 979173138Srwatson#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 980173138Srwatson#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 981173138Srwatson#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 982140628Srwatson#define BGE_RX_STD_RCB_HADDR_HI 0x2450 983173138Srwatson#define BGE_RX_STD_RCB_HADDR_LO 0x2454 984173138Srwatson#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 985140628Srwatson#define BGE_RX_STD_RCB_NICADDR 0x245C 986173138Srwatson#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 987173138Srwatson#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 988140628Srwatson#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 989173138Srwatson#define BGE_RX_MINI_RCB_NICADDR 0x246C 990173138Srwatson#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 991173138Srwatson#define BGE_RDBDI_STD_RX_CONS 0x2474 992173138Srwatson#define BGE_RDBDI_MINI_RX_CONS 0x2478 993173138Srwatson#define BGE_RDBDI_RETURN_PROD0 0x2480 994173138Srwatson#define BGE_RDBDI_RETURN_PROD1 0x2484 995173138Srwatson#define BGE_RDBDI_RETURN_PROD2 0x2488 996140628Srwatson#define BGE_RDBDI_RETURN_PROD3 0x248C 997173138Srwatson#define BGE_RDBDI_RETURN_PROD4 0x2490 998173138Srwatson#define BGE_RDBDI_RETURN_PROD5 0x2494 999173138Srwatson#define BGE_RDBDI_RETURN_PROD6 0x2498 1000173138Srwatson#define BGE_RDBDI_RETURN_PROD7 0x249C 1001173138Srwatson#define BGE_RDBDI_RETURN_PROD8 0x24A0 1002173138Srwatson#define BGE_RDBDI_RETURN_PROD9 0x24A4 1003140628Srwatson#define BGE_RDBDI_RETURN_PROD10 0x24A8 1004173138Srwatson#define BGE_RDBDI_RETURN_PROD11 0x24AC 1005140628Srwatson#define BGE_RDBDI_RETURN_PROD12 0x24B0 1006140628Srwatson#define BGE_RDBDI_RETURN_PROD13 0x24B4 1007173138Srwatson#define BGE_RDBDI_RETURN_PROD14 0x24B8 1008173138Srwatson#define BGE_RDBDI_RETURN_PROD15 0x24BC 1009173138Srwatson#define BGE_RDBDI_HWDIAG 0x24C0 1010140628Srwatson 1011173138Srwatson 1012140628Srwatson/* Receive Data and Receive BD Initiator Mode register */ 1013173138Srwatson#define BGE_RDBDIMODE_RESET 0x00000001 1014173138Srwatson#define BGE_RDBDIMODE_ENABLE 0x00000002 1015140628Srwatson#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1016173138Srwatson#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1017173138Srwatson#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1018140628Srwatson 1019173138Srwatson/* Receive Data and Receive BD Initiator Status register */ 1020140628Srwatson#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1021140628Srwatson#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1022101099Srwatson#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1023172955Srwatson 1024101099Srwatson 1025121816Sbrooks/* 1026101099Srwatson * Receive Data Completion Control registers 1027101099Srwatson */ 1028110350Srwatson#define BGE_RDC_MODE 0x2800 1029101099Srwatson 1030168976Srwatson/* Receive Data Completion Mode register */ 1031101099Srwatson#define BGE_RDCMODE_RESET 0x00000001 1032168976Srwatson#define BGE_RDCMODE_ENABLE 0x00000002 1033110350Srwatson#define BGE_RDCMODE_ATTN 0x00000004 1034101099Srwatson 1035101099Srwatson/* 1036101099Srwatson * Receive BD Initiator Control registers 1037101099Srwatson */ 1038110350Srwatson#define BGE_RBDI_MODE 0x2C00 1039101099Srwatson#define BGE_RBDI_STATUS 0x2C04 1040101099Srwatson#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1041101099Srwatson#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1042110350Srwatson#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1043101099Srwatson#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1044101099Srwatson#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1045101099Srwatson#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1046101099Srwatson 1047101099Srwatson/* Receive BD Initiator Mode register */ 1048106089Srwatson#define BGE_RBDIMODE_RESET 0x00000001 1049101099Srwatson#define BGE_RBDIMODE_ENABLE 0x00000002 1050101099Srwatson#define BGE_RBDIMODE_ATTN 0x00000004 1051101099Srwatson 1052101099Srwatson/* Receive BD Initiator Status register */ 1053101099Srwatson#define BGE_RBDISTAT_ATTN 0x00000004 1054101099Srwatson 1055101099Srwatson/* 1056101099Srwatson * Receive BD Completion Control registers 1057101099Srwatson */ 1058101099Srwatson#define BGE_RBDC_MODE 0x3000 1059168976Srwatson#define BGE_RBDC_STATUS 0x3004 1060110350Srwatson#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1061101099Srwatson#define BGE_RBDC_STD_BD_PROD 0x300C 1062101099Srwatson#define BGE_RBDC_MINI_BD_PROD 0x3010 1063106089Srwatson 1064106089Srwatson/* Receive BD completion mode register */ 1065106089Srwatson#define BGE_RBDCMODE_RESET 0x00000001 1066106089Srwatson#define BGE_RBDCMODE_ENABLE 0x00000002 1067106089Srwatson#define BGE_RBDCMODE_ATTN 0x00000004 1068101099Srwatson 1069101099Srwatson/* Receive BD completion status register */ 1070101099Srwatson#define BGE_RBDCSTAT_ERROR 0x00000004 1071101099Srwatson 1072101099Srwatson/* 1073101099Srwatson * Receive List Selector Control registers 1074101099Srwatson */ 1075172955Srwatson#define BGE_RXLS_MODE 0x3400 1076172955Srwatson#define BGE_RXLS_STATUS 0x3404 1077101099Srwatson 1078101099Srwatson/* Receive List Selector Mode register */ 1079101099Srwatson#define BGE_RXLSMODE_RESET 0x00000001 1080173138Srwatson#define BGE_RXLSMODE_ENABLE 0x00000002 1081173138Srwatson#define BGE_RXLSMODE_ATTN 0x00000004 1082101099Srwatson 1083101099Srwatson/* Receive List Selector Status register */ 1084101099Srwatson#define BGE_RXLSSTAT_ERROR 0x00000004 1085173138Srwatson 1086173138Srwatson/* 1087101099Srwatson * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1088172955Srwatson */ 1089101099Srwatson#define BGE_MBCF_MODE 0x3800 1090101099Srwatson#define BGE_MBCF_STATUS 0x3804 1091101099Srwatson 1092173138Srwatson/* Mbuf Cluster Free mode register */ 1093173138Srwatson#define BGE_MBCFMODE_RESET 0x00000001 1094101099Srwatson#define BGE_MBCFMODE_ENABLE 0x00000002 1095101099Srwatson#define BGE_MBCFMODE_ATTN 0x00000004 1096101099Srwatson 1097173138Srwatson/* Mbuf Cluster Free status register */ 1098173138Srwatson#define BGE_MBCFSTAT_ERROR 0x00000004 1099101099Srwatson 1100173138Srwatson/* 1101101099Srwatson * Host Coalescing Control registers 1102101099Srwatson */ 1103173138Srwatson#define BGE_HCC_MODE 0x3C00 1104173138Srwatson#define BGE_HCC_STATUS 0x3C04 1105173138Srwatson#define BGE_HCC_RX_COAL_TICKS 0x3C08 1106173138Srwatson#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1107173138Srwatson#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1108173138Srwatson#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1109173138Srwatson#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1110173138Srwatson#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1111173138Srwatson#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1112173138Srwatson#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1113173138Srwatson#define BGE_HCC_STATS_TICKS 0x3C28 1114173138Srwatson#define BGE_HCC_STATS_ADDR_HI 0x3C30 1115173138Srwatson#define BGE_HCC_STATS_ADDR_LO 0x3C34 1116173138Srwatson#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1117173138Srwatson#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1118183980Sbz#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1119183980Sbz#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1120183980Sbz#define BGE_FLOW_ATTN 0x3C48 1121183980Sbz#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1122183980Sbz#define BGE_HCC_STD_BD_CONS 0x3C54 1123183980Sbz#define BGE_HCC_MINI_BD_CONS 0x3C58 1124183980Sbz#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1125183980Sbz#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1126183980Sbz#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1127183980Sbz#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1128183980Sbz#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1129183980Sbz#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1130183980Sbz#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1131183980Sbz#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1132183980Sbz#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1133183980Sbz#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1134183980Sbz#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1135183980Sbz#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1136101099Srwatson#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1137173138Srwatson#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1138173138Srwatson#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1139101099Srwatson#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1140101099Srwatson#define BGE_HCC_TX_BD_CONS0 0x3CC0 1141101099Srwatson#define BGE_HCC_TX_BD_CONS1 0x3CC4 1142173138Srwatson#define BGE_HCC_TX_BD_CONS2 0x3CC8 1143173138Srwatson#define BGE_HCC_TX_BD_CONS3 0x3CCC 1144101099Srwatson#define BGE_HCC_TX_BD_CONS4 0x3CD0 1145172955Srwatson#define BGE_HCC_TX_BD_CONS5 0x3CD4 1146101099Srwatson#define BGE_HCC_TX_BD_CONS6 0x3CD8 1147101099Srwatson#define BGE_HCC_TX_BD_CONS7 0x3CDC 1148101099Srwatson#define BGE_HCC_TX_BD_CONS8 0x3CE0 1149172955Srwatson#define BGE_HCC_TX_BD_CONS9 0x3CE4 1150123607Srwatson#define BGE_HCC_TX_BD_CONS10 0x3CE8 1151123607Srwatson#define BGE_HCC_TX_BD_CONS11 0x3CEC 1152123607Srwatson#define BGE_HCC_TX_BD_CONS12 0x3CF0 1153123607Srwatson#define BGE_HCC_TX_BD_CONS13 0x3CF4 1154123607Srwatson#define BGE_HCC_TX_BD_CONS14 0x3CF8 1155123607Srwatson#define BGE_HCC_TX_BD_CONS15 0x3CFC 1156123607Srwatson 1157172955Srwatson 1158123607Srwatson/* Host coalescing mode register */ 1159123607Srwatson#define BGE_HCCMODE_RESET 0x00000001 1160123607Srwatson#define BGE_HCCMODE_ENABLE 0x00000002 1161173138Srwatson#define BGE_HCCMODE_ATTN 0x00000004 1162173138Srwatson#define BGE_HCCMODE_COAL_NOW 0x00000008 1163101099Srwatson#define BGE_HCCMODE_MSI_BITS 0x0x000070 1164101099Srwatson#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1165101099Srwatson 1166173138Srwatson#define BGE_STATBLKSZ_FULL 0x00000000 1167173138Srwatson#define BGE_STATBLKSZ_64BYTE 0x00000080 1168101099Srwatson#define BGE_STATBLKSZ_32BYTE 0x00000100 1169173138Srwatson 1170101099Srwatson/* Host coalescing status register */ 1171101099Srwatson#define BGE_HCCSTAT_ERROR 0x00000004 1172101099Srwatson 1173179781Srwatson/* Flow attention register */ 1174179781Srwatson#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1175101099Srwatson#define BGE_FLOWATTN_MEMARB 0x00000080 1176101099Srwatson#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1177101099Srwatson#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1178173138Srwatson#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1179179781Srwatson#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1180101099Srwatson#define BGE_FLOWATTN_RDBDI 0x00080000 1181172955Srwatson#define BGE_FLOWATTN_RXLS 0x00100000 1182101099Srwatson#define BGE_FLOWATTN_RXLP 0x00200000 1183101099Srwatson#define BGE_FLOWATTN_RBDC 0x00400000 1184101099Srwatson#define BGE_FLOWATTN_RBDI 0x00800000 1185179781Srwatson#define BGE_FLOWATTN_SDC 0x08000000 1186179781Srwatson#define BGE_FLOWATTN_SDI 0x10000000 1187101099Srwatson#define BGE_FLOWATTN_SRS 0x20000000 1188101099Srwatson#define BGE_FLOWATTN_SBDC 0x40000000 1189101099Srwatson#define BGE_FLOWATTN_SBDI 0x80000000 1190179781Srwatson 1191168976Srwatson/* 1192101099Srwatson * Memory arbiter registers 1193172955Srwatson */ 1194101099Srwatson#define BGE_MARB_MODE 0x4000 1195101099Srwatson#define BGE_MARB_STATUS 0x4004 1196101099Srwatson#define BGE_MARB_TRAPADDR_HI 0x4008 1197179781Srwatson#define BGE_MARB_TRAPADDR_LO 0x400C 1198173138Srwatson 1199101099Srwatson/* Memory arbiter mode register */ 1200101099Srwatson#define BGE_MARBMODE_RESET 0x00000001 1201101099Srwatson#define BGE_MARBMODE_ENABLE 0x00000002 1202179781Srwatson#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1203173138Srwatson#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1204101099Srwatson#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1205173138Srwatson#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1206173138Srwatson#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1207101099Srwatson#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1208101099Srwatson#define BGE_MARBMODE_PCI_TRAP 0x00000100 1209101099Srwatson#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1210179781Srwatson#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1211179781Srwatson#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1212101099Srwatson#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1213101099Srwatson#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1214101099Srwatson#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1215101099Srwatson#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1216101099Srwatson#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1217173138Srwatson#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1218173138Srwatson#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1219173138Srwatson#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1220173138Srwatson#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1221173138Srwatson#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1222173138Srwatson#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1223173138Srwatson#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1224173138Srwatson#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1225173138Srwatson#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1226173138Srwatson 1227173138Srwatson/* Memory arbiter status register */ 1228173138Srwatson#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1229173138Srwatson#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1230173138Srwatson#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1231173138Srwatson#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1232173138Srwatson#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1233173138Srwatson#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1234173138Srwatson#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1235173138Srwatson#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1236173138Srwatson#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1237173138Srwatson#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1238173138Srwatson#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1239173138Srwatson#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1240173138Srwatson#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1241173138Srwatson#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1242173138Srwatson#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1243173138Srwatson#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1244173138Srwatson#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1245173138Srwatson#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1246173138Srwatson#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1247173138Srwatson#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1248173138Srwatson#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1249173138Srwatson#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1250173138Srwatson#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1251173138Srwatson#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1252173138Srwatson 1253173138Srwatson/* 1254173138Srwatson * Buffer manager control registers 1255173138Srwatson */ 1256173138Srwatson#define BGE_BMAN_MODE 0x4400 1257173138Srwatson#define BGE_BMAN_STATUS 0x4404 1258122875Srwatson#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1259173138Srwatson#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1260173138Srwatson#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1261122875Srwatson#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1262122875Srwatson#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1263122875Srwatson#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1264173138Srwatson#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1265173138Srwatson#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1266122875Srwatson#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1267173138Srwatson#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1268122875Srwatson#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1269122875Srwatson#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1270162238Scsjp#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1271173095Srwatson#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1272173095Srwatson#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1273173095Srwatson#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1274173095Srwatson#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1275173095Srwatson#define BGE_BMAN_HWDIAG_1 0x444C 1276173095Srwatson#define BGE_BMAN_HWDIAG_2 0x4450 1277173095Srwatson#define BGE_BMAN_HWDIAG_3 0x4454 1278173095Srwatson 1279173095Srwatson/* Buffer manager mode register */ 1280173095Srwatson#define BGE_BMANMODE_RESET 0x00000001 1281173095Srwatson#define BGE_BMANMODE_ENABLE 0x00000002 1282173095Srwatson#define BGE_BMANMODE_ATTN 0x00000004 1283173095Srwatson#define BGE_BMANMODE_TESTMODE 0x00000008 1284173095Srwatson#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1285173095Srwatson 1286173095Srwatson/* Buffer manager status register */ 1287173095Srwatson#define BGE_BMANSTAT_ERRO 0x00000004 1288173095Srwatson#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1289173095Srwatson 1290173095Srwatson 1291173095Srwatson/* 1292173095Srwatson * Read DMA Control registers 1293173102Srwatson */ 1294173102Srwatson#define BGE_RDMA_MODE 0x4800 1295173102Srwatson#define BGE_RDMA_STATUS 0x4804 1296173102Srwatson 1297173102Srwatson/* Read DMA mode register */ 1298173102Srwatson#define BGE_RDMAMODE_RESET 0x00000001 1299173102Srwatson#define BGE_RDMAMODE_ENABLE 0x00000002 1300173102Srwatson#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1301173102Srwatson#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1302173102Srwatson#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1303173102Srwatson#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1304173102Srwatson#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1305173018Srwatson#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1306162238Scsjp#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1307162238Scsjp#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1308162238Scsjp#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1309173018Srwatson 1310162238Scsjp/* Read DMA status register */ 1311173018Srwatson#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1312172955Srwatson#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1313162238Scsjp#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1314162238Scsjp#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1315173095Srwatson#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1316173138Srwatson#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1317173138Srwatson#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1318173138Srwatson#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1319173138Srwatson 1320173138Srwatson/* 1321173138Srwatson * Write DMA control registers 1322173138Srwatson */ 1323173138Srwatson#define BGE_WDMA_MODE 0x4C00 1324173138Srwatson#define BGE_WDMA_STATUS 0x4C04 1325173138Srwatson 1326173138Srwatson/* Write DMA mode register */ 1327173138Srwatson#define BGE_WDMAMODE_RESET 0x00000001 1328173102Srwatson#define BGE_WDMAMODE_ENABLE 0x00000002 1329173102Srwatson#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1330173102Srwatson#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1331173102Srwatson#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1332173102Srwatson#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1333173102Srwatson#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1334173102Srwatson#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1335173102Srwatson#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1336173102Srwatson#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1337173102Srwatson#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1338173102Srwatson 1339173102Srwatson/* Write DMA status register */ 1340173095Srwatson#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1341173095Srwatson#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1342173095Srwatson#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1343173095Srwatson#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1344173095Srwatson#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1345173095Srwatson#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1346173095Srwatson#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1347173095Srwatson#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1348173095Srwatson 1349173095Srwatson 1350173095Srwatson/* 1351173095Srwatson * RX CPU registers 1352173095Srwatson */ 1353173095Srwatson#define BGE_RXCPU_MODE 0x5000 1354173095Srwatson#define BGE_RXCPU_STATUS 0x5004 1355173095Srwatson#define BGE_RXCPU_PC 0x501C 1356173095Srwatson 1357173095Srwatson/* RX CPU mode register */ 1358173095Srwatson#define BGE_RXCPUMODE_RESET 0x00000001 1359173095Srwatson#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1360173095Srwatson#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1361173138Srwatson#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1362173138Srwatson#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1363173138Srwatson#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1364101099Srwatson#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1365101099Srwatson#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1366173138Srwatson#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1367173138Srwatson#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1368101099Srwatson#define BGE_RXCPUMODE_HALTCPU 0x00000400 1369173138Srwatson#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1370101099Srwatson#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1371173138Srwatson#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1372101099Srwatson 1373101099Srwatson/* RX CPU status register */ 1374173138Srwatson#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1375173138Srwatson#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1376173138Srwatson#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1377172957Srwatson#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1378173138Srwatson#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1379172957Srwatson#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1380173138Srwatson#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1381173138Srwatson#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1382172957Srwatson#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1383173138Srwatson#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1384173138Srwatson#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1385101099Srwatson#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1386173138Srwatson#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1387173138Srwatson#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1388101099Srwatson#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1389173138Srwatson#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1390101099Srwatson#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1391101099Srwatson 1392101099Srwatson 1393173138Srwatson/* 1394173138Srwatson * TX CPU registers 1395101099Srwatson */ 1396173138Srwatson#define BGE_TXCPU_MODE 0x5400 1397101099Srwatson#define BGE_TXCPU_STATUS 0x5404 1398172955Srwatson#define BGE_TXCPU_PC 0x541C 1399101099Srwatson 1400101099Srwatson/* TX CPU mode register */ 1401173138Srwatson#define BGE_TXCPUMODE_RESET 0x00000001 1402173138Srwatson#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1403101099Srwatson#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1404173138Srwatson#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1405173138Srwatson#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1406173138Srwatson#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1407173138Srwatson#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1408101099Srwatson#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1409101099Srwatson#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1410101099Srwatson#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1411173138Srwatson#define BGE_TXCPUMODE_HALTCPU 0x00000400 1412173138Srwatson#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1413101099Srwatson#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1414173138Srwatson 1415105634Srwatson/* TX CPU status register */ 1416101099Srwatson#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1417173138Srwatson#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1418122524Srwatson#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1419173138Srwatson#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1420101099Srwatson#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1421101099Srwatson#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1422173138Srwatson#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1423173138Srwatson#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1424101099Srwatson#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1425173138Srwatson#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1426105634Srwatson#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1427105634Srwatson#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1428101099Srwatson#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1429101099Srwatson#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1430173138Srwatson#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1431173138Srwatson#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1432173138Srwatson#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1433173138Srwatson 1434173138Srwatson 1435173138Srwatson/* 1436173138Srwatson * Low priority mailbox registers 1437105634Srwatson */ 1438101099Srwatson#define BGE_LPMBX_IRQ0_HI 0x5800 1439173138Srwatson#define BGE_LPMBX_IRQ0_LO 0x5804 1440105634Srwatson#define BGE_LPMBX_IRQ1_HI 0x5808 1441173138Srwatson#define BGE_LPMBX_IRQ1_LO 0x580C 1442173138Srwatson#define BGE_LPMBX_IRQ2_HI 0x5810 1443110351Srwatson#define BGE_LPMBX_IRQ2_LO 0x5814 1444173138Srwatson#define BGE_LPMBX_IRQ3_HI 0x5818 1445105634Srwatson#define BGE_LPMBX_IRQ3_LO 0x581C 1446101099Srwatson#define BGE_LPMBX_GEN0_HI 0x5820 1447105634Srwatson#define BGE_LPMBX_GEN0_LO 0x5824 1448173138Srwatson#define BGE_LPMBX_GEN1_HI 0x5828 1449173138Srwatson#define BGE_LPMBX_GEN1_LO 0x582C 1450105634Srwatson#define BGE_LPMBX_GEN2_HI 0x5830 1451172955Srwatson#define BGE_LPMBX_GEN2_LO 0x5834 1452172955Srwatson#define BGE_LPMBX_GEN3_HI 0x5828 1453105634Srwatson#define BGE_LPMBX_GEN3_LO 0x582C 1454105634Srwatson#define BGE_LPMBX_GEN4_HI 0x5840 1455105634Srwatson#define BGE_LPMBX_GEN4_LO 0x5844 1456105634Srwatson#define BGE_LPMBX_GEN5_HI 0x5848 1457105634Srwatson#define BGE_LPMBX_GEN5_LO 0x584C 1458101099Srwatson#define BGE_LPMBX_GEN6_HI 0x5850 1459101099Srwatson#define BGE_LPMBX_GEN6_LO 0x5854 1460101099Srwatson#define BGE_LPMBX_GEN7_HI 0x5858 1461101099Srwatson#define BGE_LPMBX_GEN7_LO 0x585C 1462173138Srwatson#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1463173138Srwatson#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1464101099Srwatson#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1465101099Srwatson#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1466101099Srwatson#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1467172955Srwatson#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1468101099Srwatson#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1469101099Srwatson#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1470173138Srwatson#define BGE_LPMBX_RX_CONS0_HI 0x5880 1471173138Srwatson#define BGE_LPMBX_RX_CONS0_LO 0x5884 1472101099Srwatson#define BGE_LPMBX_RX_CONS1_HI 0x5888 1473172955Srwatson#define BGE_LPMBX_RX_CONS1_LO 0x588C 1474173138Srwatson#define BGE_LPMBX_RX_CONS2_HI 0x5890 1475101099Srwatson#define BGE_LPMBX_RX_CONS2_LO 0x5894 1476101099Srwatson#define BGE_LPMBX_RX_CONS3_HI 0x5898 1477101099Srwatson#define BGE_LPMBX_RX_CONS3_LO 0x589C 1478101099Srwatson#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1479101099Srwatson#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1480173138Srwatson#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1481173138Srwatson#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1482101099Srwatson#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1483173138Srwatson#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1484101099Srwatson#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1485173138Srwatson#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1486173138Srwatson#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1487173138Srwatson#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1488122524Srwatson#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1489173138Srwatson#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1490101099Srwatson#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1491173138Srwatson#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1492173138Srwatson#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1493101099Srwatson#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1494105634Srwatson#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1495101099Srwatson#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1496101099Srwatson#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1497173138Srwatson#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1498173138Srwatson#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1499173138Srwatson#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1500101099Srwatson#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1501173138Srwatson#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1502103761Srwatson#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1503173138Srwatson#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1504173138Srwatson#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1505101099Srwatson#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1506173138Srwatson#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1507173138Srwatson#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1508103759Srwatson#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1509173138Srwatson#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1510173138Srwatson#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1511173138Srwatson#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1512173138Srwatson#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1513173138Srwatson#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1514173138Srwatson#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1515173138Srwatson#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1516173138Srwatson#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1517173138Srwatson#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1518173138Srwatson#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1519101099Srwatson#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1520101099Srwatson#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1521101099Srwatson#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1522180059Sjhb#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1523173138Srwatson#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1524122875Srwatson#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1525173138Srwatson#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1526122875Srwatson#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1527172955Srwatson#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1528122875Srwatson#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1529122875Srwatson#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1530173138Srwatson#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1531173138Srwatson#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1532122875Srwatson#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1533173138Srwatson#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1534173138Srwatson#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1535173138Srwatson#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1536173138Srwatson#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1537122875Srwatson#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1538122875Srwatson#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1539122875Srwatson#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1540180059Sjhb#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1541180059Sjhb#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1542140628Srwatson#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1543140628Srwatson#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1544140628Srwatson#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1545172955Srwatson#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1546140628Srwatson#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1547140628Srwatson#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1548180059Sjhb#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1549173138Srwatson#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1550140628Srwatson#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1551180059Sjhb#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1552180059Sjhb#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1553180059Sjhb#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1554180059Sjhb#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1555180059Sjhb#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1556180059Sjhb#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1557180059Sjhb#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1558180059Sjhb#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1559180059Sjhb#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1560180059Sjhb#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1561180059Sjhb#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1562180059Sjhb#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1563180059Sjhb#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1564180059Sjhb#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1565180059Sjhb#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1566180059Sjhb 1567180059Sjhb/* 1568180059Sjhb * Flow throw Queue reset register 1569172955Srwatson */ 1570140628Srwatson#define BGE_FTQ_RESET 0x5C00 1571140628Srwatson 1572140628Srwatson#define BGE_FTQRESET_DMAREAD 0x00000002 1573140628Srwatson#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1574140628Srwatson#define BGE_FTQRESET_DMADONE 0x00000010 1575173138Srwatson#define BGE_FTQRESET_SBDC 0x00000020 1576173138Srwatson#define BGE_FTQRESET_SDI 0x00000040 1577173138Srwatson#define BGE_FTQRESET_WDMA 0x00000080 1578173138Srwatson#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1579173138Srwatson#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1580173138Srwatson#define BGE_FTQRESET_SDC 0x00000400 1581173138Srwatson#define BGE_FTQRESET_HCC 0x00000800 1582173138Srwatson#define BGE_FTQRESET_TXFIFO 0x00001000 1583173138Srwatson#define BGE_FTQRESET_MBC 0x00002000 1584173138Srwatson#define BGE_FTQRESET_RBDC 0x00004000 1585173138Srwatson#define BGE_FTQRESET_RXLP 0x00008000 1586173138Srwatson#define BGE_FTQRESET_RDBDI 0x00010000 1587173138Srwatson#define BGE_FTQRESET_RDC 0x00020000 1588173138Srwatson#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1589173138Srwatson 1590173138Srwatson/* 1591173138Srwatson * Message Signaled Interrupt registers 1592140628Srwatson */ 1593173138Srwatson#define BGE_MSI_MODE 0x6000 1594140628Srwatson#define BGE_MSI_STATUS 0x6004 1595173138Srwatson#define BGE_MSI_FIFOACCESS 0x6008 1596173138Srwatson 1597140628Srwatson/* MSI mode register */ 1598172955Srwatson#define BGE_MSIMODE_RESET 0x00000001 1599140628Srwatson#define BGE_MSIMODE_ENABLE 0x00000002 1600140628Srwatson#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1601173138Srwatson#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1602173138Srwatson#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1603173138Srwatson#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1604173138Srwatson#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1605173138Srwatson 1606173138Srwatson/* MSI status register */ 1607140628Srwatson#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1608173138Srwatson#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1609173138Srwatson#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1610173138Srwatson#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1611173138Srwatson#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1612173138Srwatson 1613173138Srwatson 1614173138Srwatson/* 1615140628Srwatson * DMA Completion registers 1616173138Srwatson */ 1617173138Srwatson#define BGE_DMAC_MODE 0x6400 1618173138Srwatson 1619173138Srwatson/* DMA Completion mode register */ 1620173138Srwatson#define BGE_DMACMODE_RESET 0x00000001 1621173138Srwatson#define BGE_DMACMODE_ENABLE 0x00000002 1622173138Srwatson 1623173138Srwatson 1624173138Srwatson/* 1625173138Srwatson * General control registers. 1626173138Srwatson */ 1627173138Srwatson#define BGE_MODE_CTL 0x6800 1628173138Srwatson#define BGE_MISC_CFG 0x6804 1629173138Srwatson#define BGE_MISC_LOCAL_CTL 0x6808 1630173138Srwatson#define BGE_EE_ADDR 0x6838 1631173138Srwatson#define BGE_EE_DATA 0x683C 1632173138Srwatson#define BGE_EE_CTL 0x6840 1633173138Srwatson#define BGE_MDI_CTL 0x6844 1634173138Srwatson#define BGE_EE_DELAY 0x6848 1635173138Srwatson 1636173138Srwatson/* Mode control register */ 1637173138Srwatson#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1638173138Srwatson#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1639173138Srwatson#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1640173138Srwatson#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1641173138Srwatson#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1642173138Srwatson#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1643173138Srwatson#define BGE_MODECTL_NO_RX_CRC 0x00000400 1644173138Srwatson#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1645173138Srwatson#define BGE_MODECTL_NO_TX_INTR 0x00002000 1646173138Srwatson#define BGE_MODECTL_NO_RX_INTR 0x00004000 1647173138Srwatson#define BGE_MODECTL_FORCE_PCI32 0x00008000 1648173138Srwatson#define BGE_MODECTL_STACKUP 0x00010000 1649173138Srwatson#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1650173138Srwatson#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1651173138Srwatson#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1652173138Srwatson#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1653173138Srwatson#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1654173138Srwatson#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1655173138Srwatson#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1656173138Srwatson#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1657173138Srwatson#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1658173138Srwatson#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1659173138Srwatson 1660173138Srwatson/* Misc. config register */ 1661173138Srwatson#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1662173138Srwatson#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1663173138Srwatson 1664173138Srwatson#define BGE_32BITTIME_66MHZ (0x41 << 1) 1665173138Srwatson 1666173138Srwatson/* Misc. Local Control */ 1667173138Srwatson#define BGE_MLC_INTR_STATE 0x00000001 1668173138Srwatson#define BGE_MLC_INTR_CLR 0x00000002 1669173138Srwatson#define BGE_MLC_INTR_SET 0x00000004 1670173138Srwatson#define BGE_MLC_INTR_ONATTN 0x00000008 1671173138Srwatson#define BGE_MLC_MISCIO_IN0 0x00000100 1672173138Srwatson#define BGE_MLC_MISCIO_IN1 0x00000200 1673173138Srwatson#define BGE_MLC_MISCIO_IN2 0x00000400 1674173138Srwatson#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1675173138Srwatson#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1676173138Srwatson#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1677173138Srwatson#define BGE_MLC_MISCIO_OUT0 0x00004000 1678173138Srwatson#define BGE_MLC_MISCIO_OUT1 0x00008000 1679173138Srwatson#define BGE_MLC_MISCIO_OUT2 0x00010000 1680173138Srwatson#define BGE_MLC_EXTRAM_ENB 0x00020000 1681173138Srwatson#define BGE_MLC_SRAM_SIZE 0x001C0000 1682173138Srwatson#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1683173138Srwatson#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1684173138Srwatson#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1685173138Srwatson#define BGE_MLC_AUTO_EEPROM 0x01000000 1686173138Srwatson 1687173138Srwatson#define BGE_SSRAMSIZE_256KB 0x00000000 1688173138Srwatson#define BGE_SSRAMSIZE_512KB 0x00040000 1689173138Srwatson#define BGE_SSRAMSIZE_1MB 0x00080000 1690173138Srwatson#define BGE_SSRAMSIZE_2MB 0x000C0000 1691173138Srwatson#define BGE_SSRAMSIZE_4MB 0x00100000 1692173138Srwatson#define BGE_SSRAMSIZE_8MB 0x00140000 1693173138Srwatson#define BGE_SSRAMSIZE_16M 0x00180000 1694173138Srwatson 1695173138Srwatson/* EEPROM address register */ 1696173138Srwatson#define BGE_EEADDR_ADDRESS 0x0000FFFC 1697173138Srwatson#define BGE_EEADDR_HALFCLK 0x01FF0000 1698173138Srwatson#define BGE_EEADDR_START 0x02000000 1699173138Srwatson#define BGE_EEADDR_DEVID 0x1C000000 1700173138Srwatson#define BGE_EEADDR_RESET 0x20000000 1701173138Srwatson#define BGE_EEADDR_DONE 0x40000000 1702173138Srwatson#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1703173138Srwatson 1704173138Srwatson#define BGE_EEDEVID(x) ((x & 7) << 26) 1705173138Srwatson#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1706173138Srwatson#define BGE_HALFCLK_384SCL 0x60 1707173138Srwatson#define BGE_EE_READCMD \ 1708173138Srwatson (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1709173138Srwatson BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1710173138Srwatson#define BGE_EE_WRCMD \ 1711173138Srwatson (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1712173138Srwatson BGE_EEADDR_START|BGE_EEADDR_DONE) 1713173138Srwatson 1714173138Srwatson/* EEPROM Control register */ 1715173138Srwatson#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1716173138Srwatson#define BGE_EECTL_CLKOUT 0x00000002 1717173138Srwatson#define BGE_EECTL_CLKIN 0x00000004 1718173138Srwatson#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1719173138Srwatson#define BGE_EECTL_DATAOUT 0x00000010 1720173138Srwatson#define BGE_EECTL_DATAIN 0x00000020 1721173138Srwatson 1722173138Srwatson/* MDI (MII/GMII) access register */ 1723173138Srwatson#define BGE_MDI_DATA 0x00000001 1724173138Srwatson#define BGE_MDI_DIR 0x00000002 1725173138Srwatson#define BGE_MDI_SEL 0x00000004 1726173138Srwatson#define BGE_MDI_CLK 0x00000008 1727173138Srwatson 1728173138Srwatson#define BGE_MEMWIN_START 0x00008000 1729173138Srwatson#define BGE_MEMWIN_END 0x0000FFFF 1730173138Srwatson 1731173138Srwatson 1732173138Srwatson#define BGE_MEMWIN_READ(sc, x, val) \ 1733173138Srwatson do { \ 1734173138Srwatson pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1735173138Srwatson (0xFFFF0000 & x), 4); \ 1736173138Srwatson val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1737173138Srwatson } while(0) 1738173138Srwatson 1739173138Srwatson#define BGE_MEMWIN_WRITE(sc, x, val) \ 1740173138Srwatson do { \ 1741173138Srwatson pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1742173138Srwatson (0xFFFF0000 & x), 4); \ 1743173138Srwatson CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1744173138Srwatson } while(0) 1745173138Srwatson 1746173138Srwatson/* 1747173138Srwatson * This magic number is used to prevent PXE restart when we 1748173138Srwatson * issue a software reset. We write this magic number to the 1749173138Srwatson * firmware mailbox at 0xB50 in order to prevent the PXE boot 1750173138Srwatson * code from running. 1751173138Srwatson */ 1752173138Srwatson#define BGE_MAGIC_NUMBER 0x4B657654 1753173138Srwatson 1754173138Srwatsontypedef struct { 1755173138Srwatson u_int32_t bge_addr_hi; 1756173138Srwatson u_int32_t bge_addr_lo; 1757173138Srwatson} bge_hostaddr; 1758173138Srwatson 1759173138Srwatson#define BGE_HOSTADDR(x, y) \ 1760173138Srwatson do { \ 1761173138Srwatson (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 1762173138Srwatson (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 1763173138Srwatson } while(0) 1764173138Srwatson 1765173138Srwatson#define BGE_ADDR_LO(y) \ 1766173138Srwatson ((u_int64_t) (y) & 0xFFFFFFFF) 1767173138Srwatson#define BGE_ADDR_HI(y) \ 1768173138Srwatson ((u_int64_t) (y) >> 32) 1769173138Srwatson 1770173138Srwatson/* Ring control block structure */ 1771173138Srwatsonstruct bge_rcb { 1772173138Srwatson bge_hostaddr bge_hostaddr; 1773140628Srwatson u_int32_t bge_maxlen_flags; 1774140628Srwatson u_int32_t bge_nicaddr; 1775140628Srwatson}; 1776173138Srwatson 1777173138Srwatson#define RCB_WRITE_4(sc, rcb, offset, val) \ 1778173138Srwatson bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1779173138Srwatson rcb + offsetof(struct bge_rcb, offset), val) 1780173138Srwatson#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1781173138Srwatson 1782173138Srwatson#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1783173138Srwatson#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1784173138Srwatson 1785173138Srwatsonstruct bge_tx_bd { 1786173138Srwatson bge_hostaddr bge_addr; 1787140628Srwatson#if BYTE_ORDER == LITTLE_ENDIAN 1788173138Srwatson u_int16_t bge_flags; 1789140628Srwatson u_int16_t bge_len; 1790140628Srwatson u_int16_t bge_vlan_tag; 1791140628Srwatson u_int16_t bge_rsvd; 1792172955Srwatson#else 1793140628Srwatson u_int16_t bge_len; 1794140628Srwatson u_int16_t bge_flags; 1795140628Srwatson u_int16_t bge_rsvd; 1796173138Srwatson u_int16_t bge_vlan_tag; 1797140628Srwatson#endif 1798173138Srwatson}; 1799172955Srwatson 1800173138Srwatson#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1801173138Srwatson#define BGE_TXBDFLAG_IP_CSUM 0x0002 1802140628Srwatson#define BGE_TXBDFLAG_END 0x0004 1803140628Srwatson#define BGE_TXBDFLAG_IP_FRAG 0x0008 1804140628Srwatson#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1805140628Srwatson#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1806140628Srwatson#define BGE_TXBDFLAG_COAL_NOW 0x0080 1807140628Srwatson#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1808173138Srwatson#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1809140628Srwatson#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1810140628Srwatson#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1811140628Srwatson#define BGE_TXBDFLAG_NO_CRC 0x8000 1812172955Srwatson 1813140628Srwatson#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1814140628Srwatson BGE_SEND_RING_1_TO_4 + \ 1815140628Srwatson ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1816173138Srwatson 1817140628Srwatsonstruct bge_rx_bd { 1818173138Srwatson bge_hostaddr bge_addr; 1819173138Srwatson#if BYTE_ORDER == LITTLE_ENDIAN 1820173138Srwatson u_int16_t bge_len; 1821172955Srwatson u_int16_t bge_idx; 1822140628Srwatson u_int16_t bge_flags; 1823140628Srwatson u_int16_t bge_type; 1824140628Srwatson u_int16_t bge_tcp_udp_csum; 1825140628Srwatson u_int16_t bge_ip_csum; 1826140628Srwatson u_int16_t bge_vlan_tag; 1827140628Srwatson u_int16_t bge_error_flag; 1828173138Srwatson#else 1829140628Srwatson u_int16_t bge_idx; 1830140628Srwatson u_int16_t bge_len; 1831140628Srwatson u_int16_t bge_type; 1832172955Srwatson u_int16_t bge_flags; 1833140628Srwatson u_int16_t bge_ip_csum; 1834140628Srwatson u_int16_t bge_tcp_udp_csum; 1835140628Srwatson u_int16_t bge_error_flag; 1836173138Srwatson u_int16_t bge_vlan_tag; 1837140628Srwatson#endif 1838173138Srwatson u_int32_t bge_rsvd; 1839172955Srwatson u_int32_t bge_opaque; 1840173138Srwatson}; 1841173138Srwatson 1842140628Srwatsonstruct bge_extrx_bd { 1843140628Srwatson bge_hostaddr bge_addr1; 1844140628Srwatson bge_hostaddr bge_addr2; 1845140628Srwatson bge_hostaddr bge_addr3; 1846140628Srwatson#if BYTE_ORDER == LITTLE_ENDIAN 1847140628Srwatson u_int16_t bge_len2; 1848173138Srwatson u_int16_t bge_len1; 1849173138Srwatson u_int16_t bge_rsvd1; 1850140628Srwatson u_int16_t bge_len3; 1851173138Srwatson#else 1852140628Srwatson u_int16_t bge_len1; 1853172955Srwatson u_int16_t bge_len2; 1854140628Srwatson u_int16_t bge_len3; 1855140628Srwatson u_int16_t bge_rsvd1; 1856173138Srwatson#endif 1857173138Srwatson bge_hostaddr bge_addr0; 1858140628Srwatson#if BYTE_ORDER == LITTLE_ENDIAN 1859173138Srwatson u_int16_t bge_len0; 1860173138Srwatson u_int16_t bge_idx; 1861140628Srwatson u_int16_t bge_flags; 1862173138Srwatson u_int16_t bge_type; 1863173138Srwatson u_int16_t bge_tcp_udp_csum; 1864173138Srwatson u_int16_t bge_ip_csum; 1865173138Srwatson u_int16_t bge_vlan_tag; 1866140628Srwatson u_int16_t bge_error_flag; 1867173138Srwatson#else 1868140628Srwatson u_int16_t bge_idx; 1869173138Srwatson u_int16_t bge_len0; 1870173138Srwatson u_int16_t bge_type; 1871173138Srwatson u_int16_t bge_flags; 1872140628Srwatson u_int16_t bge_ip_csum; 1873140628Srwatson u_int16_t bge_tcp_udp_csum; 1874173138Srwatson u_int16_t bge_error_flag; 1875173138Srwatson u_int16_t bge_vlan_tag; 1876173138Srwatson#endif 1877173138Srwatson u_int32_t bge_rsvd0; 1878173138Srwatson u_int32_t bge_opaque; 1879173138Srwatson}; 1880173138Srwatson 1881173138Srwatson#define BGE_RXBDFLAG_END 0x0004 1882173138Srwatson#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1883173138Srwatson#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1884173138Srwatson#define BGE_RXBDFLAG_ERROR 0x0400 1885173138Srwatson#define BGE_RXBDFLAG_MINI_RING 0x0800 1886140628Srwatson#define BGE_RXBDFLAG_IP_CSUM 0x1000 1887173138Srwatson#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1888173138Srwatson#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1889140628Srwatson 1890173138Srwatson#define BGE_RXERRFLAG_BAD_CRC 0x0001 1891173138Srwatson#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1892140628Srwatson#define BGE_RXERRFLAG_LINK_LOST 0x0004 1893173138Srwatson#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1894140628Srwatson#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1895173138Srwatson#define BGE_RXERRFLAG_RUNT 0x0020 1896140628Srwatson#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1897173138Srwatson#define BGE_RXERRFLAG_GIANT 0x0080 1898173138Srwatson 1899173138Srwatsonstruct bge_sts_idx { 1900173138Srwatson#if BYTE_ORDER == LITTLE_ENDIAN 1901173138Srwatson u_int16_t bge_rx_prod_idx; 1902173138Srwatson u_int16_t bge_tx_cons_idx; 1903173138Srwatson#else 1904140628Srwatson u_int16_t bge_tx_cons_idx; 1905173138Srwatson u_int16_t bge_rx_prod_idx; 1906173138Srwatson#endif 1907173138Srwatson}; 1908173138Srwatson 1909173138Srwatsonstruct bge_status_block { 1910173138Srwatson u_int32_t bge_status; 1911140628Srwatson u_int32_t bge_rsvd0; 1912173138Srwatson#if BYTE_ORDER == LITTLE_ENDIAN 1913173138Srwatson u_int16_t bge_rx_jumbo_cons_idx; 1914173138Srwatson u_int16_t bge_rx_std_cons_idx; 1915173138Srwatson u_int16_t bge_rx_mini_cons_idx; 1916173138Srwatson u_int16_t bge_rsvd1; 1917173138Srwatson#else 1918173138Srwatson u_int16_t bge_rx_std_cons_idx; 1919173138Srwatson u_int16_t bge_rx_jumbo_cons_idx; 1920173138Srwatson u_int16_t bge_rsvd1; 1921173138Srwatson u_int16_t bge_rx_mini_cons_idx; 1922173138Srwatson#endif 1923173138Srwatson struct bge_sts_idx bge_idx[16]; 1924173138Srwatson}; 1925173138Srwatson 1926173138Srwatson#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1927173138Srwatson#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1928173138Srwatson 1929173138Srwatson#define BGE_STATFLAG_UPDATED 0x00000001 1930173138Srwatson#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1931173138Srwatson#define BGE_STATFLAG_ERROR 0x00000004 1932140628Srwatson 1933140628Srwatson 1934140628Srwatson/* 1935140628Srwatson * Broadcom Vendor ID 1936140628Srwatson * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1937140628Srwatson * even though they're now manufactured by Broadcom) 1938173138Srwatson */ 1939173138Srwatson#define BCOM_VENDORID 0x14E4 1940140628Srwatson#define BCOM_DEVICEID_BCM5700 0x1644 1941140628Srwatson#define BCOM_DEVICEID_BCM5701 0x1645 1942140628Srwatson#define BCOM_DEVICEID_BCM5702 0x16A6 1943172955Srwatson#define BCOM_DEVICEID_BCM5702X 0x16C6 1944140628Srwatson#define BCOM_DEVICEID_BCM5703 0x16A7 1945140628Srwatson#define BCOM_DEVICEID_BCM5703X 0x16C7 1946140628Srwatson#define BCOM_DEVICEID_BCM5704C 0x1648 1947173138Srwatson#define BCOM_DEVICEID_BCM5704S 0x16A8 1948140628Srwatson#define BCOM_DEVICEID_BCM5705 0x1653 1949172955Srwatson#define BCOM_DEVICEID_BCM5705K 0x1654 1950173138Srwatson#define BCOM_DEVICEID_BCM5721 0x1659 1951140628Srwatson#define BCOM_DEVICEID_BCM5705M 0x165D 1952140628Srwatson#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 1953140628Srwatson#define BCOM_DEVICEID_BCM5714C 0x1668 1954140628Srwatson#define BCOM_DEVICEID_BCM5750 0x1676 1955173138Srwatson#define BCOM_DEVICEID_BCM5750M 0x167C 1956173138Srwatson#define BCOM_DEVICEID_BCM5751 0x1677 1957173138Srwatson#define BCOM_DEVICEID_BCM5751M 0x167D 1958140628Srwatson#define BCOM_DEVICEID_BCM5752 0x1600 1959173138Srwatson#define BCOM_DEVICEID_BCM5782 0x1696 1960140628Srwatson#define BCOM_DEVICEID_BCM5788 0x169C 1961173138Srwatson#define BCOM_DEVICEID_BCM5789 0x169D 1962173138Srwatson#define BCOM_DEVICEID_BCM5901 0x170D 1963140628Srwatson#define BCOM_DEVICEID_BCM5901A2 0x170E 1964173138Srwatson 1965173138Srwatson/* 1966140628Srwatson * Alteon AceNIC PCI vendor/device ID. 1967173138Srwatson */ 1968173138Srwatson#define ALT_VENDORID 0x12AE 1969173138Srwatson#define ALT_DEVICEID_ACENIC 0x0001 1970173138Srwatson#define ALT_DEVICEID_ACENIC_COPPER 0x0002 1971173138Srwatson#define ALT_DEVICEID_BCM5700 0x0003 1972140628Srwatson#define ALT_DEVICEID_BCM5701 0x0004 1973173138Srwatson 1974173138Srwatson/* 1975140628Srwatson * 3Com 3c985 PCI vendor/device ID. 1976173138Srwatson */ 1977140628Srwatson#define TC_VENDORID 0x10B7 1978140628Srwatson#define TC_DEVICEID_3C985 0x0001 1979173138Srwatson#define TC_DEVICEID_3C996 0x0003 1980173138Srwatson 1981173138Srwatson/* 1982140628Srwatson * SysKonnect PCI vendor ID 1983173138Srwatson */ 1984140628Srwatson#define SK_VENDORID 0x1148 1985173138Srwatson#define SK_DEVICEID_ALTIMA 0x4400 1986173138Srwatson#define SK_SUBSYSID_9D21 0x4421 1987140628Srwatson#define SK_SUBSYSID_9D41 0x4441 1988173138Srwatson 1989140628Srwatson/* 1990140628Srwatson * Altima PCI vendor/device ID. 1991173138Srwatson */ 1992173138Srwatson#define ALTIMA_VENDORID 0x173b 1993173138Srwatson#define ALTIMA_DEVICE_AC1000 0x03e8 1994140628Srwatson#define ALTIMA_DEVICE_AC1002 0x03e9 1995173138Srwatson#define ALTIMA_DEVICE_AC9100 0x03ea 1996140628Srwatson 1997173138Srwatson/* 1998173138Srwatson * Dell PCI vendor ID 1999140628Srwatson */ 2000173138Srwatson 2001173138Srwatson#define DELL_VENDORID 0x1028 2002140628Srwatson 2003173138Srwatson/* 2004173138Srwatson * Offset of MAC address inside EEPROM. 2005173138Srwatson */ 2006173138Srwatson#define BGE_EE_MAC_OFFSET 0x7C 2007173138Srwatson#define BGE_EE_HWCFG_OFFSET 0xC8 2008140628Srwatson 2009173138Srwatson#define BGE_HWCFG_VOLTAGE 0x00000003 2010173138Srwatson#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2011140628Srwatson#define BGE_HWCFG_MEDIA 0x00000030 2012173138Srwatson 2013140628Srwatson#define BGE_VOLTAGE_1POINT3 0x00000000 2014140628Srwatson#define BGE_VOLTAGE_1POINT8 0x00000001 2015173138Srwatson 2016173138Srwatson#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2017173138Srwatson#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2018173138Srwatson#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2019140628Srwatson 2020173138Srwatson#define BGE_MEDIA_UNSPEC 0x00000000 2021140628Srwatson#define BGE_MEDIA_COPPER 0x00000010 2022173138Srwatson#define BGE_MEDIA_FIBER 0x00000020 2023173138Srwatson 2024140628Srwatson#define BGE_PCI_READ_CMD 0x06000000 2025173138Srwatson#define BGE_PCI_WRITE_CMD 0x70000000 2026173138Srwatson 2027140628Srwatson#define BGE_TICKS_PER_SEC 1000000 2028173138Srwatson 2029173138Srwatson/* 2030173138Srwatson * Ring size constants. 2031173138Srwatson */ 2032140628Srwatson#define BGE_EVENT_RING_CNT 256 2033173138Srwatson#define BGE_CMD_RING_CNT 64 2034173138Srwatson#define BGE_STD_RX_RING_CNT 512 2035173138Srwatson#define BGE_JUMBO_RX_RING_CNT 256 2036140628Srwatson#define BGE_MINI_RX_RING_CNT 1024 2037140628Srwatson#define BGE_RETURN_RING_CNT 1024 2038173138Srwatson 2039173138Srwatson/* 5705 has smaller return ring size */ 2040173138Srwatson 2041173138Srwatson#define BGE_RETURN_RING_CNT_5705 512 2042173138Srwatson 2043173138Srwatson/* 2044173138Srwatson * Possible TX ring sizes. 2045173138Srwatson */ 2046173138Srwatson#define BGE_TX_RING_CNT_128 128 2047173138Srwatson#define BGE_TX_RING_BASE_128 0x3800 2048173138Srwatson 2049140628Srwatson#define BGE_TX_RING_CNT_256 256 2050173138Srwatson#define BGE_TX_RING_BASE_256 0x3000 2051168976Srwatson 2052110354Srwatson#define BGE_TX_RING_CNT_512 512 2053110354Srwatson#define BGE_TX_RING_BASE_512 0x2000 2054110354Srwatson 2055110354Srwatson#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2056172955Srwatson#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2057110354Srwatson 2058110354Srwatson/* 2059122524Srwatson * Tigon III statistics counters. 2060110354Srwatson */ 2061172955Srwatson/* Statistics maintained MAC Receive block. */ 2062110354Srwatsonstruct bge_rx_mac_stats { 2063110354Srwatson bge_hostaddr ifHCInOctets; 2064110354Srwatson bge_hostaddr Reserved1; 2065173138Srwatson bge_hostaddr etherStatsFragments; 2066173138Srwatson bge_hostaddr ifHCInUcastPkts; 2067173138Srwatson bge_hostaddr ifHCInMulticastPkts; 2068168976Srwatson bge_hostaddr ifHCInBroadcastPkts; 2069172955Srwatson bge_hostaddr dot3StatsFCSErrors; 2070110354Srwatson bge_hostaddr dot3StatsAlignmentErrors; 2071110354Srwatson bge_hostaddr xonPauseFramesReceived; 2072110354Srwatson bge_hostaddr xoffPauseFramesReceived; 2073110354Srwatson bge_hostaddr macControlFramesReceived; 2074110354Srwatson bge_hostaddr xoffStateEntered; 2075110354Srwatson bge_hostaddr dot3StatsFramesTooLong; 2076173138Srwatson bge_hostaddr etherStatsJabbers; 2077173138Srwatson bge_hostaddr etherStatsUndersizePkts; 2078101099Srwatson bge_hostaddr inRangeLengthError; 2079101099Srwatson bge_hostaddr outRangeLengthError; 2080173138Srwatson bge_hostaddr etherStatsPkts64Octets; 2081101099Srwatson bge_hostaddr etherStatsPkts65Octetsto127Octets; 2082172955Srwatson bge_hostaddr etherStatsPkts128Octetsto255Octets; 2083101099Srwatson bge_hostaddr etherStatsPkts256Octetsto511Octets; 2084101099Srwatson bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2085122524Srwatson bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2086101099Srwatson bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2087173138Srwatson bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2088173138Srwatson bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2089173138Srwatson bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2090173138Srwatson}; 2091173138Srwatson 2092173138Srwatson 2093173138Srwatson/* Statistics maintained MAC Transmit block. */ 2094173138Srwatsonstruct bge_tx_mac_stats { 2095173138Srwatson bge_hostaddr ifHCOutOctets; 2096101099Srwatson bge_hostaddr Reserved2; 2097101099Srwatson bge_hostaddr etherStatsCollisions; 2098101099Srwatson bge_hostaddr outXonSent; 2099101099Srwatson bge_hostaddr outXoffSent; 2100101099Srwatson bge_hostaddr flowControlDone; 2101101099Srwatson bge_hostaddr dot3StatsInternalMacTransmitErrors; 2102173138Srwatson bge_hostaddr dot3StatsSingleCollisionFrames; 2103101099Srwatson bge_hostaddr dot3StatsMultipleCollisionFrames; 2104173138Srwatson bge_hostaddr dot3StatsDeferredTransmissions; 2105173138Srwatson bge_hostaddr Reserved3; 2106103759Srwatson bge_hostaddr dot3StatsExcessiveCollisions; 2107173138Srwatson bge_hostaddr dot3StatsLateCollisions; 2108101099Srwatson bge_hostaddr dot3Collided2Times; 2109101099Srwatson bge_hostaddr dot3Collided3Times; 2110173138Srwatson bge_hostaddr dot3Collided4Times; 2111101099Srwatson bge_hostaddr dot3Collided5Times; 2112173138Srwatson bge_hostaddr dot3Collided6Times; 2113173138Srwatson bge_hostaddr dot3Collided7Times; 2114173138Srwatson bge_hostaddr dot3Collided8Times; 2115173138Srwatson bge_hostaddr dot3Collided9Times; 2116101099Srwatson bge_hostaddr dot3Collided10Times; 2117101099Srwatson bge_hostaddr dot3Collided11Times; 2118101099Srwatson bge_hostaddr dot3Collided12Times; 2119101099Srwatson bge_hostaddr dot3Collided13Times; 2120173138Srwatson bge_hostaddr dot3Collided14Times; 2121173138Srwatson bge_hostaddr dot3Collided15Times; 2122101099Srwatson bge_hostaddr ifHCOutUcastPkts; 2123173138Srwatson bge_hostaddr ifHCOutMulticastPkts; 2124173138Srwatson bge_hostaddr ifHCOutBroadcastPkts; 2125101099Srwatson bge_hostaddr dot3StatsCarrierSenseErrors; 2126172955Srwatson bge_hostaddr ifOutDiscards; 2127101099Srwatson bge_hostaddr ifOutErrors; 2128101099Srwatson}; 2129122524Srwatson 2130101099Srwatson/* Stats counters access through registers */ 2131173138Srwatsonstruct bge_mac_stats_regs { 2132173138Srwatson u_int32_t ifHCOutOctets; 2133173138Srwatson u_int32_t Reserved0; 2134101099Srwatson u_int32_t etherStatsCollisions; 2135101099Srwatson u_int32_t outXonSent; 2136101099Srwatson u_int32_t outXoffSent; 2137101099Srwatson u_int32_t Reserved1; 2138101099Srwatson u_int32_t dot3StatsInternalMacTransmitErrors; 2139173138Srwatson u_int32_t dot3StatsSingleCollisionFrames; 2140173138Srwatson u_int32_t dot3StatsMultipleCollisionFrames; 2141102115Srwatson u_int32_t dot3StatsDeferredTransmissions; 2142102115Srwatson u_int32_t Reserved2; 2143173138Srwatson u_int32_t dot3StatsExcessiveCollisions; 2144102115Srwatson u_int32_t dot3StatsLateCollisions; 2145172955Srwatson u_int32_t Reserved3[14]; 2146102115Srwatson u_int32_t ifHCOutUcastPkts; 2147102115Srwatson u_int32_t ifHCOutMulticastPkts; 2148122524Srwatson u_int32_t ifHCOutBroadcastPkts; 2149173138Srwatson u_int32_t Reserved4[2]; 2150102115Srwatson u_int32_t ifHCInOctets; 2151173138Srwatson u_int32_t Reserved5; 2152173138Srwatson u_int32_t etherStatsFragments; 2153173138Srwatson u_int32_t ifHCInUcastPkts; 2154173138Srwatson u_int32_t ifHCInMulticastPkts; 2155173138Srwatson u_int32_t ifHCInBroadcastPkts; 2156102115Srwatson u_int32_t dot3StatsFCSErrors; 2157102115Srwatson u_int32_t dot3StatsAlignmentErrors; 2158102115Srwatson u_int32_t xonPauseFramesReceived; 2159102115Srwatson u_int32_t xoffPauseFramesReceived; 2160102115Srwatson u_int32_t macControlFramesReceived; 2161102115Srwatson u_int32_t xoffStateEntered; 2162173138Srwatson u_int32_t dot3StatsFramesTooLong; 2163173138Srwatson u_int32_t etherStatsJabbers; 2164101099Srwatson u_int32_t etherStatsUndersizePkts; 2165173138Srwatson}; 2166105634Srwatson 2167101099Srwatsonstruct bge_stats { 2168173138Srwatson u_int8_t Reserved0[256]; 2169173138Srwatson 2170173138Srwatson /* Statistics maintained by Receive MAC. */ 2171122524Srwatson struct bge_rx_mac_stats rxstats; 2172101099Srwatson 2173101099Srwatson bge_hostaddr Unused1[37]; 2174173138Srwatson 2175173138Srwatson /* Statistics maintained by Transmit MAC. */ 2176101099Srwatson struct bge_tx_mac_stats txstats; 2177173138Srwatson 2178173138Srwatson bge_hostaddr Unused2[31]; 2179173138Srwatson 2180101099Srwatson /* Statistics maintained by Receive List Placement. */ 2181173138Srwatson bge_hostaddr COSIfHCInPkts[16]; 2182173138Srwatson bge_hostaddr COSFramesDroppedDueToFilters; 2183173138Srwatson bge_hostaddr nicDmaWriteQueueFull; 2184105634Srwatson bge_hostaddr nicDmaWriteHighPriQueueFull; 2185105634Srwatson bge_hostaddr nicNoMoreRxBDs; 2186101099Srwatson bge_hostaddr ifInDiscards; 2187101099Srwatson bge_hostaddr ifInErrors; 2188101099Srwatson bge_hostaddr nicRecvThresholdHit; 2189173138Srwatson 2190173138Srwatson bge_hostaddr Unused3[9]; 2191102115Srwatson 2192102115Srwatson /* Statistics maintained by Send Data Initiator. */ 2193173138Srwatson bge_hostaddr COSIfHCOutPkts[16]; 2194173138Srwatson bge_hostaddr nicDmaReadQueueFull; 2195102115Srwatson bge_hostaddr nicDmaReadHighPriQueueFull; 2196173138Srwatson bge_hostaddr nicSendDataCompQueueFull; 2197173138Srwatson 2198173138Srwatson /* Statistics maintained by Host Coalescing. */ 2199173138Srwatson bge_hostaddr nicRingSetSendProdIndex; 2200173138Srwatson bge_hostaddr nicRingStatusUpdate; 2201102115Srwatson bge_hostaddr nicInterrupts; 2202173138Srwatson bge_hostaddr nicAvoidedInterrupts; 2203173138Srwatson bge_hostaddr nicSendThresholdHit; 2204173138Srwatson 2205102115Srwatson u_int8_t Reserved4[320]; 2206173138Srwatson}; 2207102115Srwatson 2208102115Srwatson/* 2209102115Srwatson * Tigon general information block. This resides in host memory 2210173138Srwatson * and contains the status counters, ring control blocks and 2211173138Srwatson * producer pointers. 2212102115Srwatson */ 2213102115Srwatson 2214102115Srwatsonstruct bge_gib { 2215172955Srwatson struct bge_stats bge_stats; 2216102115Srwatson struct bge_rcb bge_tx_rcb[16]; 2217102115Srwatson struct bge_rcb bge_std_rx_rcb; 2218122524Srwatson struct bge_rcb bge_jumbo_rx_rcb; 2219173138Srwatson struct bge_rcb bge_mini_rx_rcb; 2220102115Srwatson struct bge_rcb bge_return_rcb; 2221173138Srwatson}; 2222102115Srwatson 2223102115Srwatson#define BGE_FRAMELEN 1518 2224102115Srwatson#define BGE_MAX_FRAMELEN 1536 2225102115Srwatson#define BGE_JUMBO_FRAMELEN 9018 2226102115Srwatson#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2227102115Srwatson#define BGE_MIN_FRAMELEN 60 2228173138Srwatson 2229173138Srwatson/* 2230145855Srwatson * Other utility macros. 2231145855Srwatson */ 2232145855Srwatson#define BGE_INC(x, y) (x) = (x + 1) % y 2233172955Srwatson 2234145855Srwatson/* 2235145855Srwatson * Vital product data and structures. 2236145855Srwatson */ 2237173138Srwatson#define BGE_VPD_FLAG 0x8000 2238145855Srwatson 2239172955Srwatson/* VPD structures */ 2240145855Srwatsonstruct vpd_res { 2241145855Srwatson u_int8_t vr_id; 2242145855Srwatson u_int8_t vr_len; 2243145855Srwatson u_int8_t vr_pad; 2244145855Srwatson}; 2245145855Srwatson 2246173138Srwatsonstruct vpd_key { 2247173138Srwatson char vk_key[2]; 2248145855Srwatson u_int8_t vk_len; 2249145855Srwatson}; 2250145855Srwatson 2251172955Srwatson#define VPD_RES_ID 0x82 /* ID string */ 2252145855Srwatson#define VPD_RES_READ 0x90 /* start of read only area */ 2253145855Srwatson#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2254145855Srwatson#define VPD_RES_END 0x78 /* end tag */ 2255173138Srwatson 2256145855Srwatson 2257172955Srwatson/* 2258145855Srwatson * Register access macros. The Tigon always uses memory mapped register 2259145855Srwatson * accesses and all registers must be accessed with 32 bit operations. 2260145855Srwatson */ 2261145855Srwatson 2262145855Srwatson#define CSR_WRITE_4(sc, reg, val) \ 2263145855Srwatson bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2264173138Srwatson 2265173138Srwatson#define CSR_READ_4(sc, reg) \ 2266101099Srwatson bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2267101099Srwatson 2268101099Srwatson#define BGE_SETBIT(sc, reg, x) \ 2269172955Srwatson CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2270101099Srwatson#define BGE_CLRBIT(sc, reg, x) \ 2271101099Srwatson CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2272122524Srwatson 2273173138Srwatson#define PCI_SETBIT(dev, reg, x, s) \ 2274101099Srwatson pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2275172955Srwatson#define PCI_CLRBIT(dev, reg, x, s) \ 2276101099Srwatson pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2277101099Srwatson 2278101099Srwatson/* 2279101099Srwatson * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2280101099Srwatson * values are tuneable. They control the actual amount of buffers 2281101099Srwatson * allocated for the standard, mini and jumbo receive rings. 2282173138Srwatson */ 2283173138Srwatson 2284101099Srwatson#define BGE_SSLOTS 256 2285101099Srwatson#define BGE_MSLOTS 256 2286103759Srwatson#define BGE_JSLOTS 384 2287172955Srwatson 2288101099Srwatson#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2289101099Srwatson#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2290122524Srwatson (BGE_JRAWLEN % sizeof(u_int64_t)))) 2291173138Srwatson#define BGE_JPAGESZ PAGE_SIZE 2292103759Srwatson#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2293172955Srwatson#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2294101099Srwatson 2295101099Srwatson#define BGE_NSEG_JUMBO 4 2296101099Srwatson#define BGE_NSEG_NEW 32 2297101099Srwatson 2298101099Srwatson/* 2299101099Srwatson * Ring structures. Most of these reside in host memory and we tell 2300173138Srwatson * the NIC where they are via the ring control blocks. The exceptions 2301173138Srwatson * are the tx and command rings, which live in NIC memory and which 2302101099Srwatson * we access via the shared memory window. 2303101099Srwatson */ 2304103759Srwatson 2305172955Srwatsonstruct bge_ring_data { 2306101099Srwatson struct bge_rx_bd *bge_rx_std_ring; 2307101099Srwatson bus_addr_t bge_rx_std_ring_paddr; 2308122524Srwatson struct bge_extrx_bd *bge_rx_jumbo_ring; 2309173138Srwatson bus_addr_t bge_rx_jumbo_ring_paddr; 2310103759Srwatson struct bge_rx_bd *bge_rx_return_ring; 2311173138Srwatson bus_addr_t bge_rx_return_ring_paddr; 2312173138Srwatson struct bge_tx_bd *bge_tx_ring; 2313173138Srwatson bus_addr_t bge_tx_ring_paddr; 2314173138Srwatson struct bge_status_block *bge_status_block; 2315173138Srwatson bus_addr_t bge_status_block_paddr; 2316173138Srwatson struct bge_stats *bge_stats; 2317173138Srwatson bus_addr_t bge_stats_paddr; 2318173138Srwatson struct bge_gib bge_info; 2319173138Srwatson}; 2320173138Srwatson 2321173138Srwatson#define BGE_STD_RX_RING_SZ \ 2322173138Srwatson (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2323173138Srwatson#define BGE_JUMBO_RX_RING_SZ \ 2324101099Srwatson (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2325173138Srwatson#define BGE_TX_RING_SZ \ 2326101099Srwatson (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2327101099Srwatson#define BGE_RX_RTN_RING_SZ(x) \ 2328101099Srwatson (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2329101099Srwatson 2330173138Srwatson#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2331173138Srwatson 2332101099Srwatson#define BGE_STATS_SZ sizeof (struct bge_stats) 2333101099Srwatson 2334173138Srwatson/* 2335173138Srwatson * Mbuf pointers. We need these to keep track of the virtual addresses 2336101099Srwatson * of our mbuf chains since we can only convert from physical to virtual, 2337173138Srwatson * not the other way around. 2338173138Srwatson */ 2339173138Srwatsonstruct bge_chain_data { 2340173138Srwatson bus_dma_tag_t bge_parent_tag; 2341173138Srwatson bus_dma_tag_t bge_rx_std_ring_tag; 2342101099Srwatson bus_dma_tag_t bge_rx_jumbo_ring_tag; 2343173138Srwatson bus_dma_tag_t bge_rx_return_ring_tag; 2344173138Srwatson bus_dma_tag_t bge_tx_ring_tag; 2345173138Srwatson bus_dma_tag_t bge_status_tag; 2346173138Srwatson bus_dma_tag_t bge_stats_tag; 2347101099Srwatson bus_dma_tag_t bge_mtag; /* mbuf mapping tag */ 2348101099Srwatson bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */ 2349101099Srwatson bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2350173138Srwatson bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2351173138Srwatson bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2352101099Srwatson bus_dmamap_t bge_rx_std_ring_map; 2353173138Srwatson bus_dmamap_t bge_rx_jumbo_ring_map; 2354101099Srwatson bus_dmamap_t bge_tx_ring_map; 2355173138Srwatson bus_dmamap_t bge_rx_return_ring_map; 2356173138Srwatson bus_dmamap_t bge_status_map; 2357173138Srwatson bus_dmamap_t bge_stats_map; 2358122524Srwatson struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2359173138Srwatson struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2360101099Srwatson struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2361173138Srwatson}; 2362173138Srwatson 2363173138Srwatsonstruct bge_dmamap_arg { 2364173138Srwatson struct bge_softc *sc; 2365173138Srwatson bus_addr_t bge_busaddr; 2366173138Srwatson u_int16_t bge_flags; 2367173138Srwatson int bge_idx; 2368173138Srwatson int bge_maxsegs; 2369101099Srwatson struct bge_tx_bd *bge_ring; 2370173138Srwatson}; 2371173138Srwatson 2372173138Srwatsonstruct bge_type { 2373173138Srwatson u_int16_t bge_vid; 2374173138Srwatson u_int16_t bge_did; 2375173138Srwatson char *bge_name; 2376173138Srwatson}; 2377173138Srwatson 2378173138Srwatson#define BGE_HWREV_TIGON 0x01 2379101099Srwatson#define BGE_HWREV_TIGON_II 0x02 2380173138Srwatson#define BGE_TIMEOUT 100000 2381173138Srwatson#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2382105634Srwatson 2383105634Srwatsonstruct bge_bcom_hack { 2384101099Srwatson int reg; 2385101099Srwatson int val; 2386101099Srwatson}; 2387101099Srwatson 2388173138Srwatsonstruct bge_softc { 2389173138Srwatson struct ifnet *bge_ifp; /* interface info */ 2390101099Srwatson device_t bge_dev; 2391101099Srwatson struct mtx bge_mtx; 2392101099Srwatson device_t bge_miibus; 2393172955Srwatson bus_space_handle_t bge_bhandle; 2394105722Srwatson bus_space_tag_t bge_btag; 2395105722Srwatson void *bge_intrhand; 2396122524Srwatson struct resource *bge_irq; 2397173138Srwatson struct resource *bge_res; 2398101099Srwatson struct ifmedia bge_ifmedia; /* TBI media info */ 2399172955Srwatson u_int8_t bge_extram; /* has external SSRAM */ 2400173138Srwatson u_int8_t bge_tbi; 2401101099Srwatson u_int8_t bge_rx_alignment_bug; 2402101099Srwatson u_int32_t bge_chipid; 2403101099Srwatson u_int8_t bge_asicrev; 2404101099Srwatson u_int8_t bge_chiprev; 2405101099Srwatson u_int8_t bge_no_3_led; 2406173138Srwatson u_int8_t bge_pcie; 2407173138Srwatson struct bge_ring_data bge_ldata; /* rings */ 2408112574Srwatson struct bge_chain_data bge_cdata; /* mbufs */ 2409173138Srwatson u_int16_t bge_tx_saved_considx; 2410112574Srwatson u_int16_t bge_rx_saved_considx; 2411172955Srwatson u_int16_t bge_ev_saved_considx; 2412112574Srwatson u_int16_t bge_return_ring_cnt; 2413112574Srwatson u_int16_t bge_std; /* current std ring head */ 2414173138Srwatson u_int16_t bge_jumbo; /* current jumo ring head */ 2415173138Srwatson u_int32_t bge_stat_ticks; 2416112574Srwatson u_int32_t bge_rx_coal_ticks; 2417173138Srwatson u_int32_t bge_tx_coal_ticks; 2418173138Srwatson u_int32_t bge_tx_prodidx; 2419173138Srwatson u_int32_t bge_rx_max_coal_bds; 2420112574Srwatson u_int32_t bge_tx_max_coal_bds; 2421173138Srwatson u_int32_t bge_tx_buf_ratio; 2422173138Srwatson int bge_if_flags; 2423173138Srwatson int bge_txcnt; 2424168951Srwatson int bge_link; /* link state */ 2425173138Srwatson int bge_link_evt; /* pending link event */ 2426173138Srwatson struct callout bge_stat_ch; 2427168951Srwatson char *bge_vpd_prodname; 2428173138Srwatson char *bge_vpd_readonly; 2429173138Srwatson u_long bge_rx_discards; 2430173138Srwatson u_long bge_tx_discards; 2431168951Srwatson u_long bge_tx_collisions; 2432173138Srwatson#ifdef DEVICE_POLLING 2433173138Srwatson int rxcycles; 2434168951Srwatson#endif /* DEVICE_POLLING */ 2435173138Srwatson}; 2436173138Srwatson 2437173138Srwatson#define BGE_LOCK_INIT(_sc, _name) \ 2438173138Srwatson mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2439173138Srwatson#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2440168951Srwatson#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2441173138Srwatson#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2442173138Srwatson#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2443168951Srwatson