if_bgereg.h revision 103103
150276Speter/* 2166124Srafan * Copyright (c) 2001 Wind River Systems 350276Speter * Copyright (c) 1997, 1998, 1999, 2001 450276Speter * Bill Paul <wpaul@windriver.com>. All rights reserved. 550276Speter * 650276Speter * Redistribution and use in source and binary forms, with or without 750276Speter * modification, are permitted provided that the following conditions 850276Speter * are met: 950276Speter * 1. Redistributions of source code must retain the above copyright 1050276Speter * notice, this list of conditions and the following disclaimer. 1150276Speter * 2. Redistributions in binary form must reproduce the above copyright 1250276Speter * notice, this list of conditions and the following disclaimer in the 1350276Speter * documentation and/or other materials provided with the distribution. 1450276Speter * 3. All advertising materials mentioning features or use of this software 1550276Speter * must display the following acknowledgement: 1650276Speter * This product includes software developed by Bill Paul. 1750276Speter * 4. Neither the name of the author nor the names of any co-contributors 1850276Speter * may be used to endorse or promote products derived from this software 1950276Speter * without specific prior written permission. 2050276Speter * 2150276Speter * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2250276Speter * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2350276Speter * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2450276Speter * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2550276Speter * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2650276Speter * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2750276Speter * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2850276Speter * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29166124Srafan * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3050276Speter * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31166124Srafan * THE POSSIBILITY OF SUCH DAMAGE. 32166124Srafan * 3350276Speter * $FreeBSD: head/sys/dev/bge/if_bgereg.h 103103 2002-09-08 19:12:02Z jdp $ 3462449Speter */ 3562449Speter 3662449Speter/* 3762449Speter * BCM570x memory map. The internal memory layout varies somewhat 3862449Speter * depending on whether or not we have external SSRAM attached. 3962449Speter * The BCM5700 can have up to 16MB of external memory. The BCM5701 4062449Speter * is apparently not designed to use external SSRAM. The mappings 4162449Speter * up to the first 4 send rings are the same for both internal and 4262449Speter * external memory configurations. Note that mini RX ring space is 4362449Speter * only available with external SSRAM configurations, which means 4462449Speter * the mini RX ring is not supported on the BCM5701. 45166124Srafan * 46166124Srafan * The NIC's memory can be accessed by the host in one of 3 ways: 4750276Speter * 4850276Speter * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49166124Srafan * registers in PCI config space can be used to read any 32-bit 5050276Speter * address within the NIC's memory. 5150276Speter * 5250276Speter * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5350276Speter * space can be used in conjunction with the memory window in the 5450276Speter * device register space at offset 0x8000 to read any 32K chunk 5550276Speter * of NIC memory. 5650276Speter * 5750276Speter * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5850276Speter * set, the device I/O mapping consumes 32MB of host address space, 5950276Speter * allowing all of the registers and internal NIC memory to be 6050276Speter * accessed directly. NIC memory addresses are offset by 0x01000000. 6150276Speter * Flat mode consumes so much host address space that it is not 6250276Speter * recommended. 6350276Speter */ 6450276Speter#define BGE_PAGE_ZERO 0x00000000 6550276Speter#define BGE_PAGE_ZERO_END 0x000000FF 6650276Speter#define BGE_SEND_RING_RCB 0x00000100 6750276Speter#define BGE_SEND_RING_RCB_END 0x000001FF 6850276Speter#define BGE_RX_RETURN_RING_RCB 0x00000200 6950276Speter#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 7050276Speter#define BGE_STATS_BLOCK 0x00000300 7150276Speter#define BGE_STATS_BLOCK_END 0x00000AFF 7250276Speter#define BGE_STATUS_BLOCK 0x00000B00 7350276Speter#define BGE_STATUS_BLOCK_END 0x00000B4F 7450276Speter#define BGE_SOFTWARE_GENCOMM 0x00000B50 7550276Speter#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 7650276Speter#define BGE_UNMAPPED 0x00001000 7750276Speter#define BGE_UNMAPPED_END 0x00001FFF 7850276Speter#define BGE_DMA_DESCRIPTORS 0x00002000 7950276Speter#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 8050276Speter#define BGE_SEND_RING_1_TO_4 0x00004000 8150276Speter#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 82166124Srafan 8350276Speter/* Mappings for internal memory configuration */ 8450276Speter#define BGE_STD_RX_RINGS 0x00006000 8550276Speter#define BGE_STD_RX_RINGS_END 0x00006FFF 8650276Speter#define BGE_JUMBO_RX_RINGS 0x00007000 87166124Srafan#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 8850276Speter#define BGE_BUFFPOOL_1 0x00008000 8950276Speter#define BGE_BUFFPOOL_1_END 0x0000FFFF 9050276Speter#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 9150276Speter#define BGE_BUFFPOOL_2_END 0x00017FFF 92166124Srafan#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 9350276Speter#define BGE_BUFFPOOL_3_END 0x0001FFFF 9450276Speter 9550276Speter/* Mappings for external SSRAM configurations */ 9650276Speter#define BGE_SEND_RING_5_TO_6 0x00006000 9750276Speter#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 9850276Speter#define BGE_SEND_RING_7_TO_8 0x00007000 9950276Speter#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 10050276Speter#define BGE_SEND_RING_9_TO_16 0x00008000 10150276Speter#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 10250276Speter#define BGE_EXT_STD_RX_RINGS 0x0000C000 103166124Srafan#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 10450276Speter#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 10550276Speter#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 10650276Speter#define BGE_MINI_RX_RINGS 0x0000E000 10750276Speter#define BGE_MINI_RX_RINGS_END 0x0000FFFF 108166124Srafan#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 10950276Speter#define BGE_AVAIL_REGION1_END 0x00017FFF 11050276Speter#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 11150276Speter#define BGE_AVAIL_REGION2_END 0x0001FFFF 11250276Speter#define BGE_EXT_SSRAM 0x00020000 11350276Speter#define BGE_EXT_SSRAM_END 0x000FFFFF 114166124Srafan 11550276Speter 116166124Srafan/* 11750276Speter * BCM570x register offsets. These are memory mapped registers 11850276Speter * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 11950276Speter * Each register must be accessed using 32 bit operations. 12050276Speter * 121166124Srafan * All registers are accessed through a 32K shared memory block. 12250276Speter * The first group of registers are actually copies of the PCI 12350276Speter * configuration space registers. 12450276Speter */ 125166124Srafan 12650276Speter/* 12750276Speter * PCI registers defined in the PCI 2.2 spec. 12850276Speter */ 12950276Speter#define BGE_PCI_VID 0x00 13050276Speter#define BGE_PCI_DID 0x02 13150276Speter#define BGE_PCI_CMD 0x04 13250276Speter#define BGE_PCI_STS 0x06 133166124Srafan#define BGE_PCI_REV 0x08 13450276Speter#define BGE_PCI_CLASS 0x09 135166124Srafan#define BGE_PCI_CACHESZ 0x0C 136166124Srafan#define BGE_PCI_LATTIMER 0x0D 137166124Srafan#define BGE_PCI_HDRTYPE 0x0E 138166124Srafan#define BGE_PCI_BIST 0x0F 139166124Srafan#define BGE_PCI_BAR0 0x10 140166124Srafan#define BGE_PCI_BAR1 0x14 141166124Srafan#define BGE_PCI_SUBSYS 0x2C 142166124Srafan#define BGE_PCI_SUBVID 0x2E 143166124Srafan#define BGE_PCI_ROMBASE 0x30 144166124Srafan#define BGE_PCI_CAPPTR 0x34 145166124Srafan#define BGE_PCI_INTLINE 0x3C 146166124Srafan#define BGE_PCI_INTPIN 0x3D 147166124Srafan#define BGE_PCI_MINGNT 0x3E 148166124Srafan#define BGE_PCI_MAXLAT 0x3F 149166124Srafan#define BGE_PCI_PCIXCAP 0x40 150166124Srafan#define BGE_PCI_NEXTPTR_PM 0x41 151166124Srafan#define BGE_PCI_PCIX_CMD 0x42 152166124Srafan#define BGE_PCI_PCIX_STS 0x44 153166124Srafan#define BGE_PCI_PWRMGMT_CAPID 0x48 154166124Srafan#define BGE_PCI_NEXTPTR_VPD 0x49 155166124Srafan#define BGE_PCI_PWRMGMT_CAPS 0x4A 156166124Srafan#define BGE_PCI_PWRMGMT_CMD 0x4C 157166124Srafan#define BGE_PCI_PWRMGMT_STS 0x4D 158166124Srafan#define BGE_PCI_PWRMGMT_DATA 0x4F 159166124Srafan#define BGE_PCI_VPD_CAPID 0x50 160166124Srafan#define BGE_PCI_NEXTPTR_MSI 0x51 161166124Srafan#define BGE_PCI_VPD_ADDR 0x52 162166124Srafan#define BGE_PCI_VPD_DATA 0x54 16350276Speter#define BGE_PCI_MSI_CAPID 0x58 16450276Speter#define BGE_PCI_NEXTPTR_NONE 0x59 16550276Speter#define BGE_PCI_MSI_CTL 0x5A 166166124Srafan#define BGE_PCI_MSI_ADDR_HI 0x5C 16750276Speter#define BGE_PCI_MSI_ADDR_LO 0x60 16850276Speter#define BGE_PCI_MSI_DATA 0x64 16950276Speter 17050276Speter/* 17150276Speter * PCI registers specific to the BCM570x family. 172166124Srafan */ 17350276Speter#define BGE_PCI_MISC_CTL 0x68 174166124Srafan#define BGE_PCI_DMA_RW_CTL 0x6C 17550276Speter#define BGE_PCI_PCISTATE 0x70 17650276Speter#define BGE_PCI_CLKCTL 0x74 17750276Speter#define BGE_PCI_REG_BASEADDR 0x78 17850276Speter#define BGE_PCI_MEMWIN_BASEADDR 0x7C 17950276Speter#define BGE_PCI_REG_DATA 0x80 18050276Speter#define BGE_PCI_MEMWIN_DATA 0x84 18150276Speter#define BGE_PCI_MODECTL 0x88 18250276Speter#define BGE_PCI_MISC_CFG 0x8C 18350276Speter#define BGE_PCI_MISC_LOCALCTL 0x90 18450276Speter#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 18550276Speter#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 18650276Speter#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 18750276Speter#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 18850276Speter#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 189#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 190#define BGE_PCI_ISR_MBX_HI 0xB0 191#define BGE_PCI_ISR_MBX_LO 0xB4 192 193/* PCI Misc. Host control register */ 194#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 195#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 196#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 197#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 198#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 199#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 200#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 201#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 202#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 203 204#define BGE_BIGENDIAN_INIT \ 205 (BGE_BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 206 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 207 BGE_PCIMISCCTL_INDIRECT_ACCESS|PCIMISCCTL_MASK_PCI_INTR) 208 209#define BGE_LITTLEENDIAN_INIT \ 210 (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 211 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 212 213#define BGE_ASICREV_TIGON_I 0x40000000 214#define BGE_ASICREV_TIGON_II 0x60000000 215#define BGE_ASICREV_BCM5700_B0 0x71000000 216#define BGE_ASICREV_BCM5700_B1 0x71020000 217#define BGE_ASICREV_BCM5700_B2 0x71030000 218#define BGE_ASICREV_BCM5700_ALTIMA 0x71040000 219#define BGE_ASICREV_BCM5700_C0 0x72000000 220#define BGE_ASICREV_BCM5701_A0 0x00000000 /* grrrr */ 221#define BGE_ASICREV_BCM5701_B0 0x01000000 222#define BGE_ASICREV_BCM5701_B2 0x01020000 223#define BGE_ASICREV_BCM5701_B5 0x01050000 224#define BGE_ASICREV_BCM5703_A0 0x10000000 225#define BGE_ASICREV_BCM5703_A1 0x10010000 226#define BGE_ASICREV_BCM5703_A2 0x10020000 227 228/* shorthand one */ 229#define BGE_ASICREV_BCM5700 0x71000000 230 231/* PCI DMA Read/Write Control register */ 232#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 233#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 234#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 235#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 236#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 237#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 238#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 239#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 240#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 241#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 242 243#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 244#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 245#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 246#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 247#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 248#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 249#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 250#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 251 252#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 253#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 254#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 255#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 256#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 257#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 258#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 259#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 260 261/* 262 * PCI state register -- note, this register is read only 263 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 264 * register is set. 265 */ 266#define BGE_PCISTATE_FORCE_RESET 0x00000001 267#define BGE_PCISTATE_INTR_STATE 0x00000002 268#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 269#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 270#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 271#define BGE_PCISTATE_WANT_EXPROM 0x00000020 272#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 273#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 274#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 275 276/* 277 * PCI Clock Control register -- note, this register is read only 278 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 279 * register is set. 280 */ 281#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 282#define BGE_PCICLOCKCTL_M66EN 0x00000080 283#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 284#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 285#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 286#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 287#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 288#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 289#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 290#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 291 292 293#ifndef PCIM_CMD_MWIEN 294#define PCIM_CMD_MWIEN 0x0010 295#endif 296 297/* 298 * High priority mailbox registers 299 * Each mailbox is 64-bits wide, though we only use the 300 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 301 * first. The NIC will load the mailbox after the lower 32 bit word 302 * has been updated. 303 */ 304#define BGE_MBX_IRQ0_HI 0x0200 305#define BGE_MBX_IRQ0_LO 0x0204 306#define BGE_MBX_IRQ1_HI 0x0208 307#define BGE_MBX_IRQ1_LO 0x020C 308#define BGE_MBX_IRQ2_HI 0x0210 309#define BGE_MBX_IRQ2_LO 0x0214 310#define BGE_MBX_IRQ3_HI 0x0218 311#define BGE_MBX_IRQ3_LO 0x021C 312#define BGE_MBX_GEN0_HI 0x0220 313#define BGE_MBX_GEN0_LO 0x0224 314#define BGE_MBX_GEN1_HI 0x0228 315#define BGE_MBX_GEN1_LO 0x022C 316#define BGE_MBX_GEN2_HI 0x0230 317#define BGE_MBX_GEN2_LO 0x0234 318#define BGE_MBX_GEN3_HI 0x0228 319#define BGE_MBX_GEN3_LO 0x022C 320#define BGE_MBX_GEN4_HI 0x0240 321#define BGE_MBX_GEN4_LO 0x0244 322#define BGE_MBX_GEN5_HI 0x0248 323#define BGE_MBX_GEN5_LO 0x024C 324#define BGE_MBX_GEN6_HI 0x0250 325#define BGE_MBX_GEN6_LO 0x0254 326#define BGE_MBX_GEN7_HI 0x0258 327#define BGE_MBX_GEN7_LO 0x025C 328#define BGE_MBX_RELOAD_STATS_HI 0x0260 329#define BGE_MBX_RELOAD_STATS_LO 0x0264 330#define BGE_MBX_RX_STD_PROD_HI 0x0268 331#define BGE_MBX_RX_STD_PROD_LO 0x026C 332#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 333#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 334#define BGE_MBX_RX_MINI_PROD_HI 0x0278 335#define BGE_MBX_RX_MINI_PROD_LO 0x027C 336#define BGE_MBX_RX_CONS0_HI 0x0280 337#define BGE_MBX_RX_CONS0_LO 0x0284 338#define BGE_MBX_RX_CONS1_HI 0x0288 339#define BGE_MBX_RX_CONS1_LO 0x028C 340#define BGE_MBX_RX_CONS2_HI 0x0290 341#define BGE_MBX_RX_CONS2_LO 0x0294 342#define BGE_MBX_RX_CONS3_HI 0x0298 343#define BGE_MBX_RX_CONS3_LO 0x029C 344#define BGE_MBX_RX_CONS4_HI 0x02A0 345#define BGE_MBX_RX_CONS4_LO 0x02A4 346#define BGE_MBX_RX_CONS5_HI 0x02A8 347#define BGE_MBX_RX_CONS5_LO 0x02AC 348#define BGE_MBX_RX_CONS6_HI 0x02B0 349#define BGE_MBX_RX_CONS6_LO 0x02B4 350#define BGE_MBX_RX_CONS7_HI 0x02B8 351#define BGE_MBX_RX_CONS7_LO 0x02BC 352#define BGE_MBX_RX_CONS8_HI 0x02C0 353#define BGE_MBX_RX_CONS8_LO 0x02C4 354#define BGE_MBX_RX_CONS9_HI 0x02C8 355#define BGE_MBX_RX_CONS9_LO 0x02CC 356#define BGE_MBX_RX_CONS10_HI 0x02D0 357#define BGE_MBX_RX_CONS10_LO 0x02D4 358#define BGE_MBX_RX_CONS11_HI 0x02D8 359#define BGE_MBX_RX_CONS11_LO 0x02DC 360#define BGE_MBX_RX_CONS12_HI 0x02E0 361#define BGE_MBX_RX_CONS12_LO 0x02E4 362#define BGE_MBX_RX_CONS13_HI 0x02E8 363#define BGE_MBX_RX_CONS13_LO 0x02EC 364#define BGE_MBX_RX_CONS14_HI 0x02F0 365#define BGE_MBX_RX_CONS14_LO 0x02F4 366#define BGE_MBX_RX_CONS15_HI 0x02F8 367#define BGE_MBX_RX_CONS15_LO 0x02FC 368#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 369#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 370#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 371#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 372#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 373#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 374#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 375#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 376#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 377#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 378#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 379#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 380#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 381#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 382#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 383#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 384#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 385#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 386#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 387#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 388#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 389#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 390#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 391#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 392#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 393#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 394#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 395#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 396#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 397#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 398#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 399#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 400#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 401#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 402#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 403#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 404#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 405#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 406#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 407#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 408#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 409#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 410#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 411#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 412#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 413#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 414#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 415#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 416#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 417#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 418#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 419#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 420#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 421#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 422#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 423#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 424#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 425#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 426#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 427#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 428#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 429#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 430#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 431#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 432 433#define BGE_TX_RINGS_MAX 4 434#define BGE_TX_RINGS_EXTSSRAM_MAX 16 435#define BGE_RX_RINGS_MAX 16 436 437/* Ethernet MAC control registers */ 438#define BGE_MAC_MODE 0x0400 439#define BGE_MAC_STS 0x0404 440#define BGE_MAC_EVT_ENB 0x0408 441#define BGE_MAC_LED_CTL 0x040C 442#define BGE_MAC_ADDR1_LO 0x0410 443#define BGE_MAC_ADDR1_HI 0x0414 444#define BGE_MAC_ADDR2_LO 0x0418 445#define BGE_MAC_ADDR2_HI 0x041C 446#define BGE_MAC_ADDR3_LO 0x0420 447#define BGE_MAC_ADDR3_HI 0x0424 448#define BGE_MAC_ADDR4_LO 0x0428 449#define BGE_MAC_ADDR4_HI 0x042C 450#define BGE_WOL_PATPTR 0x0430 451#define BGE_WOL_PATCFG 0x0434 452#define BGE_TX_RANDOM_BACKOFF 0x0438 453#define BGE_RX_MTU 0x043C 454#define BGE_GBIT_PCS_TEST 0x0440 455#define BGE_TX_TBI_AUTONEG 0x0444 456#define BGE_RX_TBI_AUTONEG 0x0448 457#define BGE_MI_COMM 0x044C 458#define BGE_MI_STS 0x0450 459#define BGE_MI_MODE 0x0454 460#define BGE_AUTOPOLL_STS 0x0458 461#define BGE_TX_MODE 0x045C 462#define BGE_TX_STS 0x0460 463#define BGE_TX_LENGTHS 0x0464 464#define BGE_RX_MODE 0x0468 465#define BGE_RX_STS 0x046C 466#define BGE_MAR0 0x0470 467#define BGE_MAR1 0x0474 468#define BGE_MAR2 0x0478 469#define BGE_MAR3 0x047C 470#define BGE_RX_BD_RULES_CTL0 0x0480 471#define BGE_RX_BD_RULES_MASKVAL0 0x0484 472#define BGE_RX_BD_RULES_CTL1 0x0488 473#define BGE_RX_BD_RULES_MASKVAL1 0x048C 474#define BGE_RX_BD_RULES_CTL2 0x0490 475#define BGE_RX_BD_RULES_MASKVAL2 0x0494 476#define BGE_RX_BD_RULES_CTL3 0x0498 477#define BGE_RX_BD_RULES_MASKVAL3 0x049C 478#define BGE_RX_BD_RULES_CTL4 0x04A0 479#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 480#define BGE_RX_BD_RULES_CTL5 0x04A8 481#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 482#define BGE_RX_BD_RULES_CTL6 0x04B0 483#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 484#define BGE_RX_BD_RULES_CTL7 0x04B8 485#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 486#define BGE_RX_BD_RULES_CTL8 0x04C0 487#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 488#define BGE_RX_BD_RULES_CTL9 0x04C8 489#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 490#define BGE_RX_BD_RULES_CTL10 0x04D0 491#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 492#define BGE_RX_BD_RULES_CTL11 0x04D8 493#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 494#define BGE_RX_BD_RULES_CTL12 0x04E0 495#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 496#define BGE_RX_BD_RULES_CTL13 0x04E8 497#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 498#define BGE_RX_BD_RULES_CTL14 0x04F0 499#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 500#define BGE_RX_BD_RULES_CTL15 0x04F8 501#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 502#define BGE_RX_RULES_CFG 0x0500 503#define BGE_RX_STATS 0x0800 504#define BGE_TX_STATS 0x0880 505 506/* Ethernet MAC Mode register */ 507#define BGE_MACMODE_RESET 0x00000001 508#define BGE_MACMODE_HALF_DUPLEX 0x00000002 509#define BGE_MACMODE_PORTMODE 0x0000000C 510#define BGE_MACMODE_LOOPBACK 0x00000010 511#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 512#define BGE_MACMODE_TX_BURST_ENB 0x00000100 513#define BGE_MACMODE_MAX_DEFER 0x00000200 514#define BGE_MACMODE_LINK_POLARITY 0x00000400 515#define BGE_MACMODE_RX_STATS_ENB 0x00000800 516#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 517#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 518#define BGE_MACMODE_TX_STATS_ENB 0x00004000 519#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 520#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 521#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 522#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 523#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 524#define BGE_MACMODE_MIP_ENB 0x00100000 525#define BGE_MACMODE_TXDMA_ENB 0x00200000 526#define BGE_MACMODE_RXDMA_ENB 0x00400000 527#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 528 529#define BGE_PORTMODE_NONE 0x00000000 530#define BGE_PORTMODE_MII 0x00000004 531#define BGE_PORTMODE_GMII 0x00000008 532#define BGE_PORTMODE_TBI 0x0000000C 533 534/* MAC Status register */ 535#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 536#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 537#define BGE_MACSTAT_RX_CFG 0x00000004 538#define BGE_MACSTAT_CFG_CHANGED 0x00000008 539#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 540#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 541#define BGE_MACSTAT_LINK_CHANGED 0x00001000 542#define BGE_MACSTAT_MI_COMPLETE 0x00400000 543#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 544#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 545#define BGE_MACSTAT_ODI_ERROR 0x02000000 546#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 547#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 548 549/* MAC Event Enable Register */ 550#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 551#define BGE_EVTENB_LINK_CHANGED 0x00001000 552#define BGE_EVTENB_MI_COMPLETE 0x00400000 553#define BGE_EVTENB_MI_INTERRUPT 0x00800000 554#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 555#define BGE_EVTENB_ODI_ERROR 0x02000000 556#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 557#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 558 559/* LED Control Register */ 560#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 561#define BGE_LEDCTL_1000MBPS_LED 0x00000002 562#define BGE_LEDCTL_100MBPS_LED 0x00000004 563#define BGE_LEDCTL_10MBPS_LED 0x00000008 564#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 565#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 566#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 567#define BGE_LEDCTL_1000MBPS_STS 0x00000080 568#define BGE_LEDCTL_100MBPS_STS 0x00000100 569#define BGE_LEDCTL_10MBPS_STS 0x00000200 570#define BGE_LEDCTL_TRADLED_STS 0x00000400 571#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 572#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 573 574/* TX backoff seed register */ 575#define BGE_TX_BACKOFF_SEED_MASK 0x3F 576 577/* Autopoll status register */ 578#define BGE_AUTOPOLLSTS_ERROR 0x00000001 579 580/* Transmit MAC mode register */ 581#define BGE_TXMODE_RESET 0x00000001 582#define BGE_TXMODE_ENABLE 0x00000002 583#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 584#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 585#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 586 587/* Transmit MAC status register */ 588#define BGE_TXSTAT_RX_XOFFED 0x00000001 589#define BGE_TXSTAT_SENT_XOFF 0x00000002 590#define BGE_TXSTAT_SENT_XON 0x00000004 591#define BGE_TXSTAT_LINK_UP 0x00000008 592#define BGE_TXSTAT_ODI_UFLOW 0x00000010 593#define BGE_TXSTAT_ODI_OFLOW 0x00000020 594 595/* Transmit MAC lengths register */ 596#define BGE_TXLEN_SLOTTIME 0x000000FF 597#define BGE_TXLEN_IPG 0x00000F00 598#define BGE_TXLEN_CRS 0x00003000 599 600/* Receive MAC mode register */ 601#define BGE_RXMODE_RESET 0x00000001 602#define BGE_RXMODE_ENABLE 0x00000002 603#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 604#define BGE_RXMODE_RX_GIANTS 0x00000020 605#define BGE_RXMODE_RX_RUNTS 0x00000040 606#define BGE_RXMODE_8022_LENCHECK 0x00000080 607#define BGE_RXMODE_RX_PROMISC 0x00000100 608#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 609#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 610 611/* Receive MAC status register */ 612#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 613#define BGE_RXSTAT_RCVD_XOFF 0x00000002 614#define BGE_RXSTAT_RCVD_XON 0x00000004 615 616/* Receive Rules Control register */ 617#define BGE_RXRULECTL_OFFSET 0x000000FF 618#define BGE_RXRULECTL_CLASS 0x00001F00 619#define BGE_RXRULECTL_HDRTYPE 0x0000E000 620#define BGE_RXRULECTL_COMPARE_OP 0x00030000 621#define BGE_RXRULECTL_MAP 0x01000000 622#define BGE_RXRULECTL_DISCARD 0x02000000 623#define BGE_RXRULECTL_MASK 0x04000000 624#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 625#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 626#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 627#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 628 629/* Receive Rules Mask register */ 630#define BGE_RXRULEMASK_VALUE 0x0000FFFF 631#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 632 633/* MI communication register */ 634#define BGE_MICOMM_DATA 0x0000FFFF 635#define BGE_MICOMM_REG 0x001F0000 636#define BGE_MICOMM_PHY 0x03E00000 637#define BGE_MICOMM_CMD 0x0C000000 638#define BGE_MICOMM_READFAIL 0x10000000 639#define BGE_MICOMM_BUSY 0x20000000 640 641#define BGE_MIREG(x) ((x & 0x1F) << 16) 642#define BGE_MIPHY(x) ((x & 0x1F) << 21) 643#define BGE_MICMD_WRITE 0x04000000 644#define BGE_MICMD_READ 0x08000000 645 646/* MI status register */ 647#define BGE_MISTS_LINK 0x00000001 648#define BGE_MISTS_10MBPS 0x00000002 649 650#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 651#define BGE_MIMODE_AUTOPOLL 0x00000010 652#define BGE_MIMODE_CLKCNT 0x001F0000 653 654 655/* 656 * Send data initiator control registers. 657 */ 658#define BGE_SDI_MODE 0x0C00 659#define BGE_SDI_STATUS 0x0C04 660#define BGE_SDI_STATS_CTL 0x0C08 661#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 662#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 663#define BGE_LOCSTATS_COS0 0x0C80 664#define BGE_LOCSTATS_COS1 0x0C84 665#define BGE_LOCSTATS_COS2 0x0C88 666#define BGE_LOCSTATS_COS3 0x0C8C 667#define BGE_LOCSTATS_COS4 0x0C90 668#define BGE_LOCSTATS_COS5 0x0C84 669#define BGE_LOCSTATS_COS6 0x0C98 670#define BGE_LOCSTATS_COS7 0x0C9C 671#define BGE_LOCSTATS_COS8 0x0CA0 672#define BGE_LOCSTATS_COS9 0x0CA4 673#define BGE_LOCSTATS_COS10 0x0CA8 674#define BGE_LOCSTATS_COS11 0x0CAC 675#define BGE_LOCSTATS_COS12 0x0CB0 676#define BGE_LOCSTATS_COS13 0x0CB4 677#define BGE_LOCSTATS_COS14 0x0CB8 678#define BGE_LOCSTATS_COS15 0x0CBC 679#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 680#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 681#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 682#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 683#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 684#define BGE_LOCSTATS_IRQS 0x0CD4 685#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 686#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 687 688/* Send Data Initiator mode register */ 689#define BGE_SDIMODE_RESET 0x00000001 690#define BGE_SDIMODE_ENABLE 0x00000002 691#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 692 693/* Send Data Initiator stats register */ 694#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 695 696/* Send Data Initiator stats control register */ 697#define BGE_SDISTATSCTL_ENABLE 0x00000001 698#define BGE_SDISTATSCTL_FASTER 0x00000002 699#define BGE_SDISTATSCTL_CLEAR 0x00000004 700#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 701#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 702 703/* 704 * Send Data Completion Control registers 705 */ 706#define BGE_SDC_MODE 0x1000 707#define BGE_SDC_STATUS 0x1004 708 709/* Send Data completion mode register */ 710#define BGE_SDCMODE_RESET 0x00000001 711#define BGE_SDCMODE_ENABLE 0x00000002 712#define BGE_SDCMODE_ATTN 0x00000004 713 714/* Send Data completion status register */ 715#define BGE_SDCSTAT_ATTN 0x00000004 716 717/* 718 * Send BD Ring Selector Control registers 719 */ 720#define BGE_SRS_MODE 0x1400 721#define BGE_SRS_STATUS 0x1404 722#define BGE_SRS_HWDIAG 0x1408 723#define BGE_SRS_LOC_NIC_CONS0 0x1440 724#define BGE_SRS_LOC_NIC_CONS1 0x1444 725#define BGE_SRS_LOC_NIC_CONS2 0x1448 726#define BGE_SRS_LOC_NIC_CONS3 0x144C 727#define BGE_SRS_LOC_NIC_CONS4 0x1450 728#define BGE_SRS_LOC_NIC_CONS5 0x1454 729#define BGE_SRS_LOC_NIC_CONS6 0x1458 730#define BGE_SRS_LOC_NIC_CONS7 0x145C 731#define BGE_SRS_LOC_NIC_CONS8 0x1460 732#define BGE_SRS_LOC_NIC_CONS9 0x1464 733#define BGE_SRS_LOC_NIC_CONS10 0x1468 734#define BGE_SRS_LOC_NIC_CONS11 0x146C 735#define BGE_SRS_LOC_NIC_CONS12 0x1470 736#define BGE_SRS_LOC_NIC_CONS13 0x1474 737#define BGE_SRS_LOC_NIC_CONS14 0x1478 738#define BGE_SRS_LOC_NIC_CONS15 0x147C 739 740/* Send BD Ring Selector Mode register */ 741#define BGE_SRSMODE_RESET 0x00000001 742#define BGE_SRSMODE_ENABLE 0x00000002 743#define BGE_SRSMODE_ATTN 0x00000004 744 745/* Send BD Ring Selector Status register */ 746#define BGE_SRSSTAT_ERROR 0x00000004 747 748/* Send BD Ring Selector HW Diagnostics register */ 749#define BGE_SRSHWDIAG_STATE 0x0000000F 750#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 751#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 752#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 753 754/* 755 * Send BD Initiator Selector Control registers 756 */ 757#define BGE_SBDI_MODE 0x1800 758#define BGE_SBDI_STATUS 0x1804 759#define BGE_SBDI_LOC_NIC_PROD0 0x1808 760#define BGE_SBDI_LOC_NIC_PROD1 0x180C 761#define BGE_SBDI_LOC_NIC_PROD2 0x1810 762#define BGE_SBDI_LOC_NIC_PROD3 0x1814 763#define BGE_SBDI_LOC_NIC_PROD4 0x1818 764#define BGE_SBDI_LOC_NIC_PROD5 0x181C 765#define BGE_SBDI_LOC_NIC_PROD6 0x1820 766#define BGE_SBDI_LOC_NIC_PROD7 0x1824 767#define BGE_SBDI_LOC_NIC_PROD8 0x1828 768#define BGE_SBDI_LOC_NIC_PROD9 0x182C 769#define BGE_SBDI_LOC_NIC_PROD10 0x1830 770#define BGE_SBDI_LOC_NIC_PROD11 0x1834 771#define BGE_SBDI_LOC_NIC_PROD12 0x1838 772#define BGE_SBDI_LOC_NIC_PROD13 0x183C 773#define BGE_SBDI_LOC_NIC_PROD14 0x1840 774#define BGE_SBDI_LOC_NIC_PROD15 0x1844 775 776/* Send BD Initiator Mode register */ 777#define BGE_SBDIMODE_RESET 0x00000001 778#define BGE_SBDIMODE_ENABLE 0x00000002 779#define BGE_SBDIMODE_ATTN 0x00000004 780 781/* Send BD Initiator Status register */ 782#define BGE_SBDISTAT_ERROR 0x00000004 783 784/* 785 * Send BD Completion Control registers 786 */ 787#define BGE_SBDC_MODE 0x1C00 788#define BGE_SBDC_STATUS 0x1C04 789 790/* Send BD Completion Control Mode register */ 791#define BGE_SBDCMODE_RESET 0x00000001 792#define BGE_SBDCMODE_ENABLE 0x00000002 793#define BGE_SBDCMODE_ATTN 0x00000004 794 795/* Send BD Completion Control Status register */ 796#define BGE_SBDCSTAT_ATTN 0x00000004 797 798/* 799 * Receive List Placement Control registers 800 */ 801#define BGE_RXLP_MODE 0x2000 802#define BGE_RXLP_STATUS 0x2004 803#define BGE_RXLP_SEL_LIST_LOCK 0x2008 804#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 805#define BGE_RXLP_CFG 0x2010 806#define BGE_RXLP_STATS_CTL 0x2014 807#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 808#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 809#define BGE_RXLP_HEAD0 0x2100 810#define BGE_RXLP_TAIL0 0x2104 811#define BGE_RXLP_COUNT0 0x2108 812#define BGE_RXLP_HEAD1 0x2110 813#define BGE_RXLP_TAIL1 0x2114 814#define BGE_RXLP_COUNT1 0x2118 815#define BGE_RXLP_HEAD2 0x2120 816#define BGE_RXLP_TAIL2 0x2124 817#define BGE_RXLP_COUNT2 0x2128 818#define BGE_RXLP_HEAD3 0x2130 819#define BGE_RXLP_TAIL3 0x2134 820#define BGE_RXLP_COUNT3 0x2138 821#define BGE_RXLP_HEAD4 0x2140 822#define BGE_RXLP_TAIL4 0x2144 823#define BGE_RXLP_COUNT4 0x2148 824#define BGE_RXLP_HEAD5 0x2150 825#define BGE_RXLP_TAIL5 0x2154 826#define BGE_RXLP_COUNT5 0x2158 827#define BGE_RXLP_HEAD6 0x2160 828#define BGE_RXLP_TAIL6 0x2164 829#define BGE_RXLP_COUNT6 0x2168 830#define BGE_RXLP_HEAD7 0x2170 831#define BGE_RXLP_TAIL7 0x2174 832#define BGE_RXLP_COUNT7 0x2178 833#define BGE_RXLP_HEAD8 0x2180 834#define BGE_RXLP_TAIL8 0x2184 835#define BGE_RXLP_COUNT8 0x2188 836#define BGE_RXLP_HEAD9 0x2190 837#define BGE_RXLP_TAIL9 0x2194 838#define BGE_RXLP_COUNT9 0x2198 839#define BGE_RXLP_HEAD10 0x21A0 840#define BGE_RXLP_TAIL10 0x21A4 841#define BGE_RXLP_COUNT10 0x21A8 842#define BGE_RXLP_HEAD11 0x21B0 843#define BGE_RXLP_TAIL11 0x21B4 844#define BGE_RXLP_COUNT11 0x21B8 845#define BGE_RXLP_HEAD12 0x21C0 846#define BGE_RXLP_TAIL12 0x21C4 847#define BGE_RXLP_COUNT12 0x21C8 848#define BGE_RXLP_HEAD13 0x21D0 849#define BGE_RXLP_TAIL13 0x21D4 850#define BGE_RXLP_COUNT13 0x21D8 851#define BGE_RXLP_HEAD14 0x21E0 852#define BGE_RXLP_TAIL14 0x21E4 853#define BGE_RXLP_COUNT14 0x21E8 854#define BGE_RXLP_HEAD15 0x21F0 855#define BGE_RXLP_TAIL15 0x21F4 856#define BGE_RXLP_COUNT15 0x21F8 857#define BGE_RXLP_LOCSTAT_COS0 0x2200 858#define BGE_RXLP_LOCSTAT_COS1 0x2204 859#define BGE_RXLP_LOCSTAT_COS2 0x2208 860#define BGE_RXLP_LOCSTAT_COS3 0x220C 861#define BGE_RXLP_LOCSTAT_COS4 0x2210 862#define BGE_RXLP_LOCSTAT_COS5 0x2214 863#define BGE_RXLP_LOCSTAT_COS6 0x2218 864#define BGE_RXLP_LOCSTAT_COS7 0x221C 865#define BGE_RXLP_LOCSTAT_COS8 0x2220 866#define BGE_RXLP_LOCSTAT_COS9 0x2224 867#define BGE_RXLP_LOCSTAT_COS10 0x2228 868#define BGE_RXLP_LOCSTAT_COS11 0x222C 869#define BGE_RXLP_LOCSTAT_COS12 0x2230 870#define BGE_RXLP_LOCSTAT_COS13 0x2234 871#define BGE_RXLP_LOCSTAT_COS14 0x2238 872#define BGE_RXLP_LOCSTAT_COS15 0x223C 873#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 874#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 875#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 876#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 877#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 878#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 879#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 880 881 882/* Receive List Placement mode register */ 883#define BGE_RXLPMODE_RESET 0x00000001 884#define BGE_RXLPMODE_ENABLE 0x00000002 885#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 886#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 887#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 888 889/* Receive List Placement Status register */ 890#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 891#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 892#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 893 894/* 895 * Receive Data and Receive BD Initiator Control Registers 896 */ 897#define BGE_RDBDI_MODE 0x2400 898#define BGE_RDBDI_STATUS 0x2404 899#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 900#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 901#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 902#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 903#define BGE_RX_STD_RCB_HADDR_HI 0x2450 904#define BGE_RX_STD_RCB_HADDR_LO 0x2454 905#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 906#define BGE_RX_STD_RCB_NICADDR 0x245C 907#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 908#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 909#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 910#define BGE_RX_MINI_RCB_NICADDR 0x246C 911#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 912#define BGE_RDBDI_STD_RX_CONS 0x2474 913#define BGE_RDBDI_MINI_RX_CONS 0x2478 914#define BGE_RDBDI_RETURN_PROD0 0x2480 915#define BGE_RDBDI_RETURN_PROD1 0x2484 916#define BGE_RDBDI_RETURN_PROD2 0x2488 917#define BGE_RDBDI_RETURN_PROD3 0x248C 918#define BGE_RDBDI_RETURN_PROD4 0x2490 919#define BGE_RDBDI_RETURN_PROD5 0x2494 920#define BGE_RDBDI_RETURN_PROD6 0x2498 921#define BGE_RDBDI_RETURN_PROD7 0x249C 922#define BGE_RDBDI_RETURN_PROD8 0x24A0 923#define BGE_RDBDI_RETURN_PROD9 0x24A4 924#define BGE_RDBDI_RETURN_PROD10 0x24A8 925#define BGE_RDBDI_RETURN_PROD11 0x24AC 926#define BGE_RDBDI_RETURN_PROD12 0x24B0 927#define BGE_RDBDI_RETURN_PROD13 0x24B4 928#define BGE_RDBDI_RETURN_PROD14 0x24B8 929#define BGE_RDBDI_RETURN_PROD15 0x24BC 930#define BGE_RDBDI_HWDIAG 0x24C0 931 932 933/* Receive Data and Receive BD Initiator Mode register */ 934#define BGE_RDBDIMODE_RESET 0x00000001 935#define BGE_RDBDIMODE_ENABLE 0x00000002 936#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 937#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 938#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 939 940/* Receive Data and Receive BD Initiator Status register */ 941#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 942#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 943#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 944 945 946/* 947 * Receive Data Completion Control registers 948 */ 949#define BGE_RDC_MODE 0x2800 950 951/* Receive Data Completion Mode register */ 952#define BGE_RDCMODE_RESET 0x00000001 953#define BGE_RDCMODE_ENABLE 0x00000002 954#define BGE_RDCMODE_ATTN 0x00000004 955 956/* 957 * Receive BD Initiator Control registers 958 */ 959#define BGE_RBDI_MODE 0x2C00 960#define BGE_RBDI_STATUS 0x2C04 961#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 962#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 963#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 964#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 965#define BGE_RBDI_STD_REPL_THRESH 0x2C18 966#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 967 968/* Receive BD Initiator Mode register */ 969#define BGE_RBDIMODE_RESET 0x00000001 970#define BGE_RBDIMODE_ENABLE 0x00000002 971#define BGE_RBDIMODE_ATTN 0x00000004 972 973/* Receive BD Initiator Status register */ 974#define BGE_RBDISTAT_ATTN 0x00000004 975 976/* 977 * Receive BD Completion Control registers 978 */ 979#define BGE_RBDC_MODE 0x3000 980#define BGE_RBDC_STATUS 0x3004 981#define BGE_RBDC_JUMBO_BD_PROD 0x3008 982#define BGE_RBDC_STD_BD_PROD 0x300C 983#define BGE_RBDC_MINI_BD_PROD 0x3010 984 985/* Receive BD completion mode register */ 986#define BGE_RBDCMODE_RESET 0x00000001 987#define BGE_RBDCMODE_ENABLE 0x00000002 988#define BGE_RBDCMODE_ATTN 0x00000004 989 990/* Receive BD completion status register */ 991#define BGE_RBDCSTAT_ERROR 0x00000004 992 993/* 994 * Receive List Selector Control registers 995 */ 996#define BGE_RXLS_MODE 0x3400 997#define BGE_RXLS_STATUS 0x3404 998 999/* Receive List Selector Mode register */ 1000#define BGE_RXLSMODE_RESET 0x00000001 1001#define BGE_RXLSMODE_ENABLE 0x00000002 1002#define BGE_RXLSMODE_ATTN 0x00000004 1003 1004/* Receive List Selector Status register */ 1005#define BGE_RXLSSTAT_ERROR 0x00000004 1006 1007/* 1008 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1009 */ 1010#define BGE_MBCF_MODE 0x3800 1011#define BGE_MBCF_STATUS 0x3804 1012 1013/* Mbuf Cluster Free mode register */ 1014#define BGE_MBCFMODE_RESET 0x00000001 1015#define BGE_MBCFMODE_ENABLE 0x00000002 1016#define BGE_MBCFMODE_ATTN 0x00000004 1017 1018/* Mbuf Cluster Free status register */ 1019#define BGE_MBCFSTAT_ERROR 0x00000004 1020 1021/* 1022 * Host Coalescing Control registers 1023 */ 1024#define BGE_HCC_MODE 0x3C00 1025#define BGE_HCC_STATUS 0x3C04 1026#define BGE_HCC_RX_COAL_TICKS 0x3C08 1027#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1028#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1029#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1030#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1031#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1032#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1033#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ 1034#define BGE_HCC_STATS_TICKS 0x3C28 1035#define BGE_HCC_STATS_ADDR_HI 0x3C30 1036#define BGE_HCC_STATS_ADDR_LO 0x3C34 1037#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1038#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1039#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1040#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1041#define BGE_FLOW_ATTN 0x3C48 1042#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1043#define BGE_HCC_STD_BD_CONS 0x3C54 1044#define BGE_HCC_MINI_BD_CONS 0x3C58 1045#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1046#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1047#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1048#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1049#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1050#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1051#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1052#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1053#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1054#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1055#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1056#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1057#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1058#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1059#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1060#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1061#define BGE_HCC_TX_BD_CONS0 0x3CC0 1062#define BGE_HCC_TX_BD_CONS1 0x3CC4 1063#define BGE_HCC_TX_BD_CONS2 0x3CC8 1064#define BGE_HCC_TX_BD_CONS3 0x3CCC 1065#define BGE_HCC_TX_BD_CONS4 0x3CD0 1066#define BGE_HCC_TX_BD_CONS5 0x3CD4 1067#define BGE_HCC_TX_BD_CONS6 0x3CD8 1068#define BGE_HCC_TX_BD_CONS7 0x3CDC 1069#define BGE_HCC_TX_BD_CONS8 0x3CE0 1070#define BGE_HCC_TX_BD_CONS9 0x3CE4 1071#define BGE_HCC_TX_BD_CONS10 0x3CE8 1072#define BGE_HCC_TX_BD_CONS11 0x3CEC 1073#define BGE_HCC_TX_BD_CONS12 0x3CF0 1074#define BGE_HCC_TX_BD_CONS13 0x3CF4 1075#define BGE_HCC_TX_BD_CONS14 0x3CF8 1076#define BGE_HCC_TX_BD_CONS15 0x3CFC 1077 1078 1079/* Host coalescing mode register */ 1080#define BGE_HCCMODE_RESET 0x00000001 1081#define BGE_HCCMODE_ENABLE 0x00000002 1082#define BGE_HCCMODE_ATTN 0x00000004 1083#define BGE_HCCMODE_COAL_NOW 0x00000008 1084#define BGE_HCCMODE_MSI_BITS 0x0x000070 1085#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1086 1087#define BGE_STATBLKSZ_FULL 0x00000000 1088#define BGE_STATBLKSZ_64BYTE 0x00000080 1089#define BGE_STATBLKSZ_32BYTE 0x00000100 1090 1091/* Host coalescing status register */ 1092#define BGE_HCCSTAT_ERROR 0x00000004 1093 1094/* Flow attention register */ 1095#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1096#define BGE_FLOWATTN_MEMARB 0x00000080 1097#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1098#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1099#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1100#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1101#define BGE_FLOWATTN_RDBDI 0x00080000 1102#define BGE_FLOWATTN_RXLS 0x00100000 1103#define BGE_FLOWATTN_RXLP 0x00200000 1104#define BGE_FLOWATTN_RBDC 0x00400000 1105#define BGE_FLOWATTN_RBDI 0x00800000 1106#define BGE_FLOWATTN_SDC 0x08000000 1107#define BGE_FLOWATTN_SDI 0x10000000 1108#define BGE_FLOWATTN_SRS 0x20000000 1109#define BGE_FLOWATTN_SBDC 0x40000000 1110#define BGE_FLOWATTN_SBDI 0x80000000 1111 1112/* 1113 * Memory arbiter registers 1114 */ 1115#define BGE_MARB_MODE 0x4000 1116#define BGE_MARB_STATUS 0x4004 1117#define BGE_MARB_TRAPADDR_HI 0x4008 1118#define BGE_MARB_TRAPADDR_LO 0x400C 1119 1120/* Memory arbiter mode register */ 1121#define BGE_MARBMODE_RESET 0x00000001 1122#define BGE_MARBMODE_ENABLE 0x00000002 1123#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1124#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1125#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1126#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1127#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1128#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1129#define BGE_MARBMODE_PCI_TRAP 0x00000100 1130#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1131#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1132#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1133#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1134#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1135#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1136#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1137#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1138#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1139#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1140#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1141#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1142#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1143#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1144#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1145#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1146#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1147 1148/* Memory arbiter status register */ 1149#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1150#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1151#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1152#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1153#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1154#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1155#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1156#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1157#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1158#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1159#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1160#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1161#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1162#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1163#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1164#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1165#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1166#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1167#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1168#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1169#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1170#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1171#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1172#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1173 1174/* 1175 * Buffer manager control registers 1176 */ 1177#define BGE_BMAN_MODE 0x4400 1178#define BGE_BMAN_STATUS 0x4404 1179#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1180#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1181#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1182#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1183#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1184#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1185#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1186#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1187#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1188#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1189#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1190#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1191#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1192#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1193#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1194#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1195#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1196#define BGE_BMAN_HWDIAG_1 0x444C 1197#define BGE_BMAN_HWDIAG_2 0x4450 1198#define BGE_BMAN_HWDIAG_3 0x4454 1199 1200/* Buffer manager mode register */ 1201#define BGE_BMANMODE_RESET 0x00000001 1202#define BGE_BMANMODE_ENABLE 0x00000002 1203#define BGE_BMANMODE_ATTN 0x00000004 1204#define BGE_BMANMODE_TESTMODE 0x00000008 1205#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1206 1207/* Buffer manager status register */ 1208#define BGE_BMANSTAT_ERRO 0x00000004 1209#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1210 1211 1212/* 1213 * Read DMA Control registers 1214 */ 1215#define BGE_RDMA_MODE 0x4800 1216#define BGE_RDMA_STATUS 0x4804 1217 1218/* Read DMA mode register */ 1219#define BGE_RDMAMODE_RESET 0x00000001 1220#define BGE_RDMAMODE_ENABLE 0x00000002 1221#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1222#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1223#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1224#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1225#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1226#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1227#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1228#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1229#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1230 1231/* Read DMA status register */ 1232#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1233#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1234#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1235#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1236#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1237#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1238#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1239#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1240 1241/* 1242 * Write DMA control registers 1243 */ 1244#define BGE_WDMA_MODE 0x4C00 1245#define BGE_WDMA_STATUS 0x4C04 1246 1247/* Write DMA mode register */ 1248#define BGE_WDMAMODE_RESET 0x00000001 1249#define BGE_WDMAMODE_ENABLE 0x00000002 1250#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1251#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1252#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1253#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1254#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1255#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1256#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1257#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1258#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1259 1260/* Write DMA status register */ 1261#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1262#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1263#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1264#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1265#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1266#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1267#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1268#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1269 1270 1271/* 1272 * RX CPU registers 1273 */ 1274#define BGE_RXCPU_MODE 0x5000 1275#define BGE_RXCPU_STATUS 0x5004 1276#define BGE_RXCPU_PC 0x501C 1277 1278/* RX CPU mode register */ 1279#define BGE_RXCPUMODE_RESET 0x00000001 1280#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1281#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1282#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1283#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1284#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1285#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1286#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1287#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1288#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1289#define BGE_RXCPUMODE_HALTCPU 0x00000400 1290#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1291#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1292#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1293 1294/* RX CPU status register */ 1295#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1296#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1297#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1298#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1299#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1300#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1301#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1302#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1303#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1304#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1305#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1306#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1307#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1308#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1309#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1310#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1311#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1312 1313 1314/* 1315 * TX CPU registers 1316 */ 1317#define BGE_TXCPU_MODE 0x5400 1318#define BGE_TXCPU_STATUS 0x5404 1319#define BGE_TXCPU_PC 0x541C 1320 1321/* TX CPU mode register */ 1322#define BGE_TXCPUMODE_RESET 0x00000001 1323#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1324#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1325#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1326#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1327#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1328#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1329#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1330#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1331#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1332#define BGE_TXCPUMODE_HALTCPU 0x00000400 1333#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1334#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1335 1336/* TX CPU status register */ 1337#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1338#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1339#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1340#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1341#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1342#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1343#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1344#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1345#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1346#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1347#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1348#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1349#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1350#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1351#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1352#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1353#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1354 1355 1356/* 1357 * Low priority mailbox registers 1358 */ 1359#define BGE_LPMBX_IRQ0_HI 0x5800 1360#define BGE_LPMBX_IRQ0_LO 0x5804 1361#define BGE_LPMBX_IRQ1_HI 0x5808 1362#define BGE_LPMBX_IRQ1_LO 0x580C 1363#define BGE_LPMBX_IRQ2_HI 0x5810 1364#define BGE_LPMBX_IRQ2_LO 0x5814 1365#define BGE_LPMBX_IRQ3_HI 0x5818 1366#define BGE_LPMBX_IRQ3_LO 0x581C 1367#define BGE_LPMBX_GEN0_HI 0x5820 1368#define BGE_LPMBX_GEN0_LO 0x5824 1369#define BGE_LPMBX_GEN1_HI 0x5828 1370#define BGE_LPMBX_GEN1_LO 0x582C 1371#define BGE_LPMBX_GEN2_HI 0x5830 1372#define BGE_LPMBX_GEN2_LO 0x5834 1373#define BGE_LPMBX_GEN3_HI 0x5828 1374#define BGE_LPMBX_GEN3_LO 0x582C 1375#define BGE_LPMBX_GEN4_HI 0x5840 1376#define BGE_LPMBX_GEN4_LO 0x5844 1377#define BGE_LPMBX_GEN5_HI 0x5848 1378#define BGE_LPMBX_GEN5_LO 0x584C 1379#define BGE_LPMBX_GEN6_HI 0x5850 1380#define BGE_LPMBX_GEN6_LO 0x5854 1381#define BGE_LPMBX_GEN7_HI 0x5858 1382#define BGE_LPMBX_GEN7_LO 0x585C 1383#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1384#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1385#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1386#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1387#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1388#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1389#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1390#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1391#define BGE_LPMBX_RX_CONS0_HI 0x5880 1392#define BGE_LPMBX_RX_CONS0_LO 0x5884 1393#define BGE_LPMBX_RX_CONS1_HI 0x5888 1394#define BGE_LPMBX_RX_CONS1_LO 0x588C 1395#define BGE_LPMBX_RX_CONS2_HI 0x5890 1396#define BGE_LPMBX_RX_CONS2_LO 0x5894 1397#define BGE_LPMBX_RX_CONS3_HI 0x5898 1398#define BGE_LPMBX_RX_CONS3_LO 0x589C 1399#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1400#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1401#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1402#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1403#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1404#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1405#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1406#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1407#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1408#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1409#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1410#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1411#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1412#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1413#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1414#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1415#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1416#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1417#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1418#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1419#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1420#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1421#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1422#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1423#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1424#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1425#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1426#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1427#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1428#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1429#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1430#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1431#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1432#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1433#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1434#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1435#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1436#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1437#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1438#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1439#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1440#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1441#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1442#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1443#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1444#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1445#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1446#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1447#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1448#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1449#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1450#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1451#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1452#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1453#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1454#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1455#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1456#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1457#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1458#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1459#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1460#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1461#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1462#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1463#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1464#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1465#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1466#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1467#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1468#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1469#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1470#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1471#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1472#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1473#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1474#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1475#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1476#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1477#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1478#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1479#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1480#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1481#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1482#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1483#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1484#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1485#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1486#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1487 1488/* 1489 * Flow throw Queue reset register 1490 */ 1491#define BGE_FTQ_RESET 0x5C00 1492 1493#define BGE_FTQRESET_DMAREAD 0x00000002 1494#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1495#define BGE_FTQRESET_DMADONE 0x00000010 1496#define BGE_FTQRESET_SBDC 0x00000020 1497#define BGE_FTQRESET_SDI 0x00000040 1498#define BGE_FTQRESET_WDMA 0x00000080 1499#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1500#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1501#define BGE_FTQRESET_SDC 0x00000400 1502#define BGE_FTQRESET_HCC 0x00000800 1503#define BGE_FTQRESET_TXFIFO 0x00001000 1504#define BGE_FTQRESET_MBC 0x00002000 1505#define BGE_FTQRESET_RBDC 0x00004000 1506#define BGE_FTQRESET_RXLP 0x00008000 1507#define BGE_FTQRESET_RDBDI 0x00010000 1508#define BGE_FTQRESET_RDC 0x00020000 1509#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1510 1511/* 1512 * Message Signaled Interrupt registers 1513 */ 1514#define BGE_MSI_MODE 0x6000 1515#define BGE_MSI_STATUS 0x6004 1516#define BGE_MSI_FIFOACCESS 0x6008 1517 1518/* MSI mode register */ 1519#define BGE_MSIMODE_RESET 0x00000001 1520#define BGE_MSIMODE_ENABLE 0x00000002 1521#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1522#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1523#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1524#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1525#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1526 1527/* MSI status register */ 1528#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1529#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1530#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1531#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1532#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1533 1534 1535/* 1536 * DMA Completion registers 1537 */ 1538#define BGE_DMAC_MODE 0x6400 1539 1540/* DMA Completion mode register */ 1541#define BGE_DMACMODE_RESET 0x00000001 1542#define BGE_DMACMODE_ENABLE 0x00000002 1543 1544 1545/* 1546 * General control registers. 1547 */ 1548#define BGE_MODE_CTL 0x6800 1549#define BGE_MISC_CFG 0x6804 1550#define BGE_MISC_LOCAL_CTL 0x6808 1551#define BGE_EE_ADDR 0x6838 1552#define BGE_EE_DATA 0x683C 1553#define BGE_EE_CTL 0x6840 1554#define BGE_MDI_CTL 0x6844 1555#define BGE_EE_DELAY 0x6848 1556 1557/* Mode control register */ 1558#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1559#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1560#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1561#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1562#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1563#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1564#define BGE_MODECTL_NO_RX_CRC 0x00000400 1565#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1566#define BGE_MODECTL_NO_TX_INTR 0x00002000 1567#define BGE_MODECTL_NO_RX_INTR 0x00004000 1568#define BGE_MODECTL_FORCE_PCI32 0x00008000 1569#define BGE_MODECTL_STACKUP 0x00010000 1570#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1571#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1572#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1573#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1574#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1575#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1576#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1577#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1578#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1579#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1580 1581/* Misc. config register */ 1582#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1583#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1584 1585#define BGE_32BITTIME_66MHZ (0x41 << 1) 1586 1587/* Misc. Local Control */ 1588#define BGE_MLC_INTR_STATE 0x00000001 1589#define BGE_MLC_INTR_CLR 0x00000002 1590#define BGE_MLC_INTR_SET 0x00000004 1591#define BGE_MLC_INTR_ONATTN 0x00000008 1592#define BGE_MLC_MISCIO_IN0 0x00000100 1593#define BGE_MLC_MISCIO_IN1 0x00000200 1594#define BGE_MLC_MISCIO_IN2 0x00000400 1595#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1596#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1597#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1598#define BGE_MLC_MISCIO_OUT0 0x00004000 1599#define BGE_MLC_MISCIO_OUT1 0x00008000 1600#define BGE_MLC_MISCIO_OUT2 0x00010000 1601#define BGE_MLC_EXTRAM_ENB 0x00020000 1602#define BGE_MLC_SRAM_SIZE 0x001C0000 1603#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1604#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1605#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1606#define BGE_MLC_AUTO_EEPROM 0x01000000 1607 1608#define BGE_SSRAMSIZE_256KB 0x00000000 1609#define BGE_SSRAMSIZE_512KB 0x00040000 1610#define BGE_SSRAMSIZE_1MB 0x00080000 1611#define BGE_SSRAMSIZE_2MB 0x000C0000 1612#define BGE_SSRAMSIZE_4MB 0x00100000 1613#define BGE_SSRAMSIZE_8MB 0x00140000 1614#define BGE_SSRAMSIZE_16M 0x00180000 1615 1616/* EEPROM address register */ 1617#define BGE_EEADDR_ADDRESS 0x0000FFFC 1618#define BGE_EEADDR_HALFCLK 0x01FF0000 1619#define BGE_EEADDR_START 0x02000000 1620#define BGE_EEADDR_DEVID 0x1C000000 1621#define BGE_EEADDR_RESET 0x20000000 1622#define BGE_EEADDR_DONE 0x40000000 1623#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1624 1625#define BGE_EEDEVID(x) ((x & 7) << 26) 1626#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1627#define BGE_HALFCLK_384SCL 0x60 1628#define BGE_EE_READCMD \ 1629 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1630 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1631#define BGE_EE_WRCMD \ 1632 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1633 BGE_EEADDR_START|BGE_EEADDR_DONE) 1634 1635/* EEPROM Control register */ 1636#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1637#define BGE_EECTL_CLKOUT 0x00000002 1638#define BGE_EECTL_CLKIN 0x00000004 1639#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1640#define BGE_EECTL_DATAOUT 0x00000010 1641#define BGE_EECTL_DATAIN 0x00000020 1642 1643/* MDI (MII/GMII) access register */ 1644#define BGE_MDI_DATA 0x00000001 1645#define BGE_MDI_DIR 0x00000002 1646#define BGE_MDI_SEL 0x00000004 1647#define BGE_MDI_CLK 0x00000008 1648 1649#define BGE_MEMWIN_START 0x00008000 1650#define BGE_MEMWIN_END 0x0000FFFF 1651 1652 1653#define BGE_MEMWIN_READ(sc, x, val) \ 1654 do { \ 1655 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1656 (0xFFFF0000 & x), 4); \ 1657 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1658 } while(0) 1659 1660#define BGE_MEMWIN_WRITE(sc, x, val) \ 1661 do { \ 1662 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1663 (0xFFFF0000 & x), 4); \ 1664 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1665 } while(0) 1666 1667/* 1668 * This magic number is used to prevent PXE restart when we 1669 * issue a software reset. We write this magic number to the 1670 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1671 * code from running. 1672 */ 1673#define BGE_MAGIC_NUMBER 0x4B657654 1674 1675typedef struct { 1676 u_int32_t bge_addr_hi; 1677 u_int32_t bge_addr_lo; 1678} bge_hostaddr; 1679#define BGE_HOSTADDR(x) x.bge_addr_lo 1680 1681/* Ring control block structure */ 1682struct bge_rcb { 1683 bge_hostaddr bge_hostaddr; 1684 u_int16_t bge_flags; 1685 u_int16_t bge_max_len; 1686 u_int32_t bge_nicaddr; 1687}; 1688 1689struct bge_rcb_opaque { 1690 u_int32_t bge_reg0; 1691 u_int32_t bge_reg1; 1692 u_int32_t bge_reg2; 1693 u_int32_t bge_reg3; 1694}; 1695 1696#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1697#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1698 1699struct bge_tx_bd { 1700 bge_hostaddr bge_addr; 1701 u_int16_t bge_flags; 1702 u_int16_t bge_len; 1703 u_int16_t bge_vlan_tag; 1704 u_int16_t bge_rsvd; 1705}; 1706 1707#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1708#define BGE_TXBDFLAG_IP_CSUM 0x0002 1709#define BGE_TXBDFLAG_END 0x0004 1710#define BGE_TXBDFLAG_IP_FRAG 0x0008 1711#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1712#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1713#define BGE_TXBDFLAG_COAL_NOW 0x0080 1714#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1715#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1716#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1717#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1718#define BGE_TXBDFLAG_NO_CRC 0x8000 1719 1720#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1721 BGE_SEND_RING_1_TO_4 + \ 1722 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1723 1724struct bge_rx_bd { 1725 bge_hostaddr bge_addr; 1726 u_int16_t bge_len; 1727 u_int16_t bge_idx; 1728 u_int16_t bge_flags; 1729 u_int16_t bge_type; 1730 u_int16_t bge_tcp_udp_csum; 1731 u_int16_t bge_ip_csum; 1732 u_int16_t bge_vlan_tag; 1733 u_int16_t bge_error_flag; 1734 u_int32_t bge_rsvd; 1735 u_int32_t bge_opaque; 1736}; 1737 1738#define BGE_RXBDFLAG_END 0x0004 1739#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1740#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1741#define BGE_RXBDFLAG_ERROR 0x0400 1742#define BGE_RXBDFLAG_MINI_RING 0x0800 1743#define BGE_RXBDFLAG_IP_CSUM 0x1000 1744#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1745#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1746 1747#define BGE_RXERRFLAG_BAD_CRC 0x0001 1748#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1749#define BGE_RXERRFLAG_LINK_LOST 0x0004 1750#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1751#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1752#define BGE_RXERRFLAG_RUNT 0x0020 1753#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1754#define BGE_RXERRFLAG_GIANT 0x0080 1755 1756struct bge_sts_idx { 1757 u_int16_t bge_rx_prod_idx; 1758 u_int16_t bge_tx_cons_idx; 1759}; 1760 1761struct bge_status_block { 1762 u_int32_t bge_status; 1763 u_int32_t bge_rsvd0; 1764 u_int16_t bge_rx_jumbo_cons_idx; 1765 u_int16_t bge_rx_std_cons_idx; 1766 u_int16_t bge_rx_mini_cons_idx; 1767 u_int16_t bge_rsvd1; 1768 struct bge_sts_idx bge_idx[16]; 1769}; 1770 1771#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1772#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1773 1774#define BGE_STATFLAG_UPDATED 0x00000001 1775#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1776#define BGE_STATFLAG_ERROR 0x00000004 1777 1778 1779/* 1780 * Broadcom Vendor ID 1781 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1782 * even though they're now manufactured by Broadcom) 1783 */ 1784#define BCOM_VENDORID 0x14E4 1785#define BCOM_DEVICEID_BCM5700 0x1644 1786#define BCOM_DEVICEID_BCM5701 0x1645 1787#define BCOM_DEVICEID_BCM5703X 0x16A7 1788 1789/* 1790 * Alteon AceNIC PCI vendor/device ID. 1791 */ 1792#define ALT_VENDORID 0x12AE 1793#define ALT_DEVICEID_ACENIC 0x0001 1794#define ALT_DEVICEID_ACENIC_COPPER 0x0002 1795#define ALT_DEVICEID_BCM5700 0x0003 1796#define ALT_DEVICEID_BCM5701 0x0004 1797 1798/* 1799 * 3Com 3c985 PCI vendor/device ID. 1800 */ 1801#define TC_VENDORID 0x10B7 1802#define TC_DEVICEID_3C985 0x0001 1803#define TC_DEVICEID_3C996 0x0003 1804 1805/* 1806 * SysKonnect PCI vendor ID 1807 */ 1808#define SK_VENDORID 0x1148 1809#define SK_DEVICEID_ALTIMA 0x4400 1810#define SK_SUBSYSID_9D21 0x4421 1811#define SK_SUBSYSID_9D41 0x4441 1812 1813/* 1814 * Altima PCI vendor/device ID. 1815 */ 1816#define ALTIMA_VENDORID 0x173b 1817#define ALTIMA_DEVICE_AC1000 0x03e8 1818#define ALTIMA_DEVICE_AC9100 0x03ea 1819 1820/* 1821 * Offset of MAC address inside EEPROM. 1822 */ 1823#define BGE_EE_MAC_OFFSET 0x7C 1824#define BGE_EE_HWCFG_OFFSET 0xC8 1825 1826#define BGE_HWCFG_VOLTAGE 0x00000003 1827#define BGE_HWCFG_PHYLED_MODE 0x0000000C 1828#define BGE_HWCFG_MEDIA 0x00000030 1829 1830#define BGE_VOLTAGE_1POINT3 0x00000000 1831#define BGE_VOLTAGE_1POINT8 0x00000001 1832 1833#define BGE_PHYLEDMODE_UNSPEC 0x00000000 1834#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1835#define BGE_PHYLEDMODE_SINGLELED 0x00000008 1836 1837#define BGE_MEDIA_UNSPEC 0x00000000 1838#define BGE_MEDIA_COPPER 0x00000010 1839#define BGE_MEDIA_FIBER 0x00000020 1840 1841#define BGE_PCI_READ_CMD 0x06000000 1842#define BGE_PCI_WRITE_CMD 0x70000000 1843 1844#define BGE_TICKS_PER_SEC 1000000 1845 1846/* 1847 * Ring size constants. 1848 */ 1849#define BGE_EVENT_RING_CNT 256 1850#define BGE_CMD_RING_CNT 64 1851#define BGE_STD_RX_RING_CNT 512 1852#define BGE_JUMBO_RX_RING_CNT 256 1853#define BGE_MINI_RX_RING_CNT 1024 1854#define BGE_RETURN_RING_CNT 1024 1855 1856/* 1857 * Possible TX ring sizes. 1858 */ 1859#define BGE_TX_RING_CNT_128 128 1860#define BGE_TX_RING_BASE_128 0x3800 1861 1862#define BGE_TX_RING_CNT_256 256 1863#define BGE_TX_RING_BASE_256 0x3000 1864 1865#define BGE_TX_RING_CNT_512 512 1866#define BGE_TX_RING_BASE_512 0x2000 1867 1868#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1869#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1870 1871/* 1872 * Tigon III statistics counters. 1873 */ 1874struct bge_stats { 1875 u_int8_t Reserved0[256]; 1876 1877 /* Statistics maintained by Receive MAC. */ 1878 bge_hostaddr ifHCInOctets; 1879 bge_hostaddr Reserved1; 1880 bge_hostaddr etherStatsFragments; 1881 bge_hostaddr ifHCInUcastPkts; 1882 bge_hostaddr ifHCInMulticastPkts; 1883 bge_hostaddr ifHCInBroadcastPkts; 1884 bge_hostaddr dot3StatsFCSErrors; 1885 bge_hostaddr dot3StatsAlignmentErrors; 1886 bge_hostaddr xonPauseFramesReceived; 1887 bge_hostaddr xoffPauseFramesReceived; 1888 bge_hostaddr macControlFramesReceived; 1889 bge_hostaddr xoffStateEntered; 1890 bge_hostaddr dot3StatsFramesTooLong; 1891 bge_hostaddr etherStatsJabbers; 1892 bge_hostaddr etherStatsUndersizePkts; 1893 bge_hostaddr inRangeLengthError; 1894 bge_hostaddr outRangeLengthError; 1895 bge_hostaddr etherStatsPkts64Octets; 1896 bge_hostaddr etherStatsPkts65Octetsto127Octets; 1897 bge_hostaddr etherStatsPkts128Octetsto255Octets; 1898 bge_hostaddr etherStatsPkts256Octetsto511Octets; 1899 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 1900 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 1901 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 1902 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 1903 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 1904 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 1905 1906 bge_hostaddr Unused1[37]; 1907 1908 /* Statistics maintained by Transmit MAC. */ 1909 bge_hostaddr ifHCOutOctets; 1910 bge_hostaddr Reserved2; 1911 bge_hostaddr etherStatsCollisions; 1912 bge_hostaddr outXonSent; 1913 bge_hostaddr outXoffSent; 1914 bge_hostaddr flowControlDone; 1915 bge_hostaddr dot3StatsInternalMacTransmitErrors; 1916 bge_hostaddr dot3StatsSingleCollisionFrames; 1917 bge_hostaddr dot3StatsMultipleCollisionFrames; 1918 bge_hostaddr dot3StatsDeferredTransmissions; 1919 bge_hostaddr Reserved3; 1920 bge_hostaddr dot3StatsExcessiveCollisions; 1921 bge_hostaddr dot3StatsLateCollisions; 1922 bge_hostaddr dot3Collided2Times; 1923 bge_hostaddr dot3Collided3Times; 1924 bge_hostaddr dot3Collided4Times; 1925 bge_hostaddr dot3Collided5Times; 1926 bge_hostaddr dot3Collided6Times; 1927 bge_hostaddr dot3Collided7Times; 1928 bge_hostaddr dot3Collided8Times; 1929 bge_hostaddr dot3Collided9Times; 1930 bge_hostaddr dot3Collided10Times; 1931 bge_hostaddr dot3Collided11Times; 1932 bge_hostaddr dot3Collided12Times; 1933 bge_hostaddr dot3Collided13Times; 1934 bge_hostaddr dot3Collided14Times; 1935 bge_hostaddr dot3Collided15Times; 1936 bge_hostaddr ifHCOutUcastPkts; 1937 bge_hostaddr ifHCOutMulticastPkts; 1938 bge_hostaddr ifHCOutBroadcastPkts; 1939 bge_hostaddr dot3StatsCarrierSenseErrors; 1940 bge_hostaddr ifOutDiscards; 1941 bge_hostaddr ifOutErrors; 1942 1943 bge_hostaddr Unused2[31]; 1944 1945 /* Statistics maintained by Receive List Placement. */ 1946 bge_hostaddr COSIfHCInPkts[16]; 1947 bge_hostaddr COSFramesDroppedDueToFilters; 1948 bge_hostaddr nicDmaWriteQueueFull; 1949 bge_hostaddr nicDmaWriteHighPriQueueFull; 1950 bge_hostaddr nicNoMoreRxBDs; 1951 bge_hostaddr ifInDiscards; 1952 bge_hostaddr ifInErrors; 1953 bge_hostaddr nicRecvThresholdHit; 1954 1955 bge_hostaddr Unused3[9]; 1956 1957 /* Statistics maintained by Send Data Initiator. */ 1958 bge_hostaddr COSIfHCOutPkts[16]; 1959 bge_hostaddr nicDmaReadQueueFull; 1960 bge_hostaddr nicDmaReadHighPriQueueFull; 1961 bge_hostaddr nicSendDataCompQueueFull; 1962 1963 /* Statistics maintained by Host Coalescing. */ 1964 bge_hostaddr nicRingSetSendProdIndex; 1965 bge_hostaddr nicRingStatusUpdate; 1966 bge_hostaddr nicInterrupts; 1967 bge_hostaddr nicAvoidedInterrupts; 1968 bge_hostaddr nicSendThresholdHit; 1969 1970 u_int8_t Reserved4[320]; 1971}; 1972 1973/* 1974 * Tigon general information block. This resides in host memory 1975 * and contains the status counters, ring control blocks and 1976 * producer pointers. 1977 */ 1978 1979struct bge_gib { 1980 struct bge_stats bge_stats; 1981 struct bge_rcb bge_tx_rcb[16]; 1982 struct bge_rcb bge_std_rx_rcb; 1983 struct bge_rcb bge_jumbo_rx_rcb; 1984 struct bge_rcb bge_mini_rx_rcb; 1985 struct bge_rcb bge_return_rcb; 1986}; 1987 1988/* 1989 * NOTE! On the Alpha, we have an alignment constraint. 1990 * The first thing in the packet is a 14-byte Ethernet header. 1991 * This means that the packet is misaligned. To compensate, 1992 * we actually offset the data 2 bytes into the cluster. This 1993 * alignes the packet after the Ethernet header at a 32-bit 1994 * boundary. 1995 */ 1996 1997#define ETHER_ALIGN 2 1998 1999#define BGE_FRAMELEN 1518 2000#define BGE_MAX_FRAMELEN 1536 2001#define BGE_JUMBO_FRAMELEN 9018 2002#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2003#define BGE_PAGE_SIZE PAGE_SIZE 2004#define BGE_MIN_FRAMELEN 60 2005 2006/* 2007 * Other utility macros. 2008 */ 2009#define BGE_INC(x, y) (x) = (x + 1) % y 2010 2011/* 2012 * Vital product data and structures. 2013 */ 2014#define BGE_VPD_FLAG 0x8000 2015 2016/* VPD structures */ 2017struct vpd_res { 2018 u_int8_t vr_id; 2019 u_int8_t vr_len; 2020 u_int8_t vr_pad; 2021}; 2022 2023struct vpd_key { 2024 char vk_key[2]; 2025 u_int8_t vk_len; 2026}; 2027 2028#define VPD_RES_ID 0x82 /* ID string */ 2029#define VPD_RES_READ 0x90 /* start of read only area */ 2030#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2031#define VPD_RES_END 0x78 /* end tag */ 2032 2033 2034/* 2035 * Register access macros. The Tigon always uses memory mapped register 2036 * accesses and all registers must be accessed with 32 bit operations. 2037 */ 2038 2039#define CSR_WRITE_4(sc, reg, val) \ 2040 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2041 2042#define CSR_READ_4(sc, reg) \ 2043 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2044 2045#define BGE_SETBIT(sc, reg, x) \ 2046 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 2047#define BGE_CLRBIT(sc, reg, x) \ 2048 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 2049 2050#define PCI_SETBIT(dev, reg, x, s) \ 2051 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s) 2052#define PCI_CLRBIT(dev, reg, x, s) \ 2053 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s) 2054 2055/* 2056 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2057 * values are tuneable. They control the actual amount of buffers 2058 * allocated for the standard, mini and jumbo receive rings. 2059 */ 2060 2061#define BGE_SSLOTS 256 2062#define BGE_MSLOTS 256 2063#define BGE_JSLOTS 384 2064 2065#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2066#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2067 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2068#define BGE_JPAGESZ PAGE_SIZE 2069#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2070#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2071 2072/* 2073 * Ring structures. Most of these reside in host memory and we tell 2074 * the NIC where they are via the ring control blocks. The exceptions 2075 * are the tx and command rings, which live in NIC memory and which 2076 * we access via the shared memory window. 2077 */ 2078struct bge_ring_data { 2079 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2080 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2081 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2082 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2083 struct bge_status_block bge_status_block; 2084 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2085 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2086 struct bge_gib bge_info; 2087}; 2088 2089/* 2090 * Mbuf pointers. We need these to keep track of the virtual addresses 2091 * of our mbuf chains since we can only convert from physical to virtual, 2092 * not the other way around. 2093 */ 2094struct bge_chain_data { 2095 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2096 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2097 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2098 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2099 /* Stick the jumbo mem management stuff here too. */ 2100 caddr_t bge_jslots[BGE_JSLOTS]; 2101 void *bge_jumbo_buf; 2102}; 2103 2104struct bge_type { 2105 u_int16_t bge_vid; 2106 u_int16_t bge_did; 2107 char *bge_name; 2108}; 2109 2110#define BGE_HWREV_TIGON 0x01 2111#define BGE_HWREV_TIGON_II 0x02 2112#define BGE_TIMEOUT 1000 2113#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2114 2115struct bge_jpool_entry { 2116 int slot; 2117 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 2118}; 2119 2120struct bge_bcom_hack { 2121 int reg; 2122 int val; 2123}; 2124 2125struct bge_softc { 2126 struct arpcom arpcom; /* interface info */ 2127 device_t bge_dev; 2128 device_t bge_miibus; 2129 bus_space_handle_t bge_bhandle; 2130 vm_offset_t bge_vhandle; 2131 bus_space_tag_t bge_btag; 2132 void *bge_intrhand; 2133 struct resource *bge_irq; 2134 struct resource *bge_res; 2135 struct ifmedia bge_ifmedia; /* TBI media info */ 2136 u_int8_t bge_unit; /* interface number */ 2137 u_int8_t bge_extram; /* has external SSRAM */ 2138 u_int8_t bge_tbi; 2139 u_int8_t bge_rx_alignment_bug; 2140 u_int32_t bge_asicrev; 2141 struct bge_ring_data *bge_rdata; /* rings */ 2142 struct bge_chain_data bge_cdata; /* mbufs */ 2143 u_int16_t bge_tx_saved_considx; 2144 u_int16_t bge_rx_saved_considx; 2145 u_int16_t bge_ev_saved_considx; 2146 u_int16_t bge_std; /* current std ring head */ 2147 u_int16_t bge_jumbo; /* current jumo ring head */ 2148 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2149 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2150 u_int32_t bge_stat_ticks; 2151 u_int32_t bge_rx_coal_ticks; 2152 u_int32_t bge_tx_coal_ticks; 2153 u_int32_t bge_rx_max_coal_bds; 2154 u_int32_t bge_tx_max_coal_bds; 2155 u_int32_t bge_tx_buf_ratio; 2156 int bge_if_flags; 2157 int bge_txcnt; 2158 int bge_link; 2159 struct callout_handle bge_stat_ch; 2160 char *bge_vpd_prodname; 2161 char *bge_vpd_readonly; 2162}; 2163 2164#ifdef __alpha__ 2165#undef vtophys 2166#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 2167#endif 2168