1139749Simp/*- 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD$ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 64166676Sjkim#define BGE_PAGE_ZERO 0x00000000 65166676Sjkim#define BGE_PAGE_ZERO_END 0x000000FF 66166676Sjkim#define BGE_SEND_RING_RCB 0x00000100 67166676Sjkim#define BGE_SEND_RING_RCB_END 0x000001FF 68166676Sjkim#define BGE_RX_RETURN_RING_RCB 0x00000200 69166676Sjkim#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70166676Sjkim#define BGE_STATS_BLOCK 0x00000300 71166676Sjkim#define BGE_STATS_BLOCK_END 0x00000AFF 72166676Sjkim#define BGE_STATUS_BLOCK 0x00000B00 73166676Sjkim#define BGE_STATUS_BLOCK_END 0x00000B4F 74226814Syongari#define BGE_SRAM_FW_MB 0x00000B50 75226814Syongari#define BGE_SRAM_DATA_SIG 0x00000B54 76226814Syongari#define BGE_SRAM_DATA_CFG 0x00000B58 77226814Syongari#define BGE_SRAM_FW_CMD_MB 0x00000B78 78226814Syongari#define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C 79226814Syongari#define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80 80226821Syongari#define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04 81226815Syongari#define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14 82226815Syongari#define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18 83166676Sjkim#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 84166676Sjkim#define BGE_UNMAPPED 0x00001000 85166676Sjkim#define BGE_UNMAPPED_END 0x00001FFF 86166676Sjkim#define BGE_DMA_DESCRIPTORS 0x00002000 87166676Sjkim#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 88214428Syongari#define BGE_SEND_RING_5717 0x00004000 89166676Sjkim#define BGE_SEND_RING_1_TO_4 0x00004000 90166676Sjkim#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 9184059Swpaul 92166676Sjkim/* Firmware interface */ 93226814Syongari#define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */ 94166676Sjkim 95226864Syongari#define BGE_FW_CMD_DRV_ALIVE 0x00000001 96226864Syongari#define BGE_FW_CMD_PAUSE 0x00000002 97226864Syongari#define BGE_FW_CMD_IPV4_ADDR_CHANGE 0x00000003 98226864Syongari#define BGE_FW_CMD_IPV6_ADDR_CHANGE 0x00000004 99226864Syongari#define BGE_FW_CMD_LINK_UPDATE 0x0000000C 100226864Syongari#define BGE_FW_CMD_DRV_ALIVE2 0x0000000D 101226864Syongari#define BGE_FW_CMD_DRV_ALIVE3 0x0000000E 102226864Syongari 103226867Syongari#define BGE_FW_HB_TIMEOUT_SEC 3 104226867Syongari 105226821Syongari#define BGE_FW_DRV_STATE_START 0x00000001 106226821Syongari#define BGE_FW_DRV_STATE_START_DONE 0x80000001 107226821Syongari#define BGE_FW_DRV_STATE_UNLOAD 0x00000002 108226821Syongari#define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002 109226821Syongari#define BGE_FW_DRV_STATE_WOL 0x00000003 110226821Syongari#define BGE_FW_DRV_STATE_SUSPEND 0x00000004 111226821Syongari 11284059Swpaul/* Mappings for internal memory configuration */ 113166676Sjkim#define BGE_STD_RX_RINGS 0x00006000 114166676Sjkim#define BGE_STD_RX_RINGS_END 0x00006FFF 115166676Sjkim#define BGE_JUMBO_RX_RINGS 0x00007000 116166676Sjkim#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 117166676Sjkim#define BGE_BUFFPOOL_1 0x00008000 118166676Sjkim#define BGE_BUFFPOOL_1_END 0x0000FFFF 119166676Sjkim#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 120166676Sjkim#define BGE_BUFFPOOL_2_END 0x00017FFF 121166676Sjkim#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 122166676Sjkim#define BGE_BUFFPOOL_3_END 0x0001FFFF 123214428Syongari#define BGE_STD_RX_RINGS_5717 0x00040000 124214428Syongari#define BGE_JUMBO_RX_RINGS_5717 0x00044400 12584059Swpaul 12684059Swpaul/* Mappings for external SSRAM configurations */ 127166676Sjkim#define BGE_SEND_RING_5_TO_6 0x00006000 128166676Sjkim#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 129166676Sjkim#define BGE_SEND_RING_7_TO_8 0x00007000 130166676Sjkim#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 131166676Sjkim#define BGE_SEND_RING_9_TO_16 0x00008000 132166676Sjkim#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 133166676Sjkim#define BGE_EXT_STD_RX_RINGS 0x0000C000 134166676Sjkim#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 135166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 136166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 137166676Sjkim#define BGE_MINI_RX_RINGS 0x0000E000 138166676Sjkim#define BGE_MINI_RX_RINGS_END 0x0000FFFF 139166676Sjkim#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 140166676Sjkim#define BGE_AVAIL_REGION1_END 0x00017FFF 141166676Sjkim#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 142166676Sjkim#define BGE_AVAIL_REGION2_END 0x0001FFFF 143166676Sjkim#define BGE_EXT_SSRAM 0x00020000 144166676Sjkim#define BGE_EXT_SSRAM_END 0x000FFFFF 14584059Swpaul 14684059Swpaul 14784059Swpaul/* 14884059Swpaul * BCM570x register offsets. These are memory mapped registers 14984059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 15084059Swpaul * Each register must be accessed using 32 bit operations. 15184059Swpaul * 15284059Swpaul * All registers are accessed through a 32K shared memory block. 15384059Swpaul * The first group of registers are actually copies of the PCI 15484059Swpaul * configuration space registers. 15584059Swpaul */ 15684059Swpaul 15784059Swpaul/* 15884059Swpaul * PCI registers defined in the PCI 2.2 spec. 15984059Swpaul */ 160166676Sjkim#define BGE_PCI_VID 0x00 161166676Sjkim#define BGE_PCI_DID 0x02 162166676Sjkim#define BGE_PCI_CMD 0x04 163166676Sjkim#define BGE_PCI_STS 0x06 164166676Sjkim#define BGE_PCI_REV 0x08 165166676Sjkim#define BGE_PCI_CLASS 0x09 166166676Sjkim#define BGE_PCI_CACHESZ 0x0C 167166676Sjkim#define BGE_PCI_LATTIMER 0x0D 168166676Sjkim#define BGE_PCI_HDRTYPE 0x0E 169166676Sjkim#define BGE_PCI_BIST 0x0F 170166676Sjkim#define BGE_PCI_BAR0 0x10 171166676Sjkim#define BGE_PCI_BAR1 0x14 172166676Sjkim#define BGE_PCI_SUBSYS 0x2C 173166676Sjkim#define BGE_PCI_SUBVID 0x2E 174166676Sjkim#define BGE_PCI_ROMBASE 0x30 175166676Sjkim#define BGE_PCI_CAPPTR 0x34 176166676Sjkim#define BGE_PCI_INTLINE 0x3C 177166676Sjkim#define BGE_PCI_INTPIN 0x3D 178166676Sjkim#define BGE_PCI_MINGNT 0x3E 179166676Sjkim#define BGE_PCI_MAXLAT 0x3F 180166676Sjkim#define BGE_PCI_PCIXCAP 0x40 181166676Sjkim#define BGE_PCI_NEXTPTR_PM 0x41 182166676Sjkim#define BGE_PCI_PCIX_CMD 0x42 183166676Sjkim#define BGE_PCI_PCIX_STS 0x44 184166676Sjkim#define BGE_PCI_PWRMGMT_CAPID 0x48 185166676Sjkim#define BGE_PCI_NEXTPTR_VPD 0x49 186166676Sjkim#define BGE_PCI_PWRMGMT_CAPS 0x4A 187166676Sjkim#define BGE_PCI_PWRMGMT_CMD 0x4C 188166676Sjkim#define BGE_PCI_PWRMGMT_STS 0x4D 189166676Sjkim#define BGE_PCI_PWRMGMT_DATA 0x4F 190166676Sjkim#define BGE_PCI_VPD_CAPID 0x50 191166676Sjkim#define BGE_PCI_NEXTPTR_MSI 0x51 192166676Sjkim#define BGE_PCI_VPD_ADDR 0x52 193166676Sjkim#define BGE_PCI_VPD_DATA 0x54 194166676Sjkim#define BGE_PCI_MSI_CAPID 0x58 195166676Sjkim#define BGE_PCI_NEXTPTR_NONE 0x59 196166676Sjkim#define BGE_PCI_MSI_CTL 0x5A 197166676Sjkim#define BGE_PCI_MSI_ADDR_HI 0x5C 198166676Sjkim#define BGE_PCI_MSI_ADDR_LO 0x60 199166676Sjkim#define BGE_PCI_MSI_DATA 0x64 20084059Swpaul 201190194Smarius/* 202190194Smarius * PCI Express definitions 203190194Smarius * According to 204190194Smarius * PCI Express base specification, REV. 1.0a 205190194Smarius */ 206190194Smarius 207190194Smarius/* PCI Express device control, 16bits */ 208190194Smarius#define BGE_PCIE_DEVCTL 0x08 209190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 210190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 211190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 212190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 213190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 214190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 215190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 216190194Smarius 217135772Sps/* PCI MSI. ??? */ 218166676Sjkim#define BGE_PCIE_CAPID_REG 0xD0 219166676Sjkim#define BGE_PCIE_CAPID 0x10 220135772Sps 22184059Swpaul/* 22284059Swpaul * PCI registers specific to the BCM570x family. 22384059Swpaul */ 224166676Sjkim#define BGE_PCI_MISC_CTL 0x68 225166676Sjkim#define BGE_PCI_DMA_RW_CTL 0x6C 226166676Sjkim#define BGE_PCI_PCISTATE 0x70 227166676Sjkim#define BGE_PCI_CLKCTL 0x74 228166676Sjkim#define BGE_PCI_REG_BASEADDR 0x78 229166676Sjkim#define BGE_PCI_MEMWIN_BASEADDR 0x7C 230166676Sjkim#define BGE_PCI_REG_DATA 0x80 231166676Sjkim#define BGE_PCI_MEMWIN_DATA 0x84 232166676Sjkim#define BGE_PCI_MODECTL 0x88 233166676Sjkim#define BGE_PCI_MISC_CFG 0x8C 234166676Sjkim#define BGE_PCI_MISC_LOCALCTL 0x90 235166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 236166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 237166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 238166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 239166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 240166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 241166676Sjkim#define BGE_PCI_ISR_MBX_HI 0xB0 242166676Sjkim#define BGE_PCI_ISR_MBX_LO 0xB4 243197832Sstas#define BGE_PCI_PRODID_ASICREV 0xBC 244214428Syongari#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 245221445Syongari#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 24684059Swpaul 24784059Swpaul/* PCI Misc. Host control register */ 248166676Sjkim#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 249166676Sjkim#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 250166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 251166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 252166676Sjkim#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 253166676Sjkim#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 254166676Sjkim#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 255166676Sjkim#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 256214428Syongari#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 257166676Sjkim#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 258197832Sstas#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 25984059Swpaul 260166676Sjkim#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 26184059Swpaul 262166676Sjkim#define BGE_INIT \ 263153437Syongari (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 264153437Syongari BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 26584059Swpaul 266197832Sstas#define BGE_CHIPID_TIGON_I 0x4000 267197832Sstas#define BGE_CHIPID_TIGON_II 0x6000 268197832Sstas#define BGE_CHIPID_BCM5700_A0 0x7000 269197832Sstas#define BGE_CHIPID_BCM5700_A1 0x7001 270197832Sstas#define BGE_CHIPID_BCM5700_B0 0x7100 271197832Sstas#define BGE_CHIPID_BCM5700_B1 0x7101 272197832Sstas#define BGE_CHIPID_BCM5700_B2 0x7102 273197832Sstas#define BGE_CHIPID_BCM5700_B3 0x7103 274197832Sstas#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 275197832Sstas#define BGE_CHIPID_BCM5700_C0 0x7200 276197832Sstas#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 277197832Sstas#define BGE_CHIPID_BCM5701_B0 0x0100 278197832Sstas#define BGE_CHIPID_BCM5701_B2 0x0102 279197832Sstas#define BGE_CHIPID_BCM5701_B5 0x0105 280197832Sstas#define BGE_CHIPID_BCM5703_A0 0x1000 281197832Sstas#define BGE_CHIPID_BCM5703_A1 0x1001 282197832Sstas#define BGE_CHIPID_BCM5703_A2 0x1002 283197832Sstas#define BGE_CHIPID_BCM5703_A3 0x1003 284197832Sstas#define BGE_CHIPID_BCM5703_B0 0x1100 285197832Sstas#define BGE_CHIPID_BCM5704_A0 0x2000 286197832Sstas#define BGE_CHIPID_BCM5704_A1 0x2001 287197832Sstas#define BGE_CHIPID_BCM5704_A2 0x2002 288197832Sstas#define BGE_CHIPID_BCM5704_A3 0x2003 289197832Sstas#define BGE_CHIPID_BCM5704_B0 0x2100 290197832Sstas#define BGE_CHIPID_BCM5705_A0 0x3000 291197832Sstas#define BGE_CHIPID_BCM5705_A1 0x3001 292197832Sstas#define BGE_CHIPID_BCM5705_A2 0x3002 293197832Sstas#define BGE_CHIPID_BCM5705_A3 0x3003 294197832Sstas#define BGE_CHIPID_BCM5750_A0 0x4000 295197832Sstas#define BGE_CHIPID_BCM5750_A1 0x4001 296197832Sstas#define BGE_CHIPID_BCM5750_A3 0x4000 297197832Sstas#define BGE_CHIPID_BCM5750_B0 0x4100 298197832Sstas#define BGE_CHIPID_BCM5750_B1 0x4101 299197832Sstas#define BGE_CHIPID_BCM5750_C0 0x4200 300197832Sstas#define BGE_CHIPID_BCM5750_C1 0x4201 301197832Sstas#define BGE_CHIPID_BCM5750_C2 0x4202 302197832Sstas#define BGE_CHIPID_BCM5714_A0 0x5000 303197832Sstas#define BGE_CHIPID_BCM5752_A0 0x6000 304197832Sstas#define BGE_CHIPID_BCM5752_A1 0x6001 305197832Sstas#define BGE_CHIPID_BCM5752_A2 0x6002 306197832Sstas#define BGE_CHIPID_BCM5714_B0 0x8000 307197832Sstas#define BGE_CHIPID_BCM5714_B3 0x8003 308197832Sstas#define BGE_CHIPID_BCM5715_A0 0x9000 309197832Sstas#define BGE_CHIPID_BCM5715_A1 0x9001 310197832Sstas#define BGE_CHIPID_BCM5715_A3 0x9003 311197832Sstas#define BGE_CHIPID_BCM5755_A0 0xa000 312197832Sstas#define BGE_CHIPID_BCM5755_A1 0xa001 313197832Sstas#define BGE_CHIPID_BCM5755_A2 0xa002 314197832Sstas#define BGE_CHIPID_BCM5722_A0 0xa200 315197832Sstas#define BGE_CHIPID_BCM5754_A0 0xb000 316197832Sstas#define BGE_CHIPID_BCM5754_A1 0xb001 317197832Sstas#define BGE_CHIPID_BCM5754_A2 0xb002 318197832Sstas#define BGE_CHIPID_BCM5761_A0 0x5761000 319197832Sstas#define BGE_CHIPID_BCM5761_A1 0x5761100 320197832Sstas#define BGE_CHIPID_BCM5784_A0 0x5784000 321197832Sstas#define BGE_CHIPID_BCM5784_A1 0x5784100 322197832Sstas#define BGE_CHIPID_BCM5787_A0 0xb000 323197832Sstas#define BGE_CHIPID_BCM5787_A1 0xb001 324197832Sstas#define BGE_CHIPID_BCM5787_A2 0xb002 325214251Syongari#define BGE_CHIPID_BCM5906_A0 0xc000 326197832Sstas#define BGE_CHIPID_BCM5906_A1 0xc001 327197832Sstas#define BGE_CHIPID_BCM5906_A2 0xc002 328197832Sstas#define BGE_CHIPID_BCM57780_A0 0x57780000 329197832Sstas#define BGE_CHIPID_BCM57780_A1 0x57780001 330214428Syongari#define BGE_CHIPID_BCM5717_A0 0x05717000 331214428Syongari#define BGE_CHIPID_BCM5717_B0 0x05717100 332221818Syongari#define BGE_CHIPID_BCM5719_A0 0x05719000 333226871Syongari#define BGE_CHIPID_BCM5720_A0 0x05720000 334253483Syongari#define BGE_CHIPID_BCM5762_A0 0x05762000 335221445Syongari#define BGE_CHIPID_BCM57765_A0 0x57785000 336221445Syongari#define BGE_CHIPID_BCM57765_B0 0x57785100 33784059Swpaul 33893751Swpaul/* shorthand one */ 339197832Sstas#define BGE_ASICREV(x) ((x) >> 12) 340166676Sjkim#define BGE_ASICREV_BCM5701 0x00 341166676Sjkim#define BGE_ASICREV_BCM5703 0x01 342166676Sjkim#define BGE_ASICREV_BCM5704 0x02 343166676Sjkim#define BGE_ASICREV_BCM5705 0x03 344166676Sjkim#define BGE_ASICREV_BCM5750 0x04 345166676Sjkim#define BGE_ASICREV_BCM5714_A0 0x05 346166676Sjkim#define BGE_ASICREV_BCM5752 0x06 347166676Sjkim#define BGE_ASICREV_BCM5700 0x07 348166676Sjkim#define BGE_ASICREV_BCM5780 0x08 349166676Sjkim#define BGE_ASICREV_BCM5714 0x09 350166676Sjkim#define BGE_ASICREV_BCM5755 0x0a 351166676Sjkim#define BGE_ASICREV_BCM5754 0x0b 352166676Sjkim#define BGE_ASICREV_BCM5787 0x0b 353178667Sjhb#define BGE_ASICREV_BCM5906 0x0c 354197832Sstas/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 355197832Sstas#define BGE_ASICREV_USE_PRODID_REG 0x0f 356197832Sstas/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 357214428Syongari#define BGE_ASICREV_BCM5717 0x5717 358221818Syongari#define BGE_ASICREV_BCM5719 0x5719 359226871Syongari#define BGE_ASICREV_BCM5720 0x5720 360197832Sstas#define BGE_ASICREV_BCM5761 0x5761 361253483Syongari#define BGE_ASICREV_BCM5762 0x5762 362197832Sstas#define BGE_ASICREV_BCM5784 0x5784 363197832Sstas#define BGE_ASICREV_BCM5785 0x5785 364221445Syongari#define BGE_ASICREV_BCM57765 0x57785 365243686Syongari#define BGE_ASICREV_BCM57766 0x57766 366197832Sstas#define BGE_ASICREV_BCM57780 0x57780 36793751Swpaul 368114813Sps/* chip revisions */ 369197832Sstas#define BGE_CHIPREV(x) ((x) >> 8) 370166676Sjkim#define BGE_CHIPREV_5700_AX 0x70 371166676Sjkim#define BGE_CHIPREV_5700_BX 0x71 372166676Sjkim#define BGE_CHIPREV_5700_CX 0x72 373166676Sjkim#define BGE_CHIPREV_5701_AX 0x00 374166676Sjkim#define BGE_CHIPREV_5703_AX 0x10 375166676Sjkim#define BGE_CHIPREV_5704_AX 0x20 376166676Sjkim#define BGE_CHIPREV_5704_BX 0x21 377166676Sjkim#define BGE_CHIPREV_5750_AX 0x40 378166676Sjkim#define BGE_CHIPREV_5750_BX 0x41 379197832Sstas/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 380214428Syongari#define BGE_CHIPREV_5717_AX 0x57170 381214428Syongari#define BGE_CHIPREV_5717_BX 0x57171 382197832Sstas#define BGE_CHIPREV_5761_AX 0x57611 383253480Syongari#define BGE_CHIPREV_57765_AX 0x577850 384197832Sstas#define BGE_CHIPREV_5784_AX 0x57841 385114813Sps 38684059Swpaul/* PCI DMA Read/Write Control register */ 387166676Sjkim#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 388214428Syongari#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 389166676Sjkim#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 390166676Sjkim#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 391169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 392169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 393169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 394166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 395166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 396166676Sjkim#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 397166676Sjkim#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 398166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 399166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 40084059Swpaul 401166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 402166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 403166676Sjkim#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 404166676Sjkim#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 40584059Swpaul 406221818Syongari#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 407221445Syongari#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 408221445Syongari 409166676Sjkim#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 410166676Sjkim#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 411166676Sjkim#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 412166676Sjkim#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 413166676Sjkim#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 414166676Sjkim#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 415166676Sjkim#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 416166676Sjkim#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 41784059Swpaul 418166676Sjkim#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 419166676Sjkim#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 420166676Sjkim#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 421166676Sjkim#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 422166676Sjkim#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 423166676Sjkim#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 424166676Sjkim#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 425166676Sjkim#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 426166676Sjkim 42784059Swpaul/* 42884059Swpaul * PCI state register -- note, this register is read only 42984059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 43084059Swpaul * register is set. 43184059Swpaul */ 432166676Sjkim#define BGE_PCISTATE_FORCE_RESET 0x00000001 433166676Sjkim#define BGE_PCISTATE_INTR_STATE 0x00000002 434166676Sjkim#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 435166676Sjkim#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 436166676Sjkim#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 437241436Syongari#define BGE_PCISTATE_ROM_ENABLE 0x00000020 438241436Syongari#define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040 439166676Sjkim#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 440166676Sjkim#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 441241436Syongari#define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 442241438Syongari#define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 443241438Syongari#define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 444241438Syongari#define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 44584059Swpaul 44684059Swpaul/* 44784059Swpaul * PCI Clock Control register -- note, this register is read only 44884059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 44984059Swpaul * register is set. 45084059Swpaul */ 451166676Sjkim#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 452166676Sjkim#define BGE_PCICLOCKCTL_M66EN 0x00000080 453166676Sjkim#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 454166676Sjkim#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 455166676Sjkim#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 456166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 457166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 458166676Sjkim#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 459166676Sjkim#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 460166676Sjkim#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 46184059Swpaul 46284059Swpaul 46384059Swpaul#ifndef PCIM_CMD_MWIEN 464166676Sjkim#define PCIM_CMD_MWIEN 0x0010 46584059Swpaul#endif 466190319Smarius#ifndef PCIM_CMD_INTxDIS 467190319Smarius#define PCIM_CMD_INTxDIS 0x0400 468190319Smarius#endif 46984059Swpaul 470241438Syongari/* BAR0 (MAC) Register Definitions */ 471241438Syongari 47284059Swpaul/* 47384059Swpaul * High priority mailbox registers 47484059Swpaul * Each mailbox is 64-bits wide, though we only use the 47584059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 47684059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 47784059Swpaul * has been updated. 47884059Swpaul */ 479166676Sjkim#define BGE_MBX_IRQ0_HI 0x0200 480166676Sjkim#define BGE_MBX_IRQ0_LO 0x0204 481166676Sjkim#define BGE_MBX_IRQ1_HI 0x0208 482166676Sjkim#define BGE_MBX_IRQ1_LO 0x020C 483166676Sjkim#define BGE_MBX_IRQ2_HI 0x0210 484166676Sjkim#define BGE_MBX_IRQ2_LO 0x0214 485166676Sjkim#define BGE_MBX_IRQ3_HI 0x0218 486166676Sjkim#define BGE_MBX_IRQ3_LO 0x021C 487166676Sjkim#define BGE_MBX_GEN0_HI 0x0220 488166676Sjkim#define BGE_MBX_GEN0_LO 0x0224 489166676Sjkim#define BGE_MBX_GEN1_HI 0x0228 490166676Sjkim#define BGE_MBX_GEN1_LO 0x022C 491166676Sjkim#define BGE_MBX_GEN2_HI 0x0230 492166676Sjkim#define BGE_MBX_GEN2_LO 0x0234 493166676Sjkim#define BGE_MBX_GEN3_HI 0x0228 494166676Sjkim#define BGE_MBX_GEN3_LO 0x022C 495166676Sjkim#define BGE_MBX_GEN4_HI 0x0240 496166676Sjkim#define BGE_MBX_GEN4_LO 0x0244 497166676Sjkim#define BGE_MBX_GEN5_HI 0x0248 498166676Sjkim#define BGE_MBX_GEN5_LO 0x024C 499166676Sjkim#define BGE_MBX_GEN6_HI 0x0250 500166676Sjkim#define BGE_MBX_GEN6_LO 0x0254 501166676Sjkim#define BGE_MBX_GEN7_HI 0x0258 502166676Sjkim#define BGE_MBX_GEN7_LO 0x025C 503166676Sjkim#define BGE_MBX_RELOAD_STATS_HI 0x0260 504166676Sjkim#define BGE_MBX_RELOAD_STATS_LO 0x0264 505166676Sjkim#define BGE_MBX_RX_STD_PROD_HI 0x0268 506166676Sjkim#define BGE_MBX_RX_STD_PROD_LO 0x026C 507166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 508166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 509166676Sjkim#define BGE_MBX_RX_MINI_PROD_HI 0x0278 510166676Sjkim#define BGE_MBX_RX_MINI_PROD_LO 0x027C 511166676Sjkim#define BGE_MBX_RX_CONS0_HI 0x0280 512166676Sjkim#define BGE_MBX_RX_CONS0_LO 0x0284 513166676Sjkim#define BGE_MBX_RX_CONS1_HI 0x0288 514166676Sjkim#define BGE_MBX_RX_CONS1_LO 0x028C 515166676Sjkim#define BGE_MBX_RX_CONS2_HI 0x0290 516166676Sjkim#define BGE_MBX_RX_CONS2_LO 0x0294 517166676Sjkim#define BGE_MBX_RX_CONS3_HI 0x0298 518166676Sjkim#define BGE_MBX_RX_CONS3_LO 0x029C 519166676Sjkim#define BGE_MBX_RX_CONS4_HI 0x02A0 520166676Sjkim#define BGE_MBX_RX_CONS4_LO 0x02A4 521166676Sjkim#define BGE_MBX_RX_CONS5_HI 0x02A8 522166676Sjkim#define BGE_MBX_RX_CONS5_LO 0x02AC 523166676Sjkim#define BGE_MBX_RX_CONS6_HI 0x02B0 524166676Sjkim#define BGE_MBX_RX_CONS6_LO 0x02B4 525166676Sjkim#define BGE_MBX_RX_CONS7_HI 0x02B8 526166676Sjkim#define BGE_MBX_RX_CONS7_LO 0x02BC 527166676Sjkim#define BGE_MBX_RX_CONS8_HI 0x02C0 528166676Sjkim#define BGE_MBX_RX_CONS8_LO 0x02C4 529166676Sjkim#define BGE_MBX_RX_CONS9_HI 0x02C8 530166676Sjkim#define BGE_MBX_RX_CONS9_LO 0x02CC 531166676Sjkim#define BGE_MBX_RX_CONS10_HI 0x02D0 532166676Sjkim#define BGE_MBX_RX_CONS10_LO 0x02D4 533166676Sjkim#define BGE_MBX_RX_CONS11_HI 0x02D8 534166676Sjkim#define BGE_MBX_RX_CONS11_LO 0x02DC 535166676Sjkim#define BGE_MBX_RX_CONS12_HI 0x02E0 536166676Sjkim#define BGE_MBX_RX_CONS12_LO 0x02E4 537166676Sjkim#define BGE_MBX_RX_CONS13_HI 0x02E8 538166676Sjkim#define BGE_MBX_RX_CONS13_LO 0x02EC 539166676Sjkim#define BGE_MBX_RX_CONS14_HI 0x02F0 540166676Sjkim#define BGE_MBX_RX_CONS14_LO 0x02F4 541166676Sjkim#define BGE_MBX_RX_CONS15_HI 0x02F8 542166676Sjkim#define BGE_MBX_RX_CONS15_LO 0x02FC 543166676Sjkim#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 544166676Sjkim#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 545166676Sjkim#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 546166676Sjkim#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 547166676Sjkim#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 548166676Sjkim#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 549166676Sjkim#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 550166676Sjkim#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 551166676Sjkim#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 552166676Sjkim#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 553166676Sjkim#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 554166676Sjkim#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 555166676Sjkim#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 556166676Sjkim#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 557166676Sjkim#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 558166676Sjkim#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 559166676Sjkim#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 560166676Sjkim#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 561166676Sjkim#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 562166676Sjkim#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 563166676Sjkim#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 564166676Sjkim#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 565166676Sjkim#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 566166676Sjkim#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 567166676Sjkim#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 568166676Sjkim#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 569166676Sjkim#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 570166676Sjkim#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 571166676Sjkim#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 572166676Sjkim#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 573166676Sjkim#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 574166676Sjkim#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 575166676Sjkim#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 576166676Sjkim#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 577166676Sjkim#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 578166676Sjkim#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 579166676Sjkim#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 580166676Sjkim#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 581166676Sjkim#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 582166676Sjkim#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 583166676Sjkim#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 584166676Sjkim#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 585166676Sjkim#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 586166676Sjkim#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 587166676Sjkim#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 588166676Sjkim#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 589166676Sjkim#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 590166676Sjkim#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 591166676Sjkim#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 592166676Sjkim#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 593166676Sjkim#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 594166676Sjkim#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 595166676Sjkim#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 596166676Sjkim#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 597166676Sjkim#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 598166676Sjkim#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 599166676Sjkim#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 600166676Sjkim#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 601166676Sjkim#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 602166676Sjkim#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 603166676Sjkim#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 604166676Sjkim#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 605166676Sjkim#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 606166676Sjkim#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 60784059Swpaul 608166676Sjkim#define BGE_TX_RINGS_MAX 4 609166676Sjkim#define BGE_TX_RINGS_EXTSSRAM_MAX 16 610166676Sjkim#define BGE_RX_RINGS_MAX 16 611214428Syongari#define BGE_RX_RINGS_MAX_5717 17 61284059Swpaul 61384059Swpaul/* Ethernet MAC control registers */ 614166676Sjkim#define BGE_MAC_MODE 0x0400 615166676Sjkim#define BGE_MAC_STS 0x0404 616166676Sjkim#define BGE_MAC_EVT_ENB 0x0408 617166676Sjkim#define BGE_MAC_LED_CTL 0x040C 618166676Sjkim#define BGE_MAC_ADDR1_LO 0x0410 619166676Sjkim#define BGE_MAC_ADDR1_HI 0x0414 620166676Sjkim#define BGE_MAC_ADDR2_LO 0x0418 621166676Sjkim#define BGE_MAC_ADDR2_HI 0x041C 622166676Sjkim#define BGE_MAC_ADDR3_LO 0x0420 623166676Sjkim#define BGE_MAC_ADDR3_HI 0x0424 624166676Sjkim#define BGE_MAC_ADDR4_LO 0x0428 625166676Sjkim#define BGE_MAC_ADDR4_HI 0x042C 626166676Sjkim#define BGE_WOL_PATPTR 0x0430 627166676Sjkim#define BGE_WOL_PATCFG 0x0434 628166676Sjkim#define BGE_TX_RANDOM_BACKOFF 0x0438 629166676Sjkim#define BGE_RX_MTU 0x043C 630166676Sjkim#define BGE_GBIT_PCS_TEST 0x0440 631166676Sjkim#define BGE_TX_TBI_AUTONEG 0x0444 632166676Sjkim#define BGE_RX_TBI_AUTONEG 0x0448 633166676Sjkim#define BGE_MI_COMM 0x044C 634166676Sjkim#define BGE_MI_STS 0x0450 635166676Sjkim#define BGE_MI_MODE 0x0454 636166676Sjkim#define BGE_AUTOPOLL_STS 0x0458 637166676Sjkim#define BGE_TX_MODE 0x045C 638166676Sjkim#define BGE_TX_STS 0x0460 639166676Sjkim#define BGE_TX_LENGTHS 0x0464 640166676Sjkim#define BGE_RX_MODE 0x0468 641166676Sjkim#define BGE_RX_STS 0x046C 642166676Sjkim#define BGE_MAR0 0x0470 643166676Sjkim#define BGE_MAR1 0x0474 644166676Sjkim#define BGE_MAR2 0x0478 645166676Sjkim#define BGE_MAR3 0x047C 646166676Sjkim#define BGE_RX_BD_RULES_CTL0 0x0480 647166676Sjkim#define BGE_RX_BD_RULES_MASKVAL0 0x0484 648166676Sjkim#define BGE_RX_BD_RULES_CTL1 0x0488 649166676Sjkim#define BGE_RX_BD_RULES_MASKVAL1 0x048C 650166676Sjkim#define BGE_RX_BD_RULES_CTL2 0x0490 651166676Sjkim#define BGE_RX_BD_RULES_MASKVAL2 0x0494 652166676Sjkim#define BGE_RX_BD_RULES_CTL3 0x0498 653166676Sjkim#define BGE_RX_BD_RULES_MASKVAL3 0x049C 654166676Sjkim#define BGE_RX_BD_RULES_CTL4 0x04A0 655166676Sjkim#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 656166676Sjkim#define BGE_RX_BD_RULES_CTL5 0x04A8 657166676Sjkim#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 658166676Sjkim#define BGE_RX_BD_RULES_CTL6 0x04B0 659166676Sjkim#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 660166676Sjkim#define BGE_RX_BD_RULES_CTL7 0x04B8 661166676Sjkim#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 662166676Sjkim#define BGE_RX_BD_RULES_CTL8 0x04C0 663166676Sjkim#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 664166676Sjkim#define BGE_RX_BD_RULES_CTL9 0x04C8 665166676Sjkim#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 666166676Sjkim#define BGE_RX_BD_RULES_CTL10 0x04D0 667166676Sjkim#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 668166676Sjkim#define BGE_RX_BD_RULES_CTL11 0x04D8 669166676Sjkim#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 670166676Sjkim#define BGE_RX_BD_RULES_CTL12 0x04E0 671166676Sjkim#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 672166676Sjkim#define BGE_RX_BD_RULES_CTL13 0x04E8 673166676Sjkim#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 674166676Sjkim#define BGE_RX_BD_RULES_CTL14 0x04F0 675166676Sjkim#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 676166676Sjkim#define BGE_RX_BD_RULES_CTL15 0x04F8 677166676Sjkim#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 678166676Sjkim#define BGE_RX_RULES_CFG 0x0500 679213255Syongari#define BGE_MAX_RX_FRAME_LOWAT 0x0504 680166676Sjkim#define BGE_SERDES_CFG 0x0590 681166676Sjkim#define BGE_SERDES_STS 0x0594 682166676Sjkim#define BGE_SGDIG_CFG 0x05B0 683166676Sjkim#define BGE_SGDIG_STS 0x05B4 684213283Syongari#define BGE_TX_MAC_STATS_OCTETS 0x0800 685213283Syongari#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 686213283Syongari#define BGE_TX_MAC_STATS_COLLS 0x0808 687213283Syongari#define BGE_TX_MAC_STATS_XON_SENT 0x080C 688213283Syongari#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 689213283Syongari#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 690213283Syongari#define BGE_TX_MAC_STATS_ERRORS 0x0818 691213283Syongari#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 692213283Syongari#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 693213283Syongari#define BGE_TX_MAC_STATS_DEFERRED 0x0824 694213283Syongari#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 695213283Syongari#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 696213283Syongari#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 697213283Syongari#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 698213283Syongari#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 699213283Syongari#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 700213283Syongari#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 701213283Syongari#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 702213283Syongari#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 703213283Syongari#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 704213283Syongari#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 705213283Syongari#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 706213283Syongari#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 707213283Syongari#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 708213283Syongari#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 709213283Syongari#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 710213283Syongari#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 711213283Syongari#define BGE_TX_MAC_STATS_UCAST 0x086C 712213283Syongari#define BGE_TX_MAC_STATS_MCAST 0x0870 713213283Syongari#define BGE_TX_MAC_STATS_BCAST 0x0874 714213283Syongari#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 715213283Syongari#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 716213283Syongari#define BGE_RX_MAC_STATS_OCTESTS 0x0880 717213283Syongari#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 718213283Syongari#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 719213283Syongari#define BGE_RX_MAC_STATS_UCAST 0x088C 720213283Syongari#define BGE_RX_MAC_STATS_MCAST 0x0890 721213283Syongari#define BGE_RX_MAC_STATS_BCAST 0x0894 722213283Syongari#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 723213283Syongari#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 724213283Syongari#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 725213283Syongari#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 726213283Syongari#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 727213283Syongari#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 728213283Syongari#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 729213283Syongari#define BGE_RX_MAC_STATS_JABBERS 0x08B4 730213283Syongari#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 73184059Swpaul 73284059Swpaul/* Ethernet MAC Mode register */ 733166676Sjkim#define BGE_MACMODE_RESET 0x00000001 734166676Sjkim#define BGE_MACMODE_HALF_DUPLEX 0x00000002 735166676Sjkim#define BGE_MACMODE_PORTMODE 0x0000000C 736166676Sjkim#define BGE_MACMODE_LOOPBACK 0x00000010 737166676Sjkim#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 738166676Sjkim#define BGE_MACMODE_TX_BURST_ENB 0x00000100 739166676Sjkim#define BGE_MACMODE_MAX_DEFER 0x00000200 740166676Sjkim#define BGE_MACMODE_LINK_POLARITY 0x00000400 741166676Sjkim#define BGE_MACMODE_RX_STATS_ENB 0x00000800 742166676Sjkim#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 743166676Sjkim#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 744166676Sjkim#define BGE_MACMODE_TX_STATS_ENB 0x00004000 745166676Sjkim#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 746166676Sjkim#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 747166676Sjkim#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 748166676Sjkim#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 749166676Sjkim#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 750166676Sjkim#define BGE_MACMODE_MIP_ENB 0x00100000 751166676Sjkim#define BGE_MACMODE_TXDMA_ENB 0x00200000 752166676Sjkim#define BGE_MACMODE_RXDMA_ENB 0x00400000 753166676Sjkim#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 754241438Syongari#define BGE_MACMODE_APE_RX_EN 0x08000000 755241438Syongari#define BGE_MACMODE_APE_TX_EN 0x10000000 75684059Swpaul 757166676Sjkim#define BGE_PORTMODE_NONE 0x00000000 758166676Sjkim#define BGE_PORTMODE_MII 0x00000004 759166676Sjkim#define BGE_PORTMODE_GMII 0x00000008 760166676Sjkim#define BGE_PORTMODE_TBI 0x0000000C 76184059Swpaul 76284059Swpaul/* MAC Status register */ 763166676Sjkim#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 764166676Sjkim#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 765166676Sjkim#define BGE_MACSTAT_RX_CFG 0x00000004 766166676Sjkim#define BGE_MACSTAT_CFG_CHANGED 0x00000008 767166676Sjkim#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 768166676Sjkim#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 769166676Sjkim#define BGE_MACSTAT_LINK_CHANGED 0x00001000 770166676Sjkim#define BGE_MACSTAT_MI_COMPLETE 0x00400000 771166676Sjkim#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 772166676Sjkim#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 773166676Sjkim#define BGE_MACSTAT_ODI_ERROR 0x02000000 774166676Sjkim#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 775166676Sjkim#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 77684059Swpaul 77784059Swpaul/* MAC Event Enable Register */ 778166676Sjkim#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 779166676Sjkim#define BGE_EVTENB_LINK_CHANGED 0x00001000 780166676Sjkim#define BGE_EVTENB_MI_COMPLETE 0x00400000 781166676Sjkim#define BGE_EVTENB_MI_INTERRUPT 0x00800000 782166676Sjkim#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 783166676Sjkim#define BGE_EVTENB_ODI_ERROR 0x02000000 784166676Sjkim#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 785166676Sjkim#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 78684059Swpaul 78784059Swpaul/* LED Control Register */ 788166676Sjkim#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 789166676Sjkim#define BGE_LEDCTL_1000MBPS_LED 0x00000002 790166676Sjkim#define BGE_LEDCTL_100MBPS_LED 0x00000004 791166676Sjkim#define BGE_LEDCTL_10MBPS_LED 0x00000008 792166676Sjkim#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 793166676Sjkim#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 794236701Syongari#define BGE_LEDCTL_TRAFLED_BLINK_2 0x00000040 795166676Sjkim#define BGE_LEDCTL_1000MBPS_STS 0x00000080 796166676Sjkim#define BGE_LEDCTL_100MBPS_STS 0x00000100 797166676Sjkim#define BGE_LEDCTL_10MBPS_STS 0x00000200 798236701Syongari#define BGE_LEDCTL_TRAFLED_STS 0x00000400 799166676Sjkim#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 800166676Sjkim#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 80184059Swpaul 80284059Swpaul/* TX backoff seed register */ 803251482Syongari#define BGE_TX_BACKOFF_SEED_MASK 0x3FF 80484059Swpaul 80584059Swpaul/* Autopoll status register */ 806166676Sjkim#define BGE_AUTOPOLLSTS_ERROR 0x00000001 80784059Swpaul 80884059Swpaul/* Transmit MAC mode register */ 809166676Sjkim#define BGE_TXMODE_RESET 0x00000001 810166676Sjkim#define BGE_TXMODE_ENABLE 0x00000002 811166676Sjkim#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 812166676Sjkim#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 813166676Sjkim#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 814214216Syongari#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 815226871Syongari#define BGE_TXMODE_JMB_FRM_LEN 0x00400000 816226871Syongari#define BGE_TXMODE_CNT_DN_MODE 0x00800000 81784059Swpaul 81884059Swpaul/* Transmit MAC status register */ 819166676Sjkim#define BGE_TXSTAT_RX_XOFFED 0x00000001 820166676Sjkim#define BGE_TXSTAT_SENT_XOFF 0x00000002 821166676Sjkim#define BGE_TXSTAT_SENT_XON 0x00000004 822166676Sjkim#define BGE_TXSTAT_LINK_UP 0x00000008 823166676Sjkim#define BGE_TXSTAT_ODI_UFLOW 0x00000010 824166676Sjkim#define BGE_TXSTAT_ODI_OFLOW 0x00000020 82584059Swpaul 82684059Swpaul/* Transmit MAC lengths register */ 827166676Sjkim#define BGE_TXLEN_SLOTTIME 0x000000FF 828166676Sjkim#define BGE_TXLEN_IPG 0x00000F00 829166676Sjkim#define BGE_TXLEN_CRS 0x00003000 830226871Syongari#define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 831226871Syongari#define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 83284059Swpaul 83384059Swpaul/* Receive MAC mode register */ 834166676Sjkim#define BGE_RXMODE_RESET 0x00000001 835166676Sjkim#define BGE_RXMODE_ENABLE 0x00000002 836166676Sjkim#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 837166676Sjkim#define BGE_RXMODE_RX_GIANTS 0x00000020 838166676Sjkim#define BGE_RXMODE_RX_RUNTS 0x00000040 839166676Sjkim#define BGE_RXMODE_8022_LENCHECK 0x00000080 840166676Sjkim#define BGE_RXMODE_RX_PROMISC 0x00000100 841166676Sjkim#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 842166676Sjkim#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 843241438Syongari#define BGE_RXMODE_IPV6_ENABLE 0x01000000 844254118Syongari#define BGE_RXMODE_IPV4_FRAG_FIX 0x02000000 84584059Swpaul 84684059Swpaul/* Receive MAC status register */ 847166676Sjkim#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 848166676Sjkim#define BGE_RXSTAT_RCVD_XOFF 0x00000002 849166676Sjkim#define BGE_RXSTAT_RCVD_XON 0x00000004 85084059Swpaul 85184059Swpaul/* Receive Rules Control register */ 852166676Sjkim#define BGE_RXRULECTL_OFFSET 0x000000FF 853166676Sjkim#define BGE_RXRULECTL_CLASS 0x00001F00 854166676Sjkim#define BGE_RXRULECTL_HDRTYPE 0x0000E000 855166676Sjkim#define BGE_RXRULECTL_COMPARE_OP 0x00030000 856166676Sjkim#define BGE_RXRULECTL_MAP 0x01000000 857166676Sjkim#define BGE_RXRULECTL_DISCARD 0x02000000 858166676Sjkim#define BGE_RXRULECTL_MASK 0x04000000 859166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 860166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 861166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 862166676Sjkim#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 86384059Swpaul 86484059Swpaul/* Receive Rules Mask register */ 865166676Sjkim#define BGE_RXRULEMASK_VALUE 0x0000FFFF 866166676Sjkim#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 86784059Swpaul 868130273Swpaul/* SERDES configuration register */ 869166676Sjkim#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 870166676Sjkim#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 871166676Sjkim#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 872166676Sjkim#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 873166676Sjkim#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 874166676Sjkim#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 875166676Sjkim#define BGE_SERDESCFG_TXMODE 0x00001000 876166676Sjkim#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 877166676Sjkim#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 878166676Sjkim#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 879166676Sjkim#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 880166676Sjkim#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 881166676Sjkim#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 882166676Sjkim#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 883166676Sjkim#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 884166676Sjkim#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 885130273Swpaul 886130273Swpaul/* SERDES status register */ 887166676Sjkim#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 888166676Sjkim#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 889130273Swpaul 890130273Swpaul/* SGDIG config (not documented) */ 891166676Sjkim#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 892166676Sjkim#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 893166676Sjkim#define BGE_SGDIGCFG_SEND 0x40000000 894166676Sjkim#define BGE_SGDIGCFG_AUTO 0x80000000 895130273Swpaul 896130273Swpaul/* SGDIG status (not documented) */ 897214428Syongari#define BGE_SGDIGSTS_DONE 0x00000002 898214428Syongari#define BGE_SGDIGSTS_IS_SERDES 0x00000100 899166676Sjkim#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 900166676Sjkim#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 901130273Swpaul 902130273Swpaul 90384059Swpaul/* MI communication register */ 904166676Sjkim#define BGE_MICOMM_DATA 0x0000FFFF 905166676Sjkim#define BGE_MICOMM_REG 0x001F0000 906166676Sjkim#define BGE_MICOMM_PHY 0x03E00000 907166676Sjkim#define BGE_MICOMM_CMD 0x0C000000 908166676Sjkim#define BGE_MICOMM_READFAIL 0x10000000 909166676Sjkim#define BGE_MICOMM_BUSY 0x20000000 91084059Swpaul 911166676Sjkim#define BGE_MIREG(x) ((x & 0x1F) << 16) 912166676Sjkim#define BGE_MIPHY(x) ((x & 0x1F) << 21) 913166676Sjkim#define BGE_MICMD_WRITE 0x04000000 914166676Sjkim#define BGE_MICMD_READ 0x08000000 91584059Swpaul 91684059Swpaul/* MI status register */ 917166676Sjkim#define BGE_MISTS_LINK 0x00000001 918166676Sjkim#define BGE_MISTS_10MBPS 0x00000002 91984059Swpaul 920213485Syongari#define BGE_MIMODE_CLK_10MHZ 0x00000001 921166676Sjkim#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 922166676Sjkim#define BGE_MIMODE_AUTOPOLL 0x00000010 923166676Sjkim#define BGE_MIMODE_CLKCNT 0x001F0000 924213485Syongari#define BGE_MIMODE_500KHZ_CONST 0x00008000 925213485Syongari#define BGE_MIMODE_BASE 0x000C0000 92684059Swpaul 92784059Swpaul 92884059Swpaul/* 92984059Swpaul * Send data initiator control registers. 93084059Swpaul */ 931166676Sjkim#define BGE_SDI_MODE 0x0C00 932166676Sjkim#define BGE_SDI_STATUS 0x0C04 933166676Sjkim#define BGE_SDI_STATS_CTL 0x0C08 934166676Sjkim#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 935166676Sjkim#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 936214219Syongari#define BGE_ISO_PKT_TX 0x0C20 937166676Sjkim#define BGE_LOCSTATS_COS0 0x0C80 938166676Sjkim#define BGE_LOCSTATS_COS1 0x0C84 939166676Sjkim#define BGE_LOCSTATS_COS2 0x0C88 940166676Sjkim#define BGE_LOCSTATS_COS3 0x0C8C 941166676Sjkim#define BGE_LOCSTATS_COS4 0x0C90 942166676Sjkim#define BGE_LOCSTATS_COS5 0x0C84 943166676Sjkim#define BGE_LOCSTATS_COS6 0x0C98 944166676Sjkim#define BGE_LOCSTATS_COS7 0x0C9C 945166676Sjkim#define BGE_LOCSTATS_COS8 0x0CA0 946166676Sjkim#define BGE_LOCSTATS_COS9 0x0CA4 947166676Sjkim#define BGE_LOCSTATS_COS10 0x0CA8 948166676Sjkim#define BGE_LOCSTATS_COS11 0x0CAC 949166676Sjkim#define BGE_LOCSTATS_COS12 0x0CB0 950166676Sjkim#define BGE_LOCSTATS_COS13 0x0CB4 951166676Sjkim#define BGE_LOCSTATS_COS14 0x0CB8 952166676Sjkim#define BGE_LOCSTATS_COS15 0x0CBC 953166676Sjkim#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 954166676Sjkim#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 955166676Sjkim#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 956166676Sjkim#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 957166676Sjkim#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 958166676Sjkim#define BGE_LOCSTATS_IRQS 0x0CD4 959166676Sjkim#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 960166676Sjkim#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 96184059Swpaul 96284059Swpaul/* Send Data Initiator mode register */ 963166676Sjkim#define BGE_SDIMODE_RESET 0x00000001 964166676Sjkim#define BGE_SDIMODE_ENABLE 0x00000002 965166676Sjkim#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 966214428Syongari#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 96784059Swpaul 96884059Swpaul/* Send Data Initiator stats register */ 969166676Sjkim#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 97084059Swpaul 97184059Swpaul/* Send Data Initiator stats control register */ 972166676Sjkim#define BGE_SDISTATSCTL_ENABLE 0x00000001 973166676Sjkim#define BGE_SDISTATSCTL_FASTER 0x00000002 974166676Sjkim#define BGE_SDISTATSCTL_CLEAR 0x00000004 975166676Sjkim#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 976166676Sjkim#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 97784059Swpaul 97884059Swpaul/* 97984059Swpaul * Send Data Completion Control registers 98084059Swpaul */ 981166676Sjkim#define BGE_SDC_MODE 0x1000 982166676Sjkim#define BGE_SDC_STATUS 0x1004 98384059Swpaul 98484059Swpaul/* Send Data completion mode register */ 985166676Sjkim#define BGE_SDCMODE_RESET 0x00000001 986166676Sjkim#define BGE_SDCMODE_ENABLE 0x00000002 987166676Sjkim#define BGE_SDCMODE_ATTN 0x00000004 988197832Sstas#define BGE_SDCMODE_CDELAY 0x00000010 98984059Swpaul 99084059Swpaul/* Send Data completion status register */ 991166676Sjkim#define BGE_SDCSTAT_ATTN 0x00000004 99284059Swpaul 99384059Swpaul/* 99484059Swpaul * Send BD Ring Selector Control registers 99584059Swpaul */ 996166676Sjkim#define BGE_SRS_MODE 0x1400 997166676Sjkim#define BGE_SRS_STATUS 0x1404 998166676Sjkim#define BGE_SRS_HWDIAG 0x1408 999166676Sjkim#define BGE_SRS_LOC_NIC_CONS0 0x1440 1000166676Sjkim#define BGE_SRS_LOC_NIC_CONS1 0x1444 1001166676Sjkim#define BGE_SRS_LOC_NIC_CONS2 0x1448 1002166676Sjkim#define BGE_SRS_LOC_NIC_CONS3 0x144C 1003166676Sjkim#define BGE_SRS_LOC_NIC_CONS4 0x1450 1004166676Sjkim#define BGE_SRS_LOC_NIC_CONS5 0x1454 1005166676Sjkim#define BGE_SRS_LOC_NIC_CONS6 0x1458 1006166676Sjkim#define BGE_SRS_LOC_NIC_CONS7 0x145C 1007166676Sjkim#define BGE_SRS_LOC_NIC_CONS8 0x1460 1008166676Sjkim#define BGE_SRS_LOC_NIC_CONS9 0x1464 1009166676Sjkim#define BGE_SRS_LOC_NIC_CONS10 0x1468 1010166676Sjkim#define BGE_SRS_LOC_NIC_CONS11 0x146C 1011166676Sjkim#define BGE_SRS_LOC_NIC_CONS12 0x1470 1012166676Sjkim#define BGE_SRS_LOC_NIC_CONS13 0x1474 1013166676Sjkim#define BGE_SRS_LOC_NIC_CONS14 0x1478 1014166676Sjkim#define BGE_SRS_LOC_NIC_CONS15 0x147C 101584059Swpaul 101684059Swpaul/* Send BD Ring Selector Mode register */ 1017166676Sjkim#define BGE_SRSMODE_RESET 0x00000001 1018166676Sjkim#define BGE_SRSMODE_ENABLE 0x00000002 1019166676Sjkim#define BGE_SRSMODE_ATTN 0x00000004 102084059Swpaul 102184059Swpaul/* Send BD Ring Selector Status register */ 1022166676Sjkim#define BGE_SRSSTAT_ERROR 0x00000004 102384059Swpaul 102484059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 1025166676Sjkim#define BGE_SRSHWDIAG_STATE 0x0000000F 1026166676Sjkim#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1027166676Sjkim#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1028166676Sjkim#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 102984059Swpaul 103084059Swpaul/* 103184059Swpaul * Send BD Initiator Selector Control registers 103284059Swpaul */ 1033166676Sjkim#define BGE_SBDI_MODE 0x1800 1034166676Sjkim#define BGE_SBDI_STATUS 0x1804 1035166676Sjkim#define BGE_SBDI_LOC_NIC_PROD0 0x1808 1036166676Sjkim#define BGE_SBDI_LOC_NIC_PROD1 0x180C 1037166676Sjkim#define BGE_SBDI_LOC_NIC_PROD2 0x1810 1038166676Sjkim#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1039166676Sjkim#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1040166676Sjkim#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1041166676Sjkim#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1042166676Sjkim#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1043166676Sjkim#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1044166676Sjkim#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1045166676Sjkim#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1046166676Sjkim#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1047166676Sjkim#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1048166676Sjkim#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1049166676Sjkim#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1050166676Sjkim#define BGE_SBDI_LOC_NIC_PROD15 0x1844 105184059Swpaul 105284059Swpaul/* Send BD Initiator Mode register */ 1053166676Sjkim#define BGE_SBDIMODE_RESET 0x00000001 1054166676Sjkim#define BGE_SBDIMODE_ENABLE 0x00000002 1055166676Sjkim#define BGE_SBDIMODE_ATTN 0x00000004 105684059Swpaul 105784059Swpaul/* Send BD Initiator Status register */ 1058166676Sjkim#define BGE_SBDISTAT_ERROR 0x00000004 105984059Swpaul 106084059Swpaul/* 106184059Swpaul * Send BD Completion Control registers 106284059Swpaul */ 1063166676Sjkim#define BGE_SBDC_MODE 0x1C00 1064166676Sjkim#define BGE_SBDC_STATUS 0x1C04 106584059Swpaul 106684059Swpaul/* Send BD Completion Control Mode register */ 1067166676Sjkim#define BGE_SBDCMODE_RESET 0x00000001 1068166676Sjkim#define BGE_SBDCMODE_ENABLE 0x00000002 1069166676Sjkim#define BGE_SBDCMODE_ATTN 0x00000004 107084059Swpaul 107184059Swpaul/* Send BD Completion Control Status register */ 1072166676Sjkim#define BGE_SBDCSTAT_ATTN 0x00000004 107384059Swpaul 107484059Swpaul/* 107584059Swpaul * Receive List Placement Control registers 107684059Swpaul */ 1077166676Sjkim#define BGE_RXLP_MODE 0x2000 1078166676Sjkim#define BGE_RXLP_STATUS 0x2004 1079166676Sjkim#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1080166676Sjkim#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1081166676Sjkim#define BGE_RXLP_CFG 0x2010 1082166676Sjkim#define BGE_RXLP_STATS_CTL 0x2014 1083166676Sjkim#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1084166676Sjkim#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1085166676Sjkim#define BGE_RXLP_HEAD0 0x2100 1086166676Sjkim#define BGE_RXLP_TAIL0 0x2104 1087166676Sjkim#define BGE_RXLP_COUNT0 0x2108 1088166676Sjkim#define BGE_RXLP_HEAD1 0x2110 1089166676Sjkim#define BGE_RXLP_TAIL1 0x2114 1090166676Sjkim#define BGE_RXLP_COUNT1 0x2118 1091166676Sjkim#define BGE_RXLP_HEAD2 0x2120 1092166676Sjkim#define BGE_RXLP_TAIL2 0x2124 1093166676Sjkim#define BGE_RXLP_COUNT2 0x2128 1094166676Sjkim#define BGE_RXLP_HEAD3 0x2130 1095166676Sjkim#define BGE_RXLP_TAIL3 0x2134 1096166676Sjkim#define BGE_RXLP_COUNT3 0x2138 1097166676Sjkim#define BGE_RXLP_HEAD4 0x2140 1098166676Sjkim#define BGE_RXLP_TAIL4 0x2144 1099166676Sjkim#define BGE_RXLP_COUNT4 0x2148 1100166676Sjkim#define BGE_RXLP_HEAD5 0x2150 1101166676Sjkim#define BGE_RXLP_TAIL5 0x2154 1102166676Sjkim#define BGE_RXLP_COUNT5 0x2158 1103166676Sjkim#define BGE_RXLP_HEAD6 0x2160 1104166676Sjkim#define BGE_RXLP_TAIL6 0x2164 1105166676Sjkim#define BGE_RXLP_COUNT6 0x2168 1106166676Sjkim#define BGE_RXLP_HEAD7 0x2170 1107166676Sjkim#define BGE_RXLP_TAIL7 0x2174 1108166676Sjkim#define BGE_RXLP_COUNT7 0x2178 1109166676Sjkim#define BGE_RXLP_HEAD8 0x2180 1110166676Sjkim#define BGE_RXLP_TAIL8 0x2184 1111166676Sjkim#define BGE_RXLP_COUNT8 0x2188 1112166676Sjkim#define BGE_RXLP_HEAD9 0x2190 1113166676Sjkim#define BGE_RXLP_TAIL9 0x2194 1114166676Sjkim#define BGE_RXLP_COUNT9 0x2198 1115166676Sjkim#define BGE_RXLP_HEAD10 0x21A0 1116166676Sjkim#define BGE_RXLP_TAIL10 0x21A4 1117166676Sjkim#define BGE_RXLP_COUNT10 0x21A8 1118166676Sjkim#define BGE_RXLP_HEAD11 0x21B0 1119166676Sjkim#define BGE_RXLP_TAIL11 0x21B4 1120166676Sjkim#define BGE_RXLP_COUNT11 0x21B8 1121166676Sjkim#define BGE_RXLP_HEAD12 0x21C0 1122166676Sjkim#define BGE_RXLP_TAIL12 0x21C4 1123166676Sjkim#define BGE_RXLP_COUNT12 0x21C8 1124166676Sjkim#define BGE_RXLP_HEAD13 0x21D0 1125166676Sjkim#define BGE_RXLP_TAIL13 0x21D4 1126166676Sjkim#define BGE_RXLP_COUNT13 0x21D8 1127166676Sjkim#define BGE_RXLP_HEAD14 0x21E0 1128166676Sjkim#define BGE_RXLP_TAIL14 0x21E4 1129166676Sjkim#define BGE_RXLP_COUNT14 0x21E8 1130166676Sjkim#define BGE_RXLP_HEAD15 0x21F0 1131166676Sjkim#define BGE_RXLP_TAIL15 0x21F4 1132166676Sjkim#define BGE_RXLP_COUNT15 0x21F8 1133166676Sjkim#define BGE_RXLP_LOCSTAT_COS0 0x2200 1134166676Sjkim#define BGE_RXLP_LOCSTAT_COS1 0x2204 1135166676Sjkim#define BGE_RXLP_LOCSTAT_COS2 0x2208 1136166676Sjkim#define BGE_RXLP_LOCSTAT_COS3 0x220C 1137166676Sjkim#define BGE_RXLP_LOCSTAT_COS4 0x2210 1138166676Sjkim#define BGE_RXLP_LOCSTAT_COS5 0x2214 1139166676Sjkim#define BGE_RXLP_LOCSTAT_COS6 0x2218 1140166676Sjkim#define BGE_RXLP_LOCSTAT_COS7 0x221C 1141166676Sjkim#define BGE_RXLP_LOCSTAT_COS8 0x2220 1142166676Sjkim#define BGE_RXLP_LOCSTAT_COS9 0x2224 1143166676Sjkim#define BGE_RXLP_LOCSTAT_COS10 0x2228 1144166676Sjkim#define BGE_RXLP_LOCSTAT_COS11 0x222C 1145166676Sjkim#define BGE_RXLP_LOCSTAT_COS12 0x2230 1146166676Sjkim#define BGE_RXLP_LOCSTAT_COS13 0x2234 1147166676Sjkim#define BGE_RXLP_LOCSTAT_COS14 0x2238 1148166676Sjkim#define BGE_RXLP_LOCSTAT_COS15 0x223C 1149166676Sjkim#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1150166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1151166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1152166676Sjkim#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1153166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1154166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1155166676Sjkim#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 115684059Swpaul 115784059Swpaul 115884059Swpaul/* Receive List Placement mode register */ 1159166676Sjkim#define BGE_RXLPMODE_RESET 0x00000001 1160166676Sjkim#define BGE_RXLPMODE_ENABLE 0x00000002 1161166676Sjkim#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1162166676Sjkim#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1163166676Sjkim#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 116484059Swpaul 116584059Swpaul/* Receive List Placement Status register */ 1166166676Sjkim#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1167166676Sjkim#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1168166676Sjkim#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 116984059Swpaul 117084059Swpaul/* 117184059Swpaul * Receive Data and Receive BD Initiator Control Registers 117284059Swpaul */ 1173166676Sjkim#define BGE_RDBDI_MODE 0x2400 1174166676Sjkim#define BGE_RDBDI_STATUS 0x2404 1175166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1176166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1177166676Sjkim#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1178166676Sjkim#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1179166676Sjkim#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1180166676Sjkim#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1181166676Sjkim#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1182166676Sjkim#define BGE_RX_STD_RCB_NICADDR 0x245C 1183166676Sjkim#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1184166676Sjkim#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1185166676Sjkim#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1186166676Sjkim#define BGE_RX_MINI_RCB_NICADDR 0x246C 1187166676Sjkim#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1188166676Sjkim#define BGE_RDBDI_STD_RX_CONS 0x2474 1189166676Sjkim#define BGE_RDBDI_MINI_RX_CONS 0x2478 1190166676Sjkim#define BGE_RDBDI_RETURN_PROD0 0x2480 1191166676Sjkim#define BGE_RDBDI_RETURN_PROD1 0x2484 1192166676Sjkim#define BGE_RDBDI_RETURN_PROD2 0x2488 1193166676Sjkim#define BGE_RDBDI_RETURN_PROD3 0x248C 1194166676Sjkim#define BGE_RDBDI_RETURN_PROD4 0x2490 1195166676Sjkim#define BGE_RDBDI_RETURN_PROD5 0x2494 1196166676Sjkim#define BGE_RDBDI_RETURN_PROD6 0x2498 1197166676Sjkim#define BGE_RDBDI_RETURN_PROD7 0x249C 1198166676Sjkim#define BGE_RDBDI_RETURN_PROD8 0x24A0 1199166676Sjkim#define BGE_RDBDI_RETURN_PROD9 0x24A4 1200166676Sjkim#define BGE_RDBDI_RETURN_PROD10 0x24A8 1201166676Sjkim#define BGE_RDBDI_RETURN_PROD11 0x24AC 1202166676Sjkim#define BGE_RDBDI_RETURN_PROD12 0x24B0 1203166676Sjkim#define BGE_RDBDI_RETURN_PROD13 0x24B4 1204166676Sjkim#define BGE_RDBDI_RETURN_PROD14 0x24B8 1205166676Sjkim#define BGE_RDBDI_RETURN_PROD15 0x24BC 1206166676Sjkim#define BGE_RDBDI_HWDIAG 0x24C0 120784059Swpaul 120884059Swpaul 120984059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 1210166676Sjkim#define BGE_RDBDIMODE_RESET 0x00000001 1211166676Sjkim#define BGE_RDBDIMODE_ENABLE 0x00000002 1212166676Sjkim#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1213166676Sjkim#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1214166676Sjkim#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 121584059Swpaul 121684059Swpaul/* Receive Data and Receive BD Initiator Status register */ 1217166676Sjkim#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1218166676Sjkim#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1219166676Sjkim#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 122084059Swpaul 122184059Swpaul 122284059Swpaul/* 122384059Swpaul * Receive Data Completion Control registers 122484059Swpaul */ 1225166676Sjkim#define BGE_RDC_MODE 0x2800 122684059Swpaul 122784059Swpaul/* Receive Data Completion Mode register */ 1228166676Sjkim#define BGE_RDCMODE_RESET 0x00000001 1229166676Sjkim#define BGE_RDCMODE_ENABLE 0x00000002 1230166676Sjkim#define BGE_RDCMODE_ATTN 0x00000004 123184059Swpaul 123284059Swpaul/* 123384059Swpaul * Receive BD Initiator Control registers 123484059Swpaul */ 1235166676Sjkim#define BGE_RBDI_MODE 0x2C00 1236166676Sjkim#define BGE_RBDI_STATUS 0x2C04 1237166676Sjkim#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1238166676Sjkim#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1239166676Sjkim#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1240166676Sjkim#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1241166676Sjkim#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1242166676Sjkim#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 124384059Swpaul 1244214428Syongari#define BGE_STD_REPLENISH_LWM 0x2D00 1245214428Syongari#define BGE_JMB_REPLENISH_LWM 0x2D04 1246214428Syongari 124784059Swpaul/* Receive BD Initiator Mode register */ 1248166676Sjkim#define BGE_RBDIMODE_RESET 0x00000001 1249166676Sjkim#define BGE_RBDIMODE_ENABLE 0x00000002 1250166676Sjkim#define BGE_RBDIMODE_ATTN 0x00000004 125184059Swpaul 125284059Swpaul/* Receive BD Initiator Status register */ 1253166676Sjkim#define BGE_RBDISTAT_ATTN 0x00000004 125484059Swpaul 125584059Swpaul/* 125684059Swpaul * Receive BD Completion Control registers 125784059Swpaul */ 1258166676Sjkim#define BGE_RBDC_MODE 0x3000 1259166676Sjkim#define BGE_RBDC_STATUS 0x3004 1260166676Sjkim#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1261166676Sjkim#define BGE_RBDC_STD_BD_PROD 0x300C 1262166676Sjkim#define BGE_RBDC_MINI_BD_PROD 0x3010 126384059Swpaul 126484059Swpaul/* Receive BD completion mode register */ 1265166676Sjkim#define BGE_RBDCMODE_RESET 0x00000001 1266166676Sjkim#define BGE_RBDCMODE_ENABLE 0x00000002 1267166676Sjkim#define BGE_RBDCMODE_ATTN 0x00000004 126884059Swpaul 126984059Swpaul/* Receive BD completion status register */ 1270166676Sjkim#define BGE_RBDCSTAT_ERROR 0x00000004 127184059Swpaul 127284059Swpaul/* 127384059Swpaul * Receive List Selector Control registers 127484059Swpaul */ 1275166676Sjkim#define BGE_RXLS_MODE 0x3400 1276166676Sjkim#define BGE_RXLS_STATUS 0x3404 127784059Swpaul 127884059Swpaul/* Receive List Selector Mode register */ 1279166676Sjkim#define BGE_RXLSMODE_RESET 0x00000001 1280166676Sjkim#define BGE_RXLSMODE_ENABLE 0x00000002 1281166676Sjkim#define BGE_RXLSMODE_ATTN 0x00000004 128284059Swpaul 128384059Swpaul/* Receive List Selector Status register */ 1284166676Sjkim#define BGE_RXLSSTAT_ERROR 0x00000004 128584059Swpaul 1286213485Syongari#define BGE_CPMU_CTRL 0x3600 1287213485Syongari#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1288213485Syongari#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1289213485Syongari#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1290213485Syongari#define BGE_CPMU_HST_ACC 0x361C 1291226871Syongari#define BGE_CPMU_CLCK_ORIDE 0x3624 1292213485Syongari#define BGE_CPMU_CLCK_STAT 0x3630 1293213485Syongari#define BGE_CPMU_MUTEX_REQ 0x365C 1294213485Syongari#define BGE_CPMU_MUTEX_GNT 0x3660 1295213485Syongari#define BGE_CPMU_PHY_STRAP 0x3664 1296253480Syongari#define BGE_CPMU_PADRNG_CTL 0x3668 1297213485Syongari 1298213485Syongari/* Central Power Management Unit (CPMU) register */ 1299213485Syongari#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1300213485Syongari#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1301213485Syongari#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1302213485Syongari#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1303213485Syongari 1304213485Syongari/* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1305213485Syongari#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1306213485Syongari#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1307213485Syongari 1308213485Syongari/* Link Speed 1000MB Power Mode Clock Policy register */ 1309213485Syongari#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1310213485Syongari#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1311213485Syongari#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1312213485Syongari 1313213485Syongari/* Link Aware Power Mode Clock Policy register */ 1314213485Syongari#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1315213485Syongari#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1316213485Syongari 1317213485Syongari#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1318213485Syongari#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1319213485Syongari 1320226871Syongari/* Clock Speed Override Policy register */ 1321226871Syongari#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1322226871Syongari 1323213485Syongari/* CPMU Clock Status register */ 1324213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1325213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1326213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1327213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1328213485Syongari 1329213485Syongari/* CPMU Mutex Request register */ 1330213485Syongari#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1331213485Syongari#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1332213485Syongari 1333213485Syongari/* CPMU GPHY Strap register */ 1334213485Syongari#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1335213485Syongari 1336253480Syongari/* CPMU Padring Control register */ 1337253480Syongari#define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000 1338253480Syongari 133984059Swpaul/* 134084059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 134184059Swpaul */ 1342166676Sjkim#define BGE_MBCF_MODE 0x3800 1343166676Sjkim#define BGE_MBCF_STATUS 0x3804 134484059Swpaul 134584059Swpaul/* Mbuf Cluster Free mode register */ 1346166676Sjkim#define BGE_MBCFMODE_RESET 0x00000001 1347166676Sjkim#define BGE_MBCFMODE_ENABLE 0x00000002 1348166676Sjkim#define BGE_MBCFMODE_ATTN 0x00000004 134984059Swpaul 135084059Swpaul/* Mbuf Cluster Free status register */ 1351166676Sjkim#define BGE_MBCFSTAT_ERROR 0x00000004 135284059Swpaul 135384059Swpaul/* 135484059Swpaul * Host Coalescing Control registers 135584059Swpaul */ 1356166676Sjkim#define BGE_HCC_MODE 0x3C00 1357166676Sjkim#define BGE_HCC_STATUS 0x3C04 1358166676Sjkim#define BGE_HCC_RX_COAL_TICKS 0x3C08 1359166676Sjkim#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1360166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1361166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1362166676Sjkim#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1363166676Sjkim#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1364166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1365166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1366166676Sjkim#define BGE_HCC_STATS_TICKS 0x3C28 1367166676Sjkim#define BGE_HCC_STATS_ADDR_HI 0x3C30 1368166676Sjkim#define BGE_HCC_STATS_ADDR_LO 0x3C34 1369166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1370166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1371166676Sjkim#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1372166676Sjkim#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1373166676Sjkim#define BGE_FLOW_ATTN 0x3C48 1374166676Sjkim#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1375166676Sjkim#define BGE_HCC_STD_BD_CONS 0x3C54 1376166676Sjkim#define BGE_HCC_MINI_BD_CONS 0x3C58 1377166676Sjkim#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1378166676Sjkim#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1379166676Sjkim#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1380166676Sjkim#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1381166676Sjkim#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1382166676Sjkim#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1383166676Sjkim#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1384166676Sjkim#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1385166676Sjkim#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1386166676Sjkim#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1387166676Sjkim#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1388166676Sjkim#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1389166676Sjkim#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1390166676Sjkim#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1391166676Sjkim#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1392166676Sjkim#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1393166676Sjkim#define BGE_HCC_TX_BD_CONS0 0x3CC0 1394166676Sjkim#define BGE_HCC_TX_BD_CONS1 0x3CC4 1395166676Sjkim#define BGE_HCC_TX_BD_CONS2 0x3CC8 1396166676Sjkim#define BGE_HCC_TX_BD_CONS3 0x3CCC 1397166676Sjkim#define BGE_HCC_TX_BD_CONS4 0x3CD0 1398166676Sjkim#define BGE_HCC_TX_BD_CONS5 0x3CD4 1399166676Sjkim#define BGE_HCC_TX_BD_CONS6 0x3CD8 1400166676Sjkim#define BGE_HCC_TX_BD_CONS7 0x3CDC 1401166676Sjkim#define BGE_HCC_TX_BD_CONS8 0x3CE0 1402166676Sjkim#define BGE_HCC_TX_BD_CONS9 0x3CE4 1403166676Sjkim#define BGE_HCC_TX_BD_CONS10 0x3CE8 1404166676Sjkim#define BGE_HCC_TX_BD_CONS11 0x3CEC 1405166676Sjkim#define BGE_HCC_TX_BD_CONS12 0x3CF0 1406166676Sjkim#define BGE_HCC_TX_BD_CONS13 0x3CF4 1407166676Sjkim#define BGE_HCC_TX_BD_CONS14 0x3CF8 1408166676Sjkim#define BGE_HCC_TX_BD_CONS15 0x3CFC 140984059Swpaul 141084059Swpaul 141184059Swpaul/* Host coalescing mode register */ 1412166676Sjkim#define BGE_HCCMODE_RESET 0x00000001 1413166676Sjkim#define BGE_HCCMODE_ENABLE 0x00000002 1414166676Sjkim#define BGE_HCCMODE_ATTN 0x00000004 1415166676Sjkim#define BGE_HCCMODE_COAL_NOW 0x00000008 1416166676Sjkim#define BGE_HCCMODE_MSI_BITS 0x00000070 1417166676Sjkim#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 141884059Swpaul 1419166676Sjkim#define BGE_STATBLKSZ_FULL 0x00000000 1420166676Sjkim#define BGE_STATBLKSZ_64BYTE 0x00000080 1421166676Sjkim#define BGE_STATBLKSZ_32BYTE 0x00000100 142284059Swpaul 142384059Swpaul/* Host coalescing status register */ 1424166676Sjkim#define BGE_HCCSTAT_ERROR 0x00000004 142584059Swpaul 142684059Swpaul/* Flow attention register */ 1427166676Sjkim#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1428166676Sjkim#define BGE_FLOWATTN_MEMARB 0x00000080 1429166676Sjkim#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1430166676Sjkim#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1431166676Sjkim#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1432166676Sjkim#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1433166676Sjkim#define BGE_FLOWATTN_RDBDI 0x00080000 1434166676Sjkim#define BGE_FLOWATTN_RXLS 0x00100000 1435166676Sjkim#define BGE_FLOWATTN_RXLP 0x00200000 1436166676Sjkim#define BGE_FLOWATTN_RBDC 0x00400000 1437166676Sjkim#define BGE_FLOWATTN_RBDI 0x00800000 1438166676Sjkim#define BGE_FLOWATTN_SDC 0x08000000 1439166676Sjkim#define BGE_FLOWATTN_SDI 0x10000000 1440166676Sjkim#define BGE_FLOWATTN_SRS 0x20000000 1441166676Sjkim#define BGE_FLOWATTN_SBDC 0x40000000 1442166676Sjkim#define BGE_FLOWATTN_SBDI 0x80000000 144384059Swpaul 144484059Swpaul/* 144584059Swpaul * Memory arbiter registers 144684059Swpaul */ 1447166676Sjkim#define BGE_MARB_MODE 0x4000 1448166676Sjkim#define BGE_MARB_STATUS 0x4004 1449166676Sjkim#define BGE_MARB_TRAPADDR_HI 0x4008 1450166676Sjkim#define BGE_MARB_TRAPADDR_LO 0x400C 145184059Swpaul 145284059Swpaul/* Memory arbiter mode register */ 1453166676Sjkim#define BGE_MARBMODE_RESET 0x00000001 1454166676Sjkim#define BGE_MARBMODE_ENABLE 0x00000002 1455166676Sjkim#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1456166676Sjkim#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1457166676Sjkim#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1458166676Sjkim#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1459166676Sjkim#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1460166676Sjkim#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1461166676Sjkim#define BGE_MARBMODE_PCI_TRAP 0x00000100 1462166676Sjkim#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1463166676Sjkim#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1464166676Sjkim#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1465166676Sjkim#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1466166676Sjkim#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1467166676Sjkim#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1468166676Sjkim#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1469166676Sjkim#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1470166676Sjkim#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1471166676Sjkim#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1472166676Sjkim#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1473166676Sjkim#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1474166676Sjkim#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1475166676Sjkim#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1476166676Sjkim#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1477166676Sjkim#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1478166676Sjkim#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 147984059Swpaul 148084059Swpaul/* Memory arbiter status register */ 1481166676Sjkim#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1482166676Sjkim#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1483166676Sjkim#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1484166676Sjkim#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1485166676Sjkim#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1486166676Sjkim#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1487166676Sjkim#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1488166676Sjkim#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1489166676Sjkim#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1490166676Sjkim#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1491166676Sjkim#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1492166676Sjkim#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1493166676Sjkim#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1494166676Sjkim#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1495166676Sjkim#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1496166676Sjkim#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1497166676Sjkim#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1498166676Sjkim#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1499166676Sjkim#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1500166676Sjkim#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1501166676Sjkim#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1502166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1503166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1504166676Sjkim#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 150584059Swpaul 150684059Swpaul/* 150784059Swpaul * Buffer manager control registers 150884059Swpaul */ 1509166676Sjkim#define BGE_BMAN_MODE 0x4400 1510166676Sjkim#define BGE_BMAN_STATUS 0x4404 1511166676Sjkim#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1512166676Sjkim#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1513166676Sjkim#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1514166676Sjkim#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1515166676Sjkim#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1516166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1517166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1518166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1519166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1520166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1521166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1522166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1523166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1524166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1525166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1526166676Sjkim#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1527166676Sjkim#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1528166676Sjkim#define BGE_BMAN_HWDIAG_1 0x444C 1529166676Sjkim#define BGE_BMAN_HWDIAG_2 0x4450 1530166676Sjkim#define BGE_BMAN_HWDIAG_3 0x4454 153184059Swpaul 153284059Swpaul/* Buffer manager mode register */ 1533166676Sjkim#define BGE_BMANMODE_RESET 0x00000001 1534166676Sjkim#define BGE_BMANMODE_ENABLE 0x00000002 1535166676Sjkim#define BGE_BMANMODE_ATTN 0x00000004 1536166676Sjkim#define BGE_BMANMODE_TESTMODE 0x00000008 1537166676Sjkim#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1538221818Syongari#define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 153984059Swpaul 154084059Swpaul/* Buffer manager status register */ 1541166676Sjkim#define BGE_BMANSTAT_ERRO 0x00000004 1542166676Sjkim#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 154384059Swpaul 154484059Swpaul 154584059Swpaul/* 154684059Swpaul * Read DMA Control registers 154784059Swpaul */ 1548166676Sjkim#define BGE_RDMA_MODE 0x4800 1549166676Sjkim#define BGE_RDMA_STATUS 0x4804 1550253483Syongari#define BGE_RDMA_RSRVCTRL_REG2 0x4890 1551253483Syongari#define BGE_RDMA_LSO_CRPTEN_CTRL_REG2 0x48A0 1552213411Syongari#define BGE_RDMA_RSRVCTRL 0x4900 1553221818Syongari#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 155484059Swpaul 155584059Swpaul/* Read DMA mode register */ 1556166676Sjkim#define BGE_RDMAMODE_RESET 0x00000001 1557166676Sjkim#define BGE_RDMAMODE_ENABLE 0x00000002 1558166676Sjkim#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1559166676Sjkim#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1560166676Sjkim#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1561166676Sjkim#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1562166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1563166676Sjkim#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1564166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1565166676Sjkim#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1566166676Sjkim#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1567197832Sstas#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1568197832Sstas#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1569197832Sstas#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1570190194Smarius#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1571190194Smarius#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1572214428Syongari#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1573199671Syongari#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1574199671Syongari#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1575226871Syongari#define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 157684059Swpaul 157784059Swpaul/* Read DMA status register */ 1578166676Sjkim#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1579166676Sjkim#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1580166676Sjkim#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1581166676Sjkim#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1582166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1583166676Sjkim#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1584166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1585166676Sjkim#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 158684059Swpaul 1587213411Syongari/* Read DMA Reserved Control register */ 1588213411Syongari#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1589221818Syongari#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1590221818Syongari#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1591221818Syongari#define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1592221818Syongari#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1593221818Syongari#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1594221818Syongari#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1595213411Syongari 1596228479Syongari#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 1597221818Syongari#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1598221818Syongari#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1599253408Syongari#define BGE_RDMA_TX_LENGTH_WA_5719 0x02000000 1600253408Syongari#define BGE_RDMA_TX_LENGTH_WA_5720 0x00200000 1601221818Syongari 1602241438Syongari/* BD Read DMA Mode register */ 1603241438Syongari#define BGE_RDMA_BD_MODE 0x4A00 1604241438Syongari/* BD Read DMA Mode status register */ 1605241438Syongari#define BGE_RDMA_BD_STATUS 0x4A04 1606241438Syongari 1607241438Syongari#define BGE_RDMA_BD_MODE_RESET 0x00000001 1608241438Syongari#define BGE_RDMA_BD_MODE_ENABLE 0x00000002 1609241438Syongari 1610241438Syongari/* Non-LSO Read DMA Mode register */ 1611241438Syongari#define BGE_RDMA_NON_LSO_MODE 0x4B00 1612241438Syongari/* Non-LSO Read DMA Mode status register */ 1613241438Syongari#define BGE_RDMA_NON_LSO_STATUS 0x4B04 1614241438Syongari 1615241438Syongari#define BGE_RDMA_NON_LSO_MODE_RESET 0x00000001 1616241438Syongari#define BGE_RDMA_NON_LSO_MODE_ENABLE 0x00000002 1617241438Syongari 1618253408Syongari#define BGE_RDMA_LENGTH 0x4BE0 1619253408Syongari#define BGE_NUM_RDMA_CHANNELS 4 1620253408Syongari 162184059Swpaul/* 162284059Swpaul * Write DMA control registers 162384059Swpaul */ 1624166676Sjkim#define BGE_WDMA_MODE 0x4C00 1625166676Sjkim#define BGE_WDMA_STATUS 0x4C04 162684059Swpaul 162784059Swpaul/* Write DMA mode register */ 1628166676Sjkim#define BGE_WDMAMODE_RESET 0x00000001 1629166676Sjkim#define BGE_WDMAMODE_ENABLE 0x00000002 1630166676Sjkim#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1631166676Sjkim#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1632166676Sjkim#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1633166676Sjkim#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1634166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1635166676Sjkim#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1636166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1637166676Sjkim#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1638166676Sjkim#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1639197837Sstas#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1640213333Syongari#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 164184059Swpaul 164284059Swpaul/* Write DMA status register */ 1643166676Sjkim#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1644166676Sjkim#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1645166676Sjkim#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1646166676Sjkim#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1647166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1648166676Sjkim#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1649166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1650166676Sjkim#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 165184059Swpaul 165284059Swpaul 165384059Swpaul/* 165484059Swpaul * RX CPU registers 165584059Swpaul */ 1656166676Sjkim#define BGE_RXCPU_MODE 0x5000 1657166676Sjkim#define BGE_RXCPU_STATUS 0x5004 1658166676Sjkim#define BGE_RXCPU_PC 0x501C 165984059Swpaul 166084059Swpaul/* RX CPU mode register */ 1661166676Sjkim#define BGE_RXCPUMODE_RESET 0x00000001 1662166676Sjkim#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1663166676Sjkim#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1664166676Sjkim#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1665166676Sjkim#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1666166676Sjkim#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1667166676Sjkim#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1668166676Sjkim#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1669166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1670166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1671166676Sjkim#define BGE_RXCPUMODE_HALTCPU 0x00000400 1672166676Sjkim#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1673166676Sjkim#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1674166676Sjkim#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 167584059Swpaul 167684059Swpaul/* RX CPU status register */ 1677166676Sjkim#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1678166676Sjkim#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1679166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1680166676Sjkim#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1681166676Sjkim#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1682166676Sjkim#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1683166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1684166676Sjkim#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1685166676Sjkim#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1686166676Sjkim#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1687166676Sjkim#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1688166676Sjkim#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1689166676Sjkim#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1690166676Sjkim#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1691166676Sjkim#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1692166676Sjkim#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1693166676Sjkim#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 169484059Swpaul 1695178667Sjhb/* 1696178667Sjhb * V? CPU registers 1697178667Sjhb */ 1698178667Sjhb#define BGE_VCPU_STATUS 0x5100 1699178667Sjhb#define BGE_VCPU_EXT_CTRL 0x6890 170084059Swpaul 1701178667Sjhb#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1702178667Sjhb#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1703178667Sjhb 1704178667Sjhb#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1705178667Sjhb#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1706178667Sjhb 170784059Swpaul/* 170884059Swpaul * TX CPU registers 170984059Swpaul */ 1710166676Sjkim#define BGE_TXCPU_MODE 0x5400 1711166676Sjkim#define BGE_TXCPU_STATUS 0x5404 1712166676Sjkim#define BGE_TXCPU_PC 0x541C 171384059Swpaul 171484059Swpaul/* TX CPU mode register */ 1715166676Sjkim#define BGE_TXCPUMODE_RESET 0x00000001 1716166676Sjkim#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1717166676Sjkim#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1718166676Sjkim#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1719166676Sjkim#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1720166676Sjkim#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1721166676Sjkim#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1722166676Sjkim#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1723166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1724166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1725166676Sjkim#define BGE_TXCPUMODE_HALTCPU 0x00000400 1726166676Sjkim#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1727166676Sjkim#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 172884059Swpaul 172984059Swpaul/* TX CPU status register */ 1730166676Sjkim#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1731166676Sjkim#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1732166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1733166676Sjkim#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1734166676Sjkim#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1735166676Sjkim#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1736166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1737166676Sjkim#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1738166676Sjkim#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1739166676Sjkim#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1740166676Sjkim#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1741166676Sjkim#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1742166676Sjkim#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1743166676Sjkim#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1744166676Sjkim#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1745166676Sjkim#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1746166676Sjkim#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 174784059Swpaul 174884059Swpaul 174984059Swpaul/* 175084059Swpaul * Low priority mailbox registers 175184059Swpaul */ 1752166676Sjkim#define BGE_LPMBX_IRQ0_HI 0x5800 1753166676Sjkim#define BGE_LPMBX_IRQ0_LO 0x5804 1754166676Sjkim#define BGE_LPMBX_IRQ1_HI 0x5808 1755166676Sjkim#define BGE_LPMBX_IRQ1_LO 0x580C 1756166676Sjkim#define BGE_LPMBX_IRQ2_HI 0x5810 1757166676Sjkim#define BGE_LPMBX_IRQ2_LO 0x5814 1758166676Sjkim#define BGE_LPMBX_IRQ3_HI 0x5818 1759166676Sjkim#define BGE_LPMBX_IRQ3_LO 0x581C 1760166676Sjkim#define BGE_LPMBX_GEN0_HI 0x5820 1761166676Sjkim#define BGE_LPMBX_GEN0_LO 0x5824 1762166676Sjkim#define BGE_LPMBX_GEN1_HI 0x5828 1763166676Sjkim#define BGE_LPMBX_GEN1_LO 0x582C 1764166676Sjkim#define BGE_LPMBX_GEN2_HI 0x5830 1765166676Sjkim#define BGE_LPMBX_GEN2_LO 0x5834 1766166676Sjkim#define BGE_LPMBX_GEN3_HI 0x5828 1767166676Sjkim#define BGE_LPMBX_GEN3_LO 0x582C 1768166676Sjkim#define BGE_LPMBX_GEN4_HI 0x5840 1769166676Sjkim#define BGE_LPMBX_GEN4_LO 0x5844 1770166676Sjkim#define BGE_LPMBX_GEN5_HI 0x5848 1771166676Sjkim#define BGE_LPMBX_GEN5_LO 0x584C 1772166676Sjkim#define BGE_LPMBX_GEN6_HI 0x5850 1773166676Sjkim#define BGE_LPMBX_GEN6_LO 0x5854 1774166676Sjkim#define BGE_LPMBX_GEN7_HI 0x5858 1775166676Sjkim#define BGE_LPMBX_GEN7_LO 0x585C 1776166676Sjkim#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1777166676Sjkim#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1778166676Sjkim#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1779166676Sjkim#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1780166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1781166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1782166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1783166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1784166676Sjkim#define BGE_LPMBX_RX_CONS0_HI 0x5880 1785166676Sjkim#define BGE_LPMBX_RX_CONS0_LO 0x5884 1786166676Sjkim#define BGE_LPMBX_RX_CONS1_HI 0x5888 1787166676Sjkim#define BGE_LPMBX_RX_CONS1_LO 0x588C 1788166676Sjkim#define BGE_LPMBX_RX_CONS2_HI 0x5890 1789166676Sjkim#define BGE_LPMBX_RX_CONS2_LO 0x5894 1790166676Sjkim#define BGE_LPMBX_RX_CONS3_HI 0x5898 1791166676Sjkim#define BGE_LPMBX_RX_CONS3_LO 0x589C 1792166676Sjkim#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1793166676Sjkim#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1794166676Sjkim#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1795166676Sjkim#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1796166676Sjkim#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1797166676Sjkim#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1798166676Sjkim#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1799166676Sjkim#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1800166676Sjkim#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1801166676Sjkim#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1802166676Sjkim#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1803166676Sjkim#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1804166676Sjkim#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1805166676Sjkim#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1806166676Sjkim#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1807166676Sjkim#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1808166676Sjkim#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1809166676Sjkim#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1810166676Sjkim#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1811166676Sjkim#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1812166676Sjkim#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1813166676Sjkim#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1814166676Sjkim#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1815166676Sjkim#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1816166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1817166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1818166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1819166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1820166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1821166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1822166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1823166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1824166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1825166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1826166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1827166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1828166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1829166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1830166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1831166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1832166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1833166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1834166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1835166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1836166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1837166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1838166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1839166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1840166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1841166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1842166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1843166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1844166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1845166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1846166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1847166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1848166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1849166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1850166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1851166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1852166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1853166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1854166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1855166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1856166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1857166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1858166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1859166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1860166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1861166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1862166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1863166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1864166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1865166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1866166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1867166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1868166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1869166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1870166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1871166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1872166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1873166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1874166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1875166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1876166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1877166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1878166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1879166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 188084059Swpaul 188184059Swpaul/* 188284059Swpaul * Flow throw Queue reset register 188384059Swpaul */ 1884166676Sjkim#define BGE_FTQ_RESET 0x5C00 188584059Swpaul 1886166676Sjkim#define BGE_FTQRESET_DMAREAD 0x00000002 1887166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1888166676Sjkim#define BGE_FTQRESET_DMADONE 0x00000010 1889166676Sjkim#define BGE_FTQRESET_SBDC 0x00000020 1890166676Sjkim#define BGE_FTQRESET_SDI 0x00000040 1891166676Sjkim#define BGE_FTQRESET_WDMA 0x00000080 1892166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1893166676Sjkim#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1894166676Sjkim#define BGE_FTQRESET_SDC 0x00000400 1895166676Sjkim#define BGE_FTQRESET_HCC 0x00000800 1896166676Sjkim#define BGE_FTQRESET_TXFIFO 0x00001000 1897166676Sjkim#define BGE_FTQRESET_MBC 0x00002000 1898166676Sjkim#define BGE_FTQRESET_RBDC 0x00004000 1899166676Sjkim#define BGE_FTQRESET_RXLP 0x00008000 1900166676Sjkim#define BGE_FTQRESET_RDBDI 0x00010000 1901166676Sjkim#define BGE_FTQRESET_RDC 0x00020000 1902166676Sjkim#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 190384059Swpaul 190484059Swpaul/* 190584059Swpaul * Message Signaled Interrupt registers 190684059Swpaul */ 1907166676Sjkim#define BGE_MSI_MODE 0x6000 1908166676Sjkim#define BGE_MSI_STATUS 0x6004 1909166676Sjkim#define BGE_MSI_FIFOACCESS 0x6008 191084059Swpaul 191184059Swpaul/* MSI mode register */ 1912166676Sjkim#define BGE_MSIMODE_RESET 0x00000001 1913166676Sjkim#define BGE_MSIMODE_ENABLE 0x00000002 1914198967Syongari#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1915198967Syongari#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 191684059Swpaul 191784059Swpaul/* MSI status register */ 1918166676Sjkim#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1919166676Sjkim#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1920166676Sjkim#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1921166676Sjkim#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1922166676Sjkim#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 192384059Swpaul 192484059Swpaul 192584059Swpaul/* 192684059Swpaul * DMA Completion registers 192784059Swpaul */ 1928166676Sjkim#define BGE_DMAC_MODE 0x6400 192984059Swpaul 193084059Swpaul/* DMA Completion mode register */ 1931166676Sjkim#define BGE_DMACMODE_RESET 0x00000001 1932166676Sjkim#define BGE_DMACMODE_ENABLE 0x00000002 193384059Swpaul 193484059Swpaul 193584059Swpaul/* 193684059Swpaul * General control registers. 193784059Swpaul */ 1938166676Sjkim#define BGE_MODE_CTL 0x6800 1939166676Sjkim#define BGE_MISC_CFG 0x6804 1940166676Sjkim#define BGE_MISC_LOCAL_CTL 0x6808 1941226820Syongari#define BGE_RX_CPU_EVENT 0x6810 1942226820Syongari#define BGE_TX_CPU_EVENT 0x6820 1943166676Sjkim#define BGE_EE_ADDR 0x6838 1944166676Sjkim#define BGE_EE_DATA 0x683C 1945166676Sjkim#define BGE_EE_CTL 0x6840 1946166676Sjkim#define BGE_MDI_CTL 0x6844 1947166676Sjkim#define BGE_EE_DELAY 0x6848 1948166676Sjkim#define BGE_FASTBOOT_PC 0x6894 194984059Swpaul 1950226866Syongari#define BGE_RX_CPU_DRV_EVENT 0x00004000 1951226866Syongari 1952178667Sjhb/* 1953178667Sjhb * NVRAM Control registers 1954178667Sjhb */ 1955178667Sjhb#define BGE_NVRAM_CMD 0x7000 1956178667Sjhb#define BGE_NVRAM_STAT 0x7004 1957178667Sjhb#define BGE_NVRAM_WRDATA 0x7008 1958178667Sjhb#define BGE_NVRAM_ADDR 0x700c 1959178667Sjhb#define BGE_NVRAM_RDDATA 0x7010 1960178667Sjhb#define BGE_NVRAM_CFG1 0x7014 1961178667Sjhb#define BGE_NVRAM_CFG2 0x7018 1962178667Sjhb#define BGE_NVRAM_CFG3 0x701c 1963178667Sjhb#define BGE_NVRAM_SWARB 0x7020 1964178667Sjhb#define BGE_NVRAM_ACCESS 0x7024 1965178667Sjhb#define BGE_NVRAM_WRITE1 0x7028 1966178667Sjhb 1967178667Sjhb#define BGE_NVRAMCMD_RESET 0x00000001 1968178667Sjhb#define BGE_NVRAMCMD_DONE 0x00000008 1969178667Sjhb#define BGE_NVRAMCMD_START 0x00000010 1970178667Sjhb#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1971178667Sjhb#define BGE_NVRAMCMD_ERASE 0x00000040 1972178667Sjhb#define BGE_NVRAMCMD_FIRST 0x00000080 1973178667Sjhb#define BGE_NVRAMCMD_LAST 0x00000100 1974178667Sjhb 1975178667Sjhb#define BGE_NVRAM_READCMD \ 1976178667Sjhb (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1977178667Sjhb BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1978178667Sjhb#define BGE_NVRAM_WRITECMD \ 1979178667Sjhb (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1980178667Sjhb BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1981178667Sjhb 1982178667Sjhb#define BGE_NVRAMSWARB_SET0 0x00000001 1983178667Sjhb#define BGE_NVRAMSWARB_SET1 0x00000002 1984178667Sjhb#define BGE_NVRAMSWARB_SET2 0x00000003 1985178667Sjhb#define BGE_NVRAMSWARB_SET3 0x00000004 1986178667Sjhb#define BGE_NVRAMSWARB_CLR0 0x00000010 1987178667Sjhb#define BGE_NVRAMSWARB_CLR1 0x00000020 1988178667Sjhb#define BGE_NVRAMSWARB_CLR2 0x00000040 1989178667Sjhb#define BGE_NVRAMSWARB_CLR3 0x00000080 1990178667Sjhb#define BGE_NVRAMSWARB_GNT0 0x00000100 1991178667Sjhb#define BGE_NVRAMSWARB_GNT1 0x00000200 1992178667Sjhb#define BGE_NVRAMSWARB_GNT2 0x00000400 1993178667Sjhb#define BGE_NVRAMSWARB_GNT3 0x00000800 1994178667Sjhb#define BGE_NVRAMSWARB_REQ0 0x00001000 1995178667Sjhb#define BGE_NVRAMSWARB_REQ1 0x00002000 1996178667Sjhb#define BGE_NVRAMSWARB_REQ2 0x00004000 1997178667Sjhb#define BGE_NVRAMSWARB_REQ3 0x00008000 1998178667Sjhb 1999178667Sjhb#define BGE_NVRAMACC_ENABLE 0x00000001 2000178667Sjhb#define BGE_NVRAMACC_WRENABLE 0x00000002 2001178667Sjhb 200284059Swpaul/* Mode control register */ 2003166676Sjkim#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 2004166676Sjkim#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 2005166676Sjkim#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 2006166676Sjkim#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 2007166676Sjkim#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 2008226871Syongari#define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 2009226871Syongari#define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 2010166676Sjkim#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 2011166676Sjkim#define BGE_MODECTL_NO_RX_CRC 0x00000400 2012166676Sjkim#define BGE_MODECTL_RX_BADFRAMES 0x00000800 2013166676Sjkim#define BGE_MODECTL_NO_TX_INTR 0x00002000 2014166676Sjkim#define BGE_MODECTL_NO_RX_INTR 0x00004000 2015166676Sjkim#define BGE_MODECTL_FORCE_PCI32 0x00008000 2016226871Syongari#define BGE_MODECTL_B2HRX_ENABLE 0x00008000 2017166676Sjkim#define BGE_MODECTL_STACKUP 0x00010000 2018166676Sjkim#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 2019226871Syongari#define BGE_MODECTL_HTX2B_ENABLE 0x00040000 2020166676Sjkim#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 2021166676Sjkim#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 2022166676Sjkim#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 2023166676Sjkim#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 2024166676Sjkim#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 2025166676Sjkim#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 2026166676Sjkim#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 2027166676Sjkim#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 2028166676Sjkim#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 202984059Swpaul 203084059Swpaul/* Misc. config register */ 2031166676Sjkim#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 2032166676Sjkim#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 2033232849Syongari#define BGE_MISCCFG_BOARD_ID_MASK 0x0001E000 2034232849Syongari#define BGE_MISCCFG_BOARD_ID_5704 0x00000000 2035232849Syongari#define BGE_MISCCFG_BOARD_ID_5704CIOBE 0x00004000 2036178785Sbz#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 2037178785Sbz#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 2038178667Sjhb#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 2039210152Syongari#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 204084059Swpaul 2041166676Sjkim#define BGE_32BITTIME_66MHZ (0x41 << 1) 204284059Swpaul 204384059Swpaul/* Misc. Local Control */ 2044166676Sjkim#define BGE_MLC_INTR_STATE 0x00000001 2045166676Sjkim#define BGE_MLC_INTR_CLR 0x00000002 2046166676Sjkim#define BGE_MLC_INTR_SET 0x00000004 2047166676Sjkim#define BGE_MLC_INTR_ONATTN 0x00000008 2048166676Sjkim#define BGE_MLC_MISCIO_IN0 0x00000100 2049166676Sjkim#define BGE_MLC_MISCIO_IN1 0x00000200 2050166676Sjkim#define BGE_MLC_MISCIO_IN2 0x00000400 2051166676Sjkim#define BGE_MLC_MISCIO_OUTEN0 0x00000800 2052166676Sjkim#define BGE_MLC_MISCIO_OUTEN1 0x00001000 2053166676Sjkim#define BGE_MLC_MISCIO_OUTEN2 0x00002000 2054166676Sjkim#define BGE_MLC_MISCIO_OUT0 0x00004000 2055166676Sjkim#define BGE_MLC_MISCIO_OUT1 0x00008000 2056166676Sjkim#define BGE_MLC_MISCIO_OUT2 0x00010000 2057166676Sjkim#define BGE_MLC_EXTRAM_ENB 0x00020000 2058166676Sjkim#define BGE_MLC_SRAM_SIZE 0x001C0000 2059166676Sjkim#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 2060166676Sjkim#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 2061166676Sjkim#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 2062166676Sjkim#define BGE_MLC_AUTO_EEPROM 0x01000000 206384059Swpaul 2064166676Sjkim#define BGE_SSRAMSIZE_256KB 0x00000000 2065166676Sjkim#define BGE_SSRAMSIZE_512KB 0x00040000 2066166676Sjkim#define BGE_SSRAMSIZE_1MB 0x00080000 2067166676Sjkim#define BGE_SSRAMSIZE_2MB 0x000C0000 2068166676Sjkim#define BGE_SSRAMSIZE_4MB 0x00100000 2069166676Sjkim#define BGE_SSRAMSIZE_8MB 0x00140000 2070166676Sjkim#define BGE_SSRAMSIZE_16M 0x00180000 207184059Swpaul 207284059Swpaul/* EEPROM address register */ 2073166676Sjkim#define BGE_EEADDR_ADDRESS 0x0000FFFC 2074166676Sjkim#define BGE_EEADDR_HALFCLK 0x01FF0000 2075166676Sjkim#define BGE_EEADDR_START 0x02000000 2076166676Sjkim#define BGE_EEADDR_DEVID 0x1C000000 2077166676Sjkim#define BGE_EEADDR_RESET 0x20000000 2078166676Sjkim#define BGE_EEADDR_DONE 0x40000000 2079166676Sjkim#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 208084059Swpaul 2081166676Sjkim#define BGE_EEDEVID(x) ((x & 7) << 26) 2082166676Sjkim#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2083166676Sjkim#define BGE_HALFCLK_384SCL 0x60 2084166676Sjkim#define BGE_EE_READCMD \ 208584059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 208684059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2087166676Sjkim#define BGE_EE_WRCMD \ 208884059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 208984059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 209084059Swpaul 209184059Swpaul/* EEPROM Control register */ 2092166676Sjkim#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2093166676Sjkim#define BGE_EECTL_CLKOUT 0x00000002 2094166676Sjkim#define BGE_EECTL_CLKIN 0x00000004 2095166676Sjkim#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2096166676Sjkim#define BGE_EECTL_DATAOUT 0x00000010 2097166676Sjkim#define BGE_EECTL_DATAIN 0x00000020 209884059Swpaul 209984059Swpaul/* MDI (MII/GMII) access register */ 2100166676Sjkim#define BGE_MDI_DATA 0x00000001 2101166676Sjkim#define BGE_MDI_DIR 0x00000002 2102166676Sjkim#define BGE_MDI_SEL 0x00000004 2103166676Sjkim#define BGE_MDI_CLK 0x00000008 210484059Swpaul 2105166676Sjkim#define BGE_MEMWIN_START 0x00008000 2106166676Sjkim#define BGE_MEMWIN_END 0x0000FFFF 210784059Swpaul 2108241438Syongari/* BAR1 (APE) Register Definitions */ 210984059Swpaul 2110241438Syongari#define BGE_APE_GPIO_MSG 0x0008 2111241438Syongari#define BGE_APE_EVENT 0x000C 2112241438Syongari#define BGE_APE_LOCK_REQ 0x002C 2113241438Syongari#define BGE_APE_LOCK_GRANT 0x004C 2114241438Syongari 2115241438Syongari#define BGE_APE_GPIO_MSG_SHIFT 4 2116241438Syongari 2117241438Syongari#define BGE_APE_EVENT_1 0x00000001 2118241438Syongari 2119241438Syongari#define BGE_APE_LOCK_REQ_DRIVER0 0x00001000 2120241438Syongari 2121241438Syongari#define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000 2122241438Syongari 2123241438Syongari/* APE Shared Memory block (writable by APE only) */ 2124241438Syongari#define BGE_APE_SEG_SIG 0x4000 2125241438Syongari#define BGE_APE_FW_STATUS 0x400C 2126241438Syongari#define BGE_APE_FW_FEATURES 0x4010 2127241438Syongari#define BGE_APE_FW_BEHAVIOR 0x4014 2128241438Syongari#define BGE_APE_FW_VERSION 0x4018 2129241438Syongari#define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024 2130241438Syongari#define BGE_APE_FW_HEARTBEAT 0x4028 2131241438Syongari#define BGE_APE_FW_ERROR_FLAGS 0x4074 2132241438Syongari 2133241438Syongari#define BGE_APE_SEG_SIG_MAGIC 0x41504521 2134241438Syongari 2135241438Syongari#define BGE_APE_FW_STATUS_READY 0x00000100 2136241438Syongari 2137241438Syongari#define BGE_APE_FW_FEATURE_DASH 0x00000001 2138241438Syongari#define BGE_APE_FW_FEATURE_NCSI 0x00000002 2139241438Syongari 2140241438Syongari#define BGE_APE_FW_VERSION_MAJMSK 0xFF000000 2141241438Syongari#define BGE_APE_FW_VERSION_MAJSFT 24 2142241438Syongari#define BGE_APE_FW_VERSION_MINMSK 0x00FF0000 2143241438Syongari#define BGE_APE_FW_VERSION_MINSFT 16 2144241438Syongari#define BGE_APE_FW_VERSION_REVMSK 0x0000FF00 2145241438Syongari#define BGE_APE_FW_VERSION_REVSFT 8 2146241438Syongari#define BGE_APE_FW_VERSION_BLDMSK 0x000000FF 2147241438Syongari 2148241438Syongari/* Host Shared Memory block (writable by host only) */ 2149241438Syongari#define BGE_APE_HOST_SEG_SIG 0x4200 2150241438Syongari#define BGE_APE_HOST_SEG_LEN 0x4204 2151241438Syongari#define BGE_APE_HOST_INIT_COUNT 0x4208 2152241438Syongari#define BGE_APE_HOST_DRIVER_ID 0x420C 2153241438Syongari#define BGE_APE_HOST_BEHAVIOR 0x4210 2154241438Syongari#define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 2155241438Syongari#define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 2156241438Syongari#define BGE_APE_HOST_DRVR_STATE 0x421C 2157241438Syongari#define BGE_APE_HOST_WOL_SPEED 0x4224 2158241438Syongari 2159241438Syongari#define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354 2160241438Syongari 2161241438Syongari#define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020 2162241438Syongari 2163241438Syongari#define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000 2164241438Syongari#define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2165241438Syongari (BGE_APE_HOST_DRIVER_ID_FBSD | \ 2166241438Syongari ((maj) & 0xffd) << 16 | ((min) & 0xff) << 8) 2167241438Syongari 2168241438Syongari#define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2169241438Syongari 2170241438Syongari#define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0 2171241438Syongari#define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000 2172241438Syongari 2173241438Syongari#define BGE_APE_HOST_DRVR_STATE_START 0x00000001 2174241438Syongari#define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2175241438Syongari#define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 2176241438Syongari#define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004 2177241438Syongari 2178241438Syongari#define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 2179241438Syongari 2180241438Syongari#define BGE_APE_EVENT_STATUS 0x4300 2181241438Syongari 2182241438Syongari#define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2183241438Syongari#define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2184241438Syongari#define BGE_APE_EVENT_STATUS_STATE_START 0x00010000 2185241438Syongari#define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2186241438Syongari#define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000 2187241438Syongari#define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2188241438Syongari#define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2189241438Syongari 2190241438Syongari#define BGE_APE_DEBUG_LOG 0x4E00 2191241438Syongari#define BGE_APE_DEBUG_LOG_LEN 0x0100 2192241438Syongari 2193241438Syongari#define BGE_APE_PER_LOCK_REQ 0x8400 2194241438Syongari#define BGE_APE_PER_LOCK_GRANT 0x8420 2195241438Syongari 2196241438Syongari#define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000 2197241438Syongari#define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002 2198241438Syongari#define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004 2199241438Syongari#define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008 2200241438Syongari 2201241438Syongari#define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000 2202241438Syongari#define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002 2203241438Syongari#define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004 2204241438Syongari#define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008 2205241438Syongari 2206241438Syongari/* APE Mutex Resources */ 2207241438Syongari#define BGE_APE_LOCK_PHY0 0 2208241438Syongari#define BGE_APE_LOCK_GRC 1 2209241438Syongari#define BGE_APE_LOCK_PHY1 2 2210241438Syongari#define BGE_APE_LOCK_PHY2 3 2211241438Syongari#define BGE_APE_LOCK_MEM 4 2212241438Syongari#define BGE_APE_LOCK_PHY3 5 2213241438Syongari#define BGE_APE_LOCK_GPIO 7 2214241438Syongari 2215166676Sjkim#define BGE_MEMWIN_READ(sc, x, val) \ 221684059Swpaul do { \ 221784059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 221884059Swpaul (0xFFFF0000 & x), 4); \ 221984059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 222084059Swpaul } while(0) 222184059Swpaul 2222166676Sjkim#define BGE_MEMWIN_WRITE(sc, x, val) \ 222384059Swpaul do { \ 222484059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 222584059Swpaul (0xFFFF0000 & x), 4); \ 222684059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 222784059Swpaul } while(0) 222884059Swpaul 222984059Swpaul/* 2230161847Sdavidch * This magic number is written to the firmware mailbox at 0xb50 2231161847Sdavidch * before a software reset is issued. After the internal firmware 2232199661Syongari * has completed its initialization it will write the opposite of 2233226814Syongari * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location, 2234226814Syongari * allowing the driver to synchronize with the firmware. 223584059Swpaul */ 2236226814Syongari#define BGE_SRAM_FW_MB_MAGIC 0x4B657654 223784059Swpaul 223884059Swpaultypedef struct { 2239159395Sglebius uint32_t bge_addr_hi; 2240159395Sglebius uint32_t bge_addr_lo; 224184059Swpaul} bge_hostaddr; 2242118026Swpaul 2243166676Sjkim#define BGE_HOSTADDR(x, y) \ 2244115200Sps do { \ 2245159395Sglebius (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 2246159395Sglebius (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 2247115200Sps } while(0) 224884059Swpaul 2249166676Sjkim#define BGE_ADDR_LO(y) \ 2250159395Sglebius ((uint64_t) (y) & 0xFFFFFFFF) 2251166676Sjkim#define BGE_ADDR_HI(y) \ 2252159395Sglebius ((uint64_t) (y) >> 32) 2253118026Swpaul 225484059Swpaul/* Ring control block structure */ 225584059Swpaulstruct bge_rcb { 225684059Swpaul bge_hostaddr bge_hostaddr; 2257159395Sglebius uint32_t bge_maxlen_flags; 2258159395Sglebius uint32_t bge_nicaddr; 225984059Swpaul}; 2260153437Syongari 2261153437Syongari#define RCB_WRITE_4(sc, rcb, offset, val) \ 2262183896Smarius bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 2263166676Sjkim#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 226484059Swpaul 2265166676Sjkim#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2266166676Sjkim#define BGE_RCB_FLAG_RING_DISABLED 0x0002 226784059Swpaul 226884059Swpaulstruct bge_tx_bd { 226984059Swpaul bge_hostaddr bge_addr; 2270153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2271159395Sglebius uint16_t bge_flags; 2272159395Sglebius uint16_t bge_len; 2273159395Sglebius uint16_t bge_vlan_tag; 2274199671Syongari uint16_t bge_mss; 2275153437Syongari#else 2276159395Sglebius uint16_t bge_len; 2277159395Sglebius uint16_t bge_flags; 2278199671Syongari uint16_t bge_mss; 2279159395Sglebius uint16_t bge_vlan_tag; 2280153437Syongari#endif 228184059Swpaul}; 228284059Swpaul 2283166676Sjkim#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2284166676Sjkim#define BGE_TXBDFLAG_IP_CSUM 0x0002 2285166676Sjkim#define BGE_TXBDFLAG_END 0x0004 2286166676Sjkim#define BGE_TXBDFLAG_IP_FRAG 0x0008 2287214428Syongari#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ 2288166676Sjkim#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2289214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */ 2290214428Syongari#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ 2291166676Sjkim#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2292166676Sjkim#define BGE_TXBDFLAG_COAL_NOW 0x0080 2293166676Sjkim#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2294166676Sjkim#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2295214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */ 2296214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */ 2297166676Sjkim#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2298214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */ 2299214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */ 2300214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */ 2301166676Sjkim#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2302166676Sjkim#define BGE_TXBDFLAG_NO_CRC 0x8000 230384059Swpaul 2304214428Syongari#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2305214428Syongari/* Bits [1:0] of the MSS header length. */ 2306214428Syongari#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2307214428Syongari 2308166676Sjkim#define BGE_NIC_TXRING_ADDR(ringno, size) \ 230984059Swpaul BGE_SEND_RING_1_TO_4 + \ 231084059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 231184059Swpaul 231284059Swpaulstruct bge_rx_bd { 231384059Swpaul bge_hostaddr bge_addr; 2314153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2315159395Sglebius uint16_t bge_len; 2316159395Sglebius uint16_t bge_idx; 2317159395Sglebius uint16_t bge_flags; 2318159395Sglebius uint16_t bge_type; 2319159395Sglebius uint16_t bge_tcp_udp_csum; 2320159395Sglebius uint16_t bge_ip_csum; 2321159395Sglebius uint16_t bge_vlan_tag; 2322159395Sglebius uint16_t bge_error_flag; 2323153437Syongari#else 2324159395Sglebius uint16_t bge_idx; 2325159395Sglebius uint16_t bge_len; 2326159395Sglebius uint16_t bge_type; 2327159395Sglebius uint16_t bge_flags; 2328159395Sglebius uint16_t bge_ip_csum; 2329159395Sglebius uint16_t bge_tcp_udp_csum; 2330159395Sglebius uint16_t bge_error_flag; 2331159395Sglebius uint16_t bge_vlan_tag; 2332153437Syongari#endif 2333159395Sglebius uint32_t bge_rsvd; 2334159395Sglebius uint32_t bge_opaque; 233584059Swpaul}; 233684059Swpaul 2337153239Sglebiusstruct bge_extrx_bd { 2338153239Sglebius bge_hostaddr bge_addr1; 2339153239Sglebius bge_hostaddr bge_addr2; 2340153239Sglebius bge_hostaddr bge_addr3; 2341153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2342159395Sglebius uint16_t bge_len2; 2343159395Sglebius uint16_t bge_len1; 2344159395Sglebius uint16_t bge_rsvd1; 2345159395Sglebius uint16_t bge_len3; 2346153437Syongari#else 2347159395Sglebius uint16_t bge_len1; 2348159395Sglebius uint16_t bge_len2; 2349159395Sglebius uint16_t bge_len3; 2350159395Sglebius uint16_t bge_rsvd1; 2351153437Syongari#endif 2352153239Sglebius bge_hostaddr bge_addr0; 2353153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2354159395Sglebius uint16_t bge_len0; 2355159395Sglebius uint16_t bge_idx; 2356159395Sglebius uint16_t bge_flags; 2357159395Sglebius uint16_t bge_type; 2358159395Sglebius uint16_t bge_tcp_udp_csum; 2359159395Sglebius uint16_t bge_ip_csum; 2360159395Sglebius uint16_t bge_vlan_tag; 2361159395Sglebius uint16_t bge_error_flag; 2362153437Syongari#else 2363159395Sglebius uint16_t bge_idx; 2364159395Sglebius uint16_t bge_len0; 2365159395Sglebius uint16_t bge_type; 2366159395Sglebius uint16_t bge_flags; 2367159395Sglebius uint16_t bge_ip_csum; 2368159395Sglebius uint16_t bge_tcp_udp_csum; 2369159395Sglebius uint16_t bge_error_flag; 2370159395Sglebius uint16_t bge_vlan_tag; 2371153437Syongari#endif 2372159395Sglebius uint32_t bge_rsvd0; 2373159395Sglebius uint32_t bge_opaque; 2374153239Sglebius}; 2375153239Sglebius 2376166676Sjkim#define BGE_RXBDFLAG_END 0x0004 2377166676Sjkim#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2378166676Sjkim#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2379166676Sjkim#define BGE_RXBDFLAG_ERROR 0x0400 2380166676Sjkim#define BGE_RXBDFLAG_MINI_RING 0x0800 2381166676Sjkim#define BGE_RXBDFLAG_IP_CSUM 0x1000 2382166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2383166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2384214428Syongari#define BGE_RXBDFLAG_IPV6 0x8000 238584059Swpaul 2386166676Sjkim#define BGE_RXERRFLAG_BAD_CRC 0x0001 2387166676Sjkim#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2388166676Sjkim#define BGE_RXERRFLAG_LINK_LOST 0x0004 2389166676Sjkim#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2390166676Sjkim#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2391166676Sjkim#define BGE_RXERRFLAG_RUNT 0x0020 2392166676Sjkim#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2393166676Sjkim#define BGE_RXERRFLAG_GIANT 0x0080 2394214428Syongari#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 239584059Swpaul 239684059Swpaulstruct bge_sts_idx { 2397153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2398159395Sglebius uint16_t bge_rx_prod_idx; 2399159395Sglebius uint16_t bge_tx_cons_idx; 2400153437Syongari#else 2401159395Sglebius uint16_t bge_tx_cons_idx; 2402159395Sglebius uint16_t bge_rx_prod_idx; 2403153437Syongari#endif 240484059Swpaul}; 240584059Swpaul 240684059Swpaulstruct bge_status_block { 2407159395Sglebius uint32_t bge_status; 2408214428Syongari uint32_t bge_status_tag; 2409153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2410159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 2411159395Sglebius uint16_t bge_rx_std_cons_idx; 2412159395Sglebius uint16_t bge_rx_mini_cons_idx; 2413159395Sglebius uint16_t bge_rsvd1; 2414153437Syongari#else 2415159395Sglebius uint16_t bge_rx_std_cons_idx; 2416159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 2417159395Sglebius uint16_t bge_rsvd1; 2418159395Sglebius uint16_t bge_rx_mini_cons_idx; 2419153437Syongari#endif 242084059Swpaul struct bge_sts_idx bge_idx[16]; 242184059Swpaul}; 242284059Swpaul 2423166676Sjkim#define BGE_STATFLAG_UPDATED 0x00000001 2424166676Sjkim#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2425166676Sjkim#define BGE_STATFLAG_ERROR 0x00000004 242684059Swpaul 242784059Swpaul 242884059Swpaul/* 242984059Swpaul * Broadcom Vendor ID 243084059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 243184059Swpaul * even though they're now manufactured by Broadcom) 243284059Swpaul */ 2433166676Sjkim#define BCOM_VENDORID 0x14E4 2434166676Sjkim#define BCOM_DEVICEID_BCM5700 0x1644 2435166676Sjkim#define BCOM_DEVICEID_BCM5701 0x1645 2436166676Sjkim#define BCOM_DEVICEID_BCM5702 0x1646 2437166676Sjkim#define BCOM_DEVICEID_BCM5702X 0x16A6 2438166676Sjkim#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2439166676Sjkim#define BCOM_DEVICEID_BCM5703 0x1647 2440166676Sjkim#define BCOM_DEVICEID_BCM5703X 0x16A7 2441166676Sjkim#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2442166676Sjkim#define BCOM_DEVICEID_BCM5704C 0x1648 2443166676Sjkim#define BCOM_DEVICEID_BCM5704S 0x16A8 2444166676Sjkim#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2445166676Sjkim#define BCOM_DEVICEID_BCM5705 0x1653 2446166676Sjkim#define BCOM_DEVICEID_BCM5705K 0x1654 2447166676Sjkim#define BCOM_DEVICEID_BCM5705F 0x166E 2448166676Sjkim#define BCOM_DEVICEID_BCM5705M 0x165D 2449166676Sjkim#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2450166676Sjkim#define BCOM_DEVICEID_BCM5714C 0x1668 2451166676Sjkim#define BCOM_DEVICEID_BCM5714S 0x1669 2452166676Sjkim#define BCOM_DEVICEID_BCM5715 0x1678 2453166676Sjkim#define BCOM_DEVICEID_BCM5715S 0x1679 2454214428Syongari#define BCOM_DEVICEID_BCM5717 0x1655 2455214428Syongari#define BCOM_DEVICEID_BCM5718 0x1656 2456221818Syongari#define BCOM_DEVICEID_BCM5719 0x1657 2457226871Syongari#define BCOM_DEVICEID_BCM5720_PP 0x1658 /* Not released to public. */ 2458226871Syongari#define BCOM_DEVICEID_BCM5720 0x165F 2459166676Sjkim#define BCOM_DEVICEID_BCM5721 0x1659 2460176883Sjhb#define BCOM_DEVICEID_BCM5722 0x165A 2461197832Sstas#define BCOM_DEVICEID_BCM5723 0x165B 2462253483Syongari#define BCOM_DEVICEID_BCM5725 0x1643 2463253483Syongari#define BCOM_DEVICEID_BCM5727 0x16F3 2464166676Sjkim#define BCOM_DEVICEID_BCM5750 0x1676 2465166676Sjkim#define BCOM_DEVICEID_BCM5750M 0x167C 2466166676Sjkim#define BCOM_DEVICEID_BCM5751 0x1677 2467166676Sjkim#define BCOM_DEVICEID_BCM5751F 0x167E 2468166676Sjkim#define BCOM_DEVICEID_BCM5751M 0x167D 2469166676Sjkim#define BCOM_DEVICEID_BCM5752 0x1600 2470166676Sjkim#define BCOM_DEVICEID_BCM5752M 0x1601 2471166676Sjkim#define BCOM_DEVICEID_BCM5753 0x16F7 2472166676Sjkim#define BCOM_DEVICEID_BCM5753F 0x16FE 2473166676Sjkim#define BCOM_DEVICEID_BCM5753M 0x16FD 2474166676Sjkim#define BCOM_DEVICEID_BCM5754 0x167A 2475166676Sjkim#define BCOM_DEVICEID_BCM5754M 0x1672 2476166676Sjkim#define BCOM_DEVICEID_BCM5755 0x167B 2477166676Sjkim#define BCOM_DEVICEID_BCM5755M 0x1673 2478202268Sdelphij#define BCOM_DEVICEID_BCM5756 0x1674 2479197832Sstas#define BCOM_DEVICEID_BCM5761 0x1681 2480197832Sstas#define BCOM_DEVICEID_BCM5761E 0x1680 2481197832Sstas#define BCOM_DEVICEID_BCM5761S 0x1688 2482197832Sstas#define BCOM_DEVICEID_BCM5761SE 0x1689 2483253483Syongari#define BCOM_DEVICEID_BCM5762 0x1687 2484197832Sstas#define BCOM_DEVICEID_BCM5764 0x1684 2485166676Sjkim#define BCOM_DEVICEID_BCM5780 0x166A 2486166676Sjkim#define BCOM_DEVICEID_BCM5780S 0x166B 2487166676Sjkim#define BCOM_DEVICEID_BCM5781 0x16DD 2488166676Sjkim#define BCOM_DEVICEID_BCM5782 0x1696 2489197832Sstas#define BCOM_DEVICEID_BCM5784 0x1698 2490197832Sstas#define BCOM_DEVICEID_BCM5785F 0x16a0 2491197832Sstas#define BCOM_DEVICEID_BCM5785G 0x1699 2492166676Sjkim#define BCOM_DEVICEID_BCM5786 0x169A 2493166676Sjkim#define BCOM_DEVICEID_BCM5787 0x169B 2494166676Sjkim#define BCOM_DEVICEID_BCM5787M 0x1693 2495197832Sstas#define BCOM_DEVICEID_BCM5787F 0x167f 2496166676Sjkim#define BCOM_DEVICEID_BCM5788 0x169C 2497166676Sjkim#define BCOM_DEVICEID_BCM5789 0x169D 2498166676Sjkim#define BCOM_DEVICEID_BCM5901 0x170D 2499166676Sjkim#define BCOM_DEVICEID_BCM5901A2 0x170E 2500166676Sjkim#define BCOM_DEVICEID_BCM5903M 0x16FF 2501178667Sjhb#define BCOM_DEVICEID_BCM5906 0x1712 2502178667Sjhb#define BCOM_DEVICEID_BCM5906M 0x1713 2503197832Sstas#define BCOM_DEVICEID_BCM57760 0x1690 2504221445Syongari#define BCOM_DEVICEID_BCM57761 0x16B0 2505243686Syongari#define BCOM_DEVICEID_BCM57762 0x1682 2506258959Syongari#define BCOM_DEVICEID_BCM57764 0x1642 2507221445Syongari#define BCOM_DEVICEID_BCM57765 0x16B4 2508243686Syongari#define BCOM_DEVICEID_BCM57766 0x1686 2509258959Syongari#define BCOM_DEVICEID_BCM57767 0x1683 2510197832Sstas#define BCOM_DEVICEID_BCM57780 0x1692 2511221445Syongari#define BCOM_DEVICEID_BCM57781 0x16B1 2512258959Syongari#define BCOM_DEVICEID_BCM57782 0x16B7 2513221445Syongari#define BCOM_DEVICEID_BCM57785 0x16B5 2514258959Syongari#define BCOM_DEVICEID_BCM57786 0x16B3 2515258959Syongari#define BCOM_DEVICEID_BCM57787 0x1641 2516197832Sstas#define BCOM_DEVICEID_BCM57788 0x1691 2517197832Sstas#define BCOM_DEVICEID_BCM57790 0x1694 2518221445Syongari#define BCOM_DEVICEID_BCM57791 0x16B2 2519221445Syongari#define BCOM_DEVICEID_BCM57795 0x16B6 252084059Swpaul 252184059Swpaul/* 252284059Swpaul * Alteon AceNIC PCI vendor/device ID. 252384059Swpaul */ 2524166676Sjkim#define ALTEON_VENDORID 0x12AE 2525166676Sjkim#define ALTEON_DEVICEID_ACENIC 0x0001 2526166676Sjkim#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2527166676Sjkim#define ALTEON_DEVICEID_BCM5700 0x0003 2528166676Sjkim#define ALTEON_DEVICEID_BCM5701 0x0004 252984059Swpaul 253084059Swpaul/* 2531162982Sglebius * 3Com 3c996 PCI vendor/device ID. 253284059Swpaul */ 2533166676Sjkim#define TC_VENDORID 0x10B7 2534166676Sjkim#define TC_DEVICEID_3C996 0x0003 253584059Swpaul 253684059Swpaul/* 253784059Swpaul * SysKonnect PCI vendor ID 253884059Swpaul */ 2539166676Sjkim#define SK_VENDORID 0x1148 2540166676Sjkim#define SK_DEVICEID_ALTIMA 0x4400 2541166676Sjkim#define SK_SUBSYSID_9D21 0x4421 2542166676Sjkim#define SK_SUBSYSID_9D41 0x4441 254384059Swpaul 254484059Swpaul/* 254589835Sjdp * Altima PCI vendor/device ID. 254689835Sjdp */ 2547166676Sjkim#define ALTIMA_VENDORID 0x173b 2548166676Sjkim#define ALTIMA_DEVICE_AC1000 0x03e8 2549166676Sjkim#define ALTIMA_DEVICE_AC1002 0x03e9 2550166676Sjkim#define ALTIMA_DEVICE_AC9100 0x03ea 255189835Sjdp 255289835Sjdp/* 2553119157Sambrisko * Dell PCI vendor ID 2554119157Sambrisko */ 2555119157Sambrisko 2556166676Sjkim#define DELL_VENDORID 0x1028 2557119157Sambrisko 2558119157Sambrisko/* 2559159637Sglebius * Apple PCI vendor ID. 2560159637Sglebius */ 2561166676Sjkim#define APPLE_VENDORID 0x106b 2562166676Sjkim#define APPLE_DEVICE_BCM5701 0x1645 2563159637Sglebius 2564159637Sglebius/* 2565169152Smarius * Sun PCI vendor ID 2566169152Smarius */ 2567169152Smarius#define SUN_VENDORID 0x108e 2568169152Smarius 2569169152Smarius/* 2570197832Sstas * Fujitsu vendor/device IDs 2571197832Sstas */ 2572197832Sstas#define FJTSU_VENDORID 0x10cf 2573197832Sstas#define FJTSU_DEVICEID_PW008GE5 0x11a1 2574197832Sstas#define FJTSU_DEVICEID_PW008GE4 0x11a2 2575197832Sstas#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */ 2576197832Sstas 2577197832Sstas/* 257884059Swpaul * Offset of MAC address inside EEPROM. 257984059Swpaul */ 2580166676Sjkim#define BGE_EE_MAC_OFFSET 0x7C 2581178667Sjhb#define BGE_EE_MAC_OFFSET_5906 0x10 2582166676Sjkim#define BGE_EE_HWCFG_OFFSET 0xC8 258384059Swpaul 2584166676Sjkim#define BGE_HWCFG_VOLTAGE 0x00000003 2585166676Sjkim#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2586166676Sjkim#define BGE_HWCFG_MEDIA 0x00000030 2587166676Sjkim#define BGE_HWCFG_ASF 0x00000080 258893751Swpaul 2589166676Sjkim#define BGE_VOLTAGE_1POINT3 0x00000000 2590166676Sjkim#define BGE_VOLTAGE_1POINT8 0x00000001 259193751Swpaul 2592166676Sjkim#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2593166676Sjkim#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2594166676Sjkim#define BGE_PHYLEDMODE_SINGLELED 0x00000008 259593751Swpaul 2596166676Sjkim#define BGE_MEDIA_UNSPEC 0x00000000 2597166676Sjkim#define BGE_MEDIA_COPPER 0x00000010 2598166676Sjkim#define BGE_MEDIA_FIBER 0x00000020 259993751Swpaul 2600166676Sjkim#define BGE_TICKS_PER_SEC 1000000 260184059Swpaul 260284059Swpaul/* 260384059Swpaul * Ring size constants. 260484059Swpaul */ 2605166676Sjkim#define BGE_EVENT_RING_CNT 256 2606166676Sjkim#define BGE_CMD_RING_CNT 64 2607166676Sjkim#define BGE_STD_RX_RING_CNT 512 2608166676Sjkim#define BGE_JUMBO_RX_RING_CNT 256 2609166676Sjkim#define BGE_MINI_RX_RING_CNT 1024 2610166676Sjkim#define BGE_RETURN_RING_CNT 1024 261184059Swpaul 2612117659Swpaul/* 5705 has smaller return ring size */ 2613117659Swpaul 2614166676Sjkim#define BGE_RETURN_RING_CNT_5705 512 2615117659Swpaul 261684059Swpaul/* 261784059Swpaul * Possible TX ring sizes. 261884059Swpaul */ 2619166676Sjkim#define BGE_TX_RING_CNT_128 128 2620166676Sjkim#define BGE_TX_RING_BASE_128 0x3800 262184059Swpaul 2622166676Sjkim#define BGE_TX_RING_CNT_256 256 2623166676Sjkim#define BGE_TX_RING_BASE_256 0x3000 262484059Swpaul 2625166676Sjkim#define BGE_TX_RING_CNT_512 512 2626166676Sjkim#define BGE_TX_RING_BASE_512 0x2000 262784059Swpaul 2628166676Sjkim#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2629166676Sjkim#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 263084059Swpaul 263184059Swpaul/* 263284059Swpaul * Tigon III statistics counters. 263384059Swpaul */ 2634117659Swpaul/* Statistics maintained MAC Receive block. */ 2635117659Swpaulstruct bge_rx_mac_stats { 263684059Swpaul bge_hostaddr ifHCInOctets; 263784059Swpaul bge_hostaddr Reserved1; 263884059Swpaul bge_hostaddr etherStatsFragments; 263984059Swpaul bge_hostaddr ifHCInUcastPkts; 264084059Swpaul bge_hostaddr ifHCInMulticastPkts; 264184059Swpaul bge_hostaddr ifHCInBroadcastPkts; 264284059Swpaul bge_hostaddr dot3StatsFCSErrors; 264384059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 264484059Swpaul bge_hostaddr xonPauseFramesReceived; 264584059Swpaul bge_hostaddr xoffPauseFramesReceived; 264684059Swpaul bge_hostaddr macControlFramesReceived; 264784059Swpaul bge_hostaddr xoffStateEntered; 264884059Swpaul bge_hostaddr dot3StatsFramesTooLong; 264984059Swpaul bge_hostaddr etherStatsJabbers; 265084059Swpaul bge_hostaddr etherStatsUndersizePkts; 265184059Swpaul bge_hostaddr inRangeLengthError; 265284059Swpaul bge_hostaddr outRangeLengthError; 265384059Swpaul bge_hostaddr etherStatsPkts64Octets; 265484059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 265584059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 265684059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 265784059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 265884059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 265984059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 266084059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 266184059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 266284059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2663117659Swpaul}; 266484059Swpaul 266584059Swpaul 2666117659Swpaul/* Statistics maintained MAC Transmit block. */ 2667117659Swpaulstruct bge_tx_mac_stats { 266884059Swpaul bge_hostaddr ifHCOutOctets; 266984059Swpaul bge_hostaddr Reserved2; 267084059Swpaul bge_hostaddr etherStatsCollisions; 267184059Swpaul bge_hostaddr outXonSent; 267284059Swpaul bge_hostaddr outXoffSent; 267384059Swpaul bge_hostaddr flowControlDone; 267484059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 267584059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 267684059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 267784059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 267884059Swpaul bge_hostaddr Reserved3; 267984059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 268084059Swpaul bge_hostaddr dot3StatsLateCollisions; 268184059Swpaul bge_hostaddr dot3Collided2Times; 268284059Swpaul bge_hostaddr dot3Collided3Times; 268384059Swpaul bge_hostaddr dot3Collided4Times; 268484059Swpaul bge_hostaddr dot3Collided5Times; 268584059Swpaul bge_hostaddr dot3Collided6Times; 268684059Swpaul bge_hostaddr dot3Collided7Times; 268784059Swpaul bge_hostaddr dot3Collided8Times; 268884059Swpaul bge_hostaddr dot3Collided9Times; 268984059Swpaul bge_hostaddr dot3Collided10Times; 269084059Swpaul bge_hostaddr dot3Collided11Times; 269184059Swpaul bge_hostaddr dot3Collided12Times; 269284059Swpaul bge_hostaddr dot3Collided13Times; 269384059Swpaul bge_hostaddr dot3Collided14Times; 269484059Swpaul bge_hostaddr dot3Collided15Times; 269584059Swpaul bge_hostaddr ifHCOutUcastPkts; 269684059Swpaul bge_hostaddr ifHCOutMulticastPkts; 269784059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 269884059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 269984059Swpaul bge_hostaddr ifOutDiscards; 270084059Swpaul bge_hostaddr ifOutErrors; 2701117659Swpaul}; 270284059Swpaul 2703117659Swpaul/* Stats counters access through registers */ 2704213283Syongaristruct bge_mac_stats { 2705213283Syongari /* TX MAC statistics */ 2706213283Syongari uint64_t ifHCOutOctets; 2707213283Syongari uint64_t Reserved0; 2708213283Syongari uint64_t etherStatsCollisions; 2709213283Syongari uint64_t outXonSent; 2710213283Syongari uint64_t outXoffSent; 2711213283Syongari uint64_t Reserved1; 2712213283Syongari uint64_t dot3StatsInternalMacTransmitErrors; 2713213283Syongari uint64_t dot3StatsSingleCollisionFrames; 2714213283Syongari uint64_t dot3StatsMultipleCollisionFrames; 2715213283Syongari uint64_t dot3StatsDeferredTransmissions; 2716213283Syongari uint64_t Reserved2; 2717213283Syongari uint64_t dot3StatsExcessiveCollisions; 2718213283Syongari uint64_t dot3StatsLateCollisions; 2719213283Syongari uint64_t Reserved3[14]; 2720213283Syongari uint64_t ifHCOutUcastPkts; 2721213283Syongari uint64_t ifHCOutMulticastPkts; 2722213283Syongari uint64_t ifHCOutBroadcastPkts; 2723213283Syongari uint64_t Reserved4[2]; 2724213283Syongari /* RX MAC statistics */ 2725213283Syongari uint64_t ifHCInOctets; 2726213283Syongari uint64_t Reserved5; 2727213283Syongari uint64_t etherStatsFragments; 2728213283Syongari uint64_t ifHCInUcastPkts; 2729213283Syongari uint64_t ifHCInMulticastPkts; 2730213283Syongari uint64_t ifHCInBroadcastPkts; 2731213283Syongari uint64_t dot3StatsFCSErrors; 2732213283Syongari uint64_t dot3StatsAlignmentErrors; 2733213283Syongari uint64_t xonPauseFramesReceived; 2734213283Syongari uint64_t xoffPauseFramesReceived; 2735213283Syongari uint64_t macControlFramesReceived; 2736213283Syongari uint64_t xoffStateEntered; 2737213283Syongari uint64_t dot3StatsFramesTooLong; 2738213283Syongari uint64_t etherStatsJabbers; 2739213283Syongari uint64_t etherStatsUndersizePkts; 2740213283Syongari /* Receive List Placement control */ 2741213283Syongari uint64_t FramesDroppedDueToFilters; 2742213283Syongari uint64_t DmaWriteQueueFull; 2743213283Syongari uint64_t DmaWriteHighPriQueueFull; 2744213283Syongari uint64_t NoMoreRxBDs; 2745213283Syongari uint64_t InputDiscards; 2746213283Syongari uint64_t InputErrors; 2747213283Syongari uint64_t RecvThresholdHit; 2748117659Swpaul}; 2749117659Swpaul 2750117659Swpaulstruct bge_stats { 2751159395Sglebius uint8_t Reserved0[256]; 2752117659Swpaul 2753117659Swpaul /* Statistics maintained by Receive MAC. */ 2754117659Swpaul struct bge_rx_mac_stats rxstats; 2755117659Swpaul 2756117659Swpaul bge_hostaddr Unused1[37]; 2757117659Swpaul 2758117659Swpaul /* Statistics maintained by Transmit MAC. */ 2759117659Swpaul struct bge_tx_mac_stats txstats; 2760117659Swpaul 276184059Swpaul bge_hostaddr Unused2[31]; 276284059Swpaul 276384059Swpaul /* Statistics maintained by Receive List Placement. */ 276484059Swpaul bge_hostaddr COSIfHCInPkts[16]; 276584059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 276684059Swpaul bge_hostaddr nicDmaWriteQueueFull; 276784059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 276884059Swpaul bge_hostaddr nicNoMoreRxBDs; 276984059Swpaul bge_hostaddr ifInDiscards; 277084059Swpaul bge_hostaddr ifInErrors; 277184059Swpaul bge_hostaddr nicRecvThresholdHit; 277284059Swpaul 277384059Swpaul bge_hostaddr Unused3[9]; 277484059Swpaul 277584059Swpaul /* Statistics maintained by Send Data Initiator. */ 277684059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 277784059Swpaul bge_hostaddr nicDmaReadQueueFull; 277884059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 277984059Swpaul bge_hostaddr nicSendDataCompQueueFull; 278084059Swpaul 278184059Swpaul /* Statistics maintained by Host Coalescing. */ 278284059Swpaul bge_hostaddr nicRingSetSendProdIndex; 278384059Swpaul bge_hostaddr nicRingStatusUpdate; 278484059Swpaul bge_hostaddr nicInterrupts; 278584059Swpaul bge_hostaddr nicAvoidedInterrupts; 278684059Swpaul bge_hostaddr nicSendThresholdHit; 278784059Swpaul 2788159395Sglebius uint8_t Reserved4[320]; 278984059Swpaul}; 279084059Swpaul 279184059Swpaul/* 279284059Swpaul * Tigon general information block. This resides in host memory 279384059Swpaul * and contains the status counters, ring control blocks and 279484059Swpaul * producer pointers. 279584059Swpaul */ 279684059Swpaul 279784059Swpaulstruct bge_gib { 279884059Swpaul struct bge_stats bge_stats; 279984059Swpaul struct bge_rcb bge_tx_rcb[16]; 280084059Swpaul struct bge_rcb bge_std_rx_rcb; 280184059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 280284059Swpaul struct bge_rcb bge_mini_rx_rcb; 280384059Swpaul struct bge_rcb bge_return_rcb; 280484059Swpaul}; 280584059Swpaul 2806166676Sjkim#define BGE_FRAMELEN 1518 2807166676Sjkim#define BGE_MAX_FRAMELEN 1536 2808166676Sjkim#define BGE_JUMBO_FRAMELEN 9018 2809166676Sjkim#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2810166676Sjkim#define BGE_MIN_FRAMELEN 60 281184059Swpaul 281284059Swpaul/* 281384059Swpaul * Other utility macros. 281484059Swpaul */ 2815166676Sjkim#define BGE_INC(x, y) (x) = (x + 1) % y 281684059Swpaul 281784059Swpaul/* 2818241438Syongari * BAR0 MAC register access macros. The Tigon always uses memory mapped register 281984059Swpaul * accesses and all registers must be accessed with 32 bit operations. 282084059Swpaul */ 282184059Swpaul 2822166676Sjkim#define CSR_WRITE_4(sc, reg, val) \ 2823183896Smarius bus_write_4(sc->bge_res, reg, val) 282484059Swpaul 2825166676Sjkim#define CSR_READ_4(sc, reg) \ 2826183896Smarius bus_read_4(sc->bge_res, reg) 282784059Swpaul 2828166676Sjkim#define BGE_SETBIT(sc, reg, x) \ 2829106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2830166676Sjkim#define BGE_CLRBIT(sc, reg, x) \ 2831106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 283284059Swpaul 2833241438Syongari/* BAR2 APE register access macros. */ 2834241438Syongari#define APE_WRITE_4(sc, reg, val) \ 2835241438Syongari bus_write_4(sc->bge_res2, reg, val) 2836241438Syongari 2837241438Syongari#define APE_READ_4(sc, reg) \ 2838241438Syongari bus_read_4(sc->bge_res2, reg) 2839241438Syongari 2840241438Syongari#define APE_SETBIT(sc, reg, x) \ 2841241438Syongari APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x))) 2842241438Syongari#define APE_CLRBIT(sc, reg, x) \ 2843241438Syongari APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x))) 2844241438Syongari 2845166676Sjkim#define PCI_SETBIT(dev, reg, x, s) \ 2846106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2847166676Sjkim#define PCI_CLRBIT(dev, reg, x, s) \ 2848106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 284984059Swpaul 285084059Swpaul/* 2851208917Syongari * Memory management stuff. 285284059Swpaul */ 285384059Swpaul 2854166676Sjkim#define BGE_NSEG_JUMBO 4 2855199671Syongari#define BGE_NSEG_NEW 32 2856199671Syongari#define BGE_TSOSEG_SZ 4096 2857153239Sglebius 2858199670Syongari/* Maximum DMA address for controllers that have 40bit DMA address bug. */ 2859199670Syongari#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2860199670Syongari#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2861199670Syongari#else 2862199670Syongari#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2863199670Syongari#endif 2864199670Syongari 286584059Swpaul/* 286684059Swpaul * Ring structures. Most of these reside in host memory and we tell 286784059Swpaul * the NIC where they are via the ring control blocks. The exceptions 286884059Swpaul * are the tx and command rings, which live in NIC memory and which 286984059Swpaul * we access via the shared memory window. 287084059Swpaul */ 2871118026Swpaul 287284059Swpaulstruct bge_ring_data { 2873118026Swpaul struct bge_rx_bd *bge_rx_std_ring; 2874118026Swpaul bus_addr_t bge_rx_std_ring_paddr; 2875153239Sglebius struct bge_extrx_bd *bge_rx_jumbo_ring; 2876118026Swpaul bus_addr_t bge_rx_jumbo_ring_paddr; 2877118026Swpaul struct bge_rx_bd *bge_rx_return_ring; 2878118026Swpaul bus_addr_t bge_rx_return_ring_paddr; 2879118026Swpaul struct bge_tx_bd *bge_tx_ring; 2880118026Swpaul bus_addr_t bge_tx_ring_paddr; 2881118026Swpaul struct bge_status_block *bge_status_block; 2882118026Swpaul bus_addr_t bge_status_block_paddr; 2883118026Swpaul struct bge_stats *bge_stats; 2884118026Swpaul bus_addr_t bge_stats_paddr; 288584059Swpaul struct bge_gib bge_info; 288684059Swpaul}; 288784059Swpaul 2888166676Sjkim#define BGE_STD_RX_RING_SZ \ 2889118026Swpaul (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2890166676Sjkim#define BGE_JUMBO_RX_RING_SZ \ 2891153239Sglebius (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2892166676Sjkim#define BGE_TX_RING_SZ \ 2893118026Swpaul (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2894166676Sjkim#define BGE_RX_RTN_RING_SZ(x) \ 2895118026Swpaul (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2896118026Swpaul 2897166676Sjkim#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2898118026Swpaul 2899166676Sjkim#define BGE_STATS_SZ sizeof (struct bge_stats) 2900118026Swpaul 290184059Swpaul/* 290284059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 290384059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 290484059Swpaul * not the other way around. 290584059Swpaul */ 290684059Swpaulstruct bge_chain_data { 2907118026Swpaul bus_dma_tag_t bge_parent_tag; 2908212061Syongari bus_dma_tag_t bge_buffer_tag; 2909118026Swpaul bus_dma_tag_t bge_rx_std_ring_tag; 2910118026Swpaul bus_dma_tag_t bge_rx_jumbo_ring_tag; 2911118026Swpaul bus_dma_tag_t bge_rx_return_ring_tag; 2912118026Swpaul bus_dma_tag_t bge_tx_ring_tag; 2913118026Swpaul bus_dma_tag_t bge_status_tag; 2914118026Swpaul bus_dma_tag_t bge_stats_tag; 2915198927Syongari bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */ 2916198927Syongari bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */ 2917198927Syongari bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */ 2918118026Swpaul bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2919199011Syongari bus_dmamap_t bge_rx_std_sparemap; 2920118026Swpaul bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2921199011Syongari bus_dmamap_t bge_rx_jumbo_sparemap; 2922118026Swpaul bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2923118026Swpaul bus_dmamap_t bge_rx_std_ring_map; 2924118026Swpaul bus_dmamap_t bge_rx_jumbo_ring_map; 2925118026Swpaul bus_dmamap_t bge_tx_ring_map; 2926118026Swpaul bus_dmamap_t bge_rx_return_ring_map; 2927118026Swpaul bus_dmamap_t bge_status_map; 2928118026Swpaul bus_dmamap_t bge_stats_map; 292984059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 293084059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 293184059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2932208862Syongari int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2933208862Syongari int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 293484059Swpaul}; 293584059Swpaul 2936118026Swpaulstruct bge_dmamap_arg { 2937118026Swpaul bus_addr_t bge_busaddr; 2938118026Swpaul}; 2939118026Swpaul 2940166676Sjkim#define BGE_HWREV_TIGON 0x01 2941166676Sjkim#define BGE_HWREV_TIGON_II 0x02 2942166676Sjkim#define BGE_TIMEOUT 100000 2943166676Sjkim#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2944252404Syongari#define BGE_TX_TIMEOUT 5 294584059Swpaul 294684059Swpaulstruct bge_bcom_hack { 294784059Swpaul int reg; 294884059Swpaul int val; 294984059Swpaul}; 295084059Swpaul 2951166676Sjkim#define ASF_ENABLE 1 2952166676Sjkim#define ASF_NEW_HANDSHAKE 2 2953166676Sjkim#define ASF_STACKUP 4 2954162169Sambrisko 295584059Swpaulstruct bge_softc { 2956147256Sbrooks struct ifnet *bge_ifp; /* interface info */ 295784059Swpaul device_t bge_dev; 2958122497Ssam struct mtx bge_mtx; 295984059Swpaul device_t bge_miibus; 296084059Swpaul void *bge_intrhand; 296184059Swpaul struct resource *bge_irq; 2962241438Syongari struct resource *bge_res; /* MAC mapped I/O */ 2963241438Syongari struct resource *bge_res2; /* APE mapped I/O */ 296484059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 2965199664Syongari int bge_expcap; 2966241388Syongari int bge_expmrq; 2967199664Syongari int bge_msicap; 2968199664Syongari int bge_pcixcap; 2969161546Sglebius uint32_t bge_flags; 2970166676Sjkim#define BGE_FLAG_TBI 0x00000001 2971166676Sjkim#define BGE_FLAG_JUMBO 0x00000002 2972220368Syongari#define BGE_FLAG_JUMBO_STD 0x00000004 2973178996Smarius#define BGE_FLAG_EADDR 0x00000008 2974202293Syongari#define BGE_FLAG_MII_SERDES 0x00000010 2975213485Syongari#define BGE_FLAG_CPMU_PRESENT 0x00000020 2976214428Syongari#define BGE_FLAG_TAGGED_STATUS 0x00000040 2977241438Syongari#define BGE_FLAG_APE 0x00000080 2978166676Sjkim#define BGE_FLAG_MSI 0x00000100 2979166676Sjkim#define BGE_FLAG_PCIX 0x00000200 2980166676Sjkim#define BGE_FLAG_PCIE 0x00000400 2981199671Syongari#define BGE_FLAG_TSO 0x00000800 2982214428Syongari#define BGE_FLAG_TSO3 0x00001000 2983214428Syongari#define BGE_FLAG_JUMBO_FRAME 0x00002000 2984213464Syongari#define BGE_FLAG_5700_FAMILY 0x00010000 2985213464Syongari#define BGE_FLAG_5705_PLUS 0x00020000 2986213464Syongari#define BGE_FLAG_5714_FAMILY 0x00040000 2987213464Syongari#define BGE_FLAG_575X_PLUS 0x00080000 2988213464Syongari#define BGE_FLAG_5755_PLUS 0x00100000 2989213464Syongari#define BGE_FLAG_5788 0x00200000 2990214428Syongari#define BGE_FLAG_5717_PLUS 0x00400000 2991243686Syongari#define BGE_FLAG_57765_PLUS 0x00800000 2992213464Syongari#define BGE_FLAG_40BIT_BUG 0x01000000 2993213464Syongari#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2994213464Syongari#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2995214087Syongari#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2996226807Syongari#define BGE_FLAG_4K_RDMA_BUG 0x10000000 2997232848Syongari#define BGE_FLAG_MBOX_REORDER 0x20000000 2998253408Syongari#define BGE_FLAG_RDMA_BUG 0x40000000 2999241438Syongari uint32_t bge_mfw_flags; /* Management F/W flags */ 3000241438Syongari#define BGE_MFW_ON_RXCPU 0x00000001 3001241438Syongari#define BGE_MFW_ON_APE 0x00000002 3002241438Syongari#define BGE_MFW_TYPE_NCSI 0x00000004 3003241438Syongari#define BGE_MFW_TYPE_DASH 0x00000008 3004241438Syongari int bge_phy_ape_lock; 3005241438Syongari int bge_func_addr; 3006241983Syongari int bge_phy_addr; 3007213464Syongari uint32_t bge_phy_flags; 3008221468Syongari#define BGE_PHY_NO_WIRESPEED 0x00000001 3009213464Syongari#define BGE_PHY_ADC_BUG 0x00000002 3010213464Syongari#define BGE_PHY_5704_A0_BUG 0x00000004 3011213464Syongari#define BGE_PHY_JITTER_BUG 0x00000008 3012213464Syongari#define BGE_PHY_BER_BUG 0x00000010 3013213464Syongari#define BGE_PHY_ADJUST_TRIM 0x00000020 3014213464Syongari#define BGE_PHY_CRC_BUG 0x00000040 3015213464Syongari#define BGE_PHY_NO_3LED 0x00000080 3016159395Sglebius uint32_t bge_chipid; 3017197832Sstas uint32_t bge_asicrev; 3018197832Sstas uint32_t bge_chiprev; 3019162169Sambrisko uint8_t bge_asf_mode; 3020162169Sambrisko uint8_t bge_asf_count; 3021241388Syongari uint16_t bge_mps; 3022118026Swpaul struct bge_ring_data bge_ldata; /* rings */ 302384059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 3024159395Sglebius uint16_t bge_tx_saved_considx; 3025159395Sglebius uint16_t bge_rx_saved_considx; 3026159395Sglebius uint16_t bge_ev_saved_considx; 3027159395Sglebius uint16_t bge_return_ring_cnt; 3028159395Sglebius uint16_t bge_std; /* current std ring head */ 3029159395Sglebius uint16_t bge_jumbo; /* current jumo ring head */ 3030159395Sglebius uint32_t bge_stat_ticks; 3031159395Sglebius uint32_t bge_rx_coal_ticks; 3032159395Sglebius uint32_t bge_tx_coal_ticks; 3033159395Sglebius uint32_t bge_tx_prodidx; 3034159395Sglebius uint32_t bge_rx_max_coal_bds; 3035159395Sglebius uint32_t bge_tx_max_coal_bds; 3036213485Syongari uint32_t bge_mi_mode; 303784059Swpaul int bge_if_flags; 303884059Swpaul int bge_txcnt; 3039155180Soleg int bge_link; /* link state */ 3040155180Soleg int bge_link_evt; /* pending link event */ 3041164769Sglebius int bge_timer; 3042200264Syongari int bge_forced_collapse; 3043211596Syongari int bge_forced_udpcsum; 3044230337Syongari int bge_msi; 3045211596Syongari int bge_csum_features; 3046122497Ssam struct callout bge_stat_ch; 3047164780Sjkim uint32_t bge_rx_discards; 3048232850Syongari uint32_t bge_rx_inerrs; 3049232850Syongari uint32_t bge_rx_nobds; 3050164780Sjkim uint32_t bge_tx_discards; 3051164780Sjkim uint32_t bge_tx_collisions; 3052151553Sglebius#ifdef DEVICE_POLLING 3053151553Sglebius int rxcycles; 3054151553Sglebius#endif /* DEVICE_POLLING */ 3055213283Syongari struct bge_mac_stats bge_mac_stats; 3056199668Syongari struct task bge_intr_task; 3057199668Syongari struct taskqueue *bge_tq; 305884059Swpaul}; 3059122497Ssam 3060122497Ssam#define BGE_LOCK_INIT(_sc, _name) \ 3061122497Ssam mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 3062122497Ssam#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 3063122497Ssam#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 3064122497Ssam#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 3065122497Ssam#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 3066