1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17203158Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_desc.h" 23185377Ssam#include "ah_internal.h" 24185377Ssam 25185377Ssam#include "ar5416/ar5416.h" 26185377Ssam#include "ar5416/ar5416reg.h" 27185377Ssam#include "ar5416/ar5416desc.h" 28185377Ssam 29185377Ssam/* 30224512Sadrian * Get the receive filter. 31224512Sadrian */ 32224512Sadrianuint32_t 33224512Sadrianar5416GetRxFilter(struct ath_hal *ah) 34224512Sadrian{ 35224512Sadrian uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER); 36224512Sadrian uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR); 37224512Sadrian 38224512Sadrian if (phybits & AR_PHY_ERR_RADAR) 39224512Sadrian bits |= HAL_RX_FILTER_PHYRADAR; 40224512Sadrian if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 41224512Sadrian bits |= HAL_RX_FILTER_PHYERR; 42224512Sadrian return bits; 43224512Sadrian} 44224512Sadrian 45224512Sadrian/* 46224512Sadrian * Set the receive filter. 47224512Sadrian */ 48224512Sadrianvoid 49224512Sadrianar5416SetRxFilter(struct ath_hal *ah, u_int32_t bits) 50224512Sadrian{ 51224512Sadrian uint32_t phybits; 52224512Sadrian 53224512Sadrian OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff)); 54224512Sadrian phybits = 0; 55224512Sadrian if (bits & HAL_RX_FILTER_PHYRADAR) 56224512Sadrian phybits |= AR_PHY_ERR_RADAR; 57224512Sadrian if (bits & HAL_RX_FILTER_PHYERR) 58224512Sadrian phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 59224512Sadrian OS_REG_WRITE(ah, AR_PHY_ERR, phybits); 60224512Sadrian if (phybits) { 61224512Sadrian OS_REG_WRITE(ah, AR_RXCFG, 62224512Sadrian OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 63224512Sadrian } else { 64224512Sadrian OS_REG_WRITE(ah, AR_RXCFG, 65224512Sadrian OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA); 66224512Sadrian } 67224512Sadrian} 68224512Sadrian 69224512Sadrian/* 70234747Sadrian * Stop Receive at the DMA engine 71234747Sadrian */ 72234747SadrianHAL_BOOL 73234747Sadrianar5416StopDmaReceive(struct ath_hal *ah) 74234747Sadrian{ 75234747Sadrian HAL_BOOL status; 76234747Sadrian 77234747Sadrian OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP); 78234747Sadrian OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ 79234747Sadrian if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { 80234747Sadrian OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR); 81234747Sadrian#ifdef AH_DEBUG 82234747Sadrian ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n" 83234747Sadrian "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", 84234747Sadrian __func__, 85234747Sadrian OS_REG_READ(ah, AR_CR), 86234747Sadrian OS_REG_READ(ah, AR_DIAG_SW)); 87234747Sadrian#endif 88234747Sadrian status = AH_FALSE; 89234747Sadrian } else { 90234747Sadrian status = AH_TRUE; 91234747Sadrian } 92234747Sadrian 93234747Sadrian /* 94234747Sadrian * XXX Is this to flush whatever is in a FIFO somewhere? 95234747Sadrian * XXX If so, what should the correct behaviour should be? 96234747Sadrian */ 97234747Sadrian if (AR_SREV_9100(ah)) 98234747Sadrian OS_DELAY(3000); 99234747Sadrian 100234747Sadrian return (status); 101234747Sadrian} 102234747Sadrian 103234747Sadrian/* 104185377Ssam * Start receive at the PCU engine 105185377Ssam */ 106185377Ssamvoid 107185377Ssamar5416StartPcuReceive(struct ath_hal *ah) 108185377Ssam{ 109185377Ssam struct ath_hal_private *ahp = AH_PRIVATE(ah); 110185377Ssam 111185377Ssam HALDEBUG(ah, HAL_DEBUG_RX, "%s: Start PCU Receive \n", __func__); 112185377Ssam ar5212EnableMibCounters(ah); 113185377Ssam /* NB: restore current settings */ 114185380Ssam ar5416AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE); 115185380Ssam /* 116185380Ssam * NB: must do after enabling phy errors to avoid rx 117185380Ssam * frames w/ corrupted descriptor status. 118185380Ssam */ 119185380Ssam OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 120185377Ssam} 121185377Ssam 122185377Ssam/* 123185377Ssam * Stop receive at the PCU engine 124185377Ssam * and abort current frame in PCU 125185377Ssam */ 126185377Ssamvoid 127185377Ssamar5416StopPcuReceive(struct ath_hal *ah) 128185377Ssam{ 129185377Ssam OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 130185377Ssam 131185377Ssam HALDEBUG(ah, HAL_DEBUG_RX, "%s: Stop PCU Receive \n", __func__); 132185377Ssam ar5212DisableMibCounters(ah); 133185377Ssam} 134185377Ssam 135185377Ssam/* 136185377Ssam * Initialize RX descriptor, by clearing the status and setting 137185377Ssam * the size (and any other flags). 138185377Ssam */ 139185377SsamHAL_BOOL 140185377Ssamar5416SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds, 141185377Ssam uint32_t size, u_int flags) 142185377Ssam{ 143185377Ssam struct ar5416_desc *ads = AR5416DESC(ds); 144185377Ssam 145185377Ssam HALASSERT((size &~ AR_BufLen) == 0); 146185377Ssam 147185377Ssam ads->ds_ctl1 = size & AR_BufLen; 148185377Ssam if (flags & HAL_RXDESC_INTREQ) 149185377Ssam ads->ds_ctl1 |= AR_RxIntrReq; 150185377Ssam 151185377Ssam /* this should be enough */ 152185377Ssam ads->ds_rxstatus8 &= ~AR_RxDone; 153185377Ssam 154220259Sadrian /* clear the rest of the status fields */ 155225922Sadrian OS_MEMZERO(&(ads->u), sizeof(ads->u)); 156220259Sadrian 157185377Ssam return AH_TRUE; 158185377Ssam} 159185377Ssam 160185377Ssam/* 161185377Ssam * Process an RX descriptor, and return the status to the caller. 162185377Ssam * Copy some hardware specific items into the software portion 163185377Ssam * of the descriptor. 164185377Ssam * 165185377Ssam * NB: the caller is responsible for validating the memory contents 166185377Ssam * of the descriptor (e.g. flushing any cached copy). 167185377Ssam */ 168185377SsamHAL_STATUS 169185377Ssamar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds, 170185377Ssam uint32_t pa, struct ath_desc *nds, uint64_t tsf, 171185377Ssam struct ath_rx_status *rs) 172185377Ssam{ 173185377Ssam struct ar5416_desc *ads = AR5416DESC(ds); 174185377Ssam 175185377Ssam if ((ads->ds_rxstatus8 & AR_RxDone) == 0) 176185377Ssam return HAL_EINPROGRESS; 177185377Ssam 178185377Ssam rs->rs_status = 0; 179185377Ssam rs->rs_flags = 0; 180185377Ssam 181185377Ssam rs->rs_datalen = ads->ds_rxstatus1 & AR_DataLen; 182185377Ssam rs->rs_tstamp = ads->AR_RcvTimestamp; 183185377Ssam 184185377Ssam /* XXX what about KeyCacheMiss? */ 185185377Ssam 186185377Ssam rs->rs_rssi = MS(ads->ds_rxstatus4, AR_RxRSSICombined); 187185377Ssam rs->rs_rssi_ctl[0] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt00); 188185377Ssam rs->rs_rssi_ctl[1] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt01); 189185377Ssam rs->rs_rssi_ctl[2] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt02); 190185377Ssam rs->rs_rssi_ext[0] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt10); 191185377Ssam rs->rs_rssi_ext[1] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt11); 192185377Ssam rs->rs_rssi_ext[2] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt12); 193185377Ssam 194185377Ssam if (ads->ds_rxstatus8 & AR_RxKeyIdxValid) 195185377Ssam rs->rs_keyix = MS(ads->ds_rxstatus8, AR_KeyIdx); 196185377Ssam else 197185377Ssam rs->rs_keyix = HAL_RXKEYIX_INVALID; 198185377Ssam 199185377Ssam /* NB: caller expected to do rate table mapping */ 200185377Ssam rs->rs_rate = RXSTATUS_RATE(ah, ads); 201185377Ssam rs->rs_more = (ads->ds_rxstatus1 & AR_RxMore) ? 1 : 0; 202185377Ssam 203185377Ssam rs->rs_isaggr = (ads->ds_rxstatus8 & AR_RxAggr) ? 1 : 0; 204185377Ssam rs->rs_moreaggr = (ads->ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; 205185377Ssam rs->rs_antenna = MS(ads->ds_rxstatus3, AR_RxAntenna); 206185377Ssam 207185377Ssam if (ads->ds_rxstatus3 & AR_GI) 208185377Ssam rs->rs_flags |= HAL_RX_GI; 209185377Ssam if (ads->ds_rxstatus3 & AR_2040) 210185377Ssam rs->rs_flags |= HAL_RX_2040; 211185377Ssam 212250346Sadrian /* 213250346Sadrian * Only the AR9280 and later chips support STBC RX, so 214250346Sadrian * ensure we only set this bit for those chips. 215250346Sadrian */ 216250346Sadrian if (AR_SREV_MERLIN_10_OR_LATER(ah) 217250346Sadrian && ads->ds_rxstatus3 & AR_STBCFrame) 218250346Sadrian rs->rs_flags |= HAL_RX_STBC; 219250346Sadrian 220185377Ssam if (ads->ds_rxstatus8 & AR_PreDelimCRCErr) 221185377Ssam rs->rs_flags |= HAL_RX_DELIM_CRC_PRE; 222185377Ssam if (ads->ds_rxstatus8 & AR_PostDelimCRCErr) 223185377Ssam rs->rs_flags |= HAL_RX_DELIM_CRC_POST; 224185377Ssam if (ads->ds_rxstatus8 & AR_DecryptBusyErr) 225185377Ssam rs->rs_flags |= HAL_RX_DECRYPT_BUSY; 226185377Ssam if (ads->ds_rxstatus8 & AR_HiRxChain) 227185377Ssam rs->rs_flags |= HAL_RX_HI_RX_CHAIN; 228185377Ssam 229185377Ssam if ((ads->ds_rxstatus8 & AR_RxFrameOK) == 0) { 230185377Ssam /* 231185377Ssam * These four bits should not be set together. The 232185377Ssam * 5416 spec states a Michael error can only occur if 233185377Ssam * DecryptCRCErr not set (and TKIP is used). Experience 234185377Ssam * indicates however that you can also get Michael errors 235185377Ssam * when a CRC error is detected, but these are specious. 236185377Ssam * Consequently we filter them out here so we don't 237185377Ssam * confuse and/or complicate drivers. 238185377Ssam */ 239237519Sadrian 240237519Sadrian /* 241237519Sadrian * The AR5416 sometimes sets both AR_CRCErr and AR_PHYErr 242237521Sadrian * when reporting radar pulses. In this instance 243237521Sadrian * set HAL_RXERR_PHY as well as HAL_RXERR_CRC and 244237521Sadrian * let the driver layer figure out what to do. 245237519Sadrian * 246237519Sadrian * See PR kern/169362. 247237519Sadrian */ 248237519Sadrian if (ads->ds_rxstatus8 & AR_PHYErr) { 249185377Ssam u_int phyerr; 250185377Ssam 251237626Sadrian /* 252237626Sadrian * Packets with OFDM_RESTART on post delimiter are CRC OK and 253237626Sadrian * usable and MAC ACKs them. 254237626Sadrian * To avoid packet from being lost, we remove the PHY Err flag 255237626Sadrian * so that driver layer does not drop them. 256237626Sadrian */ 257185377Ssam phyerr = MS(ads->ds_rxstatus8, AR_PHYErrCode); 258237626Sadrian 259237626Sadrian if ((phyerr == HAL_PHYERR_OFDM_RESTART) && 260237626Sadrian (ads->ds_rxstatus8 & AR_PostDelimCRCErr)) { 261237626Sadrian ath_hal_printf(ah, 262237626Sadrian "%s: OFDM_RESTART on post-delim CRC error\n", 263237626Sadrian __func__); 264237626Sadrian rs->rs_phyerr = 0; 265237626Sadrian } else { 266237626Sadrian rs->rs_status |= HAL_RXERR_PHY; 267237626Sadrian rs->rs_phyerr = phyerr; 268237626Sadrian } 269237521Sadrian } 270237521Sadrian if (ads->ds_rxstatus8 & AR_CRCErr) 271237519Sadrian rs->rs_status |= HAL_RXERR_CRC; 272237519Sadrian else if (ads->ds_rxstatus8 & AR_DecryptCRCErr) 273185377Ssam rs->rs_status |= HAL_RXERR_DECRYPT; 274185377Ssam else if (ads->ds_rxstatus8 & AR_MichaelErr) 275185377Ssam rs->rs_status |= HAL_RXERR_MIC; 276185377Ssam } 277185377Ssam 278185377Ssam return HAL_OK; 279185377Ssam} 280