ar5416_attach.c revision 236017
138451Smsmith/* 238451Smsmith * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 338451Smsmith * Copyright (c) 2002-2008 Atheros Communications, Inc. 438451Smsmith * 538451Smsmith * Permission to use, copy, modify, and/or distribute this software for any 638451Smsmith * purpose with or without fee is hereby granted, provided that the above 738451Smsmith * copyright notice and this permission notice appear in all copies. 838451Smsmith * 938451Smsmith * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1038451Smsmith * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1138451Smsmith * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1238451Smsmith * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1338451Smsmith * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1438451Smsmith * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1538451Smsmith * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1638451Smsmith * 1738451Smsmith * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 236017 2012-05-25 17:53:57Z adrian $ 1838451Smsmith */ 1938451Smsmith#include "opt_ah.h" 2038451Smsmith 2138451Smsmith#include "ah.h" 2238451Smsmith#include "ah_internal.h" 2338451Smsmith#include "ah_devid.h" 2438451Smsmith 2538451Smsmith#include "ah_eeprom_v14.h" 2638451Smsmith 2738451Smsmith#include "ar5416/ar5416.h" 2838451Smsmith#include "ar5416/ar5416reg.h" 2938451Smsmith#include "ar5416/ar5416phy.h" 3038451Smsmith 3138451Smsmith#include "ar5416/ar5416.ini" 3238451Smsmith 3338451Smsmithstatic void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 3438451Smsmith HAL_BOOL power_off); 3538451Smsmithstatic void ar5416DisablePCIE(struct ath_hal *ah); 3638451Smsmithstatic void ar5416WriteIni(struct ath_hal *ah, 3738451Smsmith const struct ieee80211_channel *chan); 3838451Smsmithstatic void ar5416SpurMitigate(struct ath_hal *ah, 3938451Smsmith const struct ieee80211_channel *chan); 4038451Smsmith 4138451Smsmithstatic void 4284221Sdillonar5416AniSetup(struct ath_hal *ah) 4384221Sdillon{ 4484221Sdillon static const struct ar5212AniParams aniparams = { 4538451Smsmith .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 4638451Smsmith .totalSizeDesired = { -55, -55, -55, -55, -62 }, 4738451Smsmith .coarseHigh = { -14, -14, -14, -14, -12 }, 4838451Smsmith .coarseLow = { -64, -64, -64, -64, -70 }, 4938451Smsmith .firpwr = { -78, -78, -78, -78, -80 }, 5038451Smsmith .maxSpurImmunityLevel = 2, 5138451Smsmith .cycPwrThr1 = { 2, 4, 6 }, 5238451Smsmith .maxFirstepLevel = 2, /* levels 0..2 */ 5338451Smsmith .firstep = { 0, 4, 8 }, 5438451Smsmith .ofdmTrigHigh = 500, 5538451Smsmith .ofdmTrigLow = 200, 5638451Smsmith .cckTrigHigh = 200, 5738451Smsmith .cckTrigLow = 100, 5838451Smsmith .rssiThrHigh = 40, 5938451Smsmith .rssiThrLow = 7, 6038451Smsmith .period = 100, 6138451Smsmith }; 6238451Smsmith /* NB: disable ANI noise immmunity for reliable RIFS rx */ 6338451Smsmith AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 6438451Smsmith ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 6538451Smsmith} 6638451Smsmith 6738451Smsmith/* 6838451Smsmith * AR5416 doesn't do OLC or temperature compensation. 6938451Smsmith */ 7038451Smsmithstatic void 7138451Smsmithar5416olcInit(struct ath_hal *ah) 7238451Smsmith{ 7338451Smsmith} 7438451Smsmith 7538451Smsmithstatic void 7638451Smsmithar5416olcTempCompensation(struct ath_hal *ah) 7738451Smsmith{ 7838451Smsmith} 7938451Smsmith 8038451Smsmith/* 8138451Smsmith * Attach for an AR5416 part. 8238451Smsmith */ 8338451Smsmithvoid 8438451Smsmithar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 8538451Smsmith HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 8664527Sps{ 8738451Smsmith struct ath_hal_5212 *ahp; 8864527Sps struct ath_hal *ah; 8938451Smsmith 9038451Smsmith ahp = &ahp5416->ah_5212; 9192913Sobrien ar5212InitState(ahp, devid, sc, st, sh, status); 9238451Smsmith ah = &ahp->ah_priv.h; 9338451Smsmith 9438451Smsmith /* override 5212 methods for our needs */ 9538451Smsmith ah->ah_magic = AR5416_MAGIC; 9638451Smsmith ah->ah_getRateTable = ar5416GetRateTable; 9738451Smsmith ah->ah_detach = ar5416Detach; 9838451Smsmith 9938451Smsmith /* Reset functions */ 10038451Smsmith ah->ah_reset = ar5416Reset; 10138451Smsmith ah->ah_phyDisable = ar5416PhyDisable; 10238451Smsmith ah->ah_disable = ar5416Disable; 10338451Smsmith ah->ah_configPCIE = ar5416ConfigPCIE; 10438451Smsmith ah->ah_disablePCIE = ar5416DisablePCIE; 10538451Smsmith ah->ah_perCalibration = ar5416PerCalibration; 10638451Smsmith ah->ah_perCalibrationN = ar5416PerCalibrationN, 10738451Smsmith ah->ah_resetCalValid = ar5416ResetCalValid, 10838451Smsmith ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 10938451Smsmith ah->ah_setTxPower = ar5416SetTransmitPower; 11038451Smsmith ah->ah_setBoardValues = ar5416SetBoardValues; 11138451Smsmith 11238451Smsmith /* Transmit functions */ 11338451Smsmith ah->ah_stopTxDma = ar5416StopTxDma; 11438451Smsmith ah->ah_setupTxDesc = ar5416SetupTxDesc; 11538451Smsmith ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 11638451Smsmith ah->ah_fillTxDesc = ar5416FillTxDesc; 11738451Smsmith ah->ah_procTxDesc = ar5416ProcTxDesc; 11838451Smsmith ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 11938451Smsmith ah->ah_setupTxQueue = ar5416SetupTxQueue; 12038451Smsmith ah->ah_resetTxQueue = ar5416ResetTxQueue; 12138451Smsmith 12238451Smsmith /* Receive Functions */ 12338451Smsmith ah->ah_getRxFilter = ar5416GetRxFilter; 12438451Smsmith ah->ah_setRxFilter = ar5416SetRxFilter; 12538451Smsmith ah->ah_stopDmaReceive = ar5416StopDmaReceive; 12638451Smsmith ah->ah_startPcuReceive = ar5416StartPcuReceive; 12738451Smsmith ah->ah_stopPcuReceive = ar5416StopPcuReceive; 12838451Smsmith ah->ah_setupRxDesc = ar5416SetupRxDesc; 12938451Smsmith ah->ah_procRxDesc = ar5416ProcRxDesc; 13038451Smsmith ah->ah_rxMonitor = ar5416RxMonitor; 13164527Sps ah->ah_aniPoll = ar5416AniPoll; 13264527Sps ah->ah_procMibEvent = ar5416ProcessMibIntr; 13364527Sps 13464527Sps /* Misc Functions */ 13564527Sps ah->ah_getCapability = ar5416GetCapability; 13664527Sps ah->ah_setCapability = ar5416SetCapability; 13764527Sps ah->ah_getDiagState = ar5416GetDiagState; 13864527Sps ah->ah_setLedState = ar5416SetLedState; 13964527Sps ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 14064527Sps ah->ah_gpioCfgInput = ar5416GpioCfgInput; 14164527Sps ah->ah_gpioGet = ar5416GpioGet; 14264527Sps ah->ah_gpioSet = ar5416GpioSet; 14364527Sps ah->ah_gpioSetIntr = ar5416GpioSetIntr; 14438451Smsmith ah->ah_getTsf64 = ar5416GetTsf64; 14538451Smsmith ah->ah_resetTsf = ar5416ResetTsf; 14638451Smsmith ah->ah_getRfGain = ar5416GetRfgain; 14738451Smsmith ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 14838451Smsmith ah->ah_setDecompMask = ar5416SetDecompMask; 14938451Smsmith ah->ah_setCoverageClass = ar5416SetCoverageClass; 15038451Smsmith ah->ah_setQuiet = ar5416SetQuiet; 15138451Smsmith ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts; 15238451Smsmith 15338451Smsmith ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 15438451Smsmith ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 15538451Smsmith 15638451Smsmith /* DFS Functions */ 15738451Smsmith ah->ah_enableDfs = ar5416EnableDfs; 15838451Smsmith ah->ah_getDfsThresh = ar5416GetDfsThresh; 15938451Smsmith ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 16038451Smsmith ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled; 16138451Smsmith 16238451Smsmith /* Power Management Functions */ 16338451Smsmith ah->ah_setPowerMode = ar5416SetPowerMode; 16438451Smsmith 16538451Smsmith /* Beacon Management Functions */ 16638451Smsmith ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 16738451Smsmith ah->ah_beaconInit = ar5416BeaconInit; 16838451Smsmith ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 16938451Smsmith ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 17038451Smsmith ah->ah_getNextTBTT = ar5416GetNextTBTT; 17138451Smsmith 17238451Smsmith /* 802.11n Functions */ 17338451Smsmith ah->ah_chainTxDesc = ar5416ChainTxDesc; 17438451Smsmith ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 17538451Smsmith ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 17638451Smsmith ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 17738451Smsmith ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst; 17838451Smsmith ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 17938451Smsmith ah->ah_set11nAggrLast = ar5416Set11nAggrLast; 18064527Sps ah->ah_clr11nAggr = ar5416Clr11nAggr; 18164527Sps ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 18264527Sps ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 18364527Sps ah->ah_set11nMac2040 = ar5416Set11nMac2040; 18464527Sps ah->ah_get11nRxClear = ar5416Get11nRxClear; 18564527Sps ah->ah_set11nRxClear = ar5416Set11nRxClear; 18664527Sps 18738451Smsmith /* Interrupt functions */ 18838451Smsmith ah->ah_isInterruptPending = ar5416IsInterruptPending; 18938451Smsmith ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 19038451Smsmith ah->ah_setInterrupts = ar5416SetInterrupts; 19138451Smsmith 19238451Smsmith ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 19338451Smsmith ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 19438451Smsmith#ifdef AH_SUPPORT_WRITE_EEPROM 19538451Smsmith ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 19638451Smsmith#endif 19738451Smsmith ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 19838451Smsmith 19938451Smsmith /* Internal ops */ 20038451Smsmith AH5416(ah)->ah_writeIni = ar5416WriteIni; 20138451Smsmith AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 20238451Smsmith 20338451Smsmith /* Internal baseband ops */ 20438451Smsmith AH5416(ah)->ah_initPLL = ar5416InitPLL; 20538451Smsmith 20666134Sps /* Internal calibration ops */ 20738451Smsmith AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 20866134Sps 20938451Smsmith /* Internal TX power control related operations */ 21038451Smsmith AH5416(ah)->ah_olcInit = ar5416olcInit; 21138451Smsmith AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 21238451Smsmith AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 21338451Smsmith 21438451Smsmith /* 21538451Smsmith * Start by setting all Owl devices to 2x2 21638451Smsmith */ 21738451Smsmith AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 21838451Smsmith AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 21938451Smsmith 22038451Smsmith /* Enable all ANI functions to begin with */ 22138451Smsmith AH5416(ah)->ah_ani_function = 0xffffffff; 22238451Smsmith 22338451Smsmith /* Set overridable ANI methods */ 22438451Smsmith AH5212(ah)->ah_aniControl = ar5416AniControl; 22538451Smsmith} 22638451Smsmith 22738451Smsmithuint32_t 22838451Smsmithar5416GetRadioRev(struct ath_hal *ah) 22938451Smsmith{ 23038451Smsmith uint32_t val; 23138451Smsmith int i; 23238451Smsmith 23338451Smsmith /* Read Radio Chip Rev Extract */ 23438451Smsmith OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 23538451Smsmith for (i = 0; i < 8; i++) 23638451Smsmith OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 23738451Smsmith val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 23838451Smsmith val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 23938451Smsmith return ath_hal_reverseBits(val, 8); 24038451Smsmith} 24138451Smsmith 24238451Smsmith/* 24338451Smsmith * Attach for an AR5416 part. 24438451Smsmith */ 24538451Smsmithstatic struct ath_hal * 24638451Smsmithar5416Attach(uint16_t devid, HAL_SOFTC sc, 24738451Smsmith HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 24838451Smsmith HAL_STATUS *status) 24938451Smsmith{ 25038451Smsmith struct ath_hal_5416 *ahp5416; 25138451Smsmith struct ath_hal_5212 *ahp; 25238451Smsmith struct ath_hal *ah; 25338451Smsmith uint32_t val; 25438451Smsmith HAL_STATUS ecode; 25538451Smsmith HAL_BOOL rfStatus; 25638451Smsmith 25738451Smsmith HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 25838451Smsmith __func__, sc, (void*) st, (void*) sh); 25992913Sobrien 26092913Sobrien /* NB: memory is returned zero'd */ 26192913Sobrien ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 26238451Smsmith /* extra space for Owl 2.1/2.2 WAR */ 26392913Sobrien sizeof(ar5416Addac) 26438451Smsmith ); 26538451Smsmith if (ahp5416 == AH_NULL) { 26638451Smsmith HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 26738451Smsmith "%s: cannot allocate memory for state block\n", __func__); 26838451Smsmith *status = HAL_ENOMEM; 26938451Smsmith return AH_NULL; 27038451Smsmith } 27138451Smsmith ar5416InitState(ahp5416, devid, sc, st, sh, status); 27238451Smsmith ahp = &ahp5416->ah_5212; 27338451Smsmith ah = &ahp->ah_priv.h; 27438451Smsmith 27538451Smsmith if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 27638451Smsmith /* reset chip */ 27738451Smsmith HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 27838451Smsmith ecode = HAL_EIO; 27938451Smsmith goto bad; 28038451Smsmith } 28138451Smsmith 28238451Smsmith if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 28392913Sobrien HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 28492913Sobrien ecode = HAL_EIO; 28592913Sobrien goto bad; 28638451Smsmith } 28738451Smsmith /* Read Revisions from Chips before taking out of reset */ 28892913Sobrien val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 28992913Sobrien AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 29038451Smsmith AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 29138451Smsmith AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 29238451Smsmith 29338451Smsmith /* setup common ini data; rf backends handle remainder */ 29438451Smsmith HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 29538451Smsmith HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 29638451Smsmith 29738451Smsmith HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 29838451Smsmith HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 29938451Smsmith HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 30038451Smsmith HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 30138451Smsmith HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 30238451Smsmith HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 30338451Smsmith HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 30438451Smsmith HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 30538451Smsmith 30638451Smsmith if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 30738451Smsmith ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 30838451Smsmith struct ini { 30938451Smsmith uint32_t *data; /* NB: !const */ 31038451Smsmith int rows, cols; 31138451Smsmith }; 31238451Smsmith /* override CLKDRV value */ 31338451Smsmith OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 31438451Smsmith AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 31538451Smsmith HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 31638451Smsmith } 31738451Smsmith 31838451Smsmith HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 31938451Smsmith ar5416AttachPCIE(ah); 32038451Smsmith 32138451Smsmith ecode = ath_hal_v14EepromAttach(ah); 32238451Smsmith if (ecode != HAL_OK) 32338451Smsmith goto bad; 32438451Smsmith 32538451Smsmith if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 32638451Smsmith HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 32738451Smsmith __func__); 32838451Smsmith ecode = HAL_EIO; 32938451Smsmith goto bad; 33038451Smsmith } 33138451Smsmith 33238451Smsmith AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 33338451Smsmith 33438451Smsmith if (!ar5212ChipTest(ah)) { 33538451Smsmith HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 33638451Smsmith __func__); 33738451Smsmith ecode = HAL_ESELFTEST; 33838451Smsmith goto bad; 33938451Smsmith } 34038451Smsmith 34138451Smsmith /* 34292913Sobrien * Set correct Baseband to analog shift 34338451Smsmith * setting to access analog chips. 34438451Smsmith */ 34592913Sobrien OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 34692913Sobrien 34792913Sobrien /* Read Radio Chip Rev Extract */ 34838451Smsmith AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 34938451Smsmith switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 35038451Smsmith case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 35138451Smsmith case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 35238451Smsmith case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 35338451Smsmith case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 35438451Smsmith break; 35538451Smsmith default: 35638451Smsmith if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 35738451Smsmith /* 35838451Smsmith * When RF_Silen is used the analog chip is reset. 35938451Smsmith * So when the system boots with radio switch off 36038451Smsmith * the RF chip rev reads back as zero and we need 36138451Smsmith * to use the mac+phy revs to set the radio rev. 36238451Smsmith */ 36338451Smsmith AH_PRIVATE(ah)->ah_analog5GhzRev = 36438451Smsmith AR_RAD5133_SREV_MAJOR; 36538451Smsmith break; 36638451Smsmith } 36738451Smsmith /* NB: silently accept anything in release code per Atheros */ 36838451Smsmith#ifdef AH_DEBUG 36938451Smsmith HALDEBUG(ah, HAL_DEBUG_ANY, 37038451Smsmith "%s: 5G Radio Chip Rev 0x%02X is not supported by " 37138451Smsmith "this driver\n", __func__, 37238451Smsmith AH_PRIVATE(ah)->ah_analog5GhzRev); 37338451Smsmith ecode = HAL_ENOTSUPP; 37438451Smsmith goto bad; 37538451Smsmith#endif 37638451Smsmith } 37738451Smsmith 37838451Smsmith /* 37938451Smsmith * Got everything we need now to setup the capabilities. 38038451Smsmith */ 38138451Smsmith if (!ar5416FillCapabilityInfo(ah)) { 38238451Smsmith ecode = HAL_EEREAD; 38338451Smsmith goto bad; 38438451Smsmith } 38538451Smsmith 38638451Smsmith ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 38738451Smsmith if (ecode != HAL_OK) { 38838451Smsmith HALDEBUG(ah, HAL_DEBUG_ANY, 38938451Smsmith "%s: error getting mac address from EEPROM\n", __func__); 39038451Smsmith goto bad; 39138451Smsmith } 39238451Smsmith /* XXX How about the serial number ? */ 39338451Smsmith /* Read Reg Domain */ 39438451Smsmith AH_PRIVATE(ah)->ah_currentRD = 39538451Smsmith ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 39638451Smsmith AH_PRIVATE(ah)->ah_currentRDext = 39738451Smsmith ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 39838451Smsmith 39938451Smsmith /* 40038451Smsmith * ah_miscMode is populated by ar5416FillCapabilityInfo() 40138451Smsmith * starting from griffin. Set here to make sure that 40238451Smsmith * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 40392913Sobrien * placed into hardware. 40438451Smsmith */ 40538451Smsmith if (ahp->ah_miscMode != 0) 40638451Smsmith OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 40738451Smsmith 40838451Smsmith rfStatus = ar2133RfAttach(ah, &ecode); 40938451Smsmith if (!rfStatus) { 41038451Smsmith HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 41138451Smsmith __func__, ecode); 41238451Smsmith goto bad; 41338451Smsmith } 41438451Smsmith 41538451Smsmith ar5416AniSetup(ah); /* Anti Noise Immunity */ 41638451Smsmith 41738451Smsmith AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 41838451Smsmith AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 419 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 420 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 421 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 422 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 423 424 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 425 426 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 427 428 return ah; 429bad: 430 if (ahp) 431 ar5416Detach((struct ath_hal *) ahp); 432 if (status) 433 *status = ecode; 434 return AH_NULL; 435} 436 437void 438ar5416Detach(struct ath_hal *ah) 439{ 440 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 441 442 HALASSERT(ah != AH_NULL); 443 HALASSERT(ah->ah_magic == AR5416_MAGIC); 444 445 /* Make sure that chip is awake before writing to it */ 446 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 447 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 448 "%s: failed to wake up chip\n", 449 __func__); 450 451 ar5416AniDetach(ah); 452 ar5212RfDetach(ah); 453 ah->ah_disable(ah); 454 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 455 ath_hal_eepromDetach(ah); 456 ath_hal_free(ah); 457} 458 459void 460ar5416AttachPCIE(struct ath_hal *ah) 461{ 462 if (AH_PRIVATE(ah)->ah_ispcie) 463 ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE); 464 else 465 ath_hal_disablePCIE(ah); 466} 467 468static void 469ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 470{ 471 472 /* This is only applicable for AR5418 (AR5416 PCIe) */ 473 if (! AH_PRIVATE(ah)->ah_ispcie) 474 return; 475 476 if (! restore) { 477 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 478 OS_DELAY(1000); 479 } 480 481 if (power_off) { /* Power-off */ 482 /* clear bit 19 to disable L1 */ 483 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 484 } else { /* Power-on */ 485 /* Set default WAR values for Owl */ 486 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 487 488 /* set bit 19 to allow forcing of pcie core into L1 state */ 489 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 490 } 491} 492 493/* 494 * Disable PCIe PHY if PCIe isn't used. 495 */ 496static void 497ar5416DisablePCIE(struct ath_hal *ah) 498{ 499 500 /* PCIe? Don't */ 501 if (AH_PRIVATE(ah)->ah_ispcie) 502 return; 503 504 /* .. Only applicable for AR5416v2 or later */ 505 if (! (AR_SREV_OWL(ah) && AR_SREV_OWL_20_OR_LATER(ah))) 506 return; 507 508 OS_REG_WRITE_BUFFER_ENABLE(ah); 509 510 /* 511 * Disable the PCIe PHY. 512 */ 513 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 514 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 515 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 516 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 517 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 518 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 519 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 520 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 521 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 522 523 /* Load the new settings */ 524 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 525 526 OS_REG_WRITE_BUFFER_FLUSH(ah); 527 OS_REG_WRITE_BUFFER_DISABLE(ah); 528} 529 530static void 531ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 532{ 533 u_int modesIndex, freqIndex; 534 int regWrites = 0; 535 536 /* Setup the indices for the next set of register array writes */ 537 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 538 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 539 freqIndex = 2; 540 if (IEEE80211_IS_CHAN_HT40(chan)) 541 modesIndex = 3; 542 else if (IEEE80211_IS_CHAN_108G(chan)) 543 modesIndex = 5; 544 else 545 modesIndex = 4; 546 } else { 547 freqIndex = 1; 548 if (IEEE80211_IS_CHAN_HT40(chan) || 549 IEEE80211_IS_CHAN_TURBO(chan)) 550 modesIndex = 2; 551 else 552 modesIndex = 1; 553 } 554 555 /* Set correct Baseband to analog shift setting to access analog chips. */ 556 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 557 558 /* 559 * Write addac shifts 560 */ 561 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 562 563 /* NB: only required for Sowl */ 564 if (AR_SREV_SOWL(ah)) 565 ar5416EepromSetAddac(ah, chan); 566 567 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 568 regWrites); 569 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 570 571 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 572 modesIndex, regWrites); 573 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 574 1, regWrites); 575 576 /* XXX updated regWrites? */ 577 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 578} 579 580/* 581 * Convert to baseband spur frequency given input channel frequency 582 * and compute register settings below. 583 */ 584 585static void 586ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 587{ 588 uint16_t freq = ath_hal_gethwchannel(ah, chan); 589 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 590 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 591 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 592 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 593 static const int inc[4] = { 0, 100, 0, 0 }; 594 595 int bb_spur = AR_NO_SPUR; 596 int bin, cur_bin; 597 int spur_freq_sd; 598 int spur_delta_phase; 599 int denominator; 600 int upper, lower, cur_vit_mask; 601 int tmp, new; 602 int i; 603 604 int8_t mask_m[123]; 605 int8_t mask_p[123]; 606 int8_t mask_amt; 607 int tmp_mask; 608 int cur_bb_spur; 609 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 610 611 OS_MEMZERO(mask_m, sizeof(mask_m)); 612 OS_MEMZERO(mask_p, sizeof(mask_p)); 613 614 /* 615 * Need to verify range +/- 9.5 for static ht20, otherwise spur 616 * is out-of-band and can be ignored. 617 */ 618 /* XXX ath9k changes */ 619 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 620 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 621 if (AR_NO_SPUR == cur_bb_spur) 622 break; 623 cur_bb_spur = cur_bb_spur - (freq * 10); 624 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 625 bb_spur = cur_bb_spur; 626 break; 627 } 628 } 629 if (AR_NO_SPUR == bb_spur) 630 return; 631 632 bin = bb_spur * 32; 633 634 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 635 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 636 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 637 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 638 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 639 640 OS_REG_WRITE_BUFFER_ENABLE(ah); 641 642 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 643 644 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 645 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 646 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 647 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 648 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 649 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 650 /* 651 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 652 * config, no offset for HT20. 653 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 654 * /80 for dyn2040. 655 */ 656 spur_delta_phase = ((bb_spur * 524288) / 100) & 657 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 658 /* 659 * in 11A mode the denominator of spur_freq_sd should be 40 and 660 * it should be 44 in 11G 661 */ 662 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 663 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 664 665 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 666 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 667 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 668 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 669 670 671 /* 672 * ============================================ 673 * pilot mask 1 [31:0] = +6..-26, no 0 bin 674 * pilot mask 2 [19:0] = +26..+7 675 * 676 * channel mask 1 [31:0] = +6..-26, no 0 bin 677 * channel mask 2 [19:0] = +26..+7 678 */ 679 //cur_bin = -26; 680 cur_bin = -6000; 681 upper = bin + 100; 682 lower = bin - 100; 683 684 for (i = 0; i < 4; i++) { 685 int pilot_mask = 0; 686 int chan_mask = 0; 687 int bp = 0; 688 for (bp = 0; bp < 30; bp++) { 689 if ((cur_bin > lower) && (cur_bin < upper)) { 690 pilot_mask = pilot_mask | 0x1 << bp; 691 chan_mask = chan_mask | 0x1 << bp; 692 } 693 cur_bin += 100; 694 } 695 cur_bin += inc[i]; 696 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 697 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 698 } 699 700 /* ================================================= 701 * viterbi mask 1 based on channel magnitude 702 * four levels 0-3 703 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 704 * [1 2 2 1] for -9.6 or [1 2 1] for +16 705 * - enable_mask_ppm, all bins move with freq 706 * 707 * - mask_select, 8 bits for rates (reg 67,0x990c) 708 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 709 * choose which mask to use mask or mask2 710 */ 711 712 /* 713 * viterbi mask 2 2nd set for per data rate puncturing 714 * four levels 0-3 715 * - mask_select, 8 bits for rates (reg 67) 716 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 717 * [1 2 2 1] for -9.6 or [1 2 1] for +16 718 */ 719 cur_vit_mask = 6100; 720 upper = bin + 120; 721 lower = bin - 120; 722 723 for (i = 0; i < 123; i++) { 724 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 725 if ((abs(cur_vit_mask - bin)) < 75) { 726 mask_amt = 1; 727 } else { 728 mask_amt = 0; 729 } 730 if (cur_vit_mask < 0) { 731 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 732 } else { 733 mask_p[cur_vit_mask / 100] = mask_amt; 734 } 735 } 736 cur_vit_mask -= 100; 737 } 738 739 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 740 | (mask_m[48] << 26) | (mask_m[49] << 24) 741 | (mask_m[50] << 22) | (mask_m[51] << 20) 742 | (mask_m[52] << 18) | (mask_m[53] << 16) 743 | (mask_m[54] << 14) | (mask_m[55] << 12) 744 | (mask_m[56] << 10) | (mask_m[57] << 8) 745 | (mask_m[58] << 6) | (mask_m[59] << 4) 746 | (mask_m[60] << 2) | (mask_m[61] << 0); 747 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 748 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 749 750 tmp_mask = (mask_m[31] << 28) 751 | (mask_m[32] << 26) | (mask_m[33] << 24) 752 | (mask_m[34] << 22) | (mask_m[35] << 20) 753 | (mask_m[36] << 18) | (mask_m[37] << 16) 754 | (mask_m[48] << 14) | (mask_m[39] << 12) 755 | (mask_m[40] << 10) | (mask_m[41] << 8) 756 | (mask_m[42] << 6) | (mask_m[43] << 4) 757 | (mask_m[44] << 2) | (mask_m[45] << 0); 758 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 759 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 760 761 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 762 | (mask_m[18] << 26) | (mask_m[18] << 24) 763 | (mask_m[20] << 22) | (mask_m[20] << 20) 764 | (mask_m[22] << 18) | (mask_m[22] << 16) 765 | (mask_m[24] << 14) | (mask_m[24] << 12) 766 | (mask_m[25] << 10) | (mask_m[26] << 8) 767 | (mask_m[27] << 6) | (mask_m[28] << 4) 768 | (mask_m[29] << 2) | (mask_m[30] << 0); 769 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 770 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 771 772 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 773 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 774 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 775 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 776 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 777 | (mask_m[10] << 10) | (mask_m[11] << 8) 778 | (mask_m[12] << 6) | (mask_m[13] << 4) 779 | (mask_m[14] << 2) | (mask_m[15] << 0); 780 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 781 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 782 783 tmp_mask = (mask_p[15] << 28) 784 | (mask_p[14] << 26) | (mask_p[13] << 24) 785 | (mask_p[12] << 22) | (mask_p[11] << 20) 786 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 787 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 788 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 789 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 790 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 791 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 792 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 793 794 tmp_mask = (mask_p[30] << 28) 795 | (mask_p[29] << 26) | (mask_p[28] << 24) 796 | (mask_p[27] << 22) | (mask_p[26] << 20) 797 | (mask_p[25] << 18) | (mask_p[24] << 16) 798 | (mask_p[23] << 14) | (mask_p[22] << 12) 799 | (mask_p[21] << 10) | (mask_p[20] << 8) 800 | (mask_p[19] << 6) | (mask_p[18] << 4) 801 | (mask_p[17] << 2) | (mask_p[16] << 0); 802 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 803 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 804 805 tmp_mask = (mask_p[45] << 28) 806 | (mask_p[44] << 26) | (mask_p[43] << 24) 807 | (mask_p[42] << 22) | (mask_p[41] << 20) 808 | (mask_p[40] << 18) | (mask_p[39] << 16) 809 | (mask_p[38] << 14) | (mask_p[37] << 12) 810 | (mask_p[36] << 10) | (mask_p[35] << 8) 811 | (mask_p[34] << 6) | (mask_p[33] << 4) 812 | (mask_p[32] << 2) | (mask_p[31] << 0); 813 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 814 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 815 816 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 817 | (mask_p[59] << 26) | (mask_p[58] << 24) 818 | (mask_p[57] << 22) | (mask_p[56] << 20) 819 | (mask_p[55] << 18) | (mask_p[54] << 16) 820 | (mask_p[53] << 14) | (mask_p[52] << 12) 821 | (mask_p[51] << 10) | (mask_p[50] << 8) 822 | (mask_p[49] << 6) | (mask_p[48] << 4) 823 | (mask_p[47] << 2) | (mask_p[46] << 0); 824 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 825 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 826 827 OS_REG_WRITE_BUFFER_FLUSH(ah); 828 OS_REG_WRITE_BUFFER_DISABLE(ah); 829} 830 831/* 832 * Fill all software cached or static hardware state information. 833 * Return failure if capabilities are to come from EEPROM and 834 * cannot be read. 835 */ 836HAL_BOOL 837ar5416FillCapabilityInfo(struct ath_hal *ah) 838{ 839 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 840 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 841 uint16_t val; 842 843 /* Construct wireless mode from EEPROM */ 844 pCap->halWirelessModes = 0; 845 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 846 pCap->halWirelessModes |= HAL_MODE_11A 847 | HAL_MODE_11NA_HT20 848 | HAL_MODE_11NA_HT40PLUS 849 | HAL_MODE_11NA_HT40MINUS 850 ; 851 } 852 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 853 pCap->halWirelessModes |= HAL_MODE_11G 854 | HAL_MODE_11NG_HT20 855 | HAL_MODE_11NG_HT40PLUS 856 | HAL_MODE_11NG_HT40MINUS 857 ; 858 pCap->halWirelessModes |= HAL_MODE_11A 859 | HAL_MODE_11NA_HT20 860 | HAL_MODE_11NA_HT40PLUS 861 | HAL_MODE_11NA_HT40MINUS 862 ; 863 } 864 865 pCap->halLow2GhzChan = 2312; 866 pCap->halHigh2GhzChan = 2732; 867 868 pCap->halLow5GhzChan = 4915; 869 pCap->halHigh5GhzChan = 6100; 870 871 pCap->halCipherCkipSupport = AH_FALSE; 872 pCap->halCipherTkipSupport = AH_TRUE; 873 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 874 875 pCap->halMicCkipSupport = AH_FALSE; 876 pCap->halMicTkipSupport = AH_TRUE; 877 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 878 /* 879 * Starting with Griffin TX+RX mic keys can be combined 880 * in one key cache slot. 881 */ 882 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 883 pCap->halChanSpreadSupport = AH_TRUE; 884 pCap->halSleepAfterBeaconBroken = AH_TRUE; 885 886 pCap->halCompressSupport = AH_FALSE; 887 pCap->halBurstSupport = AH_TRUE; 888 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 889 pCap->halChapTuningSupport = AH_TRUE; 890 pCap->halTurboPrimeSupport = AH_TRUE; 891 892 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 893 894 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 895 pCap->halVEOLSupport = AH_TRUE; 896 pCap->halBssIdMaskSupport = AH_TRUE; 897 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 898 pCap->halTsfAddSupport = AH_TRUE; 899 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 900 901 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 902 pCap->halTotalQueues = val; 903 else 904 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 905 906 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 907 pCap->halKeyCacheSize = val; 908 else 909 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 910 911 /* XXX not needed */ 912 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 913 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 914 915 pCap->halTstampPrecision = 32; 916 pCap->halHwPhyCounterSupport = AH_TRUE; 917 pCap->halIntrMask = HAL_INT_COMMON 918 | HAL_INT_RX 919 | HAL_INT_TX 920 | HAL_INT_FATAL 921 | HAL_INT_BNR 922 | HAL_INT_BMISC 923 | HAL_INT_DTIMSYNC 924 | HAL_INT_TSFOOR 925 | HAL_INT_CST 926 | HAL_INT_GTT 927 ; 928 929 pCap->halFastCCSupport = AH_TRUE; 930 pCap->halNumGpioPins = 14; 931 pCap->halWowSupport = AH_FALSE; 932 pCap->halWowMatchPatternExact = AH_FALSE; 933 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 934 pCap->halAutoSleepSupport = AH_FALSE; 935 pCap->hal4kbSplitTransSupport = AH_TRUE; 936 /* Disable this so Block-ACK works correctly */ 937 pCap->halHasRxSelfLinkedTail = AH_FALSE; 938#if 0 /* XXX not yet */ 939 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 940 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 941#endif 942 pCap->halHTSupport = AH_TRUE; 943 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 944 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 945 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 946 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 947 pCap->halTxStreams = 2; 948 pCap->halRxStreams = 2; 949 950 /* 951 * If the TX or RX chainmask has less than 2 chains active, 952 * mark it as a 1-stream device for the relevant stream. 953 */ 954 if (owl_get_ntxchains(pCap->halTxChainMask) == 1) 955 pCap->halTxStreams = 1; 956 /* XXX Eww */ 957 if (owl_get_ntxchains(pCap->halRxChainMask) == 1) 958 pCap->halRxStreams = 1; 959 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 960 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 961 pCap->halForcePpmSupport = AH_TRUE; 962 pCap->halEnhancedPmSupport = AH_TRUE; 963 pCap->halBssidMatchSupport = AH_TRUE; 964 pCap->halGTTSupport = AH_TRUE; 965 pCap->halCSTSupport = AH_TRUE; 966 pCap->halEnhancedDfsSupport = AH_FALSE; 967 /* Hardware supports 32 bit TSF values in the RX descriptor */ 968 pCap->halHasLongRxDescTsf = AH_TRUE; 969 /* 970 * BB Read WAR: this is only for AR5008/AR9001 NICs 971 * It is also set individually in the AR91xx attach functions. 972 */ 973 if (AR_SREV_OWL(ah)) 974 pCap->halHasBBReadWar = AH_TRUE; 975 976 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 977 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 978 /* NB: enabled by default */ 979 ahpriv->ah_rfkillEnabled = AH_TRUE; 980 pCap->halRfSilentSupport = AH_TRUE; 981 } 982 983 /* 984 * The MAC will mark frames as RXed if there's a descriptor 985 * to write them to. So if it hits a self-linked final descriptor, 986 * it'll keep ACKing frames even though they're being silently 987 * dropped. Thus, this particular feature of the driver can't 988 * be used for 802.11n devices. 989 */ 990 ahpriv->ah_rxornIsFatal = AH_FALSE; 991 992 /* 993 * If it's a PCI NIC, ask the HAL OS layer to serialise 994 * register access, or SMP machines may cause the hardware 995 * to hang. This is applicable to AR5416 and AR9220; I'm not 996 * sure about AR9160 or AR9227. 997 */ 998 if (! AH_PRIVATE(ah)->ah_ispcie) 999 pCap->halSerialiseRegWar = 1; 1000 1001 return AH_TRUE; 1002} 1003 1004static const char* 1005ar5416Probe(uint16_t vendorid, uint16_t devid) 1006{ 1007 if (vendorid == ATHEROS_VENDOR_ID) { 1008 if (devid == AR5416_DEVID_PCI) 1009 return "Atheros 5416"; 1010 if (devid == AR5416_DEVID_PCIE) 1011 return "Atheros 5418"; 1012 } 1013 return AH_NULL; 1014} 1015AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 1016