1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187831Ssam * $FreeBSD$ 18185377Ssam */ 19185377Ssam 20185377Ssam#ifndef _ATH_AH_H_ 21185377Ssam#define _ATH_AH_H_ 22185377Ssam/* 23185377Ssam * Atheros Hardware Access Layer 24185377Ssam * 25185377Ssam * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26185377Ssam * structure for use with the device. Hardware-related operations that 27185377Ssam * follow must call back into the HAL through interface, supplying the 28185377Ssam * reference as the first parameter. 29185377Ssam */ 30185377Ssam 31185377Ssam#include "ah_osdep.h" 32185377Ssam 33185377Ssam/* 34220442Sadrian * The maximum number of TX/RX chains supported. 35220442Sadrian * This is intended to be used by various statistics gathering operations 36220442Sadrian * (NF, RSSI, EVM). 37220442Sadrian */ 38240623Sadrian#define AH_MAX_CHAINS 3 39220442Sadrian#define AH_MIMO_MAX_EVM_PILOTS 6 40220442Sadrian 41220442Sadrian/* 42185377Ssam * __ahdecl is analogous to _cdecl; it defines the calling 43185377Ssam * convention used within the HAL. For most systems this 44185377Ssam * can just default to be empty and the compiler will (should) 45185377Ssam * use _cdecl. For systems where _cdecl is not compatible this 46185377Ssam * must be defined. See linux/ah_osdep.h for an example. 47185377Ssam */ 48185377Ssam#ifndef __ahdecl 49185377Ssam#define __ahdecl 50185377Ssam#endif 51185377Ssam 52185377Ssam/* 53185377Ssam * Status codes that may be returned by the HAL. Note that 54185377Ssam * interfaces that return a status code set it only when an 55185377Ssam * error occurs--i.e. you cannot check it for success. 56185377Ssam */ 57185377Ssamtypedef enum { 58185377Ssam HAL_OK = 0, /* No error */ 59185377Ssam HAL_ENXIO = 1, /* No hardware present */ 60185377Ssam HAL_ENOMEM = 2, /* Memory allocation failed */ 61185377Ssam HAL_EIO = 3, /* Hardware didn't respond as expected */ 62185377Ssam HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63185377Ssam HAL_EEVERSION = 5, /* EEPROM version invalid */ 64185377Ssam HAL_EELOCKED = 6, /* EEPROM unreadable */ 65185377Ssam HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66185377Ssam HAL_EEREAD = 8, /* EEPROM read problem */ 67185377Ssam HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68185377Ssam HAL_EESIZE = 10, /* EEPROM size not supported */ 69185377Ssam HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70185377Ssam HAL_EINVAL = 12, /* Invalid parameter to function */ 71185377Ssam HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72185377Ssam HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73185377Ssam HAL_EINPROGRESS = 15, /* Operation incomplete */ 74187831Ssam HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75187831Ssam HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76237874Sadrian HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 77185377Ssam} HAL_STATUS; 78185377Ssam 79185377Ssamtypedef enum { 80185377Ssam AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 81185377Ssam AH_TRUE = 1, 82185377Ssam} HAL_BOOL; 83185377Ssam 84185377Ssamtypedef enum { 85185377Ssam HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 86185377Ssam HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 87185377Ssam HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 88185377Ssam HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 89185377Ssam HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 90185377Ssam HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 91185377Ssam HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 92185377Ssam HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 93185377Ssam HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 94185377Ssam HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 95185377Ssam HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 96185377Ssam HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 97185377Ssam HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 98185377Ssam HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 99185377Ssam HAL_CAP_TXPOW = 15, /* global tx power limit */ 100185377Ssam HAL_CAP_TPC = 16, /* per-packet tx power control */ 101185377Ssam HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 102185377Ssam HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 103185377Ssam HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 104185377Ssam HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 105185377Ssam /* 21 was HAL_CAP_XR */ 106185377Ssam HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 107185380Ssam /* 23 was HAL_CAP_CHAN_HALFRATE */ 108185380Ssam /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 109185377Ssam HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 110185377Ssam HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 111185377Ssam HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 112185377Ssam HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 113237953Sadrian HAL_CAP_PCIE_PS = 29, 114221603Sadrian HAL_CAP_HT = 30, /* hardware can support HT */ 115221603Sadrian HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 116221603Sadrian HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 117221603Sadrian HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 118221603Sadrian HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 119221603Sadrian HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 120221581Sadrian 121221603Sadrian HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 122237953Sadrian HAL_CAP_RIFS_RX = 39, 123237953Sadrian HAL_CAP_RIFS_TX = 40, 124237953Sadrian HAL_CAP_FORCE_PPM = 41, 125221603Sadrian HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 126221603Sadrian HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 127222584Sadrian HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 128222584Sadrian HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 129222584Sadrian HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 130221603Sadrian 131221603Sadrian HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 132221603Sadrian automatically after waking up to receive TIM */ 133221603Sadrian HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 134221603Sadrian HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 135221603Sadrian HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 136237953Sadrian HAL_CAP_BB_RIFS_HANG = 52, 137237953Sadrian HAL_CAP_RIFS_RX_ENABLED = 53, 138237953Sadrian HAL_CAP_BB_DFS_HANG = 54, 139221603Sadrian 140247366Sadrian HAL_CAP_RX_STBC = 58, 141247366Sadrian HAL_CAP_TX_STBC = 59, 142247366Sadrian 143221603Sadrian HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 144237953Sadrian HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 145221603Sadrian 146237953Sadrian HAL_CAP_DS = 67, /* 2 stream */ 147237953Sadrian HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 148237953Sadrian HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 149237955Sadrian HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 150237953Sadrian 151237953Sadrian HAL_CAP_TS = 72, /* 3 stream */ 152237953Sadrian 153237953Sadrian HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 154238280Sadrian HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 155238280Sadrian HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 156238280Sadrian HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 157238280Sadrian HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 158238280Sadrian HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 159238280Sadrian HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 160238280Sadrian HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 161237953Sadrian HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 162244854Sadrian HAL_CAP_SPECTRAL_SCAN = 90, /* Hardware supports spectral scan */ 163237953Sadrian 164237953Sadrian HAL_CAP_BB_PANIC_WATCHDOG = 92, 165237953Sadrian 166221603Sadrian HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 167221603Sadrian 168239631Sadrian HAL_CAP_LDPC = 99, 169239631Sadrian 170221603Sadrian HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 171239631Sadrian 172251360Sadrian HAL_CAP_ANT_DIV_COMB = 105, /* Enable antenna diversity/combining */ 173239631Sadrian HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */ 174239631Sadrian HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */ 175239631Sadrian HAL_CAP_LDPCWAR = 108, 176239631Sadrian HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */ 177239631Sadrian HAL_CAP_ENABLE_APM = 110, /* APM enabled */ 178239631Sadrian HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111, 179239631Sadrian HAL_CAP_PCIE_LCR_OFFSET = 112, 180239631Sadrian 181222584Sadrian HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 182239632Sadrian HAL_CAP_MCI = 118, 183239632Sadrian HAL_CAP_SMARTANTENNA = 119, 184239632Sadrian HAL_CAP_TRAFFIC_FAST_RECOVER = 120, 185239632Sadrian HAL_CAP_TX_DIVERSITY = 121, 186239632Sadrian HAL_CAP_CRDC = 122, 187221603Sadrian 188221581Sadrian /* The following are private to the FreeBSD HAL (224 onward) */ 189221581Sadrian 190221603Sadrian HAL_CAP_INTMIT = 229, /* interference mitigation */ 191221603Sadrian HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 192221603Sadrian HAL_CAP_BB_HANG = 235, /* can baseband hang */ 193221603Sadrian HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 194221603Sadrian HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 195221603Sadrian HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 196221603Sadrian HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 197225444Sadrian HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 198226488Sadrian HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 199227410Sadrian HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 200243743Sadrian HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */ 201251400Sadrian HAL_CAP_RX_LNA_MIXING = 247, /* RX hardware uses LNA mixing */ 202185377Ssam} HAL_CAPABILITY_TYPE; 203185377Ssam 204185377Ssam/* 205185377Ssam * "States" for setting the LED. These correspond to 206185377Ssam * the possible 802.11 operational states and there may 207185377Ssam * be a many-to-one mapping between these states and the 208185377Ssam * actual hardware state for the LED's (i.e. the hardware 209185377Ssam * may have fewer states). 210185377Ssam */ 211185377Ssamtypedef enum { 212185377Ssam HAL_LED_INIT = 0, 213185377Ssam HAL_LED_SCAN = 1, 214185377Ssam HAL_LED_AUTH = 2, 215185377Ssam HAL_LED_ASSOC = 3, 216185377Ssam HAL_LED_RUN = 4 217185377Ssam} HAL_LED_STATE; 218185377Ssam 219185377Ssam/* 220185377Ssam * Transmit queue types/numbers. These are used to tag 221185377Ssam * each transmit queue in the hardware and to identify a set 222185377Ssam * of transmit queues for operations such as start/stop dma. 223185377Ssam */ 224185377Ssamtypedef enum { 225185377Ssam HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 226185377Ssam HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 227185377Ssam HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 228185377Ssam HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 229185377Ssam HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 230219790Sadrian HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 231237874Sadrian HAL_TX_QUEUE_CFEND = 6, 232237874Sadrian HAL_TX_QUEUE_PAPRD = 7, 233185377Ssam} HAL_TX_QUEUE; 234185377Ssam 235185377Ssam#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 236185377Ssam 237242407Sadrian/* 238242407Sadrian * Receive queue types. These are used to tag 239242407Sadrian * each transmit queue in the hardware and to identify a set 240242407Sadrian * of transmit queues for operations such as start/stop dma. 241242407Sadrian */ 242237874Sadriantypedef enum { 243237874Sadrian HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 244238280Sadrian HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 245237874Sadrian} HAL_RX_QUEUE; 246237874Sadrian 247237874Sadrian#define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 248237874Sadrian 249238857Sadrian#define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */ 250238857Sadrian 251185377Ssam/* 252185377Ssam * Transmit queue subtype. These map directly to 253185377Ssam * WME Access Categories (except for UPSD). Refer 254185377Ssam * to Table 5 of the WME spec. 255185377Ssam */ 256185377Ssamtypedef enum { 257185377Ssam HAL_WME_AC_BK = 0, /* background access category */ 258185377Ssam HAL_WME_AC_BE = 1, /* best effort access category*/ 259185377Ssam HAL_WME_AC_VI = 2, /* video access category */ 260185377Ssam HAL_WME_AC_VO = 3, /* voice access category */ 261185377Ssam HAL_WME_UPSD = 4, /* uplink power save */ 262185377Ssam} HAL_TX_QUEUE_SUBTYPE; 263185377Ssam 264185377Ssam/* 265185377Ssam * Transmit queue flags that control various 266185377Ssam * operational parameters. 267185377Ssam */ 268185377Ssamtypedef enum { 269185377Ssam /* 270185377Ssam * Per queue interrupt enables. When set the associated 271185377Ssam * interrupt may be delivered for packets sent through 272185377Ssam * the queue. Without these enabled no interrupts will 273185377Ssam * be delivered for transmits through the queue. 274185377Ssam */ 275185377Ssam HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 276185377Ssam HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 277185377Ssam HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 278185377Ssam HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 279185377Ssam HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 280185377Ssam /* 281185377Ssam * Enable hardware compression for packets sent through 282185377Ssam * the queue. The compression buffer must be setup and 283185377Ssam * packets must have a key entry marked in the tx descriptor. 284185377Ssam */ 285185377Ssam HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 286185377Ssam /* 287185377Ssam * Disable queue when veol is hit or ready time expires. 288185377Ssam * By default the queue is disabled only on reaching the 289185377Ssam * physical end of queue (i.e. a null link ptr in the 290185377Ssam * descriptor chain). 291185377Ssam */ 292185377Ssam HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 293185377Ssam /* 294185377Ssam * Schedule frames on delivery of a DBA (DMA Beacon Alert) 295185377Ssam * event. Frames will be transmitted only when this timer 296185377Ssam * fires, e.g to transmit a beacon in ap or adhoc modes. 297185377Ssam */ 298185377Ssam HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 299185377Ssam /* 300185377Ssam * Each transmit queue has a counter that is incremented 301185377Ssam * each time the queue is enabled and decremented when 302185377Ssam * the list of frames to transmit is traversed (or when 303185377Ssam * the ready time for the queue expires). This counter 304185377Ssam * must be non-zero for frames to be scheduled for 305185377Ssam * transmission. The following controls disable bumping 306185377Ssam * this counter under certain conditions. Typically this 307185377Ssam * is used to gate frames based on the contents of another 308185377Ssam * queue (e.g. CAB traffic may only follow a beacon frame). 309185377Ssam * These are meaningful only when frames are scheduled 310185377Ssam * with a non-ASAP policy (e.g. DBA-gated). 311185377Ssam */ 312185377Ssam HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 313185377Ssam HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 314185377Ssam 315185377Ssam /* 316185377Ssam * Fragment burst backoff policy. Normally the no backoff 317185377Ssam * is done after a successful transmission, the next fragment 318185377Ssam * is sent at SIFS. If this flag is set backoff is done 319185377Ssam * after each fragment, regardless whether it was ack'd or 320185377Ssam * not, after the backoff count reaches zero a normal channel 321185377Ssam * access procedure is done before the next transmit (i.e. 322185377Ssam * wait AIFS instead of SIFS). 323185377Ssam */ 324185377Ssam HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 325185377Ssam /* 326185377Ssam * Disable post-tx backoff following each frame. 327185377Ssam */ 328185377Ssam HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 329185377Ssam /* 330185377Ssam * DCU arbiter lockout control. This controls how 331185377Ssam * lower priority tx queues are handled with respect to 332185377Ssam * to a specific queue when multiple queues have frames 333185377Ssam * to send. No lockout means lower priority queues arbitrate 334185377Ssam * concurrently with this queue. Intra-frame lockout 335185377Ssam * means lower priority queues are locked out until the 336185377Ssam * current frame transmits (e.g. including backoffs and bursting). 337185377Ssam * Global lockout means nothing lower can arbitrary so 338185377Ssam * long as there is traffic activity on this queue (frames, 339185377Ssam * backoff, etc). 340185377Ssam */ 341185377Ssam HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 342185377Ssam HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 343185377Ssam 344185377Ssam HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 345185377Ssam HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 346185377Ssam} HAL_TX_QUEUE_FLAGS; 347185377Ssam 348185377Ssamtypedef struct { 349185377Ssam uint32_t tqi_ver; /* hal TXQ version */ 350185377Ssam HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 351185377Ssam HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 352185377Ssam uint32_t tqi_priority; /* (not used) */ 353185377Ssam uint32_t tqi_aifs; /* aifs */ 354185377Ssam uint32_t tqi_cwmin; /* cwMin */ 355185377Ssam uint32_t tqi_cwmax; /* cwMax */ 356185377Ssam uint16_t tqi_shretry; /* rts retry limit */ 357185377Ssam uint16_t tqi_lgretry; /* long retry limit (not used)*/ 358185377Ssam uint32_t tqi_cbrPeriod; /* CBR period (us) */ 359185377Ssam uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 360185377Ssam uint32_t tqi_burstTime; /* max burst duration (us) */ 361185377Ssam uint32_t tqi_readyTime; /* frame schedule time (us) */ 362185377Ssam uint32_t tqi_compBuf; /* comp buffer phys addr */ 363185377Ssam} HAL_TXQ_INFO; 364185377Ssam 365185377Ssam#define HAL_TQI_NONVAL 0xffff 366185377Ssam 367185377Ssam/* token to use for aifs, cwmin, cwmax */ 368185377Ssam#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 369185377Ssam 370185377Ssam/* compression definitions */ 371185377Ssam#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 372185377Ssam#define HAL_COMP_BUF_ALIGN_SIZE 512 373185377Ssam 374185377Ssam/* 375185377Ssam * Transmit packet types. This belongs in ah_desc.h, but 376185377Ssam * is here so we can give a proper type to various parameters 377185377Ssam * (and not require everyone include the file). 378185377Ssam * 379185377Ssam * NB: These values are intentionally assigned for 380185377Ssam * direct use when setting up h/w descriptors. 381185377Ssam */ 382185377Ssamtypedef enum { 383185377Ssam HAL_PKT_TYPE_NORMAL = 0, 384185377Ssam HAL_PKT_TYPE_ATIM = 1, 385185377Ssam HAL_PKT_TYPE_PSPOLL = 2, 386185377Ssam HAL_PKT_TYPE_BEACON = 3, 387185377Ssam HAL_PKT_TYPE_PROBE_RESP = 4, 388185377Ssam HAL_PKT_TYPE_CHIRP = 5, 389185377Ssam HAL_PKT_TYPE_GRP_POLL = 6, 390185377Ssam HAL_PKT_TYPE_AMPDU = 7, 391185377Ssam} HAL_PKT_TYPE; 392185377Ssam 393185377Ssam/* Rx Filter Frame Types */ 394185377Ssamtypedef enum { 395220022Sadrian /* 396220022Sadrian * These bits correspond to AR_RX_FILTER for all chips. 397220022Sadrian * Not all bits are supported by all chips. 398220022Sadrian */ 399185377Ssam HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 400185377Ssam HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 401185377Ssam HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 402185377Ssam HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 403185377Ssam HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 404185377Ssam HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 405185377Ssam HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 406220025Sadrian HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 407185377Ssam HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 408220022Sadrian HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 409220025Sadrian HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 410220022Sadrian HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 411220022Sadrian HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 412220022Sadrian /* Allow all mcast/bcast frames */ 413220022Sadrian 414220022Sadrian /* 415220022Sadrian * Magic RX filter flags that aren't targetting hardware bits 416220022Sadrian * but instead the HAL sets individual bits - eg PHYERR will result 417220022Sadrian * in OFDM/CCK timing error frames being received. 418220022Sadrian */ 419220022Sadrian HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 420185377Ssam} HAL_RX_FILTER; 421185377Ssam 422185377Ssamtypedef enum { 423185377Ssam HAL_PM_AWAKE = 0, 424185377Ssam HAL_PM_FULL_SLEEP = 1, 425185377Ssam HAL_PM_NETWORK_SLEEP = 2, 426185377Ssam HAL_PM_UNDEFINED = 3 427185377Ssam} HAL_POWER_MODE; 428185377Ssam 429185377Ssam/* 430242407Sadrian * Enterprise mode flags 431242407Sadrian */ 432242407Sadrian#define AH_ENT_DUAL_BAND_DISABLE 0x00000001 433242407Sadrian#define AH_ENT_CHAIN2_DISABLE 0x00000002 434242407Sadrian#define AH_ENT_5MHZ_DISABLE 0x00000004 435242407Sadrian#define AH_ENT_10MHZ_DISABLE 0x00000008 436242407Sadrian#define AH_ENT_49GHZ_DISABLE 0x00000010 437242407Sadrian#define AH_ENT_LOOPBACK_DISABLE 0x00000020 438242407Sadrian#define AH_ENT_TPC_PERF_DISABLE 0x00000040 439242407Sadrian#define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080 440242407Sadrian#define AH_ENT_SPECTRAL_PRECISION 0x00000300 441242407Sadrian#define AH_ENT_SPECTRAL_PRECISION_S 8 442242407Sadrian#define AH_ENT_RTSCTS_DELIM_WAR 0x00010000 443242407Sadrian 444242407Sadrian#define AH_FIRST_DESC_NDELIMS 60 445242407Sadrian 446242407Sadrian/* 447185377Ssam * NOTE WELL: 448185377Ssam * These are mapped to take advantage of the common locations for many of 449185377Ssam * the bits on all of the currently supported MAC chips. This is to make 450185377Ssam * the ISR as efficient as possible, while still abstracting HW differences. 451185377Ssam * When new hardware breaks this commonality this enumerated type, as well 452185377Ssam * as the HAL functions using it, must be modified. All values are directly 453185377Ssam * mapped unless commented otherwise. 454185377Ssam */ 455185377Ssamtypedef enum { 456185377Ssam HAL_INT_RX = 0x00000001, /* Non-common mapping */ 457238349Sadrian HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */ 458239605Sadrian HAL_INT_RXERR = 0x00000004, 459238349Sadrian HAL_INT_RXHP = 0x00000001, /* EDMA */ 460238349Sadrian HAL_INT_RXLP = 0x00000002, /* EDMA */ 461185377Ssam HAL_INT_RXNOFRM = 0x00000008, 462185377Ssam HAL_INT_RXEOL = 0x00000010, 463185377Ssam HAL_INT_RXORN = 0x00000020, 464185377Ssam HAL_INT_TX = 0x00000040, /* Non-common mapping */ 465185377Ssam HAL_INT_TXDESC = 0x00000080, 466208711Srpaulo HAL_INT_TIM_TIMER= 0x00000100, 467239605Sadrian HAL_INT_MCI = 0x00000200, 468239605Sadrian HAL_INT_BBPANIC = 0x00000400, 469185377Ssam HAL_INT_TXURN = 0x00000800, 470185377Ssam HAL_INT_MIB = 0x00001000, 471185377Ssam HAL_INT_RXPHY = 0x00004000, 472185377Ssam HAL_INT_RXKCM = 0x00008000, 473185377Ssam HAL_INT_SWBA = 0x00010000, 474239605Sadrian HAL_INT_BRSSI = 0x00020000, 475185377Ssam HAL_INT_BMISS = 0x00040000, 476192401Ssam HAL_INT_BNR = 0x00100000, 477185377Ssam HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 478185377Ssam HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 479185377Ssam HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 480185377Ssam HAL_INT_GPIO = 0x01000000, 481185377Ssam HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 482185377Ssam HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 483192400Ssam HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 484239605Sadrian /* Atheros ref driver has a generic timer interrupt now..*/ 485242407Sadrian HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */ 486185377Ssam HAL_INT_CST = 0x10000000, /* Non-common mapping */ 487185377Ssam HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 488185377Ssam HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 489185377Ssam#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 490185377Ssam HAL_INT_BMISC = HAL_INT_TIM 491185377Ssam | HAL_INT_DTIM 492185377Ssam | HAL_INT_DTIMSYNC 493192400Ssam | HAL_INT_CABEND 494192400Ssam | HAL_INT_TBTT, 495185377Ssam 496185377Ssam /* Interrupt bits that map directly to ISR/IMR bits */ 497185377Ssam HAL_INT_COMMON = HAL_INT_RXNOFRM 498185377Ssam | HAL_INT_RXDESC 499185377Ssam | HAL_INT_RXEOL 500185377Ssam | HAL_INT_RXORN 501192396Ssam | HAL_INT_TXDESC 502185377Ssam | HAL_INT_TXURN 503185377Ssam | HAL_INT_MIB 504185377Ssam | HAL_INT_RXPHY 505185377Ssam | HAL_INT_RXKCM 506185377Ssam | HAL_INT_SWBA 507185377Ssam | HAL_INT_BMISS 508239605Sadrian | HAL_INT_BRSSI 509192397Ssam | HAL_INT_BNR 510185377Ssam | HAL_INT_GPIO, 511185377Ssam} HAL_INT; 512185377Ssam 513237622Sadrian/* 514237622Sadrian * MSI vector assignments 515237622Sadrian */ 516185377Ssamtypedef enum { 517237622Sadrian HAL_MSIVEC_MISC = 0, 518237622Sadrian HAL_MSIVEC_TX = 1, 519237622Sadrian HAL_MSIVEC_RXLP = 2, 520237622Sadrian HAL_MSIVEC_RXHP = 3, 521237622Sadrian} HAL_MSIVEC; 522237622Sadrian 523237622Sadriantypedef enum { 524237622Sadrian HAL_INT_LINE = 0, 525237622Sadrian HAL_INT_MSI = 1, 526237622Sadrian} HAL_INT_TYPE; 527237622Sadrian 528237622Sadrian/* For interrupt mitigation registers */ 529237622Sadriantypedef enum { 530237622Sadrian HAL_INT_RX_FIRSTPKT=0, 531237622Sadrian HAL_INT_RX_LASTPKT, 532237622Sadrian HAL_INT_TX_FIRSTPKT, 533237622Sadrian HAL_INT_TX_LASTPKT, 534237622Sadrian HAL_INT_THRESHOLD 535237622Sadrian} HAL_INT_MITIGATION; 536237622Sadrian 537242407Sadrian/* XXX this is duplicate information! */ 538242407Sadriantypedef struct { 539242407Sadrian u_int32_t cyclecnt_diff; /* delta cycle count */ 540242407Sadrian u_int32_t rxclr_cnt; /* rx clear count */ 541242407Sadrian u_int32_t txframecnt_diff; /* delta tx frame count */ 542242407Sadrian u_int32_t rxframecnt_diff; /* delta rx frame count */ 543242407Sadrian u_int32_t listen_time; /* listen time in msec - time for which ch is free */ 544242407Sadrian u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */ 545242407Sadrian u_int32_t cckphyerr_cnt; /* CCK err count since last reset */ 546242407Sadrian u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */ 547242407Sadrian HAL_BOOL valid; /* if the stats are valid*/ 548242407Sadrian} HAL_ANISTATS; 549242407Sadrian 550242407Sadriantypedef struct { 551242407Sadrian u_int8_t txctl_offset; 552242407Sadrian u_int8_t txctl_numwords; 553242407Sadrian u_int8_t txstatus_offset; 554242407Sadrian u_int8_t txstatus_numwords; 555242407Sadrian 556242407Sadrian u_int8_t rxctl_offset; 557242407Sadrian u_int8_t rxctl_numwords; 558242407Sadrian u_int8_t rxstatus_offset; 559242407Sadrian u_int8_t rxstatus_numwords; 560242407Sadrian 561242407Sadrian u_int8_t macRevision; 562242407Sadrian} HAL_DESC_INFO; 563242407Sadrian 564237622Sadriantypedef enum { 565237611Sadrian HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 566237611Sadrian HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 567237611Sadrian HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 568237611Sadrian HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 569237611Sadrian HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 570237611Sadrian HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 571249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6, 572249131Sadrian 573249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA, 574249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK, 575249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA, 576249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK, 577249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX, 578249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX, 579249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX, 580249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX, 581249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE, 582249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA, 583249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0, 584249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1, 585249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2, 586249131Sadrian HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES 587188974Ssam} HAL_GPIO_MUX_TYPE; 588188974Ssam 589188974Ssamtypedef enum { 590188974Ssam HAL_GPIO_INTR_LOW = 0, 591188974Ssam HAL_GPIO_INTR_HIGH = 1, 592188974Ssam HAL_GPIO_INTR_DISABLE = 2 593188974Ssam} HAL_GPIO_INTR_TYPE; 594188974Ssam 595242509Sadriantypedef struct halCounters { 596242509Sadrian u_int32_t tx_frame_count; 597242509Sadrian u_int32_t rx_frame_count; 598242509Sadrian u_int32_t rx_clear_count; 599242509Sadrian u_int32_t cycle_count; 600242509Sadrian u_int8_t is_rx_active; // true (1) or false (0) 601242509Sadrian u_int8_t is_tx_active; // true (1) or false (0) 602242509Sadrian} HAL_COUNTERS; 603242509Sadrian 604188974Ssamtypedef enum { 605185377Ssam HAL_RFGAIN_INACTIVE = 0, 606185377Ssam HAL_RFGAIN_READ_REQUESTED = 1, 607185377Ssam HAL_RFGAIN_NEED_CHANGE = 2 608185377Ssam} HAL_RFGAIN; 609185377Ssam 610187831Ssamtypedef uint16_t HAL_CTRY_CODE; /* country code */ 611187831Ssamtypedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 612185377Ssam 613185377Ssam#define HAL_ANTENNA_MIN_MODE 0 614185377Ssam#define HAL_ANTENNA_FIXED_A 1 615185377Ssam#define HAL_ANTENNA_FIXED_B 2 616185377Ssam#define HAL_ANTENNA_MAX_MODE 3 617185377Ssam 618185377Ssamtypedef struct { 619185377Ssam uint32_t ackrcv_bad; 620185377Ssam uint32_t rts_bad; 621185377Ssam uint32_t rts_good; 622185377Ssam uint32_t fcs_bad; 623185377Ssam uint32_t beacons; 624185377Ssam} HAL_MIB_STATS; 625185377Ssam 626242407Sadrian/* 627242407Sadrian * These bits represent what's in ah_currentRDext. 628242407Sadrian */ 629242407Sadriantypedef enum { 630242407Sadrian REG_EXT_FCC_MIDBAND = 0, 631242407Sadrian REG_EXT_JAPAN_MIDBAND = 1, 632242407Sadrian REG_EXT_FCC_DFS_HT40 = 2, 633242407Sadrian REG_EXT_JAPAN_NONDFS_HT40 = 3, 634242407Sadrian REG_EXT_JAPAN_DFS_HT40 = 4 635242407Sadrian} REG_EXT_BITMAP; 636242407Sadrian 637185377Ssamenum { 638185377Ssam HAL_MODE_11A = 0x001, /* 11a channels */ 639185377Ssam HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 640185377Ssam HAL_MODE_11B = 0x004, /* 11b channels */ 641185377Ssam HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 642185377Ssam#ifdef notdef 643185377Ssam HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 644185377Ssam#else 645185377Ssam HAL_MODE_11G = 0x008, /* XXX historical */ 646185377Ssam#endif 647185377Ssam HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 648185377Ssam HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 649185380Ssam HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 650185380Ssam HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 651185380Ssam HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 652185380Ssam HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 653185377Ssam HAL_MODE_11NG_HT20 = 0x008000, 654185377Ssam HAL_MODE_11NA_HT20 = 0x010000, 655185377Ssam HAL_MODE_11NG_HT40PLUS = 0x020000, 656185377Ssam HAL_MODE_11NG_HT40MINUS = 0x040000, 657185377Ssam HAL_MODE_11NA_HT40PLUS = 0x080000, 658185377Ssam HAL_MODE_11NA_HT40MINUS = 0x100000, 659185377Ssam HAL_MODE_ALL = 0xffffff 660185377Ssam}; 661185377Ssam 662185377Ssamtypedef struct { 663185377Ssam int rateCount; /* NB: for proper padding */ 664239289Sadrian uint8_t rateCodeToIndex[256]; /* back mapping */ 665185377Ssam struct { 666188770Ssam uint8_t valid; /* valid for rate control use */ 667188770Ssam uint8_t phy; /* CCK/OFDM/XR */ 668185377Ssam uint32_t rateKbps; /* transfer rate in kbs */ 669185377Ssam uint8_t rateCode; /* rate for h/w descriptors */ 670185377Ssam uint8_t shortPreamble; /* mask for enabling short 671185377Ssam * preamble in CCK rate code */ 672185377Ssam uint8_t dot11Rate; /* value for supported rates 673185377Ssam * info element of MLME */ 674185377Ssam uint8_t controlRate; /* index of next lower basic 675185377Ssam * rate; used for dur. calcs */ 676185377Ssam uint16_t lpAckDuration; /* long preamble ACK duration */ 677185377Ssam uint16_t spAckDuration; /* short preamble ACK duration*/ 678239289Sadrian } info[64]; 679185377Ssam} HAL_RATE_TABLE; 680185377Ssam 681185377Ssamtypedef struct { 682185377Ssam u_int rs_count; /* number of valid entries */ 683239289Sadrian uint8_t rs_rates[64]; /* rates */ 684185377Ssam} HAL_RATE_SET; 685185377Ssam 686185377Ssam/* 687185377Ssam * 802.11n specific structures and enums 688185377Ssam */ 689185377Ssamtypedef enum { 690185377Ssam HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 691185377Ssam HAL_CHAINTYPE_RX = 2, /* RX chain type */ 692185377Ssam} HAL_CHAIN_TYPE; 693185377Ssam 694185377Ssamtypedef struct { 695185377Ssam u_int Tries; 696238840Sadrian u_int Rate; /* hardware rate code */ 697238840Sadrian u_int RateIndex; /* rate series table index */ 698185377Ssam u_int PktDuration; 699185377Ssam u_int ChSel; 700185377Ssam u_int RateFlags; 701185377Ssam#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 702185377Ssam#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 703185377Ssam#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 704238841Sadrian#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ 705242407Sadrian u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */ 706185377Ssam} HAL_11N_RATE_SERIES; 707185377Ssam 708185377Ssamtypedef enum { 709185377Ssam HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 710185377Ssam HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 711185377Ssam} HAL_HT_MACMODE; 712185377Ssam 713185377Ssamtypedef enum { 714185377Ssam HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 715185377Ssam HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 716185377Ssam} HAL_HT_PHYMODE; 717185377Ssam 718185377Ssamtypedef enum { 719185377Ssam HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 720185377Ssam HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 721185377Ssam} HAL_HT_EXTPROTSPACING; 722185377Ssam 723185377Ssam 724185377Ssamtypedef enum { 725185377Ssam HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 726185377Ssam HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 727185377Ssam} HAL_HT_RXCLEAR; 728185377Ssam 729242407Sadriantypedef enum { 730242407Sadrian HAL_FREQ_BAND_5GHZ = 0, 731242407Sadrian HAL_FREQ_BAND_2GHZ = 1, 732242407Sadrian} HAL_FREQ_BAND; 733242407Sadrian 734185377Ssam/* 735185377Ssam * Antenna switch control. By default antenna selection 736185377Ssam * enables multiple (2) antenna use. To force use of the 737185377Ssam * A or B antenna only specify a fixed setting. Fixing 738185377Ssam * the antenna will also disable any diversity support. 739185377Ssam */ 740185377Ssamtypedef enum { 741185377Ssam HAL_ANT_VARIABLE = 0, /* variable by programming */ 742185377Ssam HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 743185377Ssam HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 744185377Ssam} HAL_ANT_SETTING; 745185377Ssam 746185377Ssamtypedef enum { 747185377Ssam HAL_M_STA = 1, /* infrastructure station */ 748185377Ssam HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 749185377Ssam HAL_M_HOSTAP = 6, /* Software Access Point */ 750185377Ssam HAL_M_MONITOR = 8 /* Monitor mode */ 751185377Ssam} HAL_OPMODE; 752185377Ssam 753185377Ssamtypedef struct { 754185377Ssam uint8_t kv_type; /* one of HAL_CIPHER */ 755237874Sadrian uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 756185377Ssam uint16_t kv_len; /* length in bits */ 757185377Ssam uint8_t kv_val[16]; /* enough for 128-bit keys */ 758185377Ssam uint8_t kv_mic[8]; /* TKIP MIC key */ 759185377Ssam uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 760185377Ssam} HAL_KEYVAL; 761185377Ssam 762242407Sadrian/* 763242407Sadrian * This is the TX descriptor field which marks the key padding requirement. 764242407Sadrian * The naming is unfortunately unclear. 765242407Sadrian */ 766242407Sadrian#define AH_KEYTYPE_MASK 0x0F 767185377Ssamtypedef enum { 768242407Sadrian HAL_KEY_TYPE_CLEAR, 769242407Sadrian HAL_KEY_TYPE_WEP, 770242407Sadrian HAL_KEY_TYPE_AES, 771242407Sadrian HAL_KEY_TYPE_TKIP, 772242407Sadrian} HAL_KEY_TYPE; 773242407Sadrian 774242407Sadriantypedef enum { 775185377Ssam HAL_CIPHER_WEP = 0, 776185377Ssam HAL_CIPHER_AES_OCB = 1, 777185377Ssam HAL_CIPHER_AES_CCM = 2, 778185377Ssam HAL_CIPHER_CKIP = 3, 779185377Ssam HAL_CIPHER_TKIP = 4, 780185377Ssam HAL_CIPHER_CLR = 5, /* no encryption */ 781185377Ssam 782185377Ssam HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 783185377Ssam} HAL_CIPHER; 784185377Ssam 785185377Ssamenum { 786185377Ssam HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 787185377Ssam HAL_SLOT_TIME_9 = 9, 788185377Ssam HAL_SLOT_TIME_20 = 20, 789185377Ssam}; 790185377Ssam 791185377Ssam/* 792185377Ssam * Per-station beacon timer state. Note that the specified 793185377Ssam * beacon interval (given in TU's) can also include flags 794185377Ssam * to force a TSF reset and to enable the beacon xmit logic. 795185377Ssam * If bs_cfpmaxduration is non-zero the hardware is setup to 796185377Ssam * coexist with a PCF-capable AP. 797185377Ssam */ 798185377Ssamtypedef struct { 799185377Ssam uint32_t bs_nexttbtt; /* next beacon in TU */ 800185377Ssam uint32_t bs_nextdtim; /* next DTIM in TU */ 801185377Ssam uint32_t bs_intval; /* beacon interval+flags */ 802243589Sadrian/* 803243589Sadrian * HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF 804243589Sadrian * are all 1:1 correspondances with the pre-11n chip AR_BEACON 805243589Sadrian * register. 806243589Sadrian */ 807185377Ssam#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 808242407Sadrian#define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */ 809185377Ssam#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 810185377Ssam#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 811242407Sadrian#define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */ 812185377Ssam uint32_t bs_dtimperiod; 813185377Ssam uint16_t bs_cfpperiod; /* CFP period in TU */ 814185377Ssam uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 815185377Ssam uint32_t bs_cfpnext; /* next CFP in TU */ 816185377Ssam uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 817185377Ssam uint16_t bs_bmissthreshold; /* beacon miss threshold */ 818185377Ssam uint32_t bs_sleepduration; /* max sleep duration */ 819242407Sadrian uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */ 820185377Ssam} HAL_BEACON_STATE; 821185377Ssam 822185377Ssam/* 823185377Ssam * Like HAL_BEACON_STATE but for non-station mode setup. 824185377Ssam * NB: see above flag definitions for bt_intval. 825185377Ssam */ 826185377Ssamtypedef struct { 827185377Ssam uint32_t bt_intval; /* beacon interval+flags */ 828185377Ssam uint32_t bt_nexttbtt; /* next beacon in TU */ 829185377Ssam uint32_t bt_nextatim; /* next ATIM in TU */ 830185377Ssam uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 831185377Ssam uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 832185377Ssam uint32_t bt_flags; /* timer enables */ 833185377Ssam#define HAL_BEACON_TBTT_EN 0x00000001 834185377Ssam#define HAL_BEACON_DBA_EN 0x00000002 835185377Ssam#define HAL_BEACON_SWBA_EN 0x00000004 836185377Ssam} HAL_BEACON_TIMERS; 837185377Ssam 838185377Ssam/* 839185377Ssam * Per-node statistics maintained by the driver for use in 840185377Ssam * optimizing signal quality and other operational aspects. 841185377Ssam */ 842185377Ssamtypedef struct { 843185377Ssam uint32_t ns_avgbrssi; /* average beacon rssi */ 844185377Ssam uint32_t ns_avgrssi; /* average data rssi */ 845185377Ssam uint32_t ns_avgtxrssi; /* average tx rssi */ 846185377Ssam} HAL_NODE_STATS; 847185377Ssam 848185377Ssam#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 849185377Ssam 850242407Sadrian 851185377Ssamstruct ath_desc; 852185377Ssamstruct ath_tx_status; 853185377Ssamstruct ath_rx_status; 854187831Ssamstruct ieee80211_channel; 855185377Ssam 856185377Ssam/* 857219773Sadrian * This is a channel survey sample entry. 858219773Sadrian * 859219773Sadrian * The AR5212 ANI routines fill these samples. The ANI code then uses it 860219773Sadrian * when calculating listen time; it is also exported via a diagnostic 861219773Sadrian * API. 862219773Sadrian */ 863219773Sadriantypedef struct { 864219773Sadrian uint32_t seq_num; 865219773Sadrian uint32_t tx_busy; 866219773Sadrian uint32_t rx_busy; 867219773Sadrian uint32_t chan_busy; 868234749Sadrian uint32_t ext_chan_busy; 869219773Sadrian uint32_t cycle_count; 870234749Sadrian /* XXX TODO */ 871234749Sadrian uint32_t ofdm_phyerr_count; 872234749Sadrian uint32_t cck_phyerr_count; 873219773Sadrian} HAL_SURVEY_SAMPLE; 874219773Sadrian 875219773Sadrian/* 876219773Sadrian * This provides 3.2 seconds of sample space given an 877219773Sadrian * ANI time of 1/10th of a second. This may not be enough! 878219773Sadrian */ 879219773Sadrian#define CHANNEL_SURVEY_SAMPLE_COUNT 32 880219773Sadrian 881219773Sadriantypedef struct { 882219773Sadrian HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 883219773Sadrian uint32_t cur_sample; /* current sample in sequence */ 884219773Sadrian uint32_t cur_seq; /* current sequence number */ 885219773Sadrian} HAL_CHANNEL_SURVEY; 886219773Sadrian 887219773Sadrian/* 888222277Sadrian * ANI commands. 889222277Sadrian * 890222277Sadrian * These are used both internally and externally via the diagnostic 891222277Sadrian * API. 892222277Sadrian * 893222277Sadrian * Note that this is NOT the ANI commands being used via the INTMIT 894222277Sadrian * capability - that has a different mapping for some reason. 895222277Sadrian */ 896222277Sadriantypedef enum { 897222277Sadrian HAL_ANI_PRESENT = 0, /* is ANI support present */ 898222277Sadrian HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 899222277Sadrian HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 900222277Sadrian HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 901222277Sadrian HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 902222277Sadrian HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 903222277Sadrian HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 904222277Sadrian HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 905237874Sadrian HAL_ANI_MRC_CCK = 8, 906222277Sadrian} HAL_ANI_CMD; 907222277Sadrian 908242407Sadrian#define HAL_ANI_ALL 0xffffffff 909242407Sadrian 910222277Sadrian/* 911222277Sadrian * This is the layout of the ANI INTMIT capability. 912222277Sadrian * 913222277Sadrian * Notice that the command values differ to HAL_ANI_CMD. 914222277Sadrian */ 915222277Sadriantypedef enum { 916222277Sadrian HAL_CAP_INTMIT_PRESENT = 0, 917222277Sadrian HAL_CAP_INTMIT_ENABLE = 1, 918222277Sadrian HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 919222277Sadrian HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 920222277Sadrian HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 921222277Sadrian HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 922222277Sadrian HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 923222277Sadrian} HAL_CAP_INTMIT_CMD; 924222277Sadrian 925222584Sadriantypedef struct { 926222584Sadrian int32_t pe_firpwr; /* FIR pwr out threshold */ 927222584Sadrian int32_t pe_rrssi; /* Radar rssi thresh */ 928222584Sadrian int32_t pe_height; /* Pulse height thresh */ 929222584Sadrian int32_t pe_prssi; /* Pulse rssi thresh */ 930222584Sadrian int32_t pe_inband; /* Inband thresh */ 931222584Sadrian 932222584Sadrian /* The following params are only for AR5413 and later */ 933222584Sadrian u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 934222584Sadrian u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 935222584Sadrian u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 936224244Sadrian int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 937224244Sadrian int32_t pe_blockradar; /* 938222584Sadrian * Enable to block radar check if pkt detect is done via OFDM 939222584Sadrian * weak signal detect or pkt is detected immediately after tx 940222584Sadrian * to rx transition 941222584Sadrian */ 942224244Sadrian int32_t pe_enmaxrssi; /* 943222584Sadrian * Enable to use the max rssi instead of the last rssi during 944222584Sadrian * fine gain changes for radar detection 945222584Sadrian */ 946224244Sadrian int32_t pe_extchannel; /* Enable DFS on ext channel */ 947224244Sadrian int32_t pe_enabled; /* Whether radar detection is enabled */ 948231708Sadrian int32_t pe_enrelpwr; 949231708Sadrian int32_t pe_en_relstep_check; 950222584Sadrian} HAL_PHYERR_PARAM; 951222584Sadrian 952222584Sadrian#define HAL_PHYERR_PARAM_NOVAL 65535 953222584Sadrian 954244854Sadriantypedef struct { 955244854Sadrian u_int16_t ss_fft_period; /* Skip interval for FFT reports */ 956244854Sadrian u_int16_t ss_period; /* Spectral scan period */ 957244854Sadrian u_int16_t ss_count; /* # of reports to return from ss_active */ 958244854Sadrian u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */ 959244854Sadrian u_int8_t radar_bin_thresh_sel; /* strong signal radar FFT threshold configuration */ 960244854Sadrian u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */ 961244854Sadrian int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */ 962244854Sadrian int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */ 963244854Sadrian int32_t ss_nf_temp_data; /* temperature data taken during nf scan */ 964245281Sadrian int ss_enabled; 965245281Sadrian int ss_active; 966244854Sadrian} HAL_SPECTRAL_PARAM; 967244854Sadrian#define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF 968244854Sadrian#define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 969244854Sadrian 970224716Sadrian/* 971224716Sadrian * DFS operating mode flags. 972224716Sadrian */ 973224716Sadriantypedef enum { 974224716Sadrian HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 975224716Sadrian HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 976224716Sadrian HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 977224716Sadrian HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 978224716Sadrian} HAL_DFS_DOMAIN; 979222584Sadrian 980242407Sadrian 981222277Sadrian/* 982239606Sadrian * MFP decryption options for initializing the MAC. 983239606Sadrian */ 984239606Sadriantypedef enum { 985239606Sadrian HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */ 986239606Sadrian HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */ 987239606Sadrian HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */ 988239606Sadrian} HAL_MFP_OPT_T; 989239606Sadrian 990239890Sadrian/* LNA config supported */ 991239890Sadriantypedef enum { 992239890Sadrian HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0, 993239890Sadrian HAL_ANT_DIV_COMB_LNA2 = 1, 994239890Sadrian HAL_ANT_DIV_COMB_LNA1 = 2, 995239890Sadrian HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3, 996239890Sadrian} HAL_ANT_DIV_COMB_LNA_CONF; 997239890Sadrian 998239890Sadriantypedef struct { 999239890Sadrian u_int8_t main_lna_conf; 1000239890Sadrian u_int8_t alt_lna_conf; 1001239890Sadrian u_int8_t fast_div_bias; 1002239890Sadrian u_int8_t main_gaintb; 1003239890Sadrian u_int8_t alt_gaintb; 1004239890Sadrian u_int8_t antdiv_configgroup; 1005239890Sadrian int8_t lna1_lna2_delta; 1006239890Sadrian} HAL_ANT_COMB_CONFIG; 1007239890Sadrian 1008239890Sadrian#define DEFAULT_ANTDIV_CONFIG_GROUP 0x00 1009239890Sadrian#define HAL_ANTDIV_CONFIG_GROUP_1 0x01 1010239890Sadrian#define HAL_ANTDIV_CONFIG_GROUP_2 0x02 1011239890Sadrian#define HAL_ANTDIV_CONFIG_GROUP_3 0x03 1012239890Sadrian 1013239606Sadrian/* 1014222644Sadrian * Flag for setting QUIET period 1015222644Sadrian */ 1016222644Sadriantypedef enum { 1017222644Sadrian HAL_QUIET_DISABLE = 0x0, 1018222644Sadrian HAL_QUIET_ENABLE = 0x1, 1019222644Sadrian HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 1020222644Sadrian HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 1021222644Sadrian} HAL_QUIET_FLAG; 1022222644Sadrian 1023222815Sadrian#define HAL_DFS_EVENT_PRICH 0x0000001 1024224539Sadrian#define HAL_DFS_EVENT_EXTCH 0x0000002 1025224539Sadrian#define HAL_DFS_EVENT_EXTEARLY 0x0000004 1026224539Sadrian#define HAL_DFS_EVENT_ISDC 0x0000008 1027222815Sadrian 1028224633Sadrianstruct hal_dfs_event { 1029222815Sadrian uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 1030222815Sadrian uint32_t re_ts; /* Original 15 bit recv timestamp */ 1031222815Sadrian uint8_t re_rssi; /* rssi of radar event */ 1032222815Sadrian uint8_t re_dur; /* duration of radar pulse */ 1033222815Sadrian uint32_t re_flags; /* Flags (see above) */ 1034222815Sadrian}; 1035224633Sadriantypedef struct hal_dfs_event HAL_DFS_EVENT; 1036222815Sadrian 1037237611Sadrian/* 1038242407Sadrian * Generic Timer domain 1039242407Sadrian */ 1040242407Sadriantypedef enum { 1041242407Sadrian HAL_GEN_TIMER_TSF = 0, 1042242407Sadrian HAL_GEN_TIMER_TSF2, 1043242407Sadrian HAL_GEN_TIMER_TSF_ANY 1044242407Sadrian} HAL_GEN_TIMER_DOMAIN; 1045242407Sadrian 1046242407Sadriantypedef enum { 1047242407Sadrian HAL_RESET_NONE = 0x0, 1048242407Sadrian HAL_RESET_BBPANIC = 0x1, 1049242407Sadrian} HAL_RESET_TYPE; 1050242407Sadrian 1051242407Sadrian/* 1052237611Sadrian * BT Co-existence definitions 1053237611Sadrian */ 1054237611Sadriantypedef enum { 1055237611Sadrian HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */ 1056237611Sadrian HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */ 1057237611Sadrian HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */ 1058237611Sadrian HAL_MAX_BT_MODULES 1059237611Sadrian} HAL_BT_MODULE; 1060237611Sadrian 1061237611Sadriantypedef struct { 1062237611Sadrian HAL_BT_MODULE bt_module; 1063237611Sadrian u_int8_t bt_coex_config; 1064237611Sadrian u_int8_t bt_gpio_bt_active; 1065237611Sadrian u_int8_t bt_gpio_bt_priority; 1066237611Sadrian u_int8_t bt_gpio_wlan_active; 1067237611Sadrian u_int8_t bt_active_polarity; 1068237611Sadrian HAL_BOOL bt_single_ant; 1069237611Sadrian u_int8_t bt_dutyCycle; 1070237611Sadrian u_int8_t bt_isolation; 1071237611Sadrian u_int8_t bt_period; 1072237611Sadrian} HAL_BT_COEX_INFO; 1073237611Sadrian 1074237611Sadriantypedef enum { 1075237611Sadrian HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */ 1076237611Sadrian HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */ 1077237611Sadrian HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */ 1078237611Sadrian HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */ 1079237611Sadrian} HAL_BT_COEX_MODE; 1080237611Sadrian 1081237611Sadriantypedef enum { 1082237611Sadrian HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */ 1083237611Sadrian HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */ 1084237611Sadrian HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */ 1085237611Sadrian HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */ 1086237611Sadrian HAL_BT_COEX_CFG_3WIRE, /* 3-wire */ 1087237611Sadrian HAL_BT_COEX_CFG_MCI /* MCI */ 1088237611Sadrian} HAL_BT_COEX_CFG; 1089237611Sadrian 1090237611Sadriantypedef enum { 1091237611Sadrian HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */ 1092237611Sadrian HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */ 1093237611Sadrian HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */ 1094249131Sadrian HAL_BT_COEX_MCI_MAX_TX_PWR, /* Set max tx power for concurrent tx */ 1095249131Sadrian HAL_BT_COEX_MCI_FTP_STOMP_RX, /* Use a different weight for stomp low */ 1096237611Sadrian} HAL_BT_COEX_SET_PARAMETER; 1097237611Sadrian 1098237611Sadrian#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 1099237611Sadrian#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 1100237611Sadrian/* Check Rx Diversity is allowed */ 1101237611Sadrian#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 1102237611Sadrian/* Check Diversity is on or off */ 1103237611Sadrian#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 1104237611Sadrian 1105237611Sadrian#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b 1106237611Sadrian/* main: LNA1, alt: LNA2 */ 1107237611Sadrian#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09 1108237611Sadrian#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04 1109237611Sadrian#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09 1110237611Sadrian#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02 1111237611Sadrian#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06 1112237611Sadrian 1113237611Sadrian#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30 1114237611Sadrian 1115237611Sadrian#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666 1116237611Sadrian 1117237611Sadrian#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02 1118237611Sadrian 1119237611Sadrian#define HAL_BT_COEX_LOW_ACK_POWER 0x0 1120237611Sadrian#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f 1121237611Sadrian 1122237611Sadriantypedef enum { 1123237611Sadrian HAL_BT_COEX_NO_STOMP = 0, 1124237611Sadrian HAL_BT_COEX_STOMP_ALL, 1125237611Sadrian HAL_BT_COEX_STOMP_LOW, 1126237611Sadrian HAL_BT_COEX_STOMP_NONE, 1127237611Sadrian HAL_BT_COEX_STOMP_ALL_FORCE, 1128237611Sadrian HAL_BT_COEX_STOMP_LOW_FORCE, 1129237611Sadrian} HAL_BT_COEX_STOMP_TYPE; 1130237611Sadrian 1131237611Sadriantypedef struct { 1132237611Sadrian /* extend rx_clear after tx/rx to protect the burst (in usec). */ 1133237611Sadrian u_int8_t bt_time_extend; 1134237611Sadrian 1135237611Sadrian /* 1136237611Sadrian * extend rx_clear as long as txsm is 1137237611Sadrian * transmitting or waiting for ack. 1138237611Sadrian */ 1139237611Sadrian HAL_BOOL bt_txstate_extend; 1140237611Sadrian 1141237611Sadrian /* 1142237611Sadrian * extend rx_clear so that when tx_frame 1143237611Sadrian * is asserted, rx_clear will drop. 1144237611Sadrian */ 1145237611Sadrian HAL_BOOL bt_txframe_extend; 1146237611Sadrian 1147237611Sadrian /* 1148237611Sadrian * coexistence mode 1149237611Sadrian */ 1150237611Sadrian HAL_BT_COEX_MODE bt_mode; 1151237611Sadrian 1152237611Sadrian /* 1153237611Sadrian * treat BT high priority traffic as 1154237611Sadrian * a quiet collision 1155237611Sadrian */ 1156237611Sadrian HAL_BOOL bt_quiet_collision; 1157237611Sadrian 1158237611Sadrian /* 1159237611Sadrian * invert rx_clear as WLAN_ACTIVE 1160237611Sadrian */ 1161237611Sadrian HAL_BOOL bt_rxclear_polarity; 1162237611Sadrian 1163237611Sadrian /* 1164237611Sadrian * slotted mode only. indicate the time in usec 1165237611Sadrian * from the rising edge of BT_ACTIVE to the time 1166237611Sadrian * BT_PRIORITY can be sampled to indicate priority. 1167237611Sadrian */ 1168237611Sadrian u_int8_t bt_priority_time; 1169237611Sadrian 1170237611Sadrian /* 1171237611Sadrian * slotted mode only. indicate the time in usec 1172237611Sadrian * from the rising edge of BT_ACTIVE to the time 1173237611Sadrian * BT_PRIORITY can be sampled to indicate tx/rx and 1174237611Sadrian * BT_FREQ is sampled. 1175237611Sadrian */ 1176237611Sadrian u_int8_t bt_first_slot_time; 1177237611Sadrian 1178237611Sadrian /* 1179237611Sadrian * slotted mode only. rx_clear and bt_ant decision 1180237611Sadrian * will be held the entire time that BT_ACTIVE is asserted, 1181237611Sadrian * otherwise the decision is made before every slot boundry. 1182237611Sadrian */ 1183237611Sadrian HAL_BOOL bt_hold_rxclear; 1184237611Sadrian} HAL_BT_COEX_CONFIG; 1185237611Sadrian 1186242407Sadrianstruct hal_bb_panic_info { 1187242407Sadrian u_int32_t status; 1188242407Sadrian u_int32_t tsf; 1189242407Sadrian u_int32_t phy_panic_wd_ctl1; 1190242407Sadrian u_int32_t phy_panic_wd_ctl2; 1191242407Sadrian u_int32_t phy_gen_ctrl; 1192242407Sadrian u_int32_t rxc_pcnt; 1193242407Sadrian u_int32_t rxf_pcnt; 1194242407Sadrian u_int32_t txf_pcnt; 1195242407Sadrian u_int32_t cycles; 1196242407Sadrian u_int32_t wd; 1197242407Sadrian u_int32_t det; 1198242407Sadrian u_int32_t rdar; 1199242407Sadrian u_int32_t r_odfm; 1200242407Sadrian u_int32_t r_cck; 1201242407Sadrian u_int32_t t_odfm; 1202242407Sadrian u_int32_t t_cck; 1203242407Sadrian u_int32_t agc; 1204242407Sadrian u_int32_t src; 1205242407Sadrian}; 1206242407Sadrian 1207242407Sadrian/* Serialize Register Access Mode */ 1208242407Sadriantypedef enum { 1209242407Sadrian SER_REG_MODE_OFF = 0, 1210242407Sadrian SER_REG_MODE_ON = 1, 1211242407Sadrian SER_REG_MODE_AUTO = 2, 1212242407Sadrian} SER_REG_MODE; 1213242407Sadrian 1214223459Sadriantypedef struct 1215223459Sadrian{ 1216223459Sadrian int ah_debug; /* only used if AH_DEBUG is defined */ 1217223459Sadrian int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 1218223459Sadrian 1219223459Sadrian /* NB: these are deprecated; they exist for now for compatibility */ 1220223459Sadrian int ah_dma_beacon_response_time;/* in TU's */ 1221223459Sadrian int ah_sw_beacon_response_time; /* in TU's */ 1222223459Sadrian int ah_additional_swba_backoff; /* in TU's */ 1223227375Sadrian int ah_force_full_reset; /* force full chip reset rather then warm reset */ 1224227410Sadrian int ah_serialise_reg_war; /* force serialisation of register IO */ 1225242407Sadrian 1226242407Sadrian /* XXX these don't belong here, they're just for the ar9300 HAL port effort */ 1227242407Sadrian int ath_hal_desc_tpc; /* Per-packet TPC */ 1228242407Sadrian int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */ 1229242407Sadrian int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */ 1230242407Sadrian int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */ 1231242407Sadrian int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */ 1232242407Sadrian 1233242407Sadrian /* I'm not sure what the default values for these should be */ 1234242407Sadrian int ath_hal_pll_pwr_save; 1235242407Sadrian int ath_hal_pcie_power_save_enable; 1236242407Sadrian int ath_hal_intr_mitigation_rx; 1237242407Sadrian int ath_hal_intr_mitigation_tx; 1238242407Sadrian 1239242407Sadrian int ath_hal_pcie_clock_req; 1240242407Sadrian#define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0) 1241242407Sadrian#define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1) 1242242407Sadrian#define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2) 1243242407Sadrian 1244242407Sadrian int ath_hal_pcie_waen; 1245242407Sadrian int ath_hal_pcie_ser_des_write; 1246242407Sadrian 1247242407Sadrian /* these are important for correct AR9300 behaviour */ 1248242407Sadrian int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */ 1249242407Sadrian int ath_hal_diversity_control; 1250242407Sadrian int ath_hal_antenna_switch_swap; 1251242407Sadrian int ath_hal_ext_lna_ctl_gpio; 1252242407Sadrian int ath_hal_spur_mode; 1253242407Sadrian int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */ 1254242407Sadrian int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */ 1255242407Sadrian int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */ 1256242407Sadrian 1257242407Sadrian /* For now, set this to 0 - net80211 needs to know about hardware MFP support */ 1258242407Sadrian int ath_hal_mfp_support; 1259242407Sadrian 1260242407Sadrian int ath_hal_enable_ani; /* should set this.. */ 1261242407Sadrian int ath_hal_cwm_ignore_ext_cca; 1262242407Sadrian int ath_hal_show_bb_panic; 1263242689Sadrian int ath_hal_ant_ctrl_comm2g_switch_enable; 1264242689Sadrian int ath_hal_ext_atten_margin_cfg; 1265242689Sadrian int ath_hal_war70c; 1266249131Sadrian uint32_t ath_hal_mci_config; 1267224633Sadrian} HAL_OPS_CONFIG; 1268223459Sadrian 1269222644Sadrian/* 1270185377Ssam * Hardware Access Layer (HAL) API. 1271185377Ssam * 1272185377Ssam * Clients of the HAL call ath_hal_attach to obtain a reference to an 1273185377Ssam * ath_hal structure for use with the device. Hardware-related operations 1274185377Ssam * that follow must call back into the HAL through interface, supplying 1275185377Ssam * the reference as the first parameter. Note that before using the 1276185377Ssam * reference returned by ath_hal_attach the caller should verify the 1277185377Ssam * ABI version number. 1278185377Ssam */ 1279185377Ssamstruct ath_hal { 1280185377Ssam uint32_t ah_magic; /* consistency check magic number */ 1281185377Ssam uint16_t ah_devid; /* PCI device ID */ 1282185377Ssam uint16_t ah_subvendorid; /* PCI subvendor ID */ 1283185377Ssam HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1284185377Ssam HAL_BUS_TAG ah_st; /* params for register r+w */ 1285185377Ssam HAL_BUS_HANDLE ah_sh; 1286185377Ssam HAL_CTRY_CODE ah_countryCode; 1287185377Ssam 1288185377Ssam uint32_t ah_macVersion; /* MAC version id */ 1289185377Ssam uint16_t ah_macRev; /* MAC revision */ 1290185377Ssam uint16_t ah_phyRev; /* PHY revision */ 1291185377Ssam /* NB: when only one radio is present the rev is in 5Ghz */ 1292185377Ssam uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1293185377Ssam uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1294185377Ssam 1295217624Sadrian uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1296217624Sadrian 1297227365Sadrian uint32_t ah_intrstate[8]; /* last int state */ 1298234088Sadrian uint32_t ah_syncstate; /* last sync intr state */ 1299227365Sadrian 1300223459Sadrian HAL_OPS_CONFIG ah_config; 1301185377Ssam const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1302185377Ssam u_int mode); 1303185377Ssam void __ahdecl(*ah_detach)(struct ath_hal*); 1304185377Ssam 1305185377Ssam /* Reset functions */ 1306185377Ssam HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1307187831Ssam struct ieee80211_channel *, 1308187831Ssam HAL_BOOL bChannelChange, HAL_STATUS *status); 1309185377Ssam HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1310185377Ssam HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1311235972Sadrian void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1312235972Sadrian HAL_BOOL power_off); 1313188979Ssam void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1314185377Ssam void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1315187831Ssam HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1316187831Ssam struct ieee80211_channel *, HAL_BOOL *); 1317187831Ssam HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1318187831Ssam struct ieee80211_channel *, u_int chainMask, 1319187831Ssam HAL_BOOL longCal, HAL_BOOL *isCalDone); 1320187831Ssam HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1321187831Ssam const struct ieee80211_channel *); 1322203930Srpaulo HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1323203930Srpaulo const struct ieee80211_channel *, uint16_t *); 1324185377Ssam HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1325203930Srpaulo HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1326203930Srpaulo const struct ieee80211_channel *); 1327185377Ssam 1328185377Ssam /* Transmit functions */ 1329185377Ssam HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1330185377Ssam HAL_BOOL incTrigLevel); 1331185377Ssam int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1332185377Ssam const HAL_TXQ_INFO *qInfo); 1333185377Ssam HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1334185377Ssam const HAL_TXQ_INFO *qInfo); 1335185377Ssam HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1336185377Ssam HAL_TXQ_INFO *qInfo); 1337185377Ssam HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1338185377Ssam HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1339185377Ssam uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1340185377Ssam HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1341185377Ssam uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1342185377Ssam HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1343185377Ssam HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1344185377Ssam HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1345185377Ssam u_int pktLen, u_int hdrLen, 1346185377Ssam HAL_PKT_TYPE type, u_int txPower, 1347185377Ssam u_int txRate0, u_int txTries0, 1348185377Ssam u_int keyIx, u_int antMode, u_int flags, 1349185377Ssam u_int rtsctsRate, u_int rtsctsDuration, 1350185377Ssam u_int compicvLen, u_int compivLen, 1351185377Ssam u_int comp); 1352185377Ssam HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1353185377Ssam u_int txRate1, u_int txTries1, 1354185377Ssam u_int txRate2, u_int txTries2, 1355185377Ssam u_int txRate3, u_int txTries3); 1356185377Ssam HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1357239051Sadrian HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 1358239051Sadrian u_int descId, u_int qcuId, HAL_BOOL firstSeg, 1359185377Ssam HAL_BOOL lastSeg, const struct ath_desc *); 1360185377Ssam HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1361185377Ssam struct ath_desc *, struct ath_tx_status *); 1362185377Ssam void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1363185377Ssam void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1364217621Sadrian HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1365217621Sadrian const struct ath_desc *ds, int *rates, int *tries); 1366238607Sadrian void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds, 1367238607Sadrian uint32_t link); 1368238607Sadrian void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds, 1369238607Sadrian uint32_t *link); 1370238607Sadrian void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds, 1371238607Sadrian uint32_t **linkptr); 1372238731Sadrian void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *, 1373238731Sadrian void *ts_start, uint32_t ts_paddr_start, 1374238731Sadrian uint16_t size); 1375242509Sadrian void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *); 1376185377Ssam 1377185377Ssam /* Receive Functions */ 1378238278Sadrian uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1379238278Sadrian void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1380185377Ssam void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1381185377Ssam HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1382185377Ssam void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 1383185377Ssam void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1384185377Ssam void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1385185377Ssam uint32_t filter0, uint32_t filter1); 1386185377Ssam HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1387185377Ssam uint32_t index); 1388185377Ssam HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1389185377Ssam uint32_t index); 1390185377Ssam uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1391185377Ssam void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1392185377Ssam HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1393185377Ssam uint32_t size, u_int flags); 1394185377Ssam HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1395185377Ssam struct ath_desc *, uint32_t phyAddr, 1396185377Ssam struct ath_desc *next, uint64_t tsf, 1397185377Ssam struct ath_rx_status *); 1398185377Ssam void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1399187831Ssam const HAL_NODE_STATS *, 1400187831Ssam const struct ieee80211_channel *); 1401217684Sadrian void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1402217684Sadrian const struct ieee80211_channel *); 1403185377Ssam void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1404185377Ssam const HAL_NODE_STATS *); 1405185377Ssam 1406185377Ssam /* Misc Functions */ 1407185377Ssam HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1408185377Ssam HAL_CAPABILITY_TYPE, uint32_t capability, 1409185377Ssam uint32_t *result); 1410185377Ssam HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1411185377Ssam HAL_CAPABILITY_TYPE, uint32_t capability, 1412185377Ssam uint32_t setting, HAL_STATUS *); 1413185377Ssam HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1414185377Ssam const void *args, uint32_t argsize, 1415185377Ssam void **result, uint32_t *resultsize); 1416185377Ssam void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1417185377Ssam HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1418185377Ssam void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1419185377Ssam HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1420185377Ssam HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1421185377Ssam uint16_t, HAL_STATUS *); 1422185377Ssam void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1423185377Ssam void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1424185377Ssam const uint8_t *bssid, uint16_t assocId); 1425188974Ssam HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1426188974Ssam uint32_t gpio, HAL_GPIO_MUX_TYPE); 1427185377Ssam HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1428185377Ssam uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1429185377Ssam HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1430185377Ssam uint32_t gpio, uint32_t val); 1431185377Ssam void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1432185377Ssam uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1433185377Ssam uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1434243424Sadrian void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t); 1435185377Ssam void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1436185377Ssam HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1437185377Ssam void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1438185377Ssam HAL_MIB_STATS*); 1439185377Ssam HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1440185377Ssam u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1441185377Ssam void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1442185377Ssam HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1443185377Ssam HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1444185377Ssam HAL_ANT_SETTING); 1445185377Ssam HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1446185377Ssam u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1447185377Ssam HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1448185377Ssam u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1449185377Ssam HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1450185377Ssam u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1451185377Ssam HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1452185377Ssam u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1453185377Ssam HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1454185377Ssam u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1455185377Ssam HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1456185377Ssam void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1457222644Sadrian HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1458222644Sadrian uint32_t duration, uint32_t nextStart, 1459222644Sadrian HAL_QUIET_FLAG flag); 1460247286Sadrian void __ahdecl(*ah_setChainMasks)(struct ath_hal *, 1461247286Sadrian uint32_t, uint32_t); 1462185377Ssam 1463222584Sadrian /* DFS functions */ 1464222584Sadrian void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1465222584Sadrian HAL_PHYERR_PARAM *pe); 1466222584Sadrian void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1467222584Sadrian HAL_PHYERR_PARAM *pe); 1468239638Sadrian HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah, 1469239638Sadrian HAL_PHYERR_PARAM *pe); 1470222815Sadrian HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1471222815Sadrian struct ath_rx_status *rxs, uint64_t fulltsf, 1472222815Sadrian const char *buf, HAL_DFS_EVENT *event); 1473224709Sadrian HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1474222584Sadrian 1475244854Sadrian /* Spectral Scan functions */ 1476244854Sadrian void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah, 1477244854Sadrian HAL_SPECTRAL_PARAM *sp); 1478244854Sadrian void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah, 1479244854Sadrian HAL_SPECTRAL_PARAM *sp); 1480244854Sadrian void __ahdecl(*ah_spectralStart)(struct ath_hal *); 1481244854Sadrian void __ahdecl(*ah_spectralStop)(struct ath_hal *); 1482244854Sadrian HAL_BOOL __ahdecl(*ah_spectralIsEnabled)(struct ath_hal *); 1483244854Sadrian HAL_BOOL __ahdecl(*ah_spectralIsActive)(struct ath_hal *); 1484244854Sadrian /* XXX getNfPri() and getNfExt() */ 1485244854Sadrian 1486185377Ssam /* Key Cache Functions */ 1487185377Ssam uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1488185377Ssam HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1489185377Ssam HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1490185377Ssam uint16_t); 1491185377Ssam HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1492185377Ssam uint16_t, const HAL_KEYVAL *, 1493185377Ssam const uint8_t *, int); 1494185377Ssam HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1495185377Ssam uint16_t, const uint8_t *); 1496185377Ssam 1497185377Ssam /* Power Management Functions */ 1498185377Ssam HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1499185377Ssam HAL_POWER_MODE mode, int setChip); 1500185377Ssam HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1501187831Ssam int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1502187831Ssam const struct ieee80211_channel *); 1503185377Ssam 1504185377Ssam /* Beacon Management Functions */ 1505185377Ssam void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1506185377Ssam const HAL_BEACON_TIMERS *); 1507185377Ssam /* NB: deprecated, use ah_setBeaconTimers instead */ 1508185377Ssam void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1509185377Ssam uint32_t nexttbtt, uint32_t intval); 1510185377Ssam void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1511185377Ssam const HAL_BEACON_STATE *); 1512185377Ssam void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1513225444Sadrian uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1514185377Ssam 1515218066Sadrian /* 802.11n Functions */ 1516218066Sadrian HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1517239053Sadrian struct ath_desc *, 1518239053Sadrian HAL_DMA_ADDR *bufAddrList, 1519239053Sadrian uint32_t *segLenList, 1520239053Sadrian u_int, u_int, HAL_PKT_TYPE, 1521239053Sadrian u_int, HAL_CIPHER, uint8_t, HAL_BOOL, 1522233895Sadrian HAL_BOOL, HAL_BOOL); 1523218066Sadrian HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1524218066Sadrian struct ath_desc *, u_int, u_int, u_int, 1525218066Sadrian u_int, u_int, u_int, u_int, u_int); 1526218066Sadrian HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1527218066Sadrian struct ath_desc *, const struct ath_desc *); 1528218066Sadrian void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1529218066Sadrian struct ath_desc *, u_int, u_int, 1530218066Sadrian HAL_11N_RATE_SERIES [], u_int, u_int); 1531242407Sadrian 1532242407Sadrian /* 1533242407Sadrian * The next 4 (set11ntxdesc -> set11naggrlast) are specific 1534242407Sadrian * to the EDMA HAL. Descriptors are chained together by 1535242407Sadrian * using filltxdesc (not ChainTxDesc) and then setting the 1536242407Sadrian * aggregate flags appropriately using first/middle/last. 1537242407Sadrian */ 1538242407Sadrian void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *, 1539242407Sadrian void *, u_int, HAL_PKT_TYPE, u_int, u_int, 1540242407Sadrian u_int); 1541226767Sadrian void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1542242509Sadrian struct ath_desc *, u_int, u_int); 1543218066Sadrian void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1544218066Sadrian struct ath_desc *, u_int); 1545226767Sadrian void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1546226767Sadrian struct ath_desc *); 1547218066Sadrian void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1548218066Sadrian struct ath_desc *); 1549218066Sadrian void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1550218066Sadrian struct ath_desc *, u_int); 1551247774Sadrian void __ahdecl(*ah_set11nVirtMoreFrag)(struct ath_hal *, 1552247774Sadrian struct ath_desc *, u_int); 1553247774Sadrian 1554234873Sadrian HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1555234873Sadrian HAL_SURVEY_SAMPLE *); 1556227374Sadrian 1557218066Sadrian uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1558218066Sadrian void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1559218066Sadrian HAL_HT_MACMODE); 1560218066Sadrian HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1561218066Sadrian void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1562218066Sadrian HAL_HT_RXCLEAR); 1563218066Sadrian 1564185377Ssam /* Interrupt functions */ 1565185377Ssam HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1566185377Ssam HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1567185377Ssam HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1568185377Ssam HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1569243840Sadrian 1570243840Sadrian /* Bluetooth Coexistence functions */ 1571243840Sadrian void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *, 1572243840Sadrian HAL_BT_COEX_INFO *); 1573243840Sadrian void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *, 1574243840Sadrian HAL_BT_COEX_CONFIG *); 1575243840Sadrian void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *, 1576243840Sadrian int); 1577243840Sadrian void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *, 1578243840Sadrian uint32_t); 1579243840Sadrian void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *, 1580243840Sadrian uint32_t); 1581251483Sadrian void __ahdecl(*ah_btCoexSetParameter)(struct ath_hal *, 1582243840Sadrian uint32_t, uint32_t); 1583243840Sadrian void __ahdecl(*ah_btCoexDisable)(struct ath_hal *); 1584243840Sadrian int __ahdecl(*ah_btCoexEnable)(struct ath_hal *); 1585251655Sadrian 1586251655Sadrian /* LNA diversity configuration */ 1587251655Sadrian void __ahdecl(*ah_divLnaConfGet)(struct ath_hal *, 1588251655Sadrian HAL_ANT_COMB_CONFIG *); 1589251655Sadrian void __ahdecl(*ah_divLnaConfSet)(struct ath_hal *, 1590251655Sadrian HAL_ANT_COMB_CONFIG *); 1591185377Ssam}; 1592185377Ssam 1593185377Ssam/* 1594185377Ssam * Check the PCI vendor ID and device ID against Atheros' values 1595185377Ssam * and return a printable description for any Atheros hardware. 1596185377Ssam * AH_NULL is returned if the ID's do not describe Atheros hardware. 1597185377Ssam */ 1598185377Ssamextern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1599185377Ssam 1600185377Ssam/* 1601185377Ssam * Attach the HAL for use with the specified device. The device is 1602185377Ssam * defined by the PCI device ID. The caller provides an opaque pointer 1603185377Ssam * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1604185377Ssam * HAL state block for later use. Hardware register accesses are done 1605185377Ssam * using the specified bus tag and handle. On successful return a 1606185377Ssam * reference to a state block is returned that must be supplied in all 1607185377Ssam * subsequent HAL calls. Storage associated with this reference is 1608185377Ssam * dynamically allocated and must be freed by calling the ah_detach 1609185377Ssam * method when the client is done. If the attach operation fails a 1610185377Ssam * null (AH_NULL) reference will be returned and a status code will 1611185377Ssam * be returned if the status parameter is non-zero. 1612185377Ssam */ 1613185377Ssamextern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1614217624Sadrian HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 1615185377Ssam 1616188968Ssamextern const char *ath_hal_mac_name(struct ath_hal *); 1617188968Ssamextern const char *ath_hal_rf_name(struct ath_hal *); 1618188968Ssam 1619185377Ssam/* 1620187831Ssam * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1621187831Ssam * request a set of channels for a particular country code and/or 1622187831Ssam * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1623187831Ssam * this list is constructed according to the contents of the EEPROM. 1624187831Ssam * ath_hal_getchannels acts similarly but does not alter the operating 1625187831Ssam * state; this can be used to collect information for a particular 1626187831Ssam * regulatory configuration. Finally ath_hal_set_channels installs a 1627187831Ssam * channel list constructed outside the driver. The HAL will adopt the 1628187831Ssam * channel list and setup internal state according to the specified 1629187831Ssam * regulatory configuration (e.g. conformance test limits). 1630185377Ssam * 1631187831Ssam * For all interfaces the channel list is returned in the supplied array. 1632187831Ssam * maxchans defines the maximum size of this array. nchans contains the 1633187831Ssam * actual number of channels returned. If a problem occurred then a 1634187831Ssam * status code != HAL_OK is returned. 1635185377Ssam */ 1636187831Ssamstruct ieee80211_channel; 1637185377Ssam 1638185377Ssam/* 1639187831Ssam * Return a list of channels according to the specified regulatory. 1640185377Ssam */ 1641187831Ssamextern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1642187831Ssam struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1643187831Ssam u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1644187831Ssam HAL_BOOL enableExtendedChannels); 1645185377Ssam 1646185377Ssam/* 1647187831Ssam * Return a list of channels and install it as the current operating 1648187831Ssam * regulatory list. 1649185377Ssam */ 1650187831Ssamextern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1651187831Ssam struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1652187831Ssam u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1653187831Ssam HAL_BOOL enableExtendedChannels); 1654185377Ssam 1655185377Ssam/* 1656187831Ssam * Install the list of channels as the current operating regulatory 1657187831Ssam * and setup related state according to the country code and sku. 1658185377Ssam */ 1659187831Ssamextern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1660187831Ssam struct ieee80211_channel *chans, int nchans, 1661187831Ssam HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1662185377Ssam 1663185377Ssam/* 1664220443Sadrian * Fetch the ctl/ext noise floor values reported by a MIMO 1665220443Sadrian * radio. Returns 1 for valid results, 0 for invalid channel. 1666220443Sadrian */ 1667220443Sadrianextern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1668220444Sadrian const struct ieee80211_channel *chan, int16_t *nf_ctl, 1669220444Sadrian int16_t *nf_ext); 1670220443Sadrian 1671220443Sadrian/* 1672187831Ssam * Calibrate noise floor data following a channel scan or similar. 1673187831Ssam * This must be called prior retrieving noise floor data. 1674185377Ssam */ 1675187831Ssamextern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1676185377Ssam 1677185377Ssam/* 1678187831Ssam * Return bit mask of wireless modes supported by the hardware. 1679185377Ssam */ 1680187831Ssamextern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1681185377Ssam 1682185377Ssam/* 1683239634Sadrian * Get the HAL wireless mode for the given channel. 1684239634Sadrian */ 1685239635Sadrianextern int ath_hal_get_curmode(struct ath_hal *ah, 1686239634Sadrian const struct ieee80211_channel *chan); 1687239634Sadrian 1688239634Sadrian/* 1689218011Sadrian * Calculate the packet TX time for a legacy or 11n frame 1690185377Ssam */ 1691218011Sadrianextern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1692218011Sadrian const HAL_RATE_TABLE *rates, uint32_t frameLen, 1693218011Sadrian uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1694218011Sadrian 1695218011Sadrian/* 1696218011Sadrian * Calculate the duration of an 11n frame. 1697218011Sadrian */ 1698218011Sadrianextern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1699218011Sadrian int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1700218011Sadrian 1701218011Sadrian/* 1702218011Sadrian * Calculate the transmit duration of a legacy frame. 1703218011Sadrian */ 1704187831Ssamextern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1705187831Ssam const HAL_RATE_TABLE *rates, uint32_t frameLen, 1706187831Ssam uint16_t rateix, HAL_BOOL shortPreamble); 1707225444Sadrian 1708225444Sadrian/* 1709225444Sadrian * Adjust the TSF. 1710225444Sadrian */ 1711225444Sadrianextern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1712225444Sadrian 1713225444Sadrian/* 1714225444Sadrian * Enable or disable CCA. 1715225444Sadrian */ 1716225444Sadrianvoid __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1717225444Sadrian 1718225444Sadrian/* 1719225444Sadrian * Get CCA setting. 1720225444Sadrian */ 1721225444Sadrianint __ahdecl ath_hal_getcca(struct ath_hal *ah); 1722225444Sadrian 1723230147Sadrian/* 1724230147Sadrian * Read EEPROM data from ah_eepromdata 1725230147Sadrian */ 1726230147SadrianHAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1727230147Sadrian u_int off, uint16_t *data); 1728230147Sadrian 1729239606Sadrian/* 1730239606Sadrian * For now, simply pass through MFP frames. 1731239606Sadrian */ 1732239606Sadrianstatic inline u_int32_t 1733239606Sadrianath_hal_get_mfp_qos(struct ath_hal *ah) 1734239606Sadrian{ 1735239606Sadrian //return AH_PRIVATE(ah)->ah_mfp_qos; 1736239606Sadrian return HAL_MFP_QOSDATA; 1737239606Sadrian} 1738239606Sadrian 1739185377Ssam#endif /* _ATH_AH_H_ */ 1740