ah_osdep.c revision 222031 
1/*-
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer,
10 *    without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 *    redistribution must be conditioned upon including a substantially
14 *    similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
29 * $FreeBSD: head/sys/dev/ath/ah_osdep.c 222031 2011-05-17 16:30:34Z adrian $
30 */
31#include "opt_ah.h"
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/sysctl.h>
38#include <sys/bus.h>
39#include <sys/malloc.h>
40#include <sys/proc.h>
41
42#include <machine/stdarg.h>
43
44#include <net/ethernet.h>		/* XXX for ether_sprintf */
45
46#include <dev/ath/ath_hal/ah.h>
47
48/*
49 * WiSoC boards overload the bus tag with information about the
50 * board layout.  We must extract the bus space tag from that
51 * indirect structure.  For everyone else the tag is passed in
52 * directly.
53 * XXX cache indirect ref privately
54 */
55#ifdef AH_SUPPORT_AR5312
56#define	BUSTAG(ah) \
57	((bus_space_tag_t) ((struct ar531x_config *)((ah)->ah_st))->tag)
58#else
59#define	BUSTAG(ah)	((ah)->ah_st)
60#endif
61
62extern	void ath_hal_printf(struct ath_hal *, const char*, ...)
63		__printflike(2,3);
64extern	void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
65		__printflike(2, 0);
66extern	const char* ath_hal_ether_sprintf(const u_int8_t *mac);
67extern	void *ath_hal_malloc(size_t);
68extern	void ath_hal_free(void *);
69#ifdef AH_ASSERT
70extern	void ath_hal_assert_failed(const char* filename,
71		int lineno, const char* msg);
72#endif
73#ifdef AH_DEBUG
74extern	void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...);
75#endif /* AH_DEBUG */
76
77/* NB: put this here instead of the driver to avoid circular references */
78SYSCTL_NODE(_hw, OID_AUTO, ath, CTLFLAG_RD, 0, "Atheros driver parameters");
79SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0, "Atheros HAL parameters");
80
81#ifdef AH_DEBUG
82int ath_hal_debug = 0;
83SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug,
84	    0, "Atheros HAL debugging printfs");
85TUNABLE_INT("hw.ath.hal.debug", &ath_hal_debug);
86#endif /* AH_DEBUG */
87
88int ath_hal_ar5416_biasadj = 0;
89SYSCTL_INT(_hw_ath_hal, OID_AUTO, ar5416_biasadj, CTLFLAG_RW,
90	&ath_hal_ar5416_biasadj, 0, "Enable 2ghz AR5416 direction sensitivity"
91	" bias adjust");
92
93/* NB: these are deprecated; they exist for now for compatibility */
94int	ath_hal_dma_beacon_response_time = 2;	/* in TU's */
95SYSCTL_INT(_hw_ath_hal, OID_AUTO, dma_brt, CTLFLAG_RW,
96	   &ath_hal_dma_beacon_response_time, 0,
97	   "Atheros HAL DMA beacon response time");
98int	ath_hal_sw_beacon_response_time = 10;	/* in TU's */
99SYSCTL_INT(_hw_ath_hal, OID_AUTO, sw_brt, CTLFLAG_RW,
100	   &ath_hal_sw_beacon_response_time, 0,
101	   "Atheros HAL software beacon response time");
102int	ath_hal_additional_swba_backoff = 0;	/* in TU's */
103SYSCTL_INT(_hw_ath_hal, OID_AUTO, swba_backoff, CTLFLAG_RW,
104	   &ath_hal_additional_swba_backoff, 0,
105	   "Atheros HAL additional SWBA backoff time");
106
107MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data");
108
109void*
110ath_hal_malloc(size_t size)
111{
112	return malloc(size, M_ATH_HAL, M_NOWAIT | M_ZERO);
113}
114
115void
116ath_hal_free(void* p)
117{
118	free(p, M_ATH_HAL);
119}
120
121void
122ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)
123{
124	vprintf(fmt, ap);
125}
126
127void
128ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)
129{
130	va_list ap;
131	va_start(ap, fmt);
132	ath_hal_vprintf(ah, fmt, ap);
133	va_end(ap);
134}
135
136const char*
137ath_hal_ether_sprintf(const u_int8_t *mac)
138{
139	return ether_sprintf(mac);
140}
141
142#ifdef AH_DEBUG
143
144/* This must match the definition in ath_hal/ah_debug.h */
145#define	HAL_DEBUG_UNMASKABLE	0xf0000000
146void
147DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
148{
149	if ((mask == HAL_DEBUG_UNMASKABLE) || (ath_hal_debug & mask)) {
150		__va_list ap;
151		va_start(ap, fmt);
152		ath_hal_vprintf(ah, fmt, ap);
153		va_end(ap);
154	}
155}
156#undef	HAL_DEBUG_UNMASKABLE
157#endif /* AH_DEBUG */
158
159#ifdef AH_DEBUG_ALQ
160/*
161 * ALQ register tracing support.
162 *
163 * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
164 * writes to the file /tmp/ath_hal.log.  The file format is a simple
165 * fixed-size array of records.  When done logging set hw.ath.hal.alq=0
166 * and then decode the file with the arcode program (that is part of the
167 * HAL).  If you start+stop tracing the data will be appended to an
168 * existing file.
169 *
170 * NB: doesn't handle multiple devices properly; only one DEVICE record
171 *     is emitted and the different devices are not identified.
172 */
173#include <sys/alq.h>
174#include <sys/pcpu.h>
175#include <dev/ath/ath_hal/ah_decode.h>
176
177static	struct alq *ath_hal_alq;
178static	int ath_hal_alq_emitdev;	/* need to emit DEVICE record */
179static	u_int ath_hal_alq_lost;		/* count of lost records */
180static	char ath_hal_logfile[MAXPATHLEN] = "/tmp/ath_hal.log";
181
182SYSCTL_STRING(_hw_ath_hal, OID_AUTO, alq_logfile, CTLFLAG_RW,
183    &ath_hal_logfile, sizeof(kernelname), "Name of ALQ logfile");
184
185static	u_int ath_hal_alq_qsize = 64*1024;
186
187static int
188ath_hal_setlogging(int enable)
189{
190	int error;
191
192	if (enable) {
193		error = alq_open(&ath_hal_alq, ath_hal_logfile,
194			curthread->td_ucred, ALQ_DEFAULT_CMODE,
195			sizeof (struct athregrec), ath_hal_alq_qsize);
196		ath_hal_alq_lost = 0;
197		ath_hal_alq_emitdev = 1;
198		printf("ath_hal: logging to %s enabled\n",
199			ath_hal_logfile);
200	} else {
201		if (ath_hal_alq)
202			alq_close(ath_hal_alq);
203		ath_hal_alq = NULL;
204		printf("ath_hal: logging disabled\n");
205		error = 0;
206	}
207	return (error);
208}
209
210static int
211sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS)
212{
213	int error, enable;
214
215	enable = (ath_hal_alq != NULL);
216        error = sysctl_handle_int(oidp, &enable, 0, req);
217        if (error || !req->newptr)
218                return (error);
219	else
220		return (ath_hal_setlogging(enable));
221}
222SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW,
223	0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging");
224SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW,
225	&ath_hal_alq_qsize, 0, "In-memory log size (#records)");
226SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW,
227	&ath_hal_alq_lost, 0, "Register operations not logged");
228
229static struct ale *
230ath_hal_alq_get(struct ath_hal *ah)
231{
232	struct ale *ale;
233
234	if (ath_hal_alq_emitdev) {
235		ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
236		if (ale) {
237			struct athregrec *r =
238				(struct athregrec *) ale->ae_data;
239			r->op = OP_DEVICE;
240			r->reg = 0;
241			r->val = ah->ah_devid;
242			alq_post(ath_hal_alq, ale);
243			ath_hal_alq_emitdev = 0;
244		} else
245			ath_hal_alq_lost++;
246	}
247	ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
248	if (!ale)
249		ath_hal_alq_lost++;
250	return ale;
251}
252
253void
254ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
255{
256	bus_space_tag_t tag = BUSTAG(ah);
257	bus_space_handle_t h = ah->ah_sh;
258
259	if (ath_hal_alq) {
260		struct ale *ale = ath_hal_alq_get(ah);
261		if (ale) {
262			struct athregrec *r = (struct athregrec *) ale->ae_data;
263			r->op = OP_WRITE;
264			r->reg = reg;
265			r->val = val;
266			alq_post(ath_hal_alq, ale);
267		}
268	}
269#if _BYTE_ORDER == _BIG_ENDIAN
270	if (OS_REG_UNSWAPPED(reg))
271		bus_space_write_4(tag, h, reg, val);
272	else
273#endif
274		bus_space_write_stream_4(tag, h, reg, val);
275}
276
277u_int32_t
278ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
279{
280	bus_space_tag_t tag = BUSTAG(ah);
281	bus_space_handle_t h = ah->ah_sh;
282	u_int32_t val;
283
284#if _BYTE_ORDER == _BIG_ENDIAN
285	if (OS_REG_UNSWAPPED(reg))
286		val = bus_space_read_4(tag, h, reg);
287	else
288#endif
289		val = bus_space_read_stream_4(tag, h, reg);
290	if (ath_hal_alq) {
291		struct ale *ale = ath_hal_alq_get(ah);
292		if (ale) {
293			struct athregrec *r = (struct athregrec *) ale->ae_data;
294			r->op = OP_READ;
295			r->reg = reg;
296			r->val = val;
297			alq_post(ath_hal_alq, ale);
298		}
299	}
300	return val;
301}
302
303void
304OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
305{
306	if (ath_hal_alq) {
307		struct ale *ale = ath_hal_alq_get(ah);
308		if (ale) {
309			struct athregrec *r = (struct athregrec *) ale->ae_data;
310			r->op = OP_MARK;
311			r->reg = id;
312			r->val = v;
313			alq_post(ath_hal_alq, ale);
314		}
315	}
316}
317#elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
318/*
319 * Memory-mapped device register read/write.  These are here
320 * as routines when debugging support is enabled and/or when
321 * explicitly configured to use function calls.  The latter is
322 * for architectures that might need to do something before
323 * referencing memory (e.g. remap an i/o window).
324 *
325 * NB: see the comments in ah_osdep.h about byte-swapping register
326 *     reads and writes to understand what's going on below.
327 */
328
329void
330ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
331{
332	bus_space_tag_t tag = BUSTAG(ah);
333	bus_space_handle_t h = ah->ah_sh;
334
335#if _BYTE_ORDER == _BIG_ENDIAN
336	if (OS_REG_UNSWAPPED(reg))
337		bus_space_write_4(tag, h, reg, val);
338	else
339#endif
340		bus_space_write_stream_4(tag, h, reg, val);
341}
342
343u_int32_t
344ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
345{
346	bus_space_tag_t tag = BUSTAG(ah);
347	bus_space_handle_t h = ah->ah_sh;
348	u_int32_t val;
349
350#if _BYTE_ORDER == _BIG_ENDIAN
351	if (OS_REG_UNSWAPPED(reg))
352		val = bus_space_read_4(tag, h, reg);
353	else
354#endif
355		val = bus_space_read_stream_4(tag, h, reg);
356	return val;
357}
358#endif /* AH_DEBUG || AH_REGOPS_FUNC */
359
360#ifdef AH_ASSERT
361void
362ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
363{
364	printf("Atheros HAL assertion failure: %s: line %u: %s\n",
365		filename, lineno, msg);
366	panic("ath_hal_assert");
367}
368#endif /* AH_ASSERT */
369